Non-volatile memory device

Abstract

A nonvolatile memory device is disclosed. A nonvolatile memory device includes a memory bank and a programming current generator. The memory bank includes: a memory cell array including phase change memory cells storing data based on programming current; and a transmission element transmitting the programming current to the memory cell array through current mirroring. The programming current generator generates the programming current based on a reference current.

Description

[0001] Priority is claimed on Korean Patent Application No. 10-2018-0136490 filed on November 8, 2018, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The inventive concepts herein relate to semiconductor memories, and more particularly, to nonvolatile memory devices including transfer elements. Background Art

[0003] Semiconductor memory may include nonvolatile memory (such as phase change memory, ferroelectric memory, magnetic memory, resistive memory and flash memory). Specifically, phase change memory is configured to change the resistance value of a memory cell using an electric current. That is, a write operation of a memory cell in a phase change memory may be based on a programming current corresponding to a set operation or a reset operation.

[0004] The memory cells may be arranged in two dimensions. However, the optimized programming current for the write operation may vary with the relative positions of the memory cells. If the same programming current corresponding to the set operation is applied to all the two-dimensionally arranged memory cells, or if the same programming current corresponding to the reset operation is applied to all the two-dimensionally arranged memory cells, the write operation may not be performed or an error may occur during the write operation depending on the positions of the memory cells. Therefore, it is necessary to improve the reliability of the write operation of the non-volatile memory device. Summary of the invention

[0005] Embodiments of the inventive concept provide a nonvolatile memory device including a transmission element, which can improve accuracy and reliability during a write operation and can reduce errors during a write operation.

[0006] Embodiments of the inventive concept provide a nonvolatile memory device including a memory bank and a programming current generator. The memory bank includes a memory cell array, and the memory cell array includes a phase change memory cell that stores data based on a programming current. A transmission element transmits a programming current to the memory cell array through a current mirror. The programming current generator generates a programming current based on a reference current.

[0007] Embodiments of the inventive concept also provide a nonvolatile memory device including a peripheral circuit and a memory bank. The peripheral circuit includes a programming current generator that generates a programming current based on a reference current. The memory bank includes: a memory cell array; a transmission element that receives the programming current from the programming current generator; and a write driver that mirrors the programming current from the transmission element and performs a write operation on a selected memory cell of the memory cell array.

[0008] An embodiment of the present invention also provides a non-volatile memory device, comprising: a first layer, including a first storage body that performs a write operation based on a first programming current; a second layer, including a second storage body that performs a write operation based on a second programming current, the second layer being located above the first layer; a programming current generator, configured to generate a first programming current and a second programming current based on a reference current; a first transmission element, configured to transmit the first programming current received from the programming current generator to the first storage body through a current mirror; and a second transmission element, configured to transmit the second programming current received from the programming current generator to the second storage body through a current mirror. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other objects and features of the present inventive concept will become apparent in view of the following detailed description of exemplary embodiments with reference to the accompanying drawings.

[0010] Figure 1 A block diagram of a nonvolatile memory device according to an embodiment of the inventive concept is shown.

[0011] Figure 2 Show Figure 1 Schematic diagram of an exemplary embodiment of a memory bank.

[0012] Figure 3 Show Figure 2 An exemplary circuit diagram of a memory cell array.

[0013] Figure 4 Show reference Figure 1 and Figure 2 A diagram of an exemplary structure of a nonvolatile memory device is described.

[0014] Figure 5 Show Figure 4 Schematic diagram of a memory bank array.

[0015] Figure 6 Show Figure 4 Circuit diagram of the programming current generator.

[0016] Figure 7 A circuit diagram of a programming current generator including a pass element is shown.

[0017] Figure 8 Shown in Figure 1 and Figure 2 A diagram of an exemplary structure of a nonvolatile memory device described in .

[0018] Fig. 9 Show Figure 8 A flowchart of a method of operating a non-volatile memory system.

[0019] Fig.10 Shown in Figure 1 and Figure 2 A diagram of an exemplary structure of a nonvolatile memory device described in .

[0020] Fig.11 Diagram illustrating an exemplary structure of a nonvolatile memory device according to an embodiment of the inventive concept.

[0021] Fig.12 A block diagram of a computing device according to an embodiment of the inventive concept is shown. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments of the inventive concept will be described clearly and in detail with reference to the accompanying drawings to the extent that those having ordinary skill in the art can implement the embodiments of the inventive concept.

[0023] As in the tradition of the field of the present invention, the embodiment can be described and illustrated according to the block of one or more functions of the execution description.These blocks, which may be referred to as units or modules, are physically implemented by analog and / or digital circuits (such as, logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hard-wired circuits, etc.), and can be selectively driven by firmware and / or software.The circuit may be, for example, implemented in one or more semiconductor chips, or implemented on substrate supports such as printed circuit boards.The circuit constituting the block may be implemented by dedicated hardware, or by a processor (for example, one or more programmed microprocessors and associated circuits), or by a combination of dedicated hardware for executing some functions of the block and a processor for executing other functions of the block.Without departing from the scope of the present invention, each block of the embodiment may be physically divided into two or more interacting and discrete blocks.Similarly, without departing from the scope of the present invention, the block of the embodiment may be physically combined into more complex blocks.

[0024] Figure 1 FIG. 1 is a block diagram of a nonvolatile memory device according to an embodiment of the inventive concept. Figure 1 , the nonvolatile memory device 100 includes a memory bank array 110 , an address buffer 120 , a command buffer 130 , a programming (PGM) current generator 140 , and a control logic circuit 150 .

[0025] The memory bank array 110 may include a first memory bank 111 to a k-th memory bank 11k (i.e., a first memory bank 111, a second memory bank 112, a third memory bank 113 to a k-th memory bank 11k as shown). Each of the first memory bank 111 to the k-th memory bank 11k may include a memory cell for storing data. The first memory bank 111 to the k-th memory bank 11k may perform a write operation or a read operation independently of each other. The write operation may include a set operation of changing a logic value "0" to a logic value "1" and a reset operation of changing a logic value "1" to a logic value "0". The number of memory banks included in the memory bank array 110 is not limited.

[0026] The address buffer 120 may receive an address ADDR from an external device. The address buffer 120 may provide a bank address BA of the address ADDR to the control logic circuit 150. The address buffer 120 may provide a row address RA and a column address CA to the bank array 110. The address buffer 120 may provide a row address RA and a column address CA to a bank selected by the control logic circuit 150 based on the bank address BA. The address buffer 120 may operate at a determined timing under the control of the control logic circuit 150.

[0027] The command buffer 130 may receive a command CMD from an external device. The command buffer 130 may provide the received command CMD to the control logic circuit 150. The command buffer 130 may operate at a determined timing under the control of the control logic circuit 150.

[0028] The programming current generator 140 may receive a data signal DQ for a write operation from an external device. The programming current generator 140 may generate a programming current IPGM based on the data signal DQ. The programming current generator 140 may supply the programming current IPGM to a memory bank selected from the first memory bank 111 to the kth memory bank 11k. The programming current generator 140 may generate a different programming current IPGM for each memory bank or each group of memory banks, the number of memory banks of each group of memory banks being predetermined, taking into account the physical locations of the first memory bank 111 to the kth memory bank 11k. This will be described in more detail later.

[0029] The control logic circuit 150 may control the operation of the nonvolatile memory device 100. The control logic circuit 150 may receive control information CTRL from an external device. The control logic circuit 150 may receive a bank address BA from the address buffer 120, and may receive a command CMD from the command buffer 130. The control logic circuit 150 may operate based on the control information CTRL, the bank address BA, and the command CMD. For example, the control logic circuit 150 may generate a first control signal C1, a second control signal C2, a third control signal C3, and a fourth control signal C4 for controlling the timing of the bank array 110, the address buffer 120, the command buffer 130, and the programming current generator 140 operations, respectively.

[0030] Figure 2 Show Figure 1 Schematic diagram of an exemplary embodiment of a memory bank. Figure 2 The memory bank 200 may be Figure 1 One of the first memory bank 111 to the kth memory bank 11k. Figure 2 , the memory bank 200 includes a memory cell array 210 , a row decoder 220 , a write driver and sense amplifier 230 , a transfer element 240 , and a column decoder 250 .

[0031] The memory cell array 210 may include memory cells connected to word lines WL and bit lines BL. For example, the memory cells in each row may be connected to one word line. The memory cells in each column may be connected to one bit line. The memory cell array 210 may include phase change memory cells.

[0032] The memory cell array 210 may be divided into a first cell region 211, a second cell region 212 to an m-th cell region 21m. Each of the first cell region 211 to the m-th cell region 21m may include a memory cell corresponding to at least one word line. Here, "m" indicating the number of divided regions may correspond to the number of write drivers. For example, one cell region and one write driver may be defined as one bay in the memory bank 200.

[0033] The row decoder 220 is connected to the memory cell array 210 through word lines WL. The row decoder 220 can be Figure 1 The address buffer 120 receives the row address RA. The row decoder 220 may select one of the word lines WL based on the row address RA. The row decoder 220 may apply a selection voltage or a selection current to the selected word line, and may apply a non-selection voltage or a non-selection current to each of the unselected word lines.

[0034] The write driver and sense amplifier 230 is connected to the memory cell array 210 through the word line WL. The write driver and sense amplifier 230 may write data to a selected memory cell connected to a selected bit line by applying a programming current IPGM to the word line selected by the row decoder 220. For example, the write driver and sense amplifier 230 may perform a set operation or a reset operation on the selected memory cell to change the resistance value of the selected memory cell, thereby writing or erasing data.

[0035] The write driver and sense amplifier 230 may read data from the selected memory cell by sensing the current of the word line WL. For example, the write driver and sense amplifier 230 may perform a read operation on the selected memory cell to determine the range of the resistance value of the selected memory cell, thereby reading the data.

[0036] During a write operation, the write driver may mirror (or copy) the programming current IPGM provided to the transmission element 240 so that the programming current IPGM is applied to the selected memory cell. The write driver and sense amplifier 230 may be divided into a first driver region 231, a second driver region 232 to an m-th driver region 23m. Each of the first driver region 231 to the m-th driver region 23m may include a write driver and a sense amplifier. The first driver region 231 to the m-th driver region 23m may be arranged in parallel. The positions of the write drivers respectively included in the first driver region 231 to the m-th driver region 23m may be different from each other, and the result of mirroring the programming current IPGM may vary with the position of the write driver. The reason why the mirror characteristics of the write driver vary with the position and the method for overcoming the difference between the mirror characteristics will be described later.

[0037] The transmission element 240 can be Figure 1 The programming current generator 140 receives the programming current IPGM. The transmission element 240 may provide the received programming current IPGM to the write driver and the sense amplifier 230. The transmission element 240 may include a transistor that may mirror the programming current IPGM and may transmit the mirrored current to the write driver. For example, in order to mirror the programming current IPGM, the gate terminal of the transistor included in the transmission element 240 may be connected to the gate terminal of the transistor respectively included in the write driver.

[0038] The column decoder 250 can be Figure 1 The address buffer 120 receives the column address CA. The column decoder 250 may select at least one of the bit lines BL based on the column address CA.

[0039] Figure 3 Show Figure 2An exemplary circuit diagram of a memory cell array of FIG. Figure 3 , the memory cell array 210 includes memory cells MC. The memory cells MC may be arranged in rows and columns. The memory cells MC arranged in rows may be connected to word lines WL1, WL2, WL3 to WLn. The memory cells MC arranged in columns may be connected to a first bit line BL1, a second bit line BL2, a third bit line BL3, a fourth bit line BL4 to an mth bit line BLm.

[0040] Each of the memory cells MC is connected to a word line and a bit line. Each of the memory cells MC includes a selection element SE and a resistance element RE. The selection element SE can be controlled by the word line connected thereto, and the resistance element RE can be electrically connected to the word line corresponding thereto. For example, the selection element SE may include a transistor or a bidirectional threshold switch (OTS) controlled by the voltage of the word line.

[0041] The resistance element RE may have a resistance value changed by a set operation or a reset operation. The resistance element RE may be connected to a corresponding bit line. The resistance element RE may include a phase change material whose resistance value is determined differently according to a crystalline state and an amorphous state. The phase change material may change with a programming current IPGM.

[0042] In the set operation, a programming current for the set operation may be applied to the resistance element RE in the form of a set pulse. When the set pulse is applied to the resistance element RE, the phase change material of the resistance element RE may have a crystalline state and may have a low resistance value (i.e., a logical value of "1"). In the reset operation, a programming current for the reset operation may be applied to the resistance element RE in the form of a reset pulse. When the reset pulse is applied to the resistance element RE, the phase change material of the resistance element RE may have an amorphous state and may have a high resistance value (i.e., a logical value of "0"). The set pulse may be provided during a longer time than the reset pulse and may have a smaller current level than the reset pulse.

[0043] Figure 4 Shown in Figure 1 and Figure 2 Schematic diagram of an exemplary structure of a nonvolatile memory device described in . Figure 4 The nonvolatile memory device 300 includes a first memory bank 311 to a sixteenth memory bank 326 (i.e., the first memory bank 311, the second memory bank 312, the third memory bank 313 to the fifteenth memory bank 325, and the sixteenth memory bank 326 as shown) and a programming current generator 340. The first memory bank 311 to the sixteenth memory bank 326 and the programming current generator 340 may be formed on a semiconductor substrate. The first memory bank 311 to the sixteenth memory bank 326 correspond to Figure 1 The first memory bank 111 to the kth memory bank 11k, the programming current generator 340 corresponds to Figure 1 The programming current generator 140 is provided.

[0044] exist Figure 4 In the following drawings, a first direction DR1 and a second direction DR2 are defined. The first direction DR1 is defined as a direction in which the first to sixteenth memory banks 311 to 326 are arranged. The second direction DR2 is defined as a direction perpendicular to or intersecting the first direction DR1 and in which the first to sixteenth memory banks 311 to 326 extend. The number of memory banks included in the nonvolatile memory device 300 is not limited.

[0045] Each of the first to sixteenth banks 311 to 326 includes a first partition B1 to a kth partition Bk (i.e., a first partition B1, a second partition B2, a third partition B3 to a k / 2th partition Bk / 2 to a (k-1)th partition Bk-1 and a kth partition Bk). Each of the first to kth partitions B1 to Bk may include a write driver and a memory cell corresponding to the write driver. The memory cell may be connected to the write driver through a word line. The first to sixteenth banks 311 to 326 may be arranged along a first direction DR1, respectively.

[0046] The first memory bank 311 to the sixteenth memory bank 326 may further include the first transmission element 351 to the sixteenth transmission element 366, respectively. For example, the first memory bank 311 includes the first transmission element 351, the second memory bank 312 includes the second transmission element 352, the third memory bank 313 includes the third transmission element 353, the fifteenth memory bank 325 includes the fifteenth transmission element 365, and the sixteenth memory bank 326 includes the sixteenth transmission element 366. Each of the first transmission element 351 to the sixteenth transmission element 366 receives a programming current from the programming current generator 340. The programming currents received by the first transmission element 351 to the sixteenth transmission element 366 may be different from each other. That is, the first programming current received by the first transmission element 351 may be different from the second programming current received by the second transmission element 352. To this end, the first transmission element 351 to the sixteenth transmission element 366 may receive the programming current through different lines.

[0047] Since the first memory bank 311 to the sixteenth memory bank 326 include independent transmission elements, respectively, a programming current optimized according to the memory bank position can be provided to the write driver. The optimized programming current can be a current that allows data to be stored without error for all programming states when a write operation is performed on any selected memory cell included in the memory bank. The performance of the write driver may vary with the memory bank position.

[0048] The degree of degradation due to the manufacturing process, the electrical signal provided to the memory cell, and the use of the memory cell may vary with the memory cell location. As the distance between the memory cells increases, the difference in characteristics of the elements included in the respective memory cells may increase, thereby causing an increase in the difference between the optimized programming currents. In addition, since one memory cell is located based on Figure 1 After the bank address BA of the memory bank is selected, the operation is performed, so the characteristic difference between the elements (e.g., write driver) in the memory bank can be smaller than the difference between the element characteristics of different memory banks. The characteristic difference may depend on the retention time, temperature, the number of program / erase cycles, or the transmission path of the programming current of each memory bank, or the degree of variation of the power supply voltage provided to the write driver.

[0049] The first transmission element 351 to the sixteenth transmission element 366 are formed in the memory body center area BCA. The memory body center area BCA may include an area arranged at the center of the first memory body 311 to the sixteenth memory body 326 relative to the second direction DR2. For example, the first partition B1 to the k / 2 partition Bk / 2 (first memory area) of the memory body are formed on one side of the memory body center area BCA, and the (k / 2+1)th partition (not shown) to the kth partition Bk (second memory area) of the memory body are formed on the opposite side of the memory body center area BCA. Each of the first memory area and the second memory area may include "k / 2" partitions. The memory body center area BCA may be defined between the first memory area and the second memory area.

[0050] Since the first transmission element 351 to the sixteenth transmission element 366 are formed in the memory body center area BCA, the programming current can be provided to the write driver included in each of the first partition B1 to the kth partition Bk through the optimized transmission path. The write driver connected to one of the first transmission element 351 to the sixteenth transmission element 366 can mirror the programming current so that the programming current is supplied to the selected memory cell. The distance between the transmission element formed in the memory body center area BCA and the write driver can be reduced, so the current mirroring characteristic can be improved. That is, the accuracy and reliability of the write operation can be improved, and the error with respect to the write operation can be reduced.

[0051] The programming current generator 340 may be disposed on the periphery of the nonvolatile memory device 300. The programming current generator 340 may generate first to sixteenth programming currents respectively optimized for the first to sixteenth memory banks 311 to 326. The first to sixteenth programming currents may be supplied to the first to sixteenth transmission elements 351 to 366 through different paths, respectively. The programming current generator 340 may be located adjacent to the memory bank center area BCA.

[0052] Although not in Figure 4 , but the nonvolatile memory device 300 may also include Figure 1 The address buffer 120, the command buffer 130, and the control logic circuit 150 in the embodiment of the present invention are shown in FIG. 1 . For example, the address buffer 120, the command buffer 130, and the control logic circuit 150 may be located in the peripheral area (or peripheral circuit). Figure 4 However, each of the first memory bank 311 to the sixteenth memory bank 326 may also include Figure 2 The row decoder 220 and the column decoder 250 are provided. For example, the row decoder 220 may be located in the memory bank center area BCA. For example, the column decoder 250 may be located adjacent to the first to k-th partitions B1 to Bk along the first direction DR1, or may be located in the memory bank center area BCA.

[0053] Figure 5 Show Figure 4 A diagram of a memory bank array. Figure 5 , the memory bank array 310 includes a first memory bank 311 to a sixteenth memory bank 326. The first memory bank 311 to the sixteenth memory bank 326 correspond to Figure 4 The first memory bank 311 to the sixteenth memory bank 326. For convenience, reference will be made to Figure 4 Reference Number / Description of Symbol Figure 5 .

[0054] The first to sixteenth memory banks 311 to 326 may include first to sixteenth transmission elements 351 to 366, respectively. The first to sixteenth transmission elements 351 to 366 correspond to Figure 4 Each of the first to sixteenth transmission elements 351 to 366 receives a corresponding programming current of the first to sixteenth programming currents Ib1 to Ib16 (i.e., the programming currents Ib1, Ib2, Ib3 to Ib15, and Ib16 as shown). The first to sixteenth transmission elements 351 to 366 may be formed at a reference position. Figure 4 The described memory bank center area BCA.

[0055] The first to sixteenth transmission elements 351 to 366 include first to sixteenth mirror source transistors Tb1 to Tb16, respectively (i.e., mirror source transistors Tb1, Tb2, Tb3 to Tb15 and Tb16 as shown), each of which transmits a received programming current to a selected memory cell by mirroring. Each of the first to sixteenth mirror source transistors Tb1 to Tb16 includes: a first terminal connected to receive a corresponding programming current of the first to sixteenth programming currents Ib1 to Ib16; a second terminal connected to receive a power supply voltage Vneg; and a gate terminal connected to the first terminal.

[0056] Each of the first memory bank 311 to the sixteenth memory bank 326 includes a mirror source transistor and a mirror transistor. For example, the first memory bank 311 may include a first mirror source transistor Tb1 and a first mirror transistor T11 to a kth mirror transistor T1k (i.e., mirror transistors T11, T12 to T1k / 2 to T1k-1 and T1k as shown). Here, "k" may correspond to the number of bays or write drivers of each memory bank. One mirror transistor may be included in one write driver.

[0057] Each of the first mirror transistor T11 to the kth mirror transistor T1k, ..., T161 to T16k includes: a first terminal for transmitting a mirrored programming current to a memory cell; a second terminal for receiving a power supply voltage in a write operation; and a gate terminal connected to the gate terminal of a corresponding mirror source transistor among the first mirror source transistor Tb1 to the sixteenth mirror source transistor Tb16. The mirror source transistor and the mirror transistor may form a current mirror structure together. The mirror transistors (e.g., T11 to T1k, ..., or T161 to T16K) included in one memory bank may be connected in parallel to each other to perform a write operation on a selected partition. Since the first mirror source transistor Tb1 to the sixteenth mirror source transistor Tb16 are arranged in the memory bank center area BCA, each of the first mirror source transistor Tb1 to the sixteenth mirror source transistor Tb16 may be located adjacent to the mirror source transistor. Therefore, noise in the process of transmitting the programming current in order to mirror the programming current may be reduced.

[0058] Specifically, the mirrored programming current may depend on transistor characteristics (such as the channel width, channel length, and threshold voltage of each of the mirror transistor and the mirror source transistor). In this way, when the mirror source transistor and the mirror transistor have the same characteristics, the programming current may be accurately mirrored. Since a memory-based operation is performed, a characteristic variation of the mirror transistor may have a given correlation with respect to the memory bank. Since the mirror source transistor is provided for each memory bank, an optimized programming current may be transmitted for each memory bank, and therefore, errors regarding write operations may be reduced.

[0059] In addition, when the power supply voltage Vneg supplied to the mirror source transistor is the same as the power supply voltage supplied to the mirror transistor, the programming current can be accurately mirrored. As the distance between the mirror transistor and the mirror source transistor increases, the variation of the power supply voltage can increase. Since the mirror source transistor is disposed in the memory center area BCA, the difference between the power supply voltage Vneg supplied to the mirror source transistor and the power supply voltage supplied to the mirror transistor can be minimized.

[0060] Figure 5 The mirror transistor and the mirror source transistor arranged in a simple current mirror circuit are shown, but the inventive concept is not limited thereto. For example, various circuit structures for current mirroring can be provided. For example, a transistor can be connected in series to each of the mirror source transistor and the mirror transistor so as to form a current mirror circuit of a cascade structure. For example, a resistor element can be connected in series to each of the mirror source transistor and the mirror transistor so as to form a current mirror circuit for source degeneration.

[0061] Figure 6 Show Figure 4 The circuit diagram of the programming current generator. Figure 6 , the programming current generator 340 includes a reference current generator 341 and a current regulator 342 . Figure 6 The circuit diagram of can be understood as an exemplary circuit for providing various programming currents, and Figure 4 The circuit of the programming current generator 340 is not limited to Figure 6 .

[0062] The reference current generator 341 generates a reference current Iref. To this end, the reference current generator 341 may include an amplifier Amp, a reference transistor Tr, and a current source CS. The amplifier Amp includes: a first input terminal receiving a reference voltage Vref; a second input terminal receiving a feedback voltage; and an output terminal outputting a gate voltage based on a difference between the reference voltage Vref and the feedback voltage.

[0063] The reference transistor Tr is configured to transmit the reference current Iref to the current regulator 342 through a current mirror. The reference transistor Tr includes a first terminal receiving a first voltage VH1, a second terminal connected to the second terminal of the amplifier Amp and transmitting a feedback voltage, and a gate terminal receiving a gate voltage. The reference current Iref may flow between the first terminal and the second terminal of the reference transistor Tr based on the gate voltage, and the feedback voltage may be determined.

[0064] The current source CS may output a reference current Iref. When the channel of the reference transistor Tr is established based on the gate voltage, the reference current Iref may flow through the reference transistor Tr, and the reference current Iref may be transmitted to the current regulator 342 through the current mirror. The current source CS includes: a first terminal connected to the second terminal of the reference transistor Tr and the second input terminal of the amplifier Amp; and a second terminal connected to the ground.

[0065] The current regulator 342 includes a first current regulating transistor Ta1 to a sixteenth current regulating transistor Ta16 (ie, current regulating transistors Ta1, Ta2, Ta3 to Ta15, and Ta16 as shown). The number of current regulating transistors may be Figure 4 or Figure 5 The number of transmission elements is the same as (16). Figure 4 and Figure 5 In an embodiment of the present invention, the number of current regulating transistors may correspond to the number of memory banks. The first current regulating transistor Ta1 to the sixteenth current regulating transistor Ta16 may mirror the reference current Iref. Each of the first current regulating transistor Ta1 to the sixteenth current regulating transistor Ta16 includes: a first terminal for receiving a second voltage VH2; a second terminal for outputting a corresponding programming current from the first programming current Ib1 to the sixteenth programming current Ib16 to the Figure 5 and a gate terminal connected to the gate terminal of the reference transistor Tr. For example, the second voltage VH2 may be the same as the first voltage VH1 to provide a current mirror.

[0066] The first current regulating transistor Ta1 to the sixteenth current regulating transistor Ta16 may regulate the mirrored reference current Iref to generate the first programming current Ib1 to the sixteenth programming current Ib16. The first programming current Ib1 to the sixteenth programming current Ib16 may be regulated based on the first code TC1 to the sixteenth code TC16 (i.e., codes TC1, TC2, TC3 to TC15, and TC16), respectively. The first code TC1 to the sixteenth code TC16 are provided to the first current regulating transistor Ta1 to the sixteenth current regulating transistor Ta16, respectively. The first code TC1 to the sixteenth code TC16 may be provided from an external device and may be included in Figure 1of the data signal DQ.

[0067] Each of the first current regulating transistor Ta1 to the sixteenth current regulating transistor Ta16 may be a variable transistor. For example, each of the first current regulating transistor Ta1 to the sixteenth current regulating transistor Ta16 may include a reference mirror transistor connected to the gate terminal of the reference transistor Tr to mirror the reference current Iref, and a variable element connected in series with the reference mirror transistor, the variable element adjusting the level of the mirror current based on the code. For example, the variable element may be a variable resistor whose resistance value varies with the code. For example, the variable element may be a transistor including a gate terminal for receiving the code and connected in series with the reference mirror transistor.

[0068] Each of the first to sixteenth codes TC1 to TC16 may be generated based on data to be written to a corresponding memory bank. For example, each of the first to sixteenth codes TC1 to TC16 may be generated based on binary data to be written. For example, each of the first to sixteenth codes TC1 to TC16 may have a voltage level depending on the size of the data value to be written. The levels of the first to sixteenth programming currents Ib1 to Ib16 may be adjusted based on the voltage levels of the first to sixteenth codes TC1 to TC16.

[0069] Each of the first to sixteenth codes TC1 to TC16 may be generated in consideration of a characteristic change according to a location of a corresponding memory bank. For example, even if the same data value may be intended to be written to each memory bank, the first to sixteenth codes TC1 to TC16 may have different levels in consideration of a change in the power supply voltage Vneg of each memory bank. For example, in the case where the distribution range of the programming current of the first memory bank 311 is formed to be higher than the distribution range of the programming current of the second memory bank 312, the first programming current Ib1 generated based on the first code TC1 may have a higher level than the second programming current Ib2 generated based on the second code TC2.

[0070] Figure 7 A circuit diagram of a programming current generator including a pass element is shown. Figure 7 The programming current generator 40 includes a reference current generator 41, a current regulator 42 and a transmission circuit 43. The reference current generator 41 includes an amplifier Amp for generating a reference current Iref, a reference transistor Tr and a current source CS. The structure of the reference current generator 41 can be similar to Figure 6 The structure of the reference current generator 341 is the same.

[0071] The current regulator 42 may mirror the reference current Iref to generate the programming current IPGM. To this end, the current regulator 42 may include a current regulating transistor Ta1. Figure 6 Differently, in the case where the separate transmission element is not located in the memory bank array 310 (such as in Figure 7 middle), Figure 7 The current regulator 42 in the embodiment can generate a programming current IPGM. The current regulating transistor Ta1 can regulate the mirrored reference current Iref based on the code TC1. The programming current IPGM is provided to the transmission circuit 43.

[0072] The transmission circuit 43 can transmit the programming current IPGM to the write driver of the selected memory bank through current mirroring. To this end, the transmission circuit 43 may include a mirror source transistor Ts and a buffer BF. The mirror source transistor Ts corresponds to Figure 5 The mirror source transistor Ts includes: a first terminal receiving the programming current IPGM; a second terminal receiving the power supply voltage Vneg; and a gate terminal connected to the first terminal.

[0073] The buffer BF is connected between the gate terminal of the mirror source transistor Ts and Figure 5 The buffer BF may temporarily store a program voltage VPGM generated based on a program current IPGM flowing through the mirror source transistor Ts, and may output the program voltage VPGM to the mirror transistor.

[0074] By using the reference Figure 7 In the case where a programming current IPGM generated by the programming current generator 40 described above performs a write operation on a plurality of memory banks, a loading time or a noise recovery time increases. Therefore, a buffer BF for performing a write operation is required. In other words, in accordance with Figures 4 to 6 In the nonvolatile memory device 300 of the embodiment, since the pass element for current mirroring is located in the bank center region of each bank, a separate buffer BF may not be required.

[0075] In addition, by using the reference Figure 7 In the case where one programming current IPGM generated by the described programming current generator 40 performs a write operation on multiple storage bodies, since a write operation is performed on the entire storage body array by one programming current, it is difficult to cope with characteristic changes according to the storage body position. The optimized programming current may vary with the storage body position. Therefore, in the case of performing a write operation based on one programming current IPGM, an error may occur at a specific storage body. For example, the data value to be written and the data value stored may be different, or the data may not be stored in the memory cell targeted for the write operation.

[0076] Figure 8 Shown in Figure 1 and Figure 2Schematic diagram of an exemplary structure of a nonvolatile memory device described in . Figure 8 , the nonvolatile memory device 400 includes a first memory bank 411 to a sixteenth memory bank 426 (i.e., memory banks 411, 412, 413 to 418 to 425 and 426 as shown) and a programming current generator 440. Each of the first memory bank 411 to the sixteenth memory bank 426 includes a first partition B1 to a kth partition Bk, wherein one write driver (mirror transistor) is provided in each partition. The first transmission element 451 to the sixteenth transmission element 466 are formed in the memory bank center area BCA and correspond to the first memory bank 411 to the sixteenth memory bank 426.

[0077] The nonvolatile memory device 400 includes first to fifteenth switches SW1 to SW15 (i.e., switches SW1, SW2 to SW7 to SW14 and SW15 as shown). The first to fifteenth switches SW1 to SW15 are located in the memory body center area BCA. Each of the first to fifteenth switches SW1 to SW15 is connected between two adjacent transmission elements among the first to sixteenth transmission elements 451 to 466 (or connected to two adjacent transmission elements among the first to sixteenth transmission elements 451 to 466). For example, the first switch SW1 is connected between the first transmission element 451 and the second transmission element 452 (or connected to the first transmission element 451 and the second transmission element 452), and the fifteenth switch SW15 is connected between the fifteenth transmission element 465 and the sixteenth transmission element 466 (or connected to the fifteenth transmission element 465 and the sixteenth transmission element 466). Each of the first to fifteenth switches SW1 to SW15 may be connected to a gate terminal of a mirror source transistor included in each of the two adjacent transmission elements (the first terminal of the mirror source transistor is connected to the gate terminal (for example, see Figure 5 )).

[0078] In the standby mode, the first switch SW1 to the fifteenth switch SW15 are closed. For example, the first switch SW1 to the fifteenth switch SW15 can be closed by Figure 1The standby mode is defined as an operation mode before or after storing data in order to perform a write operation. In the standby mode, the programming current generator 440 can generate a standby current by using a current regulating transistor corresponding to a transmission element. For example, the current regulating transistor for generating the standby current may correspond to the eighth transmission element 458 included in the storage body (e.g., the eighth storage body 418), which is centered with respect to the first direction DR1. The standby current can be provided to the first transmission element 451 to the sixteenth transmission element 466 through the first switch SW1 to the fifteenth switch SW15 that have been closed. Therefore, the standby current can be provided to the first storage body 411 to the sixteenth storage body 426 through the first switch SW1 to the fifteenth switch SW15 that have been closed.

[0079] In the active mode, the first to fifteenth switches SW1 to SW15 are turned off. For example, the first to fifteenth switches SW1 to SW15 can be turned on by Figure 1 The active mode may be defined as an operation mode in which a write operation is performed. In the active mode, the programming current generator 440 may generate the first to sixteenth programming currents by using the first to sixteenth current regulating transistors. In the case where the first to fifteenth switches SW1 to SW15 are disconnected, the nonvolatile memory device 400 may have the same Figure 4 The nonvolatile memory device 300 has substantially the same circuit structure. The first to sixteenth programming currents may be provided to the first to sixteenth memory banks 411 to 426, respectively.

[0080] because Figure 4 The nonvolatile memory device 300 reduces errors in write operations and transmits programming current and standby current through 16 lines, so power consumption in standby mode may increase. On the other hand, since Figure 8 In the nonvolatile memory device 400, the standby current is generated in the standby mode by using the current regulating transistor and the first to fifteenth switches SW15, so the power consumption of the nonvolatile memory device 400 can be reduced. In addition, since the standby current is provided to all of the first to sixteenth memory banks 411 to 426, the wake-up time taken to change to the active mode does not increase.

[0081] Fig. 9 Show Figure 8 A flowchart of a method for operating a non-volatile memory system. Fig. 9 , which can be found in the reference Figure 8 The nonvolatile memory device 400 described herein performs an operation method of the nonvolatile memory device. For ease of description, reference will be made to Figure 8 Reference Number / Description of Symbol Fig. 9 Flowchart of the process.

[0082] In operation S110, it is determined whether the nonvolatile memory device 400 is operating in the active mode. Figure 1 The control logic circuit 150 makes this determination. In the case where it is determined that the nonvolatile memory device 400 operates in the active mode (“Yes” in S110), for example, in the case of performing a write operation, operations S150 and S160 are performed. In the case where it is determined that the nonvolatile memory device 400 does not operate in the active mode (“No” in S110), for example, in the case where it is determined that the nonvolatile memory device 400 operates in the standby mode, operations S120 to S140 are performed.

[0083] In operation S120, the nonvolatile memory device 400 operates in a standby mode. The programming current generator 440 outputs a standby current using one of the current regulating transistors. For example, the current regulating transistor corresponding to the eighth transmission element 458 may be turned on, and the remaining current regulating transistors may be turned off. The standby current may be provided to the eighth transmission element 458 through the turned-on current regulating transistor.

[0084] In operation S130, the first to fifteenth switches SW1 to SW15 are closed. For example, the first to fifteenth switches SW1 to SW15 may be closed by Figure 1 The nonvolatile memory device 400 is closed by a switch signal received by the control logic circuit 150. Alternatively, the nonvolatile memory device 400 may receive a switch signal from an external device.

[0085] In operation S140, the standby current may be provided to the first memory bank 411 to the sixteenth memory bank 426 through the first transmission element 451 to the sixteenth transmission element 466. The standby current may be provided to the first memory bank 411 to the sixteenth memory bank 426 through a current regulating transistor outputting the standby current. The standby current may be provided to the first memory bank 411 to the sixteenth memory bank 426 through the closed first switch SW1 to the fifteenth switch SW15. In the case of being in the standby mode, Fig. 9 Unlike that shown in , after performing operation S140, the process returns to operation S110 where a determination is made as to whether the nonvolatile memory device 400 is operating in the active mode.

[0086] In operation S150, the nonvolatile memory device 400 operates in an active mode. The first to fifteenth switches SW1 to SW15 are turned off. For example, the first to fifteenth switches SW1 to SW15 may be turned off by Figure 1The nonvolatile memory device 400 is disconnected by a switch signal received by the control logic circuit 150. Alternatively, the nonvolatile memory device 400 may receive a switch signal from an external device.

[0087] In operation S160, the first to sixteenth programming currents are provided to the first to sixteenth memory banks 411 to 426, respectively. The programming current generator 440 may be configured to generate a plurality of currents through the first to sixteenth current regulating transistors (see FIG. Figure 6 ) generates the first programming current to the sixteenth programming current. The first programming current to the sixteenth programming current can be provided to the first transmission element 451 to the sixteenth transmission element 466 through 16 lines arranged in parallel. In the case of being in the active mode, Fig. 9 Unlike that shown in , after performing operation S160, the process returns to operation S110 where a determination is made as to whether the nonvolatile memory device 400 is operating in the active mode.

[0088] Fig.10 Shown in Figure 1 and Figure 2 Schematic diagram of an exemplary structure of a nonvolatile memory device described in . Fig.10 , the nonvolatile memory device 500 includes first to sixteenth memory banks 511 to 526 and a programming current generator 540. Each of the first to sixteenth memory banks 511 to 526 includes first to kth partitions B1 to Bk, and one write driver (mirror transistor) is provided in each partition.

[0089] The nonvolatile memory device 500 includes first to fourth mirror source transistors Tz1, Tz2, Tz3, and Tz4 (first to fourth transfer elements) in a bank center area BCA. Figure 4 Unlike the non-volatile memory device 300, the number of pass elements or mirror source transistors does not correspond to the number of memory banks. Fig.10In the case of the non-volatile memory device 500, one mirror source transistor is located at a group for each four memory banks. For example, the first mirror source transistor Tz1 is connected to the memory banks 511, 512, 513 and 514, the second mirror source transistor Tz2 is connected to the memory banks 515, 516, 517 and 518, the third mirror source transistor Tz3 is connected to the memory banks 519, 520, 521 and 522, and the fourth mirror source transistor Tz4 is connected to the memory banks 523, 524, 525 and 526. The four memory banks are defined as one area and share one mirror source transistor. The 16 memory banks are divided into the first area Zone1 to the fourth area Zone4, each area including 4 memory banks. It should be understood that each of the first mirror source transistor Tz1 to the fourth mirror source transistor Tz4 is included in one of the four memory banks.

[0090] Each of the first to fourth mirror source transistors Tz1 to Tz4 can transmit a corresponding programming current among the first to fourth programming currents to a memory cell selected from four memory banks. Each of the first to fourth mirror source transistors Tz1 to Tz4 includes: a first terminal for receiving a corresponding programming current among the first to fourth programming currents; a second terminal for receiving a power supply voltage Vneg; and a gate terminal connected to the first terminal. The gate terminal can be connected to the gate terminals of the mirror transistors included in the four memory banks, and can be configured to allow the four memory banks to mirror the programming current.

[0091] The width of the memory center area BCA may depend on the number of transmission elements or mirror source transistors and the number of lines used to transmit programming current. As the number of transmission elements or mirror source transistors increases, the width of the memory center area BCA increases. Fig.10 Since a plurality of memory banks share one mirror source transistor, the width of the memory bank center area BCA can be reduced. As a result, the width of the nonvolatile memory device 500 is reduced.

[0092] In addition, adjacent memory banks may have similar programming current distribution ranges. When the distance between memory banks becomes closer, characteristic differences according to changes in process or power supply voltage Vneg may be similar. Therefore, even if adjacent memory banks share mirror source transistors, errors in write operations may be reduced compared to the case where all memory banks are programmed using one mirror source transistor.

[0093] The programming current generator 540 may generate the first programming current to the fourth programming current based on the reference current. The programming current generator 540 may generate the first programming current to the fourth programming current by using four current regulating transistors. In this case, four codes may be used to generate the first programming current to the fourth programming current. Therefore, the number of transistors included in the programming current generator 540 may be reduced. In addition, since the number of lines for transmitting the programming current is reduced, the width of the memory center area BCA may be reduced.

[0094] Although not in Fig.10 shown in, but with Figure 8 Similar to the nonvolatile memory device 400, the nonvolatile memory device 500 may further include a switch for considering the operation in the standby mode and the active mode. Figure 5 As described above, the transmission element of the nonvolatile memory device 500 may be implemented by a current mirror circuit of a cascade structure or a source negative feedback structure.

[0095] Fig.11 A diagram showing an exemplary structure of a nonvolatile memory device according to an embodiment of the inventive concept. Fig.11 , the nonvolatile memory device 600 includes a first layer 600_1, a second layer 600_2, a programming current generator 640, and a plurality of transmission elements 651 and 652. The second layer 600_2 may be located adjacent to the first layer 600_1 along a third direction DR3 perpendicular to the first direction DR1 and the second direction DR2. For ease of description, the first layer 600_1 and the second layer 600_2 are shown as being separated from each other, but the first layer 600_1 and the second layer 600_2 may contact each other. For example, the first layer 600_1 and the second layer 600_2 may be stacked on one semiconductor substrate.

[0096] The first layer 600_1 may include a plurality of memory banks 611_1 and 612_1 and other memory banks. The plurality of memory banks 611_1 and 612_1 may be arranged along a first direction DR1. The plurality of transmission elements 651 and 652 formed in the memory bank center area BCA may correspond to the plurality of memory banks 611_1 and 612_1, respectively. The structure of the first layer 600_1 may be similar to Figure 4 The structures of the nonvolatile memory devices 300 are basically the same.

[0097] The second layer 600_2 may include a plurality of banks 611_2 and 612_2 and other banks. The plurality of banks 611_2 and 612_2 may be arranged along the first direction DR1. The plurality of transmission elements 651 and 652 formed in the bank center area BCA may correspond to the plurality of banks 611_2 and 612_2, respectively.

[0098] For example, a word line (not shown) connected to the first layer 600_1 may be different from a word line (not shown) connected to the second layer 600_2. However, a bit line (not shown) may be shared between the first layer 600_1 and the second layer 600_2. The bit line is provided between the first layer 600_1 and the second layer 600_2. A write driver may be shared between the first layer 600_1 and the second layer 600_2. In this way, a plurality of transmission elements 651 and 652 may be shared between the first layer 600_1 and the second layer 600_2. For example, a programming current may be provided to a first memory cell 611_1 of the first layer 600_1 and a first memory cell 611_2 of the second layer 600_2 by a first transmission element 651.

[0099] The programming current generator 640 may be disposed on the periphery of the nonvolatile memory device 600. The programming current used by the plurality of memory banks 611_1 and 612_1 included in the first layer 600_1 to perform a write operation may be different from the programming current used by the plurality of memory banks 611_2 and 612_2 included in the second layer 600_2 to perform a write operation. The programming current may be generated by one programming current generator 640. Figure 6 The code is used to optimize the programming current of a selected memory bank among the memory banks sharing a pass element.

[0100] Although not in Fig.11 shown in, but with Figure 8 Similar to the nonvolatile memory device 400, the nonvolatile memory device 600 may further include a switch for operating in consideration of the standby mode and the active mode. For example, the nonvolatile memory device 600 may be implemented in such a manner that: Fig.10 Similar to the nonvolatile memory device 500, adjacent memory banks share a transmission element. Figure 5 As described above, the transmission element of the nonvolatile memory device 600 may be implemented by a simple current mirror circuit or a current mirror circuit with a cascade structure or a source negative feedback structure.

[0101] Fig.12 FIG. 1 is a block diagram showing a computing device according to an embodiment of the inventive concept. Fig.12 , the computing device 1000 includes a processor 1100, a memory controller 1200, a main memory 1300, a system interconnect 1400, a storage device 1500, a user interface 1600, and a modem 1700. The computing device 1000 may be implemented with one of various computing devices such as a desktop computer, a notebook computer, a data server, an application server, a smart phone, a smart tablet, etc.

[0102] The processor 1100 may be a central processing unit (CPU) or an application processor (AP) that performs various operations. The processor 1100 controls various components of the computing device 1000 to perform a write operation, a read operation, or any other operation. For example, the processor 1100 may access the main memory 1300 by using the memory controller 1200.

[0103] The memory controller 1200 may control the main memory 1300 to perform a set operation, a reset operation, or a read operation under the control of the processor 1100. For example, the memory controller 1200 may receive a write command from the processor 1100, and may control the main memory 1300 to perform a write operation on the data signal DQ. For example, the memory controller 1200 may generate a code TC for generating a programming current optimized according to a bank location.

[0104] The main memory 1300 may include reference Figures 1 to 11 One of the nonvolatile memory devices described. The main memory 1300 may receive an address ADDR, a command CMD, and control information CTRL from the memory controller 1200. The main memory 1300 may receive a code TC for generating a plurality of programming currents from the memory controller 1200. A programming current generator included in the main memory 1300 may include a plurality of current regulating transistors, and the plurality of current regulating transistors may generate a plurality of programming currents based on the code TC. The main memory 1300 may exchange a data signal DQ with the memory controller 1200. The main memory 1300 may include a phase change memory cell.

[0105] The system interconnect 1400 may provide a channel between components of the computing device 1000. The system interconnect 1400 may be implemented according to one of various standards, such as Peripheral Component Interconnect Express (PCIe) and Advanced Microcontroller Bus Architecture (AMBA).

[0106] The storage device 1500 may be used as an auxiliary memory of the computing device 1000. The storage device 1500 may have a slower access speed than the main memory 1300, and may have a larger storage capacity than the main memory 1300. The storage device 1500 may include, for example, a hard disk drive (HDD), a solid state drive (SSD), a portable memory, etc.

[0107] The user interface 1600 may exchange information with the user. The user interface 1600 may include a user input interface (such as a keyboard, mouse, touch panel, microphone, or other device for receiving information from the user) and a user output interface (such as a monitor, speaker, motor, or other device for providing information to the user).

[0108] The modem 1700 is configured to perform wired or wireless communication with an external device. The modem 1700 may be configured to implement at least one of various standards such as Long Term Evolution (LTE), Ethernet, Wireless Fidelity (Wi-Fi), and Bluetooth. In an embodiment, the modem 1700 may be included in the processor 1100.

[0109] According to the nonvolatile memory device of the inventive concept, errors in a write operation can be reduced by locating a transfer element for mirroring a programming current in a central region of a memory bank.

[0110] While the inventive concepts have been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the inventive concepts as set forth in the appended claims.

Claims

1. A non-volatile memory device, comprising: a first memory bank including a first memory cell array and a first pass element, wherein the first memory cell array includes phase change memory cells storing data based on a first programming current, wherein the first pass element is configured to transfer the first programming current to the first memory cell array through current mirroring; a programming current generator configured to generate a first programming current based on a reference current; and a second memory bank including a second memory cell array and a second transmission element, the second memory cell array storing data based on a second programming current, the second transmission element being configured to transmit the second programming current to the second memory cell array, The programming current generator is further configured to generate a second programming current based on the reference current. Wherein, the programming current generator includes: a reference current generator configured to generate a reference current, and The current regulator is configured to generate a first programming current based on a reference current and a first code, and to generate a second programming current based on the reference current and a second code.

2. The nonvolatile memory device according to claim 1, wherein: The first pass element includes a mirror source transistor, The mirror source transistor includes a first terminal connected to receive a first programming current, a second terminal connected to receive a power supply voltage, and a gate terminal connected to the first terminal.

3. The nonvolatile memory device according to claim 1, wherein: The first memory bank also includes a plurality of write drivers configured to mirror a first programming current from the first pass element to program selected phase change memory cells of the first memory cell array.

4. The nonvolatile memory device according to claim 1, wherein: The first memory bank is divided into: a first memory region, wherein some phase change memory cells of the first memory cell array are arranged in the first memory region; a second memory region, in which the remaining phase-change memory cells of the first memory cell array except for the some phase-change memory cells are arranged; as well as a memory bank central region, inserted between the first memory region and the second memory region, The first transmission element is located in the central area of ​​the storage body.

5. The nonvolatile memory device according to claim 1, wherein: The current regulator includes: a first current regulating transistor connected to the reference current generator and configured to: mirror the reference current to provide a first mirror reference current, and regulate a level of the first mirror reference current based on a first code to provide a first programming current; and The second current regulating transistor is connected to the reference current generator and is configured to mirror the reference current to provide a second mirror reference current and to adjust a level of the second mirror reference current based on a second code to provide a second programming current.

6. The nonvolatile memory device according to claim 1, further comprising: A switch is configured to electrically connect the first pass element and the second pass element in a standby mode and disconnect the first pass element from the second pass element in an active mode during a programming operation of the first memory bank and the second memory bank.

7. The nonvolatile memory device according to claim 6, wherein: The programming current generator is configured to output a standby current to one of the first pass element and the second pass element in the standby mode, and The programming current generator is configured to output a first programming current to the first transmission element and a second programming current to the second transmission element in an active mode.

8. The nonvolatile memory device according to claim 1, wherein: The first memory bank and the second memory bank are arranged along a first direction, The first memory bank further includes: a plurality of first write drivers configured to mirror the first programming current from the first transmission element to program the selected phase change memory cells of the first memory cell array, the plurality of first write drivers being arranged along a second direction intersecting the first direction, and The second storage body includes: a plurality of second write drivers configured to mirror a second programming current from a second transmission element to program selected phase change memory cells of a second memory cell array, and the plurality of second write drivers are arranged along a second direction.

9. The nonvolatile memory device according to claim 8, wherein: The first transmission element is located adjacent to the plurality of first write drivers along the second direction, and The second transmission element is located adjacent to the plurality of second write drivers along the second direction.

10. The nonvolatile memory device according to claim 1, further comprising: A fourth memory bank includes a fourth memory cell array storing data based on the first programming current transmitted from the first transmission element.

11. The nonvolatile memory device according to claim 10, further comprising: a third memory bank including a third memory cell array storing data based on a third programming current and a third transmission element, the third transmission element being configured to transmit the third programming current to the third memory cell array, and Wherein, the programming current generator is further configured to generate a third programming current based on the reference current.

12. A non-volatile memory device comprising: The peripheral circuit includes a programming current generator configured to generate a first programming current based on a reference current; a first memory bank configured to store data based on a first programming current, Wherein, the first storage body includes: a first memory cell array, a first pass element configured to receive a first programming current from a programming current generator, and a first write driver configured to mirror the first programming current from the first pass element and perform a write operation on a selected memory cell of the first memory cell array; and a second memory bank, inserted between the first memory bank and the peripheral circuit, Wherein, the second storage body includes: a second memory cell array, a second pass element configured to receive a second programming current from the programming current generator, and The second write driver is configured to mirror the second programming current from the second pass element and perform a second write operation on the selected memory cell of the second memory cell array.

13. The nonvolatile memory device according to claim 12, wherein: The first memory bank also includes: a fourth write driver configured to mirror the first programming current from the first pass element and perform a fourth write operation on a second selected memory cell of the first memory cell array, The first transmission element is inserted between the first write driver and the fourth write driver.

14. The nonvolatile memory device according to claim 12, further comprising: a third memory bank inserted between the second memory bank and the peripheral circuit, Wherein, the third storage body includes: a third memory cell array; and The third write driver is configured to mirror the second programming current from the second pass element and perform a third write operation on the selected memory cell of the third memory cell array.

15. The nonvolatile memory device according to claim 12, wherein: The first memory bank is divided into: a first memory region, some memory cells of the first memory cell array being arranged in the first memory region; a second memory region, in which remaining memory cells of the first memory cell array except for the some memory cells are arranged; as well as a memory bank central region, inserted between the first memory region and the second memory region, The first transmission element is located in the central area of ​​the storage body.

16. A non-volatile memory device comprising: A first layer including a first memory bank that performs a write operation based on a first programming current; A second layer including a second memory bank that performs a write operation based on a second programming current, the second layer being located above the first layer; a programming current generator configured to generate a first programming current and a second programming current based on a reference current; a first pass element configured to transfer a first programming current received from a programming current generator to a first memory bank through a current mirror; as well as The second pass element is configured to transfer the second programming current received from the programming current generator to the second memory bank through a current mirror.

17. The nonvolatile memory device according to claim 16, wherein: The first layer also includes memory banks arranged along a first direction relative to the first memory bank, The second layer further includes storage bodies arranged along the first direction relative to the second storage bodies. wherein each of the first memory bank and the second memory bank extends along a second direction intersecting the first direction, and The first layer and the second layer are located adjacent to each other along a third direction intersecting the first direction and the second direction.

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