An ultra-low loss low-side ideal diode

Abstract

The present invention discloses an ultra-low loss low-end ideal diode, comprising a combination logic control circuit and a first NMOS tube, the combination logic control circuit comprising a second NMOS tube, a third NMOS tube, a first resistor and a second resistor, the drain of the first NMOS tube is connected to the source of the second NMOS tube and the negative electrode of the power supply, the source of the first NMOS tube is electrically connected to the source of the third NMOS tube, the gate of the first NMOS tube is electrically connected to the drain of the third NMOS tube, the gate of the second NMOS tube is connected to the drain of the second NMOS tube and the gate of the third NMOS tube, the drain of the second NMOS tube is connected to the positive electrode of the power supply through the first resistor, the drain of the third NMOS tube is connected to the positive electrode of the power supply through the second resistor, and the load is connected between the positive electrode of the power supply and the source of the first NMOS tube. The present invention has a backflow prevention function, can protect the previous stage circuit, has very low loss, simple circuit, and strong practicality.

Description

Technical Field

[0001] The invention relates to the technical field of power diodes, and in particular to an ultra-low loss low-end ideal diode. Background Art

[0002] Diodes have a unidirectional conduction characteristic and a backflow prevention function, and are being used more and more. In particular, Schottky diodes have a small voltage drop on the power supply connected in series, which is welcomed by more and more designers. Since the voltage drop of Schottky diodes is still greater than that of MOS tubes, for some voltage-sensitive circuits, MOS tubes with low impedance characteristics are more likely to be used to improve product reliability. Now there are many USB power switches (power distribution switches) with built-in backflow prevention functions, such as the MP62055 chip. Because when an external device is connected to the USB port of a computer, the device must not reverse the current into the VBus of the computer, otherwise it will burn the computer. At present, the Oring circuit is used in many occasions. Its function is to ensure that each single power supply is independent of each other and does not have a backflow phenomenon. It is most commonly used in current sharing circuits to meet different power requirements.

[0003] Therefore, an ideal diode with ultra-low loss is needed to further reduce the voltage drop and have the functions of preventing backflow and protecting the previous stage, so as to minimize the loss and extend the battery working time.

[0004] In addition, the technical implementation solutions closest to the present invention are as follows, but they all have certain shortcomings:

[0005] Diode solution: Since the diode has unidirectional conductivity, it is a natural Oring circuit. The most basic Oring circuit is to add a diode at the output end. Using a diode in series with the power supply makes the circuit simple, but its disadvantage is that the diode has a voltage drop of about 0.6V, and the voltage drop will cause power loss proportional to the input current. As the current increases, the voltage drop will also increase. For example, replacing it with a Schottky diode can reduce power, but the power loss is relatively large: Taking the Schottky diode SS54 as an example, the voltage drops corresponding to currents of 0.1A, 1A, 10A, and 20A are 0.3V, 0.4V, 0.85V, and 1.4V respectively, and the corresponding losses are 0.03W, 0.4W, 8.5W, and 28W respectively, which means that the greater the current passing through, the greater the loss. The disadvantage of the Schottky diode is the voltage drop, which is converted into current loss, and its static current loss is at least milliampere level.

[0006] MCU+PMOS tube solution: The circuit characteristics require an additional auxiliary voltage and microcontroller (MCU). The two AD channels of the MCU are used to collect the voltage of the drain (D pole) and source (S pole) of the PMOS tube, and the voltages of the two are compared to control the conduction and cutoff of the PMOS tube. The disadvantage is that the working current loss is at least in the milliampere level, which is very large, and an additional auxiliary voltage and MCU are required, so the solution cost is high.

[0007] NPN pair + NMOS solution: The circuit characteristics require an additional auxiliary voltage. Use two NPN tubes from the same manufacturer and the same batch to ensure that the two collector voltages are basically equal, or preferably use two NPN transistor pairs packaged together, so that they are almost equal, thereby ensuring proper switching and anti-backflow functions. The disadvantage is that the bias resistance of the transistor is in the kilo-ohm level, and the static operating current loss is at least in the milliampere level. The current loss is large, and an additional auxiliary voltage is required.

[0008] PNP pair + PMOS solution: Using two PNP transistors packaged together can ensure that the two collectors are almost equal, thereby ensuring proper switching and anti-backflow functions. The disadvantage is that the bias resistance of the transistor is in the kilo-ohm level, and the static operating current loss is at least in the milliampere level, which is very large.

[0009] Ideal diode solution: Using the chip LTC4413, Linear Technology has launched the dual-channel ideal diode LTC4413, which is specially designed to reduce heat, voltage drop and board area and extend battery life. This device is very suitable for applications that require an ideal diode "OR" function to achieve load sharing or automatic switching between two input power supplies. The LTC4413 has a low forward voltage of 80mV and 210mV at 500mA and 2A respectively, and a leakage current of only 1uA, which is a great improvement over the discrete diode "OR" solution. The LTC4413 contains two 100mOhm P-channel MOSFETs. The maximum forward current of each MOSFET is limited to a constant 2.6A, and the internal thermal limiting circuit can protect the device in the event of a fault. Disadvantages: The maximum output current is 1A, the quiescent current is less than 40μA, and there is a reverse current of less than 1μA that will flow from the output terminal OUT to the input terminal IN; the 9uA open-drain STAT pin indicates the conduction state of the selected channel and can be used to drive an external P-channel MOSFET to control the third backup power supply; LTC4413 is expensive.

[0010] PMOS pair + power PMOS solution: Apply for invention patent (an ultra-low loss ideal diode, application number: CN201810920906.3), use dual PMOS pair to control logic circuit to control power PMOS tube, which has very low insertion loss and is suitable for ultra-low power applications. It can be used as a high-end (used between the load and the positive pole of the power supply) ultra-low power ideal power diode. However, due to the large channel conduction resistance of PMOS tube, high price, slow speed, few replacement types, etc., NMOS tubes are usually used in low-end (used between the load and the negative pole of the power supply) applications.

[0011] NMOS tubes use electrons as "majority carriers". Compared with the "majority carrier" holes of PMOS tubes, electrons have higher mobility. At the same physical density, NMOS has higher transconductance and lower on-resistance than PMOS. The on-resistance of NMOS is generally 1 / 3 to 1 / 2 of that of PMOS of the same size. For the same on-resistance, NMOS generally requires less silicon wafers, so the gate capacitance and threshold voltage of NMOS are lower than those of PMOS.

[0012] NMOS tubes are used in a much wider range of applications than PMOS tubes. What PMOS tubes can do, NMOS tubes can also do. Almost all switching power supply topologies tend to use NMOS tubes (rather than PMOS tubes), such as forward, flyback, push-pull, half-bridge, full-bridge and other topologies. Under the same process and size area conditions, the on-resistance of PMOS tubes is larger than that of NMOS tubes, so the conduction loss of PMOS switch tubes is larger than that of NMOS. In addition, NMOS tubes have many applications, many demands, many models, and are cheap, making them suitable for use when connected to the negative pole of the power supply (low-end drive).

[0013] The ultra-low power high-side ideal diode is suitable for connecting to the positive pole of the power supply (high-side drive), "flowing" current to the load circuit, while the ultra-low power low-side ideal diode turns the load on or off the negative pole of the power supply, so it "draws" current from the load.

[0014] Therefore, in order to solve the above problems, it is necessary to develop an ideal diode for low-end applications based on NMOS tubes with lower loss, lower price and richer selection. Summary of the invention

[0015] In view of the above-mentioned defects of the prior art, the technical problem to be solved by the present invention is to provide an ultra-low loss low-end ideal diode to solve the shortcomings of the prior art.

[0016] To achieve the above-mentioned purpose, the present invention provides an ultra-low loss low-end ideal diode, characterized in that it includes a combination logic control circuit and a first NMOS tube, the combination logic control circuit includes a second NMOS tube, a third NMOS tube, a first resistor and a second resistor, the drain of the first NMOS tube is connected to the source of the second NMOS tube and the negative electrode of the power supply, the source of the first NMOS tube is electrically connected to the source of the third NMOS tube, the gate of the first NMOS tube is electrically connected to the drain of the third NMOS tube, the gate of the second NMOS tube is connected to the drain of the second NMOS tube and the gate of the third NMOS tube, the drain of the second NMOS tube is connected to the positive electrode of the power supply through the first resistor, and the drain of the third NMOS tube is connected to the positive electrode of the power supply through the second resistor. The load is connected between the positive electrode of the power supply VCC (LOAD+) and the source of the first NMOS tube (LOAD-), when the voltage load- is not less than the voltage GND, the NMOS tube is turned on; otherwise, the NMOS tube is turned off to prevent the GND current from flowing back to the load-, thereby protecting the load-load circuit. When the positive pole VCC (LOAD+) of the power supply is connected reversely with the negative pole GND of the power supply, it can provide protection against reverse connection.

[0017] Preferably, the gate of the first NMOS tube is electrically connected to the drain of the third NMOS tube, and the drain of the third NMOS tube is connected to the positive electrode of the power supply through the second resistor.

[0018] Preferably, the gate of the second NMOS tube is connected to the drain of the second NMOS tube and the gate of the third NMOS tube, and the drain of the second NMOS tube is connected to the positive electrode of the power supply through the first resistor.

[0019] Preferably, the static loss of the combinational logic control circuit is very low, and the current loss is less than microampere level. If two resistors are connected in series with a 100MΩ resistor, the static current loss can be as low as 100nA.

[0020] Preferably, the circuit has a function of preventing backflow and has a very low conduction voltage drop.

[0021] Preferably, the second NMOS transistor and the third NMOS transistor are two NMOS transistors of the same model or a pair of NMOS transistors with the same parameters and packaged together.

[0022] Preferably, the first NMOS tube can use NMOS tubes with different conduction current sizes. Compared with PMOS tubes, NMOS tubes have more advantages: low conduction resistance, low conduction loss, multiple models, cheaper price, and much wider application. For high-power power supply control, NMOS tubes can be selected with a conduction resistance of several milliohms between the D pole and the S pole, and a power tube device with large current. The combinational logic control circuit is composed of dual NMOS tubes and resistors. After selecting and comparing the voltage between the drain (D pole) and the source (S pole) of the NMOS tube, different levels are output to control the conduction and cutoff of the NMOS tube. The NMOS tube with an on-resistance of several milliohms between the D pole and the S pole can pass a large current (hundred amperes), so the voltage drop through the NMOS tube is very small, which can be approximated as an ideal diode, suitable for the situation when connected to the negative pole of the power supply (low-end drive).

[0023] The beneficial effects of the present invention are:

[0024] The present invention has the function of preventing backflow and can protect the previous stage circuit; it has very low loss, and the static current loss can be as low as 100nA; it uses a combinational logic control circuit, the circuit is simple, the circuit is simple, the application is large, the demand is large, the model is large, the price is low, and the practicability is strong.

[0025] The concept, specific structure and technical effects of the present invention will be further described below in conjunction with the accompanying drawings to fully understand the purpose, characteristics and effects of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a circuit principle diagram of the present invention using discrete NMOS tubes. DETAILED DESCRIPTION

[0027] The embodiments of the present invention are described in detail below with reference to the accompanying drawings, but the present invention can be implemented in many different ways as defined and covered by the claims.

[0028] like Figure 1As shown, the combinational logic control circuit is composed of two NMOS tubes (V2, V3) of the same model or NMOS tube pairs with the same parameters and packaged together, and two series resistors (R1, R2), which control the conduction and cutoff of the NMOS tube (V1): when the voltage LOAD- is not less than the voltage GND, the NMOS tube (V1) is turned on; otherwise, the NMOS tube (V1) is cut off to prevent the GND current from flowing back to LOAD- through the NMOS tube (V1), thereby protecting the LOAD- load circuit. Since the NMOS tube is a voltage device, the current of the NMOS tube when it is turned on and off is very small, and a large resistance resistor is connected in series, which can be ignored. When it is turned on, only a small current (less than microamperes) is lost. Compared with the traditional Schottky diode or dual NPN tube pair + NMOS tube (or PMOS tube controlled by dual PNP tube pair) circuit, the loss is greatly reduced. The circuit composed of the NMOS tube pair belongs to an ultra-low loss controller, and the current loss of the ideal diode circuit is less than microamperes.

[0029] Furthermore, the NMOS pair has the same parameters and symmetrical dual N-channel MOS tubes, which can ensure that the parameters are kept as consistent as possible when the temperature changes. The circuit adjusts the size of the two drain (D pole) series resistors of the NMOS pair according to different loss requirements to meet the loss requirements. The static loss of the circuit is very low, and the current loss is less than the microampere level. If two resistors are connected in series with a 100MΩ resistor, the static current loss is less than 100nA. The circuit has the function of preventing backflow and has a very low forward voltage.

[0030] The combinational logic control circuit is composed of two NMOS tubes (V2, V3) and two resistors (R1, R2). The NMOS tube (V1) can use NMOS tubes with different conduction currents to meet different power requirements. The present invention has a backflow prevention function and can protect the previous circuit; it has very low loss, and the static current loss is less than 100nA; it uses a combinational logic control circuit, the circuit is simple, the cost is very low, and the practicability is strong. It is particularly suitable for the application of ultra-low loss ideal diode circuits in the Internet of Things NB-IoT. The circuit is very simple and has a very low cost.

[0031] According to different loss requirements, select an NMOS tube with a suitable on-resistance between the D pole and the S pole to meet the loss requirements. For high-power power supply control, NMOS can be selected with an on-resistance of several milliohms between the D pole and the S pole and a large current passing through the power tube device combination logic control circuit composed of dual NMOS tubes and resistors. After selecting and comparing the voltage between the drain (D pole) and the source (S pole) of the NMOS tube, different levels are output to control the conduction and cutoff of the NMOS tube. Since the NMOS tube is a voltage device, the current when the NMOS tube is turned on and off is very small and can be ignored. When it is turned on, only a small current (less than microamperes) is lost. Select an NMOS tube with an on-resistance of several milliohms between the D pole and the S pole, which can pass a large current (hundreds of amperes), then the voltage drop through the NMOS tube is very small, which can be approximated as an ideal diode.

[0032] According to the above schematic diagram, a PCB board is designed for testing. The model of the NMOS tube (V1, V2, V3) is 2N7002, and it is tested after assembly.

[0033] The NMOS tubes (V2 and V3) use two independent 2N7002. The test circuit is as follows: Figure 1 As shown, the typical value of 2N7002 tube conduction VGS (th) = 1.6V (1V ~ 2.5V), the test results are shown in Table 1: When VCC is powered by 5.0V (the series resistors are all 10MΩ), the static loss current IL is 0.7μA, V2 and V3 are both in the variable resistance area, V1 is turned on, and 0.1A current can pass after connecting the load; after GND is connected to the positive pole of the 5.0V power supply (equivalent to reverse connection, VCC is connected to the negative pole of the power supply), the reverse static loss current IB is 0.4μA (no backflow current flows into LOAD-, LOAD- voltage is 0V). The two series resistors are welded to 100MΩ, 1MΩ, and 100kΩ respectively, and the test results are shown in Table 1. In addition, all three NMOS tube models are changed to AO3420, and the test results are shown in Table 1. The combinational logic control circuit can effectively control the conduction and cutoff of the NMOS (V1) tube. After connecting the load, it can pass several amperes of current, that is, it can pass large current and has the function of preventing backflow, which greatly expands the scope of application.

[0034] Table 1 Two different types of NMOS tubes

[0035]

[0036] The beneficial effects of the present invention are: compared with the milliampere level of current loss controlled by traditional power diodes or triodes, the static current loss is more than two orders of magnitude smaller; compared with the ideal diode (LTC4413), the static loss current is reduced by more than one order of magnitude, and there is no backflow current. The use of the circuit of the present invention greatly reduces the static loss of the equipment, prolongs the working time of the battery, reduces the equipment maintenance cost, and greatly reduces the loss. It is suitable for the application of ultra-low loss low-end ideal diode circuits in the Internet of Things NB-IoT. The circuit is very simple and has a very low cost advantage.

[0037] The preferred specific embodiments of the present invention are described in detail above. It should be understood that a person skilled in the art can make many modifications and changes based on the concept of the present invention without creative work. Therefore, any technical solution that can be obtained by a person skilled in the art through logical analysis, reasoning or limited experiments based on the concept of the present invention on the basis of the prior art should be within the scope of protection determined by the claims.

Claims

1. An ultra-low loss low-end ideal diode, characterized in that: The invention comprises a combination logic control circuit and a first NMOS tube, wherein the combination logic control circuit comprises a second NMOS tube, a third NMOS tube, a first resistor and a second resistor, wherein the drain of the first NMOS tube is connected to the source of the second NMOS tube and the negative electrode of the power supply, the source of the first NMOS tube is electrically connected to the source of the third NMOS tube, the gate of the first NMOS tube is electrically connected to the drain of the third NMOS tube, the gate of the second NMOS tube is connected to the drain of the second NMOS tube and the gate of the third NMOS tube, the drain of the second NMOS tube is connected to the positive electrode of the power supply through the first resistor, and the drain of the third NMOS tube is connected to the positive electrode of the power supply through the second resistor; The combinational logic control circuit controls the conduction and cutoff of the first NMOS tube, and the load is connected between the positive electrode of the power supply and the source of the first NMOS tube. When the voltage load- at the source of the first NMOS tube is not less than the voltage GND at the negative electrode of the power supply, the first NMOS tube is turned on; otherwise, the first NMOS tube is cut off to prevent the GND current at the negative electrode of the power supply from flowing back to the load- at the source of the first NMOS tube, thereby protecting the load- load circuit; when the positive electrode of the power supply and the negative electrode of the power supply are connected reversely, it plays an anti-reverse connection protection role; the second NMOS tube and the third NMOS tube are two NMOS tubes of the same model or NMOS pairs with the same parameters and packaged together.

2. An ultra-low loss low-end ideal diode as claimed in claim 1, characterized in that: The first NMOS tubes use NMOS tubes with different conduction current sizes.

3. The ultra-low loss low-end ideal diode according to claim 1, characterized in that: The static current consumption of the combinational logic control circuit is less than microampere level.

4. The ultra-low loss low-end ideal diode according to claim 1, characterized in that: The resistance values ​​of the first resistor and the second resistor are adjustable to meet the requirement of low power consumption.

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