Random Number Generator

Abstract

A random number generator is provided. The random number generator includes: a first ring oscillator, the first ring oscillator includes a first inverter chain, the first inverter chain includes a plurality of first inverters connected in series, the first ring oscillator is configured to output a first random signal generated at a first subnode between two adjacent first inverters among the plurality of first inverters; a second ring oscillator, the second ring oscillator includes a second inverter chain, the second inverter chain includes a plurality of second inverters connected in series, the second ring oscillator is configured to output a second random signal generated at a second subnode between two adjacent second inverters among the plurality of second inverters; and a signal processing circuit, the signal processing circuit is used to generate a random number by combining the first random signal and the second random signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0143913 filed on November 20, 2018, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2019-0020054 filed on February 20, 2019, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The inventive concept relates to a random number generator, and more particularly, to a random number generator for generating random numbers based on random signals generated by a plurality of ring oscillators. Background Art

[0004] Typically, smart cards use encrypted keys in data communications to protect the user's personal information. The encrypted keys are usually random numbers that are specifically generated for scrambling and descrambling data. Random numbers can be classified as pseudo-random numbers or true random numbers.

[0005] Pseudo-random numbers are artificially generated by using logic circuits and software. Pseudo-random numbers can be obtained by using the Rivest-Shamir-Adelman (RSA) algorithm and the elliptic curve cryptography system.

[0006] True random numbers are generated by using physical phenomena that exist in nature. The physical phenomenon can be, for example, thermal noise of a resistor, short noise of a PN junction of a semiconductor, short noise caused by the generation of photons, waves of generated radiation, or metastable states. True random numbers can be called physical random numbers due to their unpredictability.

[0007] The ring oscillator can vibrate by repeatedly inverting and amplifying the output signal. The jump time point of the signal output by the ring oscillator can be randomly changed according to the Gaussian distribution. The Gaussian distribution area of ​​the output signal can be called jitter. The random number generator can generate true random numbers based on the randomly changed jitter. Summary of the invention

[0008] According to an exemplary embodiment of the inventive concept, there is provided a random number generator, the random number generator comprising: a first ring oscillator, the first ring oscillator comprising a first inverter chain, the first inverter chain comprising a plurality of first inverters connected in series, the first ring oscillator being configured to output a first random signal generated at a first subnode between two adjacent first inverters among the plurality of first inverters; a second ring oscillator, the second ring oscillator comprising a second inverter chain, the second inverter chain comprising a plurality of second inverters connected in series, the second ring oscillator being configured to output a second random signal generated at a second subnode between two adjacent second inverters among the plurality of second inverters; and a signal processing circuit for generating a random number by combining the first random signal and the second random signal.

[0009] According to an exemplary embodiment of the inventive concept, there is provided a random number generator, the random number generator comprising: a first ring oscillator group, the first ring oscillator group comprising a plurality of first ring oscillators, the plurality of first ring oscillators being configured to output a plurality of first random signals generated at a plurality of first subnodes between two adjacent first inverters among a plurality of first inverters, the plurality of first inverters being included in each of the plurality of first ring oscillators; a second ring oscillator group, the second ring oscillator group comprising a plurality of second ring oscillators, the plurality of second ring oscillators being configured to output a plurality of second random signals generated at a plurality of first subnodes between two adjacent second inverters among a plurality of second inverters a plurality of second random signals generated at a plurality of third subnodes between two adjacent third inverters among the plurality of third inverters, the plurality of third inverters being included in each of the plurality of second ring oscillators; a third ring oscillator group, the third ring oscillator group comprising a plurality of third ring oscillators, the plurality of third ring oscillators being configured to output a plurality of third random signals generated at a plurality of third subnodes between two adjacent third inverters among the plurality of third inverters, the plurality of third inverters being included in each of the plurality of third ring oscillators; and a signal processing circuit for generating a random number based on a combination of the plurality of first random signals, the plurality of second random signals and the plurality of third random signals.

[0010] According to an exemplary embodiment of the present inventive concept, a random number generator is provided, the random number generator comprising: a first inverter chain, the first inverter chain comprising a plurality of first inverters connected in series; a second inverter chain, the second inverter chain comprising a plurality of second inverters connected in series; and a logic element, the logic element being connected to a first sub-node between two adjacent first inverters among the plurality of first inverters and a second sub-node between two adjacent second inverters among the plurality of second inverters, the logic element being configured to generate a combined signal by combining a first random signal of the first sub-node and a second random signal of the second sub-node, wherein a random number is generated by sampling the combined signal.

[0011] According to an exemplary embodiment of the present invention, there is provided a random number generator, comprising: a plurality of first inverters connected in series, the plurality of first inverters being configured to output a first random signal; a plurality of second inverters connected in series, the plurality of second inverters being configured to output a second random signal; and a signal processing circuit for generating a random number by using the first random signal and the second random signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other features of the present inventive concept will be more clearly understood by describing in detail exemplary embodiments of the present inventive concept with reference to the accompanying drawings, in which:

[0013] Figure 1 is a block diagram illustrating an electronic system according to an exemplary embodiment of the inventive concept;

[0014] Figure 2 is a block diagram illustrating a random number generator according to an exemplary embodiment of the inventive concept;

[0015] Figure 3A , Figure 3B and Figure 3C is a circuit diagram illustrating a ring oscillator group according to an exemplary embodiment of the inventive concept;

[0016] Figure 4 is a circuit diagram illustrating a signal processing circuit according to an exemplary embodiment of the inventive concept;

[0017] Figure 5 is a circuit diagram illustrating a signal processing circuit according to an exemplary embodiment of the inventive concept;

[0018] Figure 6 is a timing diagram illustrating a random signal according to an exemplary embodiment of the inventive concept;

[0019] Fig. 7A is a circuit diagram illustrating a ring oscillator group according to an exemplary embodiment of the inventive concept;

[0020] Figure 7B is a circuit diagram illustrating a ring oscillator group according to an exemplary embodiment of the inventive concept;

[0021] Figure 8 and Fig. 9 is a graph showing an output waveform produced by a ring oscillator; and

[0022] Fig.10 is a block diagram illustrating a security system according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0023] Figure 1 is a block diagram illustrating an electronic system 1 according to an exemplary embodiment of the inventive concept.

[0024] refer to Figure 1 , the electronic system 1 may include a random number generator 10 and a control circuit 20. The electronic system 1 may be a device for performing various operations by using random numbers, and may be, for example, a laptop computer, a mobile phone, a smart phone, a tablet personal computer (PC), a personal digital assistant (PDA), a smart card, or a semiconductor package.

[0025] The control circuit 20 may output a constantly changing control signal Ctrl for controlling the random number generator 10. The control signal Ctrl may be a mode determination signal for determining the mode of the plurality of ring oscillators included in the first ring oscillator group 110, the second ring oscillator group 120, and the third ring oscillator group 130, a start signal for starting the first ring oscillator to the ninth ring oscillator, or a sampling control signal SS for changing a random signal in an analog region into a random number RN in a digital region. Figure 2 The control signal Ctrl is described in detail.

[0026] The random number generator 10 may generate a random number RN randomly composed of 0 or 1 in a digital area based on a control signal Ctrl. To this end, the random number generator 10 may include a first ring oscillator group 110 , a second ring oscillator group 120 , a third ring oscillator group 130 and a signal processing circuit 200 .

[0027] The first ring oscillator group 110 may include a plurality of ring oscillators. Each of the plurality of ring oscillators may include a plurality of inverters. A random signal vibrating by repeatedly inverting and amplifying the plurality of inverters may be generated by a sub-node included in each of the plurality of ring oscillators. The second ring oscillator group 120 and the third ring oscillator group 130 may respectively generate a plurality of random signals by a method similar to that of the first ring oscillator group 110. The jump time points of the plurality of random signals generated by the first ring oscillator group 110 to the third ring oscillator group 130 may be randomly changed in the jitter region. In the jitter region, the randomness of the random signal may be ensured.

[0028] The signal processing circuit 200 may generate a combined signal by combining a plurality of random signals generated by the first to third ring oscillator groups 110 to 130. The jitter region of each of the plurality of random signals generated by the first to third ring oscillator groups 110 to 130 does not cover the entire period.

[0029] The random number generator 10 according to an exemplary embodiment of the inventive concept can generate a combined signal having a jitter region covering the entire cycle by combining a plurality of random signals generated by the first ring oscillator group 110 to the third ring oscillator group 130, and can generate a random number RN by sampling the combined signal. Since the random number RN is generated by sampling the combined signal having a jitter region covering the entire cycle, the randomness of the random number RN is increased, and since sampling is not performed multiple times, the random number RN can be generated quickly.

[0030] exist Figure 1 , it is shown that the random number generator 10 includes the first ring oscillator group 110 to the third ring oscillator group 130. However, this is only an example, and the random number generator 10 may include more or less than three ring oscillator groups.

[0031] Figure 2 is a block diagram illustrating a random number generator according to an exemplary embodiment of the inventive concept.

[0032] refer to Figure 2, the random number generator 10 may include a first ring oscillator group 110, a second ring oscillator group 120, a third ring oscillator group 130, and a signal processing circuit 200. The first ring oscillator group 110 may include a first ring oscillator 111, a second ring oscillator 112, and a third ring oscillator 113. In addition, the second ring oscillator group 120 may include a fourth ring oscillator 121, a fifth ring oscillator 122, and a sixth ring oscillator 123. The third ring oscillator group 130 may include a seventh ring oscillator 131, an eighth ring oscillator 132, and a ninth ring oscillator 133. In addition, the signal processing circuit 200 may include a logic circuit 210, a duty cycle correction circuit 220, a sampling circuit 230, and a merging circuit 240.

[0033] Each of the first ring oscillator 111 to the ninth ring oscillator 133 may include a plurality of inverters. A plurality of sub-nodes may be provided between adjacent inverters in the plurality of inverters. At least one connection node CN1 to CN9 among the plurality of sub-nodes may be connected to the logic circuit 210. Figure 2 , each of the first to ninth ring oscillators 111 to 133 is shown to be connected to the logic circuit 210 through each of the first connection node CN1, the second connection node CN2, the third connection node CN3, the fourth connection node CN4, the fifth connection node CN5, the sixth connection node CN6, the seventh connection node CN7, the eighth connection node CN8, and the ninth connection node CN9. However, the first to ninth ring oscillators 111 to 133 may be connected to the logic circuit 210 through one or more connection nodes of the plurality of sub-nodes, referring to Figure 3A and Figure 4 This is described in detail.

[0034] Each of the first ring oscillators 111 to the ninth ring oscillator 133 may determine the mode of each of the first ring oscillators 111 to the ninth ring oscillator 133 as a metastable mode or an oscillation mode based on each of the mode selection signals MS1, MS2, MS3, MS4, MS5, MS6, MS7, MS8, and MS9. Figure 1 ) receives mode selection signals MS1 to MS9, and controls the first ring oscillator 111 to the ninth ring oscillator 133 through different mode selection signals MS1 to MS9 or through a common mode selection signal. Fig. 7A and Figure 7B The modes of the first ring oscillator 111 to the ninth ring oscillator 133 are described in detail.

[0035] The first to ninth ring oscillators 111 to 133 may output first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth random signals RS1, RS2, RS3, RS4, RS5, RS6, RS7, RS8, and RS9 having irregular periods to the logic circuit 210 through the first to ninth connection nodes CN1 to CN9. The logic circuit 210 may include a first logic element LE1, a second logic element LE2, and a third logic element LE3, and the first to third logic elements LE1 to LE3 may be connected to the first to ninth ring oscillators 111 to 133. In an exemplary embodiment of the inventive concept, each of the first to third logic elements LE1 to LE3 receives one random signal from each of the first to third ring oscillator groups 110 to 130, and may perform a logic operation on the received random signal. For example, each of the first to third logic elements LE1 to LE3 may be an XOR gate, and the first to third logic elements LE1 to LE3 may perform an OR operation (or an XOR operation) on the first to ninth random signals RS1 to RS9 .

[0036] For example, the first logic element LE1 is connected to the first ring oscillator 111 through the first connection node CN1, to the fourth ring oscillator 121 through the fourth connection node CN4, and to the seventh ring oscillator 131 through the seventh connection node CN7. In addition, the first logic element LE1 receives the first random signal RS1 from the first ring oscillator 111, the fourth random signal RS4 from the fourth ring oscillator 121, and the seventh random signal RS7 from the seventh ring oscillator 131. The first logic element LE1 may generate a first combination signal CS1 by performing an OR operation on the received first random signal RS1, the fourth random signal RS4, and the seventh random signal RS7.

[0037] In addition, the second logic element LE2 receives the second random signal RS2 from the second ring oscillator 112, the fifth random signal RS5 from the fifth ring oscillator 122, and the eighth random signal RS8 from the eighth ring oscillator 132. The second logic element LE2 can generate a second combination signal CS2 by performing an OR operation on the received second random signal RS2, the fifth random signal RS5, and the eighth random signal RS8. In addition, the third logic element LE3 receives the third random signal RS3 from the third ring oscillator 113, the sixth random signal RS6 from the sixth ring oscillator 123, and the ninth random signal RS9 from the ninth ring oscillator 133. The third logic element LE3 can generate a third combination signal CS3 by performing an OR operation on the received third random signal RS3, the sixth random signal RS6, and the ninth random signal RS9.

[0038] In an exemplary embodiment of the inventive concept, the first to third logic elements LE1 to LE3 may receive first to ninth random signals RS1 to RS9 from evenly spaced subnodes (eg, may receive random signals from subnodes located after the same number of inverters).

[0039] According to an exemplary embodiment of the present invention, the first random signal RS1 to the ninth random signal RS9 received by each of the first logic element LE1 to the third logic element LE3 may have different phases. Therefore, the first random signal RS1 to the ninth random signal RS9 may have different jump time points. In other words, since the jitter regions of the first random signal RS1 to the ninth random signal RS9 are different from each other, the jitter regions of the first combination signal CS1 to the third combination signal CS3 obtained by combining the first random signal RS1 to the ninth random signal RS9 may cover a large area of ​​the cycle, and the reference signal CS1 to the third combination signal CS3 may cover a large area of ​​the cycle. Figure 8 This is described in detail.

[0040] The duty cycle correction circuit 220 may include a first duty cycle corrector DC1, a second duty cycle corrector DC2, and a third duty cycle corrector DC3. The first to third duty cycle correctors DC1 to DC3 receive first to third combination signals CS1 to CS3 from the logic circuit 210, respectively, and may control the duty cycle of the first to third combination signals CS1 to CS3 (e.g., the ratio between the logic high and the logic low of the first to third combination signals CS1 to CS3). For example, the first duty cycle corrector DC1 connected to the first logic element LE1 receives the first combination signal CS1 from the first logic element LE1, and may control the duty cycle of the first combination signal CS1 to 50%. In other words, the first duty cycle corrector DC1 may control the first combination signal CS1 so that the ratio between the logic high and the logic low of the first combination signal CS1 is 1:1.

[0041] In addition, the second duty cycle corrector DC2 receives the second combination signal CS2 from the second logic element LE2 and can control the duty cycle of the second combination signal CS2, and the third duty cycle corrector DC3 receives the third combination signal CS3 from the third logic element LE3 and can control the duty cycle of the third combination signal CS3.

[0042] The sampling circuit 230 may include a first signal sampler SP1, a second signal sampler SP2, and a third signal sampler SP3. The first signal samplers SP1 to the third signal samplers SP3 may generate sub-random numbers SRN1, sub-random numbers SRN2, and sub-random numbers SRN3 in the digital region by sampling the first combination signal CS1 to the third combination signal CS3 having a duty cycle controlled by the duty cycle correction circuit 200 in the analog region based on the sampling control signal SS, respectively. For example, the first signal sampler SP1 may generate the first sub-random number SRN1 by sampling the first combination signal CS1 in response to the sampling control signal SS, the second signal sampler SP2 may generate the second sub-random number SRN2 by sampling the second combination signal CS2 in response to the sampling control signal SS, and the third sampler SP3 may generate the third sub-random number SRN3 by sampling the third combination signal CS3 in response to the sampling control signal SS. For example, the sampling circuit 230 may generate the third sub-random number SRN3 by sampling the third combination signal CS3 in response to the sampling control signal SS from the control circuit 20( Figure 1 ) receives the sampling control signal SS. The merging circuit 240 can generate a random number RN by receiving and merging the first sub-random number SRN1 to the third sub-random number SRN3.

[0043] exist Figure 2, it is shown that each of the first to third ring oscillator groups 110 to 130 includes three ring oscillators from the first to ninth ring oscillators 111 to 133. However, one of the first to third ring oscillator groups 110 to 130 may include more or less than three ring oscillators. Figure 2 In FIG. 1 , it is shown that the random number generator 10 includes the first ring oscillator group 110 to the third ring oscillator group 130. However, the random number generator 10 may include more or less than three ring oscillator groups. For example, when the random number generator 10 includes four ring oscillator groups, the random number generator 10 may include four logic elements. In addition, the number of random signals combined by one logic element may vary. For example, one logic element may combine more or less than three random signals.

[0044] In addition, Figure 2 , it is shown that the first to ninth ring oscillators 111 to 133 are connected to the logic circuit 210 through the first to ninth connection nodes CN1 to CN9, respectively. However, each of the first to ninth ring oscillators 111 to 133 may be connected to the logic circuit 210 through a different connection configuration.

[0045] FIG. 3A to FIG. 3C is a circuit diagram showing a ring oscillator group according to an exemplary embodiment of the inventive concept. For example, Figure 3A Shows Figure 2 The first ring oscillator group 110, Figure 3B Shows Figure 2 The second ring oscillator group 120, Figure 3C Shows Figure 2 The third ring oscillator group 130 is provided.

[0046] refer to Figure 2 and Figure 3A , the first ring oscillator group 110 includes first to third ring oscillators 111 to 113, and the first ring oscillator 111 may include a first multiplexer MUX1 and a first inverter chain IC1. The first inverter chain IC1 may include a plurality of first inverters INV1. The first inverter chain IC1 may include first sub-nodes SN11 to SN1k located between adjacent first inverters INV1. For example, the first sub-node SN11 is located between adjacent first inverters INV1. The first sub-nodes SN11 to SN1k may be connected to different logic elements, respectively. Each of the first sub-nodes SN11 to SN1k may be connected to a logic element (for example, a first a-line a(1) to a ka-th line a(k)) through each a-line of the first a-line a(1) to the ka-th line a(k). Figure 4 The first logic element LE1, the fourth logic element LE4 or the seventh logic element LE7 in the embodiment will be referred to later. Figure 4 Describe this.

[0047] In the first multiplexer MUX1, the first input terminal is connected to the first sub-node SN11, the second input terminal is connected to another ring oscillator, and the output terminal can be connected to the input terminal of the first inverter chain IC1. The first multiplexer MUX1 can set the first ring oscillator 111 to be in a metastable mode or an oscillation mode by connecting the input terminal of the first inverter chain IC1 to another ring oscillator or the first sub-node SN11 in response to the first mode selection signal MS1, which will be referred to later. Fig. 7A and Figure 7B Describe this.

[0048] The second ring oscillator 112 includes a second multiplexer MUX2 and a second inverter chain IC2, and the second inverter chain IC2 may include a plurality of second inverters INV2. The second inverter chain IC2 may include second sub-nodes SN21 to SN2k located between adjacent second inverters INV2. Each of the second sub-nodes SN21 to SN2k may be connected to a logic element (e.g., Figure 4 The second logic element LE2, the fifth logic element LE5 or the eighth logic element LE8).

[0049] The third ring oscillator 113 includes a third multiplexer MUX3 and a third inverter chain IC3, and the third inverter chain IC3 may include a plurality of third inverters INV3. The third inverter chain IC3 may include third sub-nodes SN31 to SN3k located between adjacent third inverters INV3. Each of the third sub-nodes SN31 to SN3k may be connected to a logic element (e.g., Figure 4 The operation of the second ring oscillator 112 and the operation of the third ring oscillator 113 may be the same as or similar to the operation of the first ring oscillator 111. For example, the second multiplexer MUX2 may set the second ring oscillator 112 to be in a metastable mode or an oscillation mode in response to the second mode selection signal MS2. The third multiplexer MUX3 may set the mode of the third ring oscillator 113 in response to the third mode selection signal MS3.

[0050] In an exemplary embodiment of the inventive concept, the number of inverters included in each of the first to third ring oscillators 111 to 113 may be the same.

[0051] See also Figure 3B , the second ring oscillator group 120 may include fourth ring oscillators 121 to sixth ring oscillators 123. The fourth ring oscillator 121 includes a fourth multiplexer MUX4 and a fourth inverter chain IC4, and the fourth inverter chain IC4 may include a plurality of fourth inverters INV4. The fourth inverter chain IC4 may include fourth sub-nodes SN41 to SN4k located between adjacent fourth inverters INV4. Each of the fourth sub-nodes SN41 to SN4k may be connected to a logic element (e.g., a logic element) through each of the first d-line d(1) to the kth d-line d(k). Figure 4 The first logic element LE1, the fourth logic element LE4 or the seventh logic element LE7).

[0052] The fifth ring oscillator 122 includes a fifth multiplexer MUX5 and a fifth inverter chain IC5, and the fifth inverter chain IC5 may include a plurality of fifth inverters INV5. The fifth inverter chain IC5 may include fifth sub-nodes SN51 to SN5k located between adjacent fifth inverters INV5. Each of the fifth sub-nodes SN51 to SN5k may be connected to a logic element (e.g., Figure 4 The second logic element LE2, the fifth logic element LE5 or the eighth logic element LE8).

[0053] The sixth ring oscillator 123 includes a sixth multiplexer MUX6 and a sixth inverter chain IC6, and the sixth inverter chain IC6 may include a plurality of sixth inverters INV6. The sixth inverter chain IC6 may include sixth sub-nodes SN61 to SN6k located between adjacent sixth inverters INV6. Each of the sixth sub-nodes SN61 to SN6k may be connected to a logic element (e.g., Figure 4 The third logic element LE3, the sixth logic element LE6 or the ninth logic element LE9).

[0054] The operation of the second ring oscillator group 120 may be the same as or similar to the operation of the first ring oscillator group 110. For example, the fourth multiplexer MUX4 may set the mode of the fourth ring oscillator 121 in response to the fourth mode selection signal MS4, the fifth multiplexer MUX5 may set the mode of the fifth ring oscillator 122 in response to the fifth mode selection signal MS5, and the sixth multiplexer MUX6 may set the mode of the sixth ring oscillator 123 in response to the sixth mode selection signal MS6.

[0055] refer to Figure 3C , the third ring oscillator group 130 may include seventh to ninth ring oscillators 131 to 133. The seventh ring oscillator 131 includes a seventh multiplexer MUX7 and a seventh inverter chain IC7, and the seventh inverter chain IC7 may include a plurality of seventh inverters INV7. The seventh inverter chain IC7 may include seventh sub-nodes SN71 to SN7k located between adjacent seventh inverters INV7. Each of the seventh sub-nodes SN71 to SN7k may be connected to a logic element (e.g., a logic element) through each of the first g-line g(1) to the kg-line g(k). Figure 4 The first logic element LE1, the fourth logic element LE4 or the seventh logic element LE7).

[0056] The eighth ring oscillator 132 includes an eighth multiplexer MUX8 and an eighth inverter chain IC8, and the eighth inverter chain IC8 may include a plurality of eighth inverters INV8. The eighth inverter chain IC8 may include eighth sub-nodes SN81 to SN8k located between adjacent eighth inverters INV8. Each of the eighth sub-nodes SN81 to SN8k may be connected to a logic element (e.g., Figure 4 The second logic element LE2, the fifth logic element LE5 or the eighth logic element LE8).

[0057] The ninth ring oscillator 133 includes a ninth multiplexer MUX9 and a ninth inverter chain IC9, and the ninth inverter chain IC9 may include a plurality of ninth inverters INV9. The ninth inverter chain IC9 may include ninth sub-nodes SN91 to SN9k located between adjacent ninth inverters INV9. Each of the ninth sub-nodes SN91 to SN9k may be connected to a logic element (e.g., Figure 4 The third logic element LE3, the sixth logic element LE6 or the ninth logic element LE9).

[0058] The operation of the third ring oscillator group 130 may be the same as or similar to the operation of the first ring oscillator group 110. For example, the seventh multiplexer MUX7 may set the mode of the seventh ring oscillator 131 in response to the seventh mode selection signal MS7, the eighth multiplexer MUX8 may set the mode of the eighth ring oscillator 132 in response to the eighth mode selection signal MS8, and the ninth multiplexer MUX9 may set the mode of the ninth ring oscillator 133 in response to the ninth mode selection signal MS9.

[0059] In an exemplary embodiment of the present inventive concept, the number of inverters connected to the same logic element included in each of the first to ninth ring oscillators may be the same. Figure 3A ) includes connections to Figure 4 The number of inverters INV1 of the first logic element LE1 in the fourth ring oscillator 121 (FIG. 3B) connected to Figure 4 The number of inverters INV4 of the first logic element LE1 and the seventh ring oscillator 131 ( Figure 3C ) includes connections to Figure 4 The numbers of inverters INV7 of the first logic element LE1 in the embodiment may be equal to each other. Therefore, the same number of sub-nodes may be connected to one logic element (eg, Figure 4 The first logic element LE1 in .

[0060] Figure 4 is a circuit diagram illustrating a signal processing circuit 200 according to an exemplary embodiment of the inventive concept.

[0061] refer to FIG. 3A to FIG. 3C and Figure 4 The signal processing circuit 200 may include a logic circuit 210 , a duty cycle correction circuit 220 , a sampling circuit 230 and a merging circuit 240 .

[0062] The logic circuit 210 may include a first logic element LE1, a second logic element LE2, a third logic element LE3, a fourth logic element LE4, a fifth logic element LE5, a sixth logic element LE6, a seventh logic element LE7, an eighth logic element LE8, and a ninth logic element LE9. The first logic element LE1 to the ninth logic element LE9 may each be connected to a plurality of ring oscillators through a plurality of sub-nodes. For example, the first logic element LE1 may be connected to the first sub-node SN11( Figure 3A ), which can be connected to the fourth subnode SN41 ( Figure 3B), which can be connected to the seventh sub-node SN71( Figure 3C ). The first logic element LE1 may receive a plurality of random signals through the first a line a(1), the first d line d(1), and the first g line g(1), and may generate a combined signal by combining the received signals. In addition, the first logic element LE1 may output the generated combined signal to the first duty cycle corrector DC1 of the duty cycle correction circuit 220.

[0063] The second logic element LE2 to the ninth logic element LE9 can receive multiple random signals from multiple sub-nodes of multiple ring oscillators by a method similar to the method of the first logic element LE1, can generate a combined signal by combining the received random signals, and can output the generated combined signal to the duty cycle correction circuit 220.

[0064] The duty cycle correction circuit 220 includes a first duty cycle corrector DC1, a second duty cycle corrector DC2, a third duty cycle corrector DC3, a fourth duty cycle corrector DC4, a fifth duty cycle corrector DC5, a sixth duty cycle corrector DC6, a seventh duty cycle corrector DC7, an eighth duty cycle corrector DC8, and a ninth duty cycle corrector DC9. The first duty cycle corrector DC1 to the ninth duty cycle corrector DC9 can correct the duty cycle of the received combined signal. According to an exemplary embodiment of the inventive concept, the first duty cycle corrector DC1 to the ninth duty cycle corrector DC9 can be a trigger in which a data input terminal D and an inverting output terminal Q are connected to each other to receive the combined signal through a clock input unit. For example, the first duty cycle corrector DC1 includes a clock input unit connected to the first logic element LE1, and the first duty cycle corrector DC1 can output the combined signal as a clock to the first signal sampler SP1, and the combined signal has a duty cycle corrected based on the combined signal received from the first logic element LE1.

[0065] The second duty cycle corrector DC2 to the ninth duty cycle corrector DC9 respectively include clock input units connected to the second logic element LE2 to the ninth logic element LE9 in a manner similar to the first duty cycle corrector DC1, and each clock input unit can output a combined signal having a duty cycle corrected based on a combined signal received from a corresponding one of the second logic element LE2 to the ninth logic element LE9 as a clock to the sampling circuit 230.

[0066] The sampling circuit 230 includes a first signal sampler SP1, a second signal sampler SP2, a third signal sampler SP3, a fourth signal sampler SP4, a fifth signal sampler SP5, a sixth signal sampler SP6, a seventh signal sampler SP7, an eighth signal sampler SP8, and a ninth signal sampler SP9. Each of the first signal sampler SP1 to the ninth signal sampler SP9 can generate a first sub-random number SRN1, a second sub-random number SRN2, a third sub-random number SRN3, a fourth sub-random number SRN4, a fifth sub-random number SRN5, a sixth sub-random number SRN6, a seventh sub-random number SRN7, an eighth sub-random number SRN8, and a ninth sub-random number SRN9 in the digital region by sampling the combined signal after the duty cycle is corrected based on the sampling control signal SS. In an exemplary embodiment of the inventive concept, the data input terminals D of the first to ninth signal samplers SP1 to SP9 are respectively connected to the first to ninth duty cycle correctors DC1 to DC9, and the non-inverting output terminals Q of the first to ninth signal samplers SP1 to SP9 may be connected to the merging circuit 240. For example, the first signal sampler SP1 receives the duty cycle corrected merged signal from the first duty cycle corrector DC1, and may generate the first sub-random number SRN1 by sampling the duty cycle corrected merged signal based on the sampling control signal SS received from the clock input terminal of the first signal sampler SP1.

[0067] By a method similar to that of the first signal sampler SP1, the second signal samplers SP2 to the ninth signal samplers SP9 can generate second sub-random numbers SRN2 to ninth sub-random numbers SRN9 by sampling the combined signals received from the second duty cycle corrector DC2 to the ninth duty cycle corrector DC9 and having their duty cycles corrected, respectively, based on the sampling control signal SS. The second signal samplers SP2 to the ninth signal samplers SP9 can output the generated second sub-random numbers SRN2 to the ninth sub-random numbers SRN9 to the merging circuit 240.

[0068] The merging circuit 240 includes a first merging element ME1, a second merging element ME2, a third merging element ME3 and a fourth merging element ME4. The merging circuit 240 generates a random number RS ​​by merging the received first to ninth sub-random numbers SRN1 to SRN9, and can output the generated random number RS. Figure 4 In FIG. 2 , the merging circuit 240 is composed of the first merging element ME1 to the fourth merging element ME4. However, the number of merging elements constituting the merging circuit 240 may vary according to the number of sub-random numbers.

[0069] Figure 51 is a circuit diagram showing a signal processing circuit according to an exemplary embodiment of the present invention. Figure 4 The description is the same as the description of .

[0070] refer to Figure 5 , the signal processing circuit 200a may include a logic circuit 210a, a duty cycle correction circuit 220a, a merging circuit 240a and a signal sampler 230a. Because the logic circuit 210a and the duty cycle correction circuit 220a may be respectively connected to Figure 4 The logic circuit 210a and the duty cycle correction circuit 220a are the same or similar, so the description of the logic circuit 210a and the duty cycle correction circuit 220a is omitted.

[0071] The merging circuit 240a receives the first combination signal SRS1, the second combination signal SRS2, the third combination signal SRS3, the fourth combination signal SRS4, the fifth combination signal SRS5, the sixth combination signal SRS6, the seventh combination signal SRS7, the eighth combination signal SRS8 and the ninth combination signal SRS9 whose duty ratios are corrected, and can generate a merged random signal MRS by merging the first combination signal SRS1 to the ninth combination signal SRS9. To achieve this, the merging circuit 240a may include the following: Figure 4 The first merging element ME1 to the fourth merging element ME4 of the merging circuit 240 are shown in FIG.

[0072] The signal sampler 230a can generate a random number RN in the digital region by sampling the merged random signal MRS in the analog region based on the sampling control signal SS. In an exemplary embodiment of the inventive concept, the data input terminal D of the signal sampler 230a is connected to the merging circuit 240a, and the non-inverting output terminal Q of the signal sampler 230a can be connected to the output OUT.

[0073] Figure 6 is a timing diagram showing a random signal according to an exemplary embodiment of the inventive concept. Figure 6 In the diagram, the y-axis represents logic level and the x-axis represents time.

[0074] refer to Figure 2 and Figure 6, the first random signal RS1, the fourth random signal RS4, and the seventh random signal RS7 input to the first logic element LE1 can repeatedly output logic high (e.g., "1") and logic low (e.g., "0") with the same period T. Due to the characteristics of the ring oscillator, the transition time points of the first random signal RS1, the fourth random signal RS4, and the seventh random signal RS7 from logic low to logic high or from logic high to logic low will change randomly. The transition time point can generate jitter JT that changes according to Gaussian distribution. In the current specification, the time region where the jitter JT is located is referred to as the jitter region JA. The jitter JT is composed of Figure 6 The shadow in is shown.

[0075] According to an exemplary embodiment of the inventive concept, a plurality of random signals (eg, the first random signal RS1 , the fourth random signal RS4 , and the seventh random signal RS7 ) input to one logic element (eg, the first logic element LE1 ) may have different phase differences.

[0076] For example, when three random signals are input to a logic element, the three random signals may have a phase difference of 120 degrees. Figure 6 , the first random signal RS1 has a falling edge at a first time point (a), the fourth random signal RS4 has a falling edge at a second time point (a+T / 3), and the seventh random signal RS7 has a falling edge at a third time point (a+2T / 3).

[0077] In an exemplary embodiment of the inventive concept, since the first random signal RS1, the fourth random signal RS4, and the seventh random signal RS7 are generated by a plurality of ring oscillators each having the same number of inverters, the first random signal RS1, the fourth random signal RS4, and the seventh random signal RS7 may have the same period. Since the first random signal RS1, the fourth random signal RS4, and the seventh random signal RS7 are generated by child nodes located at the same position of the ring oscillator group, the first random signal RS1, the fourth random signal RS4, and the seventh random signal RS7 may have a phase difference of 120 degrees. In other words, the first random signal RS1, the fourth random signal RS4, and the seventh random signal RS7 may have a phase difference of 1 / 3 period (T / 3).

[0078] In the example where the jitter area JA is not less than 1 / 6 period (T / 6), the jitter JT of the first combination signal CS1 combining the first random signal RS1, the fourth random signal RS4 and the seventh random signal RS7 can cover the entire period. In other words, the jitter JT of the first combination signal CS1 exists in the entire period T.

[0079] Equation 1

[0080]

[0081] Equation 2

[0082]

[0083] Equation 1 is used to obtain the sigma (or standard deviation) σ required for sufficient randomness according to the present invention. need , Equation 2 is used to obtain the time t required for sufficient randomness according to the present invention. need .freq RO represents the operating frequency of the ring oscillator, σ cycle is the standard deviation accumulated in one cycle, and n represents the number of random signals RS1, RS4, and RS7. According to equations 1 and 2, as the number of random signals n increases, the required standard deviation σ need and the time required t need can be reduced to 1 / n and 1 / n respectively 2 .

[0084] According to an exemplary embodiment of the inventive concept, a random number with high randomness is generated based on a signal (eg, the first combination signal CS1) whose entire period is covered by the jitter JT, and therefore, the randomness of the random number can be increased and the random number with high randomness can be generated quickly.

[0085] exist Figure 6 In FIG. 3 , three random signals are shown to be combined. However, in another example, more or less than three random signals may be combined.

[0086] Fig. 7A is a circuit diagram showing a ring oscillator group according to an exemplary embodiment of the inventive concept. For example, Fig. 7A An embodiment in which the ring oscillator group operates in an oscillation mode is shown. Figure 3A The description is the same as the description of .

[0087] See also Fig. 7A , the first ring oscillator group 110 may include a first ring oscillator 111, a second ring oscillator 112, and a third ring oscillator 113. The first to third ring oscillators 111 to 113 may operate in an oscillation mode based on the first to third mode selection signals MS1 to MS3, respectively.

[0088] The first multiplexer MUX1 can connect the input terminal of the first inverter chain IC1 to another ring oscillator (eg, Figure 2The first sub-path Pa1_1 including the plurality of first inverters INV1 can be configured by the ninth ring oscillator 133 in the embodiment of the present invention. In addition, the second multiplexer MUX2 can configure the second sub-path Pa1_2 including the plurality of second inverters INV2 by connecting the input end of the second inverter chain IC2 to the first ring oscillator 111 based on the second mode selection signal MS2. The third multiplexer MUX3 can configure the third sub-path Pa1_3 including the plurality of third inverters INV3 by connecting the input end of the third inverter chain IC3 to the second ring oscillator 112 based on the third mode selection signal MS3.

[0089] The first to third sub-paths Pa1_1 to Pa1_3 may form a first path configured by a plurality of first to third inverters INV1 to INV3. The plurality of inverters continuously invert and amplify the input signal, so the sub-nodes SN11 to SN3k may generate random signals.

[0090] Figure 7B is a circuit diagram showing a ring oscillator group according to an exemplary embodiment of the inventive concept. For example, Figure 7B An embodiment in which a ring oscillator group operates in a metastable mode is shown. Figure 3A The description is the same as the description of .

[0091] refer to Figure 7B The first ring oscillator group 110 may include a first ring oscillator 111, a second ring oscillator 112, and a third ring oscillator 113. The first to third ring oscillators 111 to 113 may operate in a metastable mode based on the first to third mode selection signals MS1 to MS3, respectively.

[0092] The first multiplexer MUX1 can connect the input end of the first inverter chain IC1 to the output end (e.g., the first node SN11) of the first inverter INV1 located at the front of the first inverter chain IC1 based on the first mode selection signal MS1, and can configure the fourth sub-path Pa2_1 including the first inverter INV1. In addition, the second multiplexer MUX2 can connect the input end of the second inverter chain IC2 to the output end (e.g., the second node SN21) of the second inverter INV2 located at the front of the second inverter chain IC2 based on the second mode selection signal MS2, and can configure the fifth sub-path Pa2_2 including the second inverter INV2. The third multiplexer MUX3 can connect the input end of the third inverter chain IC3 to the output end (e.g., the third node SN31) of the third inverter INV3 located at the front of the third inverter chain IC3 based on the third mode selection signal MS3, and can configure the sixth sub-path Pa2_3 including the third inverter INV3.

[0093] The fourth sub-path Pa2_1 to the sixth sub-path Pa2_3 may form a plurality of loops each including one inverter. Since one inverter is repeatedly inverted and amplified, a metastable signal may be generated. Figure 8 and Fig. 9 As described, the signal generated in the metastable mode can be input as the initial value of the oscillation mode. Therefore, the first to third ring oscillators 111 to 113 can generate stable random signals by repeatedly inverting and amplifying the metastable signal in the oscillation mode.

[0094] The second ring oscillator group 120 ( Figure 3B ) and the third ring oscillator group 130 ( Figure 3C ) may be operated by a method that is the same as or similar to that of the first ring oscillator group 110.

[0095] Figure 8 and Fig. 9 is a graph showing an output waveform generated by a ring oscillator.

[0096] refer to Figure 8 and Fig. 9 , showing a random signal output from a subnode of a ring oscillator. In the metastable mode, the subnode of the ring oscillator outputs a metastable signal due to thermal noise. In the oscillation mode, an oscillation signal generated by inverting and amplifying the metastable signal is output from the subnode.

[0097] In the metastable mode, a metastable signal that may not be clearly determined as a logic high or logic low based on the intermediate level MS Level is generated as a random signal. The metastable signal is input as the initial value of the oscillation mode and is inverted and amplified by the ring oscillator, so that an oscillation signal that can be determined as a logic low or logic high can be generated.

[0098] According to an exemplary embodiment of the inventive concept, since a signal level of a metastable signal in a metastable mode is unclear, randomness of an initial value in an oscillation mode may be increased, and thus randomness of a random signal may be increased.

[0099] Fig.10 is a block diagram illustrating a security system according to an exemplary embodiment of the inventive concept.

[0100] refer to Fig.10 , the security system 1000 includes a central processing unit (CPU) 1100, a security processor 1200, a read-only memory (ROM) 1300, a random access memory (RAM) 1400, and a password memory 1500. The security system 1000 may correspond to various systems using security measures, and may be, for example, a laptop computer, a mobile phone, a smart phone, a tablet PC, a PDA, or a smart card.

[0101] The CPU 1100 may output various control signals for controlling the operation of the security system 1000. In another exemplary embodiment of the present inventive concept, an application processor (AP) may be used as the CPU 1100.

[0102] In addition to the CPU 1100, the security processor 1200 can also achieve an operation processing speed related to fast security. The security processor 1200 can perform operations using personal information and can be called a security operator. For example, the security processor 1200 can perform an encryption operation or a decryption operation by using a private key in a public key infrastructure (PKI).

[0103] The security processor 1200 may perform various operations related to encryption or decryption operations. For example, the security processor 1200 may perform the entire operation for encrypting or decrypting data, or a portion of multiple operations required for encryption or decryption. The security processor 1200 may include the processor according to the above reference. Figures 1 to 9 The random number generator of the embodiment of the inventive concept described above is used to perform an encryption operation or a decryption operation. In other words, the security processor 1200 can perform an encryption operation or a decryption operation using a random number generated by combining random signals generated by a plurality of sub-nodes included in a plurality of ring oscillators, thereby improving the security of the security processor 1200.

[0104] The ROM 1300 and the RAM 1400 may store data for driving the security system 1000. The password memory 1500 stores data for driving the security processor 1200. In other words, the password memory 1500 records data to be encrypted or to be decrypted and may store encrypted or decrypted restoration data.

[0105] Exemplary embodiments of the inventive concept provide a random number generator for increasing a range covered by dithering by combining sub-output signals generated by a plurality of sub-nodes and generating a random number based on the combined signal.

[0106] While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as set forth in the following claims.

Claims

1. A random number generator, comprising: a first ring oscillator, the first ring oscillator comprising a first inverter chain, the first inverter chain comprising a plurality of first inverters connected in series, the first ring oscillator being configured to output a plurality of first random signals generated at a plurality of first sub-nodes, each of the plurality of first sub-nodes being located between two adjacent first inverters of the plurality of first inverters; a second ring oscillator, the second ring oscillator comprising a second inverter chain, the second inverter chain comprising a plurality of second inverters connected in series, the second ring oscillator being configured to output a plurality of second random signals generated at a plurality of second sub-nodes, each of the plurality of second sub-nodes being located between two adjacent second inverters of the plurality of second inverters; a third ring oscillator, the third ring oscillator comprising a third inverter chain, the third inverter chain comprising a plurality of third inverters connected in series, the third ring oscillator being configured to output a plurality of third random signals generated at a plurality of third sub-nodes, each of the plurality of third sub-nodes being located between two adjacent third inverters of the plurality of third inverters, wherein the number of the plurality of first inverters, the number of the plurality of second inverters, and the number of the plurality of third inverters are the same; and a signal processing circuit, wherein the signal processing circuit generates a random number by combining the plurality of first random signals, the plurality of second random signals, and the plurality of third random signals, The signal processing circuit includes a plurality of logic elements, each of the plurality of logic elements is configured to: receive a first random signal from a first sub-node among the plurality of first sub-nodes, receive a second random signal from a second sub-node among the plurality of second sub-nodes, receive a third random signal from a third sub-node among the plurality of third sub-nodes, and perform a logic operation on the first random signal, the second random signal and the third random signal to generate a combination signal, wherein a position of the first sub-node in the first ring oscillator, a position of the second sub-node in the second ring oscillator and a position of the third sub-node in the third ring oscillator are the same.

2. The random number generator according to claim 1, wherein: The phase difference between the first random signal, the second random signal and the third random signal is 120 degrees.

3. The random number generator according to claim 1, in, The first random signal, the second random signal and the third random signal all include a jitter region, wherein the logic level in the jitter region jumps at any time, and The jitter region of each of the first random signal, the second random signal and the third random signal is not less than 1 / 6 of the period.

4. The random number generator according to claim 3, wherein: The jitter region of the combined signal generated by combining the first random signal, the second random signal, and the third random signal covers the entire period of the combined signal.

5. The random number generator according to claim 1, wherein: The signal processing circuit further includes: a duty cycle corrector, the duty cycle corrector being used to correct the duty cycle of the combined signal; and A signal sampler is used to generate the random number by sampling the combined signal with the corrected duty cycle.

6. The random number generator according to claim 5, wherein: The logic element includes an XOR gate.

7. The random number generator according to claim 5, wherein: The duty cycle corrector includes a first trigger, which includes a data input terminal and an inverting output terminal connected to each other, and the first trigger is configured to receive the combined signal at a clock input terminal and output the combined signal with a corrected duty cycle to the inverting output terminal.

8. The random number generator according to claim 5, wherein: The signal sampler includes a second trigger, which is used to receive a sampling control signal at a clock input terminal, receive the combined signal with a corrected duty cycle at a data input terminal, and output the random number at a non-inverting output terminal.

9. The random number generator according to claim 1 , further comprising a fourth ring oscillator, the fourth ring oscillator comprising a fourth inverter chain, the fourth inverter chain comprising a plurality of fourth inverters connected in series, in, The first ring oscillator further comprises a multiplexer, wherein the multiplexer is used to set the first ring oscillator to be in a metastable mode or an oscillation mode, wherein the multiplexer forms a first path connecting a first input node to a fourth subnode in the metastable mode, a signal is input to the first inverter chain at the first input node, a signal is output from a first inverter located at the front of the plurality of first inverters at the fourth subnode, and Wherein, in the oscillation mode, a second path connecting the first input node to the first output node is formed, and at the first output node, a signal is output from the fourth inverter located at the rear of the plurality of fourth inverters.

10. The random number generator according to claim 9, in, A first input terminal of the multiplexer is connected to the first output node, a second input terminal of the multiplexer is connected to the fourth child node, and an output terminal of the multiplexer is connected to the first input node, and The multiplexer connects the first input terminal or the second input terminal to one of the first output node and the fourth sub-node in response to a mode control signal.

11. A random number generator, comprising: a first ring oscillator group, the first ring oscillator group comprising a plurality of first ring oscillators, each of the plurality of first ring oscillators being configured to output a plurality of first random signals generated at a plurality of first sub-nodes, each of the plurality of first sub-nodes being located between two adjacent first inverters of a plurality of first inverters, and the plurality of first inverters being included in each of the plurality of first ring oscillators; a second ring oscillator group, the second ring oscillator group comprising a plurality of second ring oscillators, each of the plurality of second ring oscillators being configured to output a plurality of second random signals generated at a plurality of second sub-nodes, each of the plurality of second sub-nodes being located between two adjacent second inverters of a plurality of second inverters, and the plurality of second inverters being included in each of the plurality of second ring oscillators; a third ring oscillator group, the third ring oscillator group comprising a plurality of third ring oscillators, the plurality of third ring oscillators each configured to output a plurality of third random signals generated at a plurality of third sub-nodes, each of the plurality of third sub-nodes being located between two adjacent third inverters of a plurality of third inverters, the plurality of third inverters being included in each of the plurality of third ring oscillators, wherein the number of the plurality of first inverters, the number of the plurality of second inverters, and the number of the plurality of third inverters are the same; and a signal processing circuit, the signal processing circuit being configured to generate a random number based on a combination of the plurality of first random signals, the plurality of second random signals, and the plurality of third random signals, wherein the signal processing circuit comprises a logic circuit, the logic circuit being configured to generate a plurality of output signals by performing a logic operation on the plurality of first random signals, the plurality of second random signals and the plurality of third random signals, and Wherein, generating one of the plurality of output signals comprises: receiving one of the plurality of first random signals from a first sub-node among the plurality of first sub-nodes, receiving one of the plurality of second random signals from a second sub-node among the plurality of second sub-nodes, receiving one of the plurality of third random signals from a third sub-node among the plurality of third sub-nodes, and performing a logic operation on the first random signal, the second random signal and the third random signal to generate a combined signal, wherein a position of the first sub-node in one of the plurality of first ring oscillators, a position of the second sub-node in one of the plurality of second ring oscillators and a position of the third sub-node in one of the plurality of third ring oscillators are the same.

12. The random number generator according to claim 11, wherein: The signal processing circuit further includes: A duty cycle correction circuit, the duty cycle correction circuit is used to correct the duty cycle of each output signal of the plurality of output signals; a sampling circuit for generating a plurality of sub-random numbers by sampling the plurality of output signals having the corrected duty cycle; and A merging circuit is used to generate a random number based on the multiple sub-random numbers.

13. The random number generator according to claim 12, wherein: The logic circuit includes a plurality of XOR gates, each of the plurality of XOR gates being used to generate one of the plurality of output signals by receiving one of the plurality of first random signals, one of the plurality of second random signals, and one of the plurality of third random signals and performing an XOR operation on the received first random signal, the second random signal, and the third random signal.

14. The random number generator according to claim 13, wherein: The duty cycle correction circuit includes a plurality of first triggers, each of which includes a data input terminal and an inverting output terminal connected to each other, and each of which is configured to receive one of the plurality of output signals at a clock input terminal and output the output signal with a corrected duty cycle to the inverting output terminal.

15. The random number generator according to claim 13, wherein: The sampling circuit includes multiple second triggers, each of which is configured to receive a sampling control signal at a clock input terminal, receive one of the multiple output signals with a corrected duty cycle at a data input terminal, and output one of the multiple sub-random numbers to a non-inverting output terminal.

16. The random number generator according to claim 13, wherein: The merging circuit includes at least one logic element configured to receive the plurality of sub-random numbers and generate the random number by performing a logic operation on the plurality of sub-random numbers.

17. A random number generator, comprising: a first inverter chain, the first inverter chain comprising a plurality of first inverters connected in series, each first sub-node of the plurality of first sub-nodes being located between two adjacent first inverters of the plurality of first inverters; a second inverter chain, the second inverter chain comprising a plurality of second inverters connected in series, each second sub-node of the plurality of second sub-nodes being located between two adjacent second inverters of the plurality of second inverters; a third inverter chain, the third inverter chain comprising a plurality of third inverters connected in series, each of a plurality of third sub-nodes being located between two adjacent third inverters of the plurality of third inverters, wherein the number of the plurality of first inverters, the number of the plurality of second inverters and the number of the plurality of third inverters are the same; and a plurality of logic elements, each of the plurality of logic elements being connected to a first sub-node among the plurality of first sub-nodes, a second sub-node among the plurality of second sub-nodes, and a third sub-node among the plurality of third sub-nodes, and the logic element being configured to generate a combined signal by combining a first random signal of the first sub-node, a second random signal of the second sub-node, and a third random signal of the third sub-node, The position of the first subnode in the first inverter chain, the position of the second subnode in the second inverter chain, and the position of the third subnode in the third inverter chain are the same, and The random number is generated by sampling the combined signal.

18. The random number generator according to claim 17, further comprising: a duty cycle corrector, the duty cycle corrector being used to correct the duty cycle of the combined signal output from the logic element; as well as A signal sampler is used to generate a random number by sampling the combined signal including the corrected duty cycle.

19. The random number generator according to claim 17, in, The first random signal, the second random signal, and the third random signal all include a jitter region, wherein a logic level jumps at any time in the jitter region.

20. The random number generator according to claim 17, further comprising: a fourth inverter chain, the fourth inverter chain comprising a plurality of fourth inverters connected in series; as well as a multiplexer connected to the first inverter chain to place the first inverter chain in a metastable mode or an oscillating mode, wherein the multiplexer forms a first path connecting a first input node to a fourth subnode in the metastable mode, a signal is input to the first inverter chain at the first input node, and a signal is output from a first inverter located at the front of the plurality of first inverters at the fourth subnode, wherein a second path connecting the first input node to the first output node is formed in the oscillation mode, and a signal is output from the fourth inverter located at the rear of the plurality of fourth inverters at the first output node, wherein the first input terminal of the multiplexer is connected to the first output node, the second input terminal of the multiplexer is connected to the fourth sub-node, the output terminal of the multiplexer is connected to the first input node, and The multiplexer connects the first input terminal or the second input terminal to one of the first output node and the fourth sub-node in response to a mode control signal.

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