Single-line transmission circuit and single-line transmission circuit for cascade data of diode integrated circuit

Abstract

The embodiments of the present invention disclose a single-line transmission circuit and a single-line transmission circuit for cascade data of a light-emitting diode integrated circuit, comprising a charging module, a voltage level detection module and a latch module; wherein the latch module is used to convert an input pulse signal into a control signal, and to start the charging module according to the control signal; the charging module is used to charge a capacitor according to a preset logic rule; the voltage level detection module is used to judge the capacitor value after charging, and to determine a level logic signal according to the capacitor value; the latch module is also used to receive the level logic signal returned by the voltage level detection module, and output the level logic signal in the form of a single pulse, thereby realizing the shaping of the output signal of the single-line transmission circuit or the breakpoint-resume transmission circuit for cascade data of a light-emitting diode integrated circuit, and can effectively reduce the layout area.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit control, and in particular to a single-line transmission circuit and a single-line transmission circuit for cascaded data of a light-emitting diode integrated circuit. Background Art

[0002] The traditional single-line data transmission method of LED integrated circuit cascade signal is as follows:

[0003] The integrated circuit (IC) receives data from the controller. Since the signal sent by the controller is transmitted to the integrated circuit via only one transmission line in the single-line transmission architecture, each bit of data is defined as consisting of two high and low level bits. The data logic "1" or "0" is determined by the time ratio of the high and low potential levels.

[0004] Each integrated circuit receives the signal sent from the controller, deducts its own display data, and then transmits the rest of the data to the next integrated circuit. During the transmission process, due to changes in the manufacturing process and the influence of line stray capacitance, the signal waveform will have a slight delay when it changes state. However, the rising delay time and falling delay time of the signal waveform are not the same. Once the number of integrated circuits connected increases, the time ratio of the high and low potential levels of the signal may be incorrect, so the data needs to be shaped before it can be transmitted to the next integrated circuit.

[0005] like Figure 1 and Figure 2 As shown, the conventional signal reshaping circuit includes a built-in oscillator to generate an oscillation signal of a fixed frequency, and the oscillation signal is divided by a frequency division process to create a time ratio of the high and low level bits.

[0006] The first disadvantage of this circuit resetting method is that the design accuracy of the oscillator module is very high. Once the oscillation frequency is offset, the reset waveform will be incorrect. The second disadvantage is that due to the high design accuracy requirements, a bandgap reference voltage circuit and a comparator circuit are often used, which occupies a large layout area. Summary of the invention

[0007] In view of the above technical problems, the embodiments of the present invention provide a single-line transmission circuit and a single-line transmission circuit for cascading data of a diode integrated circuit.

[0008] In a first aspect, an embodiment of the present invention provides a single-line transmission circuit, comprising: a charging module, a voltage level detection module and a latch module;

[0009] The latch module is used to convert the input pulse signal into a control signal, and start the charging module according to the control signal;

[0010] The charging module is used to charge the capacitor according to a preset logic rule;

[0011] The voltage level detection module is used to judge the capacitance value after charging and determine the level logic signal according to the capacitance value;

[0012] The latch module is further used for receiving the level logic signal returned by the voltage level detection module, and outputting the level logic signal in the form of a single pulse.

[0013] Optionally, the charging module includes a first charging unit and a second charging unit, wherein the first charging unit uses a first current to charge the capacitor, and the second charging unit uses a second current to charge the capacitor, wherein a current value of the second current is greater than a current value of the first current.

[0014] Optionally, the charging module is used to charge the capacitor according to a preset logic rule, including:

[0015] When the level logic signal is a high level signal, the charging module uses the first charging unit to charge the capacitor;

[0016] When the level logic signal is a low level signal, the charging module uses the second charging unit to charge the capacitor.

[0017] Optionally, the charging module uses the first charging unit to charge the capacitor, including:

[0018] When the first switch is closed, the second switch is closed, and the third switch is opened, the charging module charges the capacitor using a first current.

[0019] Optionally, the charging module uses the second charging unit to charge the capacitor, including:

[0020] When the first switch is closed, the second switch is closed, and the third switch is opened, the charging module charges the capacitor using a second current.

[0021] Optionally, the voltage level detection module is used to judge the capacitance value after charging, and determine the level logic signal according to the capacitance value, including:

[0022] The voltage level detection module determines the capacitance value after charging;

[0023] If the charged capacitance value is less than the preset transition input voltage critical value, a low level signal is output;

[0024] If the charged capacitance value is greater than the preset transition input voltage threshold, a high level signal is output.

[0025] Optionally, the circuit further includes a reset module, and the reset module is used to reset the latch module.

[0026] Optionally, the first switch, the second switch and the third switch are all CMOS tubes.

[0027] Optionally, the latch module includes two NOR gates, and the output ends of the two NOR gates serve as inputs of the other NOR gate respectively.

[0028] In a second aspect, an embodiment of the present invention provides a single-line transmission circuit for cascade data of a light emitting diode integrated circuit, comprising n single-line transmission circuits as described in any one of the first aspect.

[0029] In the technical solution provided by the embodiment of the present invention, a single-line transmission circuit and a single-line transmission circuit of cascade data of a light-emitting diode integrated circuit are provided, including a charging module, a voltage level detection module and a latch module; wherein the latch module is used to convert an input pulse signal into a control signal, and turn on the charging module according to the control signal; the charging module is used to charge the capacitor according to a preset logic rule; the voltage level detection module is used to judge the capacitor value after charging, and determine the level logic signal according to the capacitor value; the latch module is also used to receive the level logic signal returned by the voltage level detection module, and output the level logic signal in the form of a single pulse, thereby realizing the shaping of the output signal of the single-line transmission circuit of cascade data of the light-emitting diode integrated circuit or the breakpoint-resume transmission circuit, and can effectively reduce the layout area. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of a logical method of transmitting data in an integrated circuit in the prior art;

[0031] Figure 2 A schematic diagram of a conventional integrated circuit output signal shaping implementation;

[0032] Figure 3 A schematic diagram of the structure of a single-line transmission circuit provided by an embodiment of the present invention;

[0033] Figure 4 A schematic diagram of a single-line transmission circuit provided by another embodiment of the present invention;

[0034] Figure 5 A circuit diagram of single-line transmission integrated circuit signal shaping provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0036] See also Figure 3 , an embodiment of the present invention provides a single-line transmission circuit, including: a charging module 102, a voltage level detection module 103 and a latch module 101;

[0037] The latch module 101 is used to convert the input pulse signal into a control signal, and start the charging module according to the control signal;

[0038] The charging module 102 is used to charge the capacitor according to a preset logic rule;

[0039] The voltage level detection module 103 is used to determine the capacitance value after charging and determine the level logic signal according to the capacitance value;

[0040] The latch module 101 is further configured to receive the level logic signal returned by the voltage level detection module, and output the level logic signal in the form of a single pulse.

[0041] Specifically, the input part of the entire embodiment circuit has a fixed pulse signal, namely an input pulse signal, and a transmission logic signal. After the fixed pulse signal passes through the latch circuit, namely the latch module, a control signal is generated to open the charging circuit, namely, to turn on the charging module, and the charging module starts to charge the capacitor; the transmission logic signal, namely the level logic signal, is a high level signal maintained when the logic is "1" and a low level signal maintained when the logic is "0" after the previous logic judgment.

[0042] The voltage level detection module 103 is used to judge the capacitance value after charging, determine the level logic signal according to the capacitance value, that is, the transmission logic signal described above, and return the level logic signal to the latch module, thereby outputting a shaped single pulse signal.

[0043] The single-line transmission circuit provided by the embodiment of the present invention includes a charging module, a voltage level detection module and a latch module; wherein the latch module is used to convert an input pulse signal into a control signal and start the charging module according to the control signal; the charging module is used to charge the capacitor according to a preset logic rule; the voltage level detection module is used to judge the capacitor value after charging and determine the level logic signal according to the capacitor value; the latch module is also used to receive the level logic signal returned by the voltage level detection module, and output the level logic signal in the form of a single pulse, thereby realizing the shaping of the output signal of the single-line transmission circuit or the breakpoint-resume transmission circuit of the cascade data of the light-emitting diode integrated circuit, and can effectively reduce the layout area.

[0044] Optionally, the charging module includes a first charging unit and a second charging unit, wherein the first charging unit uses a first current to charge the capacitor, and the second charging unit uses a second current to charge the capacitor, wherein a current value of the second current is greater than a current value of the first current.

[0045] Specifically, the charging module is a dual current charging circuit, which can provide a large current and a small current to charge the capacitor, for example, the current value of the second current is greater than the current value of the first current.

[0046] Optionally, the charging module is used to charge the capacitor according to a preset logic rule, including:

[0047] When the level logic signal is a high level signal, the charging module uses the first charging unit to charge the capacitor;

[0048] When the level logic signal is a low level signal, the charging module uses the second charging unit to charge the capacitor.

[0049] Specifically, the dual current charging circuit charges the capacitor according to the data logic judgment circuit, that is, the preset logic rules. Different data logic judgment circuits will charge the capacitor with different currents, resulting in different high-level times, thereby achieving the output waveform shaping effect.

[0050] Optionally, the charging module uses the first charging unit to charge the capacitor, including:

[0051] When the first switch is closed, the second switch is closed, and the third switch is opened, the charging module charges the capacitor using a first current.

[0052] Optionally, the charging module uses the second charging unit to charge the capacitor, including:

[0053] When the first switch is closed, the second switch is closed, and the third switch is opened, the charging module charges the capacitor using a second current.

[0054] Figure 4 A schematic diagram of a single-line transmission circuit provided by another embodiment of the present invention is shown as follows: Figure 4 As shown, the input signals in this embodiment are a start pulse signal and a transmission logic signal, wherein the start pulse signal is an input pulse signal, and the transmission logic signal is a level logic signal, which has been confirmed through previous logic judgment to maintain a high level signal when logic "1" and a low level signal when logic "0".

[0055] When the input pulse signal passes through the latch circuit, SW1 and SW2 are turned on, VC starts to charge, and when the capacitor voltage reaches the critical value of the input voltage of the voltage level detection circuit, the output changes state and resets the latch circuit to form a single pulse output, where SW1 is the first switch, SW2 is the second switch, and SW3 is the third switch.

[0056] When the transmission logic signal is at a high level, i.e., "1", the switch SW3 is turned off, and the capacitor is only supplied by the first current, i.e., the current I 1 To charge, the capacitor charges slowly, and the VC potential rises slowly from 0V. It takes a longer time to reach the transition input voltage critical value of the voltage level detection circuit, so the circuit generates a wider single pulse width.

[0057] When the transmission logic signal is at a low level "0", the switch SW3 is turned on, and the capacitor is charged by the second current, that is, the current I 1 and I 2 At the same time, the capacitor is charged, the capacitor charges faster, the VC potential rises quickly from 0V, and the time to reach the transition input voltage critical value of the voltage level detection circuit is shorter, so the single pulse width generated by the circuit is narrower.

[0058] Optionally, the voltage level detection module is used to judge the capacitance value after charging, and determine the level logic signal according to the capacitance value, including:

[0059] The voltage level detection module determines the capacitance value after charging;

[0060] If the charged capacitance value is less than the preset transition input voltage critical value, a low level signal is output;

[0061] If the charged capacitance value is greater than the preset transition input voltage threshold, a high level signal is output.

[0062] It should be noted that the preset transition input voltage critical value can be set according to actual needs and is not specifically limited in the embodiment of the present invention.

[0063] For example, if the capacitance value after charging is 2.1V, and the preset transition input voltage threshold value is 3.5V, and 2.1V is less than 3.5V, then a low level signal is output, that is, "0" is output;

[0064] If the capacitor is charged continuously, the capacitance value after charging is 3.7V. At this time, 3.7V is less than 3.5V, so a high-level signal is output, that is, "1".

[0065] Optionally, the circuit further includes a reset module, and the reset module is used to reset the latch module.

[0066] Specifically, the circuit also includes a reset module, which is used to reset the signal of the latch module and start the next round of pulse shaping.

[0067] Optionally, the first switch, the second switch and the third switch are all CMOS tubes.

[0068] Optionally, the latch module includes two NOR gates, and the output ends of the two NOR gates serve as inputs of the other NOR gate respectively.

[0069] Figure 5 A circuit diagram of a single-line transmission integrated circuit signal shaping circuit provided by an embodiment of the present invention, such as Figure 5 As shown, the NOT gate I_11 receives the input pulse signal WIN, the output end of the NOT gate I_11 is connected to the NOR gate, and then connected to each COMS. Finally, the level logic signal I_252_VC3 is returned to the input end of the NOR gate. The output end of the NOR gate is connected to two NOT gates, and the output of the NOT gate is the shaped pulse signal.

[0070] An embodiment of the present invention further provides a single-line transmission circuit for cascade data of a light emitting diode integrated circuit, comprising n single-line transmission circuits as described above, where n is a positive integer greater than 0.

[0071] Specifically, the single-line transmission circuit for cascaded data of the light-emitting diode integrated circuit includes n of any of the above single-line transmission circuits, namely single-line transmission circuit 1, single-line transmission circuit 2...single-line transmission circuit n, D1, D2...Dn are the private data of single-line transmission circuit 1, single-line transmission circuit 2...single-line transmission circuit n, and the number of bits of D1, D2...Dn are all n bits;

[0072] It also includes a controller, which is used to send transmission data C1, C2, D1, D2, ... Dn to the single-line transmission circuit 1; the output end DO of the single-line transmission circuit 1 is connected to the input end DIN of the single-line transmission circuit 2, the output end DO of the single-line transmission circuit 2 is connected to the input end DIN of the single-line transmission circuit 3...the output end DO of the single-line transmission circuit n-1 is connected to the input end DIN of the single-line transmission circuit n;

[0073] The single-line transmission circuit 1 intercepts and stores D1, and then outputs C1C2D2D3…Dn to the single-line transmission circuit 2. The single-line transmission circuit 2 intercepts and stores D2, and then outputs C1C2D3D4…Dn to the single-line transmission circuit 3. The single-line transmission circuit 3 intercepts and stores D3, and then outputs C1C2D4D5…Dn to the integrated circuit 4, … the single-line transmission circuit n-1 intercepts and stores Dn-1 and then outputs C1C2Dn to the single-line transmission circuit Dn.

[0074] An embodiment of the present invention also provides a single-line transmission circuit for cascade data of an LED integrated circuit, comprising a charging module, a voltage level detection module and a latch module; wherein the latch module is used to convert an input pulse signal into a control signal, and to start the charging module according to the control signal; the charging module is used to charge the capacitor according to a preset logic rule; the voltage level detection module is used to judge the capacitor value after charging, and to determine the level logic signal according to the capacitor value; the latch module is also used to receive the level logic signal returned by the voltage level detection module, and output the level logic signal in the form of a single pulse, thereby realizing the shaping of the output signal of the single-line transmission circuit or the breakpoint-resume transmission circuit for cascade data of the LED integrated circuit, and can effectively reduce the layout area.

[0075] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A single-line transmission circuit, characterized in that: include: Charging module, voltage level detection module and latch module; The latch module is used to convert the input pulse signal into a control signal, and start the charging module according to the control signal; The charging module is used to charge the capacitor according to a preset logic rule; The voltage level detection module is used to judge the capacitance value after charging and determine the level logic signal according to the capacitance value; The latch module is also used to receive the level logic signal returned by the voltage level detection module, and output the level logic signal in the form of a single pulse; The charging module comprises a first charging unit and a second charging unit, wherein the first charging unit uses a first current to charge the capacitor, and the second charging unit uses a second current to charge the capacitor, wherein the current value of the second current is greater than the current value of the first current; The charging module is used to charge the capacitor according to a preset logic rule, including: when the level logic signal is a high level signal, the charging module uses the first charging unit to charge the capacitor; When the level logic signal is a low level signal, the charging module uses the second charging unit to charge the capacitor; The circuit further comprises a reset module, and the reset module is used to reset the latch module; The latch module includes two NOR gates, and the output ends of the two NOR gates serve as the inputs of the other NOR gates respectively.

2. The circuit according to claim 1, characterized in that The charging module uses the first charging unit to charge the capacitor, including: when the first switch is turned off, the second switch is turned off, and the third switch is turned on, the charging module uses a first current to charge the capacitor.

3. The circuit according to claim 1, characterized in that The charging module uses the second charging unit to charge the capacitor, including: when the first switch is turned off, the second switch is turned off, and the third switch is turned on, the charging module uses the second current to charge the capacitor.

4. The circuit according to claim 1, characterized in that The voltage level detection module is used to determine the capacitance value after charging, and determine the level logic signal according to the capacitance value, including: the voltage level detection module determines the capacitance value after charging; If the charged capacitance value is less than the preset transition input voltage critical value, a low level signal is output; If the charged capacitance value is greater than the preset transition input voltage threshold value, a high level signal is output.

5. The circuit according to claim 2 or 3, characterized in that: The first switch, the second switch and the third switch are all CMOS tubes.

6. A single-line transmission circuit for cascade data of a light-emitting diode integrated circuit, characterized in that: The invention comprises n single-line transmission circuits as claimed in any one of claims 1 to 5, wherein n is a positive integer greater than 0.

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