A true random number generator

Abstract

The invention discloses a true random number generator, comprising: an XOR circuit and a plurality of random entropy source circuits; each random entropy source circuit comprises: a low-frequency sampling oscillation loop, an XOR unit, N inverters and at least two triggers; N is an odd number greater than 1; the N inverters are connected end to end to form a high-frequency oscillation loop; the input end of each trigger is connected to the output end of the corresponding inverter, the output end of each trigger is connected to the XOR unit, and each trigger corresponds to a different inverter; and all the triggers sample the input ends of all the triggers under the control of a sampling clock signal output by the same low-frequency sampling oscillation loop, and the sampling results are input to the XOR unit for XOR processing; the output of the XOR unit is the output end of each random entropy source circuit, the output ends of all the high-frequency oscillation loops are respectively connected to different input ends of the XOR circuit, and the output end of the XOR circuit outputs a random number sequence, thereby improving the speed of random number generation.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a true random number generator. Background Art

[0002] The random number generator is an important component of the information security system and is widely used in key generation, identity authentication, etc., providing a trusted root for the information security system. Among them, the random number generator refers to a dedicated integrated circuit chip or a random number generation component in the chip that generates unexpected random numbers by collecting random quantities in the natural environment. Usually, the natural random quantity collected by the random number generator is thermal noise, which is provided by the amplifier method, oscillator sampling method and chaos method, and then the true random number required by the system is generated based on the thermal noise.

[0003] Among the commonly used methods of providing thermal noise, the amplifier method is easily affected by the environment in principle and is therefore not widely used. The random number rate generated by the thermal noise provided by the chaos method cannot meet the application of high-speed systems. The oscillator method is more flexible in implementation and can be implemented using either a fully customized digital-analog hybrid circuit or a semi-customized digital method. Therefore, this method is widely used.

[0004] However, with the development of high-speed systems, the requirements for the rate of generating true random numbers are becoming higher and higher. The rate of generating true random numbers by the existing oscillator method cannot meet the requirements of high-speed systems. Summary of the invention

[0005] In view of this, an embodiment of the present application provides a true random number generator, which can improve the generation rate of true random numbers and solve the problem in the prior art that the true random number generation rate cannot meet system requirements.

[0006] A true random number generator provided in an embodiment of the present application includes: an XOR circuit and a plurality of random entropy source circuits; each of the random entropy source circuits includes: a low-frequency sampling oscillation loop, an XOR unit, N inverters and at least two triggers; N is an odd number greater than 1;

[0007] The N inverters are connected end to end to form a high-frequency oscillation loop;

[0008] In each of the random entropy source circuits, the input end of each of the triggers is connected to the output end of the corresponding inverter, the output end of each of the triggers is connected to the XOR unit, and each of the triggers corresponds to a different inverter; and all of the triggers sample the input ends of all of the triggers under the control of the same sampling clock signal output by the low-frequency sampling oscillation loop, and the sampling results are input into the XOR unit for XOR processing;

[0009] The output of the XOR unit is the output end of each of the random entropy source circuits, the output ends of all the high-frequency vibration loops are respectively connected to different input ends of the XOR circuit, and the output end of the XOR circuit outputs a random number sequence.

[0010] Optionally, the sampling clock signal used by each random entropy source circuit is the same clock, and the sampling clock signal used by all random entropy source circuits is the same clock.

[0011] Optionally, each of the random entropy source circuits includes N triggers, and the triggers and the inverters in each of the random entropy source circuits correspond one to one;

[0012] The input end of each trigger is connected to the output end of the corresponding inverter, the clock input end of each trigger is connected to the sampling clock signal output by the low-frequency sampling oscillation loop, and the output end of each trigger is connected to different input ends of the corresponding XOR unit.

[0013] Optionally, the low-frequency sampling oscillation loop included in each of the random entropy source circuits is the same circuit.

[0014] Optionally, the low-frequency sampling oscillation loop included in each of the random entropy source circuits is an independent circuit.

[0015] Compared with the prior art, this application has at least the following advantages:

[0016] In the embodiment of the present application, since multiple random entropy source circuits are used, at the output ends of at least two inverters of the multiple random entropy source circuits, the corresponding triggers are used to sample the entropy source once, and the obtained sampling results are input into the XOR unit for XOR processing, and then the XOR processing results output by all random entropy source circuits are output to the XOR circuit for XOR processing to obtain a random number sequence. Compared with the traditional true random number generator based on phase jitter, the random number generator of this structure is structurally changed from a single tap of each oscillator to a multi-tap structure; under the condition of achieving the same random number quality, the random number generator involved in the present invention can support a higher sampling clock frequency, thereby improving the speed of random number generation. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 The figure is a schematic diagram of the structure of an existing random number generator.

[0019] Figure 2 A schematic diagram of the structure of a true random number generator provided in an embodiment of the present application.

[0020] Figure 3 This is a schematic diagram of the structure of a high-frequency oscillation loop.

[0021] Figure 4 A schematic diagram of the structure of a random entropy source circuit in a true random number generator provided in a specific embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0023] To facilitate understanding, we first introduce the specific working principle of the true random number generator implemented using the oscillator method.

[0024] See also Figure 1 , which is a schematic diagram of the structure of an existing true random number generator.

[0025] The D end of the D flip-flop is connected to the high-frequency oscillation signal generated by the high-frequency oscillator, the clock signal end of the D flip-flop is connected to the low-frequency clock signal, and the output end of the D flip-flop outputs a random sequence. The high-frequency oscillation signal is sampled using the low-frequency clock signal with jitter, or the high-frequency oscillation signal with jitter is sampled using the low-frequency clock signal to obtain a true random number.

[0026] Taking the use of a low-frequency clock signal to sample a high-frequency oscillation signal with jitter to obtain a true random number as an example, since the output of a true random number requires that the data sampled in each sampling period of the low-frequency clock signal is random, the period of the low-frequency clock signal must be greater than the variation of the high-frequency oscillation signal, that is, the period of the low-frequency clock signal is greater than the phase deviation of the high-frequency oscillation signal. In some current technologies, due to the large phase deviation of the high-frequency oscillation signal generated by the high-frequency oscillator, the period of the low-frequency clock signal is large and the sampling frequency is low, which also makes the rate of generating true random numbers low and cannot meet the needs of high-frequency systems.

[0027] To this end, an embodiment of the present application provides a true random number generator, which converts a high-frequency oscillation loop with a single output into a high-frequency oscillation loop with multiple outputs by performing multiple sampling processes on a ring oscillator that generates a high-frequency oscillation signal. The phase deviation between the multiple output signals of the high-frequency oscillation loop is smaller than the phase deviation of the overall output of the ring oscillator with a single output, and the period of the required low-frequency clock signal can be correspondingly reduced, thereby increasing the sampling frequency and the generation rate of true random numbers, so that the random number generation rate of the true random number generator can meet the requirements of the high-frequency system.

[0028] Based on the above ideas, in order to make the above objects, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.

[0029] See also Figure 2 , which is a schematic diagram of the structure of a true random number generator provided in an embodiment of the present application.

[0030] The true random number generator provided in the embodiment of the present application includes: an XOR circuit 100 and a plurality of random entropy source circuits 200; each random entropy source circuit 200 includes: a low-frequency sampling oscillation loop Sample OSC, an XOR unit 201, N inverters Inv and at least two triggers 202; N is an odd number greater than 1;

[0031] N inverters Inv are connected end to end to form a high-frequency oscillation loop.

[0032] In the embodiment of the present application, the high-frequency oscillation loop is formed by connecting an odd number of inverters end to end using the inherent transmission delay time of the gate circuit, and the source of the thermal noise is the delay of the inverter flipping in the high-frequency oscillation loop 201 (i.e., the delay time of the inverter). Figure 3 An example is shown of a high-frequency oscillation loop structure including three inverters. In practical applications, N can be any odd number greater than 1, such as 5, 7, 9, 11, 13, etc., and this application does not limit this.

[0033] by Figure 3 Taking the three inverters shown as an example, the output of inverter A is connected to the input of inverter B, the output of inverter B is connected to the input of inverter C, and the output of inverter C is connected to the input of inverter A. An output signal can be derived from any of the connection positions.

[0034] Assuming that at a certain time T0, the input of inverter A becomes high level, then the output of inverter A (that is, the input of inverter B) becomes low level after the inverter delay time ΔT (at time T=T0+ΔT), and after time T=T0+2ΔT, the output of inverter B (that is, the input of inverter C) becomes high level, and after time T=T0+3ΔT, the output of inverter C (that is, the input of inverter A) changes from high level to low level, and at this time, the level of the input of inverter A is exactly opposite to that at time T0; and so on, after time T=T0+6ΔT, the input of inverter A changes back to high level to complete one cycle of oscillation, and so on. That is, the oscillation period of the high-frequency oscillation loop 201 is equal to twice the product of the delay time of a single inverter and the number of inverters.

[0035] In each random entropy source circuit 200, the input end of each trigger 202 is connected to the output end of the corresponding inverter Inv, the output end of each trigger 202 is connected to the XOR unit 201, and each trigger 202 corresponds to a different inverter Inv; and all the triggers 202 sample the input ends of all the triggers 202 under the control of the sampling clock signal fs output by the same low-frequency sampling oscillation loop Sample OSC, and the sampling results are input to the XOR unit 201 for XOR processing;

[0036] The output of the XOR unit 201 is the output end of each random entropy source circuit 200. The output ends of all high-frequency vibration loops 200 are respectively connected to different input ends of the XOR circuit 100. The output end of the XOR circuit 100 outputs a random number sequence.

[0037] In the embodiment of the present application, the sampling clock signal fs is a low-frequency clock signal, which is used to sample the input terminals of all triggers 202. Generating true random numbers requires ensuring that the data sampled in each sampling cycle of the sampling clock signal fs is random, and the cycle of the sampling clock signal fs must be greater than the change of the random source (i.e., the input terminal of the trigger 202). Since multiple triggers 202 sample multiple different inverters Inv, the change frequency of the random source is faster than that of the prior art. Figure 3 In the high-frequency oscillation loop shown, the phase deviation between the level state of the output end of inverter A and the level state of the output end of inverter B is equal to the delay time of one inverter (i.e., inverter B), which is much smaller than the phase deviation of the level state of the output end of inverter C, i.e., the sum of the delay times of three inverters. The input ends of all triggers 202 can be sampled using a sampling clock signal fs with a smaller period, and a random number sequence can be obtained after XOR processing by the XOR unit 201 and the XOR circuit 100, thereby increasing the sampling rate and thus increasing the rate of generating true random numbers.

[0038] It is understandable that the main method to measure the quality of a true random number generator is first to measure the entropy of the random number. At the information theory level, entropy is a measure of uncertainty, and bits can be used as its unit. The closer the entropy is to 1, the better the quality of the random number, and the better the random number. To this end, in some possible implementations of the embodiments of the present application, each random entropy source circuit 200 may include N triggers 202, and each random entropy source circuit 200 has a one-to-one correspondence with the trigger 202 and the inverter Inv;

[0039] The input end of each trigger 200 is connected to the output end of the corresponding inverter Inv, the clock input end of each trigger is connected to the sampling clock signal fs output by the low-frequency sampling oscillation loop Sample OSC, the output end of each trigger 202 is connected to the different input ends of the corresponding XOR unit 201, and the entropy source is sampled once at the output end of each inverter of the random entropy source circuit 200.

[0040] Figure 4 Taking N equal to 3 as an example, the circuit topology of a random entropy source circuit provided in a specific embodiment of the present application is shown.

[0041] In one example, the flip-flop 202 may be a D flip-flop. The sampling clock signal fs used by each random entropy source circuit 200 is the same clock, and the sampling clock signal fs used by all random entropy source circuits is the same clock.

[0042] Optionally, the low-frequency sampling oscillation loop Sample OSC included in each random entropy source circuit 200 is the same circuit, or the low-frequency sampling oscillation loop Sample OSC included in each random entropy source circuit 200 is a different circuit.

[0043] In the embodiment of the present application, since multiple random entropy source circuits are used, at the output ends of at least two inverters of the multiple random entropy source circuits, the corresponding triggers are used to sample the entropy source once, and the obtained sampling results are input into the XOR unit for XOR processing, and then the XOR processing results output by all random entropy source circuits are output to the XOR circuit for XOR processing to obtain a random number sequence. Compared with the traditional true random number generator based on phase jitter, the random number generator of this structure is structurally changed from a single tap of each oscillator to a multi-tap structure; under the condition of achieving the same random number quality, the random number generator involved in the present invention can support a higher sampling clock frequency, thereby improving the speed of random number generation.

[0044] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple. For the sake of ease of explanation, the attached drawings only illustrate two sampling branches and a sampling module including two D flip-flops as an example, which should not be regarded as limiting the scope of protection of the present application. In practical applications, the number of flip-flops included in the true random number generator can be specifically set according to requirements such as the quality of random numbers, the rate at which random numbers are generated, the chip area, and whether the implementation method is simple, and they are not listed one by one here.

[0045] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0046] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0047] The above is only a preferred embodiment of the present application and does not constitute any formal limitation to the present application. Although the present application has been disclosed as above with a preferred embodiment, it is not intended to limit the present application. Any technician familiar with the art can make many possible changes and modifications to the technical solution of the present application using the methods and technical contents disclosed above without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of protection of the technical solution of the present application.

Claims

1. A true random number generator, characterized in that: include: XOR circuit and multiple random entropy source circuits; Each of the random entropy source circuits comprises: a low-frequency sampling oscillation loop, an XOR unit, N inverters and at least two triggers; N is an odd number greater than 1; By utilizing the inherent transmission delay time of the gate circuit, the N inverters are connected end to end to form a high-frequency oscillation loop; In each of the random entropy source circuits, the input end of each of the triggers is connected to the output end of the corresponding inverter in the high-frequency oscillation loop, the output end of each of the triggers is connected to the XOR unit, and each of the triggers corresponds to a different inverter; and all of the triggers sample the input ends of all of the triggers under the control of the same sampling clock signal output by the low-frequency sampling oscillation loop, and the sampling results are input into the XOR unit for XOR processing; The output of the XOR unit is the output end of each of the random entropy source circuits, the output ends of all the high-frequency oscillation loops are respectively connected to different input ends of the XOR circuit, and the output end of the XOR circuit outputs a random number sequence.

2. The true random number generator according to claim 1, characterized in that: The sampling clock signal used by each random entropy source circuit is the same clock, and the sampling clock signal used by all random entropy source circuits is the same clock.

3. The true random number generator according to claim 1, characterized in that: Each of the random entropy source circuits includes N triggers, and the triggers and inverters in each of the random entropy source circuits correspond one to one; The input end of each trigger is connected to the output end of the corresponding inverter, the clock input end of each trigger is connected to the sampling clock signal output by the low-frequency sampling oscillation loop, and the output end of each trigger is connected to different input ends of the corresponding XOR unit.

4. The true random number generator according to claim 1, characterized in that: The low-frequency sampling oscillation loop included in each of the random entropy source circuits is the same circuit.

5. The true random number generator according to claim 1, characterized in that: The low-frequency sampling oscillation loop included in each of the random entropy source circuits is an independent circuit.

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