Fan-out wafer-level packaging structure and manufacturing method thereof

Abstract

Provided is a fan-out wafer-level packaging structure and a manufacturing method thereof, the method comprising: providing a supporting wafer layer, forming an adhesive layer on the supporting wafer layer; bonding a plurality of bare chips to the surface of the adhesive layer, the bare chips having pins, the pins facing the surface of the adhesive layer; forming a pre-curing layer on the side of the adhesive layer and the bare chips away from the supporting wafer layer, the pre-curing layer covering the bare chips; forming a curing layer on the side of the pre-curing layer away from the supporting wafer layer; removing the supporting wafer layer and the adhesive layer to expose the pins of the bare chips; forming a redistribution layer on the surface of the side where the pins of the bare chips are exposed, and forming ball pins on the redistribution layer; grinding the curing layer to a predetermined thickness; cutting to form a fan-out wafer-level packaging structure; wherein the curing layer and the pre-curing layer have different thermal expansion coefficients, and the curing layer and the bare chips have the same thermal expansion coefficient. The packaging structure produced by this method reduces the warping of the wafer in the fan-out wafer-level packaging process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor chip packaging, and in particular to a fan-out wafer-level packaging structure and a manufacturing method thereof. Background Art

[0002] In the development of the manufacturing process of dynamic random access memory (DRAM), a DRAM packaging structure 100 (such as Figure 1A The DRAM package structure is packaged as shown in FIG. 1 , including a bare die 101, a plastic layer 102, and pins 103. For the opening 110, the design of the pad position on the bare die 101 has strict requirements and needs to match the manufacturing capacity of the substrate factory. In addition, the DRAM package structure using the WBGA method needs to transmit signals through the substrate, and the thickness of the DRAM package structure and the metal wiring lines in the substrate have strict requirements.

[0003] The fan-out wafer-level packaging structure in the related art (such as Figure 1B As shown in FIG. 1 , the die 101 ′, the plastic layer 102 ′ and the ball pin 103 ′ are included. Since the thermal expansion coefficients of the plastic layer and the die are quite different, the whole structure is prone to warping after the plastic layer is formed, which increases the difficulty of forming the redistribution layer and the ball pin process.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] In view of the above problems, the present invention provides a fan-out wafer-level packaging structure and a manufacturing method thereof, thereby solving the bottleneck of substrate design and the warping problem of the fan-out wafer-level packaging structure to a certain extent.

[0006] The present invention provides a method for manufacturing a fan-out wafer-level packaging structure, comprising: providing a supporting wafer layer, forming an adhesive layer on the supporting wafer layer; bonding a plurality of bare chips to the surface of the adhesive layer, wherein the bare chips have pins, and the pins face the surface of the adhesive layer; forming a pre-curing layer on the side of the adhesive layer and the bare chips away from the supporting wafer layer, wherein the pre-curing layer covers the bare chips; forming a curing layer on the side of the pre-curing layer away from the supporting wafer layer; removing the supporting wafer layer and the adhesive layer to expose the pins of the bare chips; forming a redistribution layer on the surface of the side where the pins of the bare chips are exposed, and forming spherical pins on the redistribution layer; grinding the curing layer to a predetermined thickness; and cutting to form a fan-out wafer-level packaging structure; wherein the curing layer and the pre-curing layer have different thermal expansion coefficients, and the curing layer and the bare chips have the same thermal expansion coefficient.

[0007] In some embodiments of the present invention, the step of forming a pre-cured layer includes: laminating the pre-cured layer to the adhesive layer and the side of the bare chip away from the supporting wafer layer at 100-120°C for 1 minute; after laminating, pre-curing at 100-120°C for 0.5-1.5 hours.

[0008] In some embodiments of the present invention, the temperature for forming the solidified layer on the side of the pre-solidified layer away from the supporting wafer layer is between 150 and 200° C. and the time is 1 to 3 hours.

[0009] In some embodiments of the present invention, the thickness of the pre-cured layer is 200-250 μm, and the predetermined thickness of the cured layer is 200-400 μm.

[0010] In some embodiments of the present invention, the pre-cured layer is an epoxy molding compound, and the cured layer is a silicon wafer.

[0011] Applying the above manufacturing method, the present invention also provides a fan-out wafer-level packaging structure, comprising: a bare chip, a pre-curing layer, a redistribution layer, a plurality of ball pins and a curing layer. The bare chip has pins; the pre-curing layer covers and envelops the bare chip, and one side of the bare chip's pins exposes the surface of the pre-curing layer; the redistribution layer is formed on the side where the bare chip's pins are exposed, and the redistribution layer includes a passivation layer and a metal layer; a plurality of ball pins are formed on the redistribution layer, and the ball pins are electrically connected to the bare chip's pins through the metal layer; the curing layer is formed on the side of the pre-curing layer away from the redistribution layer, covering the pre-curing layer; wherein the curing layer and the pre-curing layer have different thermal expansion coefficients, and the curing layer and the bare chip have the same thermal expansion coefficient.

[0012] In some embodiments of the present invention, the pre-cured layer is an epoxy molding compound, and the cured layer is a silicon wafer.

[0013] In some embodiments of the present invention, the thickness of the pre-cured layer is 200-250 μm.

[0014] In some embodiments of the present invention, the thickness of the solidified layer is 200-400 μm.

[0015] In some embodiments of the invention, the die is a dynamic random access memory.

[0016] The beneficial effect of the present invention is that the packaging method utilizes fan-out wafer-level packaging technology for rewiring, and performs a ball planting process on the rewiring opening, replacing the substrate design, patch, wiring and other processes in the traditional packaging, which can improve the transmission performance of the packaging structure, reduce the size of the packaging structure, and avoid the bottleneck of substrate design in the traditional WBGA packaging method. In addition, the method of the present invention reduces the warping of the wafer in the fan-out wafer-level packaging process, especially in the process of forming the rewiring layer and the solder ball pins, by applying an extra curing layer on the pre-curing layer, reducing the difficulty of subsequent processes, and also reducing the warping of the packaging structure after cutting, which is beneficial to the subsequent re-packaging process. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1A FIG. 1 is a schematic diagram of a WBGA DRAM packaging structure in the prior art.

[0018] Figure 1B It is a schematic diagram of a conventional fan-out wafer-level packaging structure in the prior art.

[0019] Figure 1C Schematic diagram of a conventional fan-out wafer-level packaging structure warping in the prior art.

[0020] Figure 2A-2I It is a schematic diagram of the states of the fan-out wafer-level packaging structure of the present invention in various steps of the manufacturing method.

[0021] Figure 3 A fan-out wafer-level packaging structure is manufactured by applying the manufacturing method of the fan-out wafer-level packaging structure of the present invention.

[0022] Figure 4 The figure is a flow chart of an embodiment of a method for manufacturing a fan-out wafer-level packaging structure of the present invention. DETAILED DESCRIPTION

[0023] The following is an explanation of the implementation methods of the "manufacturing method of a fan-out wafer-level packaging structure" and the "fan-out wafer-level packaging structure" disclosed in the present invention through specific examples. Those skilled in the art can understand the advantages and effects of the present invention from the contents disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed in various ways based on different viewpoints and applications without departing from the concept of the present invention. The following implementation methods will further explain the relevant technical contents of the present invention in detail, but the disclosed contents are not intended to limit the scope of protection of the present invention.

[0024] The present invention provides a method for manufacturing a fan-out wafer-level packaging structure. Figure 2A-2I as well as Figure 4 . Figure 2A-2I Schematic diagram of the fan-out wafer-level packaging structure of the present invention in various steps of the manufacturing method. The manufacturing method is performed on a component 200 to be processed. The specific steps are as follows:

[0025] Step S101: providing a supporting wafer layer, and forming an adhesive layer on the supporting wafer layer.

[0026] like Figure 2A As shown, a supporting wafer layer 207 is provided, and an adhesive is applied on one side surface of the supporting wafer layer 207 to form an adhesive layer 208. The adhesive layer 208 should completely cover the surface of the supporting wafer layer 207. Then, alignment marks are made, and multiple alignment marks are set at the same predetermined distance according to the bare chip specifications. The supporting wafer layer 207 can be selected as transparent glass or silicon wafer, and there are incision marks on the supporting wafer layer 207. The adhesive layer 208 can be silicone, and those skilled in the art can select a suitable material according to actual needs.

[0027] Step 102 . Bond a plurality of dies to the surface of the adhesive layer.

[0028] like Figure 2B As shown, a plurality of pre-cut single dies 201 are bonded to the surface of the adhesive layer 208, and each die 201 is bonded to a designated position according to the previous alignment mark to form a predetermined arrangement. The die has pins, and the pins face the surface of the adhesive layer. The spacing distance between the dies 201 is 80 to 120 μm, for example, the spacing distance between the dies 201 is 90 μm, 100 μm or 110 μm. The present disclosure does not make specific restrictions on this.

[0029] Step S103: forming a pre-curing layer on the adhesive layer and the side of the die away from the supporting wafer layer.

[0030] like Figure 2CAs shown, the epoxy molding compound (EMC) layer is bonded to the surface of the supporting wafer layer through an adhesive layer to form a pre-cured layer 202. The pre-cured layer 202 covers the previously bonded multiple single bare chips 201. Specifically, the pre-curing step S103 is performed in a vacuum operating chamber. First, the EMC layer is attached to the surface of the supporting wafer layer 207 through an adhesive layer 208 to cover and encapsulate the previously bonded multiple single bare chips 201. The EMC layer is attached within 1 minute at 100 to 120°C. Thereafter, the pre-curing is performed for 0.5 to 1.5 hours at a temperature of 100 to 120°C, thereby completing the pre-curing of the epoxy molding compound. In one embodiment of the present disclosure, the EMC layer is attached at 110°C and then pre-cured for 1 hour at 110°C. The pre-cured epoxy molding compound is in the form of a solid colloid. The thickness of the pre-curing layer can be 200 to 250 μm, for example, the thickness of the pre-curing layer can be 210 μm, 220 μm, 230 μm or 240 μm. Those skilled in the art can select a suitable thickness according to actual needs, and the present disclosure does not limit this. During the pre-curing process, by observing from bottom to top, that is, observing from the supporting wafer layer 207 to the pre-curing layer 202, if there are no bubbles between the bare die 201 and the EMC that forms the pre-curing layer and covers the bare die 201, it can be considered that the pre-curing step is completed.

[0031] Step S104: forming a solidified layer on a side of the pre-solidified layer away from the supporting wafer layer.

[0032] like Figure 2D As shown, a curing layer 204 is formed on one side of the pre-curing layer 202 away from the supporting wafer layer 207, and the curing layer 204 completely covers the pre-curing layer 202, and then the curing is performed. In some preferred embodiments, a silicon wafer is selected as the curing layer 202. Those skilled in the art may also select other materials as the curing layer according to actual needs. The curing step S104 is performed in the above-mentioned vacuum operating chamber, and the curing layer 204 is attached to the surface of the pre-curing layer 202, completely covering the pre-curing layer 202, and maintained at 150-200°C for about 1-3 hours, that is, the curing is completed. For example, at 180°C, the curing is performed for 2 hours. The thickness of the curing layer can be 750-850μm, for example, the thickness of the curing layer can be 800μm. Those skilled in the art may select a suitable thickness according to actual needs. Since some volatiles that are not completely volatilized are still present in the EMC in the pre-curing step, the curing layer can form a bond when attached to the silicon wafer. After the volatiles are completely volatilized, the curing is completely formed. A cured layer is formed on the surface of the pre-cured layer. Since the thermal expansion coefficient of the cured layer and the bare chip are the same, the warping of the entire wafer is reduced, and the difficulty of the subsequent process of forming a redistribution layer and ball pins is reduced.

[0033] Step S105: Remove the support wafer layer and the adhesive layer. Figure 2EAs shown, the support wafer layer 207 and the adhesive layer 208 are removed to expose the pins 2011 of the bare chips 201 arranged in the pre-cured layer 202. Afterwards, the exposed bare chips 201 are cleaned to ensure that there is no adhesive layer residue on the surface of the pins 2011 of the bare chips 201.

[0034] Step S106: Form a redistribution layer on a surface of the side where the pins of the die are exposed.

[0035] like Figure 2F As shown, a first passivation layer is deposited on the surface of one side of the pre-cured layer 202 exposing the die pin 2011, and then a groove is formed by photolithography, development and etching methods, the groove exposing the die pin 2011, and then a metal is deposited in the groove to form a metal layer, and finally a second passivation layer is deposited on the surface of the metal layer and the surface of the first passivation layer, and finally a redistribution layer 205 is formed. The redistribution layer includes a first passivation layer, a second passivation layer and a metal layer. The method of depositing the first passivation layer and the second passivation layer can be chemical vapor deposition or atomic layer deposition. The material of the passivation layer can be polyimide. The method of depositing the metal layer can be physical vapor deposition or electroplating. The material of the metal layer can be one of copper, aluminum, tungsten, etc. or an alloy material of the above materials. The present disclosure does not limit this.

[0036] In one embodiment of the present disclosure, the thickness of the first passivation layer and the second passivation layer is 5 to 10 μm, for example, 6 μm, 7 μm, 8 μm or 9 μm. The thickness of the first passivation layer and the second passivation layer may be the same or different. The thickness of the metal layer is between 3 and 5 μm, for example, 4 μm. The present disclosure does not limit this.

[0037] Step S107: Forming ball contacts on the redistribution layer.

[0038] like Figure 2G As shown, solder balls are soldered to the surface of the redistribution layer 205 and connected to the exposed bare chip pins 2011 to form ball pins 203. In one embodiment of the present disclosure, the ball implantation method can be selected from the methods of using a ball implanter, a template, a solder paste brush or manual mounting according to actual needs.

[0039] S108. Grind the solidified layer to a predetermined thickness.

[0040] like Figure 2H As shown, a mechanical polishing method is used to grind the side of the solidified layer away from the ball pin, so that the solidified layer 204 is polished to a predetermined thickness to meet the packaging specifications. The thickness of the solidified layer after grinding is between 200 and 400 μm. For example, the thickness of the solidified layer can be 250 μm, 300 μm or 350 μm. Those skilled in the art can select a suitable thickness according to actual needs. The present disclosure does not limit this.

[0041] S109. Cutting to form a fan-out wafer-level packaging structure.

[0042] like Fig.2I As shown, the polished component 200 to be processed is measured and marked, and then cut according to the mark, as shown in FIG. Fig.2I The element to be processed 200 is cut into the following shapes by laser or diamond cutting: Figure 3 The fan-out wafer-level packaging structure 300 including a single die is shown. Those skilled in the art may also select other cutting methods according to actual needs. The fan-out wafer-level packaging structure 300 includes a single die 301, a pre-curing layer 302, a die pin 303, a curing layer 304, and a redistribution layer 305.

[0043] In some embodiments, the manufacturing method is used to manufacture a package structure of a dynamic random access memory, that is, the die 201 / 301 is a dynamic random access memory.

[0044] In the above-described process, in order to carry out subsequent steps and ensure the electrical performance of the fan-out wafer-level packaging structure, it is necessary to clean the surface of the die after removing the adhesive layer and the supporting die layer after the support removal step S105. Usually, the cleaning step is performed after the support removal step S105 and before the passivation wiring step S106. A cleaning agent is used to remove the residues of the adhesive layer and the supporting wafer layer on the surface of the pre-cured layer, so that the exposed part of the die is kept clean to ensure the electrical performance. For example, the cleaning method can be water washing, and the cleaning agent is selected as water.

[0045] The above is the manufacturing method of the fan-out wafer-level packaging structure of the present invention. The method uses fan-out wafer-level packaging technology to replace the substrate design, patch and other processes in traditional packaging, which can improve the transmission performance of the fan-out wafer-level packaging structure and reduce the size of the fan-out wafer-level packaging structure, avoiding the bottleneck of substrate design in the traditional WBGA packaging method. In addition, the method of the present invention reduces the warping of the wafer in the fan-out wafer-level packaging process, especially in the process of forming the redistribution layer and the solder ball pins, by applying an extra curing layer on the pre-curing layer, reducing the difficulty of subsequent processes, and also reducing the warping of the fan-out wafer-level packaging structure after cutting, which is beneficial to the subsequent re-packaging process.

[0046] Applying the manufacturing method of the present invention, the present invention also provides a fan-out fan-out type wafer level packaging structure, see Figure 3 .like Figure 3As shown, the fan-out wafer-level packaging structure 300 includes: a bare die 301, a pre-curing layer 302, a redistribution layer 305, ball pins 303 and a curing layer 304. The redistribution layer 305 includes a passivation layer and a metal layer. The pre-curing layer 302 is generally an epoxy molding compound, which covers and encapsulates the bare die 301, and the pin side of the bare die 301 exposes the surface of the pre-curing layer 302. The redistribution layer 305 is formed on the side of the pre-curing layer 302 where the pins of the bare die 301 are exposed, and is connected to the pins of the bare die 301. A plurality of ball pins 303 are formed on the redistribution layer 305. The curing layer 304 is formed on the side of the pre-curing layer away from the redistribution layer, and completely covers the pre-curing layer 302. The curing layer 304 has a different thermal expansion coefficient from the pre-curing layer 302, and the curing layer 304 has the same thermal expansion coefficient as the bare die 301.

[0047] The main difference between the fan-out wafer-level packaging structure and the packaging structure of the traditional WBGA packaging is that a curing layer with a different thermal expansion coefficient from the EMC and the same thermal expansion coefficient as the bare chip is applied on the EMC layer (precuring layer in the present disclosure). The EMC layer is precured first, and then the curing layer is bonded and then the secondary curing is performed. Due to the double-layer curing, the packaging process is also different from the traditional fan-out wafer-level packaging process. First, the arrangement of the bare chip 201 / 301 is achieved by bonding on the surface of a supporting wafer layer 207 to which an adhesive layer 208 is applied. Then, the EMC is attached to the surface of the supporting wafer layer 207 through the adhesive layer 208, covering and encapsulating the previously bonded multiple single bare chips 201 / 301, and the precuring is completed under the set temperature and pressure conditions for a period of time. The precured EMC is in the form of a solid colloid. After the precuring is completed, the curing layer 204 is attached to the surface of the precuring layer 202, completely covering the precuring layer 202, and the curing is completed under the set temperature and pressure conditions for a period of time. After curing, the supporting chip layer and adhesive layer are removed, and then the subsequent steps such as laying the redistribution layer, planting balls, grinding, and cutting are carried out.

[0048] In some preferred embodiments, a silicon wafer is selected as the curing layer 304. Those skilled in the art may also select other materials as the curing layer according to actual needs. The thickness of the curing layer 304 is preferably 200 to 400 μm. The thickness of the pre-curing layer 302 is preferably 200 to 250 μm. Those skilled in the art may select the corresponding thickness according to actual needs to meet the packaging standards.

[0049] In some embodiments, the fan-out wafer-level packaging structure is a packaging structure of a dynamic random access memory, that is, the bare chip 301 is a dynamic random access memory.

[0050] The beneficial effect of this fan-out wafer-level packaging structure is that it replaces the substrate design, patch and other processes in the traditional packaging, can improve the transmission performance of the packaging structure, and reduce the size of the packaging structure, avoiding the bottleneck of the substrate design in the traditional WBGA packaging method. In addition, the packaging structure of the present invention reduces the warping of the wafer in the fan-out wafer-level packaging process, especially in the process of forming the redistribution layer and the solder ball pins, by applying an extra curing layer on the pre-curing layer, reducing the difficulty of subsequent processes, and also reducing the warping of the packaging structure after cutting, which is beneficial to the subsequent re-packaging process.

[0051] The above are some embodiments of the fan-out wafer-level packaging structure and its manufacturing method provided by the present invention. Through the description of the embodiments, it is believed that those skilled in the art can understand the technical solution of the present invention and its operating principle. However, the above is only a preferred embodiment of the present invention and does not limit the present invention. Those skilled in the art may make appropriate modifications to the technical solution provided by the present invention according to actual needs, and the modifications and equivalent transformations made shall not depart from the scope of protection claimed by the present invention. The scope of rights claimed for protection by the present invention shall be subject to the attached claims.

Claims

1. A method for manufacturing a fan-out wafer-level packaging structure, characterized in that: include: providing a supporting wafer layer, and forming an adhesive layer on the supporting wafer layer; bonding a plurality of dies to the surface of the adhesive layer, the dies having pins, the pins facing the surface of the adhesive layer; forming a pre-curing layer on the adhesive layer and the side of the die away from the supporting wafer layer, wherein the pre-curing layer covers the die; forming a solidified layer on a side of the pre-solidified layer away from the supporting wafer layer; removing the supporting wafer layer and the adhesive layer to expose the pins of the die; Forming a redistribution layer on a surface of one side of the die where the pins are exposed, and forming ball pins on the redistribution layer; grinding the solidified layer to a predetermined thickness; Cutting to form the fan-out wafer-level packaging structure; The cured layer and the pre-cured layer have different thermal expansion coefficients, and the cured layer and the die have the same thermal expansion coefficient.

2. The method for manufacturing a fan-out wafer-level packaging structure according to claim 1, characterized in that: The step of forming the pre-cured layer comprises: At 100-120° C., laminating the pre-cured layer to the adhesive layer and the side of the die away from the supporting wafer layer for 1 minute; After lamination, pre-cure at 100~120℃ for 0.5~1.5h.

3. The method for manufacturing a fan-out wafer-level packaging structure according to claim 1, characterized in that: The temperature for forming the solidified layer on the side of the pre-solidified layer away from the supporting wafer layer is between 150 and 200° C. and the time is 1 to 3 hours.

4. The method for manufacturing a fan-out wafer-level packaging structure according to claim 1, characterized in that: The thickness of the pre-cured layer is 200-250 μm, and the predetermined thickness of the cured layer is 200-400 μm.

5. The method for manufacturing a fan-out wafer-level packaging structure according to claim 1, characterized in that: The pre-cured layer is an epoxy molding compound, and the cured layer is a silicon wafer.

6. A fan-out wafer-level packaging structure, characterized in that: include: A bare die having pins; A pre-curing layer, wherein the pre-curing layer covers and encapsulates the bare die, and the pin side of the bare die exposes the surface of the pre-curing layer; A redistribution layer, the redistribution layer is formed on a side of the bare chip where the pins are exposed, the redistribution layer comprising a first passivation layer, a second passivation layer and a metal layer; A plurality of ball pins are formed on the redistribution layer, and the ball pins are electrically connected to the pins of the bare chip through the metal layer; as well as A solidified layer, the solidified layer is formed on a side of the pre-cured layer away from the redistribution layer, and the solidified layer covers the pre-cured layer; The cured layer and the pre-cured layer have different thermal expansion coefficients, and the cured layer and the die have the same thermal expansion coefficient.

7. The fan-out wafer-level packaging structure according to claim 6, characterized in that: The pre-cured layer is an epoxy molding compound, and the cured layer is a silicon wafer.

8. The fan-out wafer-level packaging structure according to claim 6, characterized in that: The thickness of the pre-cured layer is 200-250 μm.

9. The fan-out wafer-level packaging structure according to claim 6, characterized in that: The thickness of the solidified layer is 200-400 μm.

10. The fan-out wafer-level packaging structure according to claim 6, characterized in that: The die is a dynamic random access memory.

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