Integrated Circuit Devices

Abstract

An integrated circuit (IC) device is provided, the IC device comprising: a line structure, comprising a conductive line formed on a substrate and an insulating cover pattern covering the conductive line; an insulating spacer covering a side wall of the line structure; a conductive plug separated from the conductive line in a first horizontal direction, the insulating spacer being located between the conductive plug and the conductive line; a conductive bonding pad arranged on the conductive plug to vertically overlap the conductive plug; and a cover layer, comprising a first portion located between the conductive bonding pad and the insulating cover pattern, wherein the first portion of the cover layer has a shape located between the conductive bonding pad and the insulating cover pattern, wherein a width in the first horizontal direction gradually increases with increasing distance from the substrate.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2018-0163310 filed on December 17, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The inventive concept relates to an integrated circuit (IC) device, and more particularly, to an IC device including a plurality of conductive patterns adjacent to each other. Background Art

[0003] Recently, as the miniaturization of IC devices has rapidly progressed, the gaps between a plurality of wirings have been reduced. Therefore, it is necessary to develop an IC device having a structure that can prevent the occurrence of undesired short circuits between conductive patterns arranged at high density in a limited area. Summary of the invention

[0004] The inventive concept provides an integrated circuit (IC) device having a structure that prevents short circuits from occurring by ensuring sufficient insulation distances between a plurality of conductive patterns formed in a limited area in an IC device having a smaller unit cell size due to shrinkage of the IC device, thereby improving reliability by preventing the occurrence of short circuits.

[0005] According to some aspects, disclosed is an integrated circuit (IC) device, which includes: a line structure, including a conductive line formed on a substrate and an insulating cover pattern covering the conductive line; an insulating spacer, covering a side wall of the line structure; a conductive plug, separated from the conductive line in a first horizontal direction, the insulating spacer being located between the conductive plug and the conductive line; a conductive bonding pad, arranged on the conductive plug to vertically overlap with the conductive plug; and a cover layer, including a first portion located between the conductive bonding pad and the insulating cover pattern, wherein the first portion of the cover layer has a shape located between the conductive bonding pad and the insulating cover pattern, wherein a width in the first horizontal direction gradually increases as the distance from the substrate in the vertical direction increases.

[0006] According to some aspects, disclosed is an integrated circuit (IC) device, which includes: a pair of line structures, including a pair of conductive wires extending parallel to each other and adjacent to each other in a first horizontal direction on a substrate, and a pair of insulating cover patterns covering the pair of conductive wires; a conductive plug placed between the pair of line structures; a conductive bonding pad arranged on the conductive plug between the pair of line structures; and a cover layer, including a first portion located between one of the pair of line structures and the conductive bonding pad, wherein the first portion of the cover layer has a shape located between one of the pair of line structures and the conductive bonding pad, wherein the width in the first horizontal direction gradually increases as the distance from the substrate in the vertical direction increases.

[0007] According to some aspects, disclosed is an integrated circuit (IC) device, which includes: a pair of line structures, including a pair of conductive wires extending parallel to each other and adjacent to each other in a first horizontal direction on a substrate, and a pair of insulating cover patterns covering the pair of conductive wires; a plurality of contact structures placed between the pair of line structures and aligned in a second horizontal direction perpendicular to the first horizontal direction; a plurality of insulating fences alternating with the plurality of contact structures between the pair of line structures such that one insulating fence is located between two adjacent contact structures; a cover layer, including a first portion located between one of the pair of line structures and one of the plurality of contact structures, wherein the first portion of the cover layer has a shape located between one of the pair of line structures and one of the plurality of contact structures, wherein the width in the first horizontal direction gradually increases with increasing distance from the substrate in the vertical direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments of the inventive concept will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a schematic plan layout of main components of a memory cell array region of an integrated circuit (IC) device according to some example embodiments of the inventive concept;

[0010] Figure 2A is a cross-sectional view for explaining an IC device according to an example embodiment of the inventive concept, and Figure 2B yes Figure 2A enlarged cross-sectional views of some areas;

[0011] Figure 3A is a cross-sectional view for explaining an IC device according to an example embodiment of the inventive concept, and Figure 3B yes Figure 3A enlarged cross-sectional views of some areas;

[0012] FIG. 4A to FIG. 4N is a cross-sectional view for explaining a method of manufacturing an IC device according to an example embodiment of the inventive concept;

[0013] FIG. 5A to FIG. 5D are cross-sectional views illustrating sequential processes of a method of forming a plurality of insulating spacers included in an IC device according to an example embodiment of the inventive concept;

[0014] Figures 6 to 11 yes FIG. 4I to FIG. 4N enlarged cross-sectional views of some areas of the resulting structure;

[0015] FIG. 12A to FIG. 15Bis a cross-sectional view for explaining a method of manufacturing an IC device according to other example embodiments of the inventive concept, wherein: Fig. 12A , Fig.13A , Fig.14A and Fig.15A They are respectively along Figure 1 The cross-section taken along the line A-A' corresponds to a cross-sectional view of some components of the part, Fig. 12B , Fig. 13B , Fig. 14B and Fig. 15B Respectively in Fig. 12A , Fig.13A , Fig.14A and Fig.15A Cross-sectional views of some components of the resulting structure obtained in the corresponding process. DETAILED DESCRIPTION

[0016] Embodiments will now be described more fully with reference to the accompanying drawings. In the accompanying drawings, like reference numerals may indicate like elements, and repeated description of the like elements will be omitted.

[0017] Figure 1 is a schematic plan layout for explaining main components of a memory cell array region of an integrated circuit (IC) device 10 according to some example embodiments of the inventive concepts.

[0018] Reference Figure 1 In the IC device 10, a plurality of active areas ACT may be arranged to extend longitudinally in a plane along an oblique direction relative to the X direction and the Y direction. A plurality of word lines WL may extend longitudinally in parallel with each other in the X direction across the plurality of active areas ACT. Above the plurality of word lines WL, a plurality of bit lines BL may extend longitudinally in parallel with each other in the Y direction intersecting the X direction. The plurality of bit lines BL may be connected to the plurality of active areas ACT via direct contacts DC. An object, a layer, or a portion of an object or a layer described as extending "longitudinally" in a particular direction has a length in the particular direction and a width perpendicular to the direction, wherein the length is greater than the width.

[0019] A plurality of buried contacts BC may be formed between two bit lines BL adjacent to each other among the plurality of bit lines BL. A plurality of conductive landing pads (or "landing pads") LP may be formed on the plurality of buried contacts BC. The plurality of buried contacts BC and the plurality of conductive landing pads LP may connect the bottom electrode (not shown) of the capacitor formed above the plurality of bit lines BL to the active area ACT. Each of the plurality of conductive landing pads LP may be arranged to at least partially overlap the buried contact BC.

[0020] Figure 2A is a cross-sectional view for explaining an IC device according to an example embodiment of the inventive concept, Figure 2B yes Figure 2A Enlarged cross-sectional views of some areas of Figure 2A In the figure, (a) is along Figure 1 A cross-sectional view of some components of the section corresponding to the section taken along the line A-A', (b) is a cross-sectional view of some components of the section corresponding to the section taken along the line A-A', Figure 1 The cross-section taken along the line BB' corresponds to a cross-sectional view of some of the components. Figure 2B In the equation (a-1), Figure 2A The enlarged cross-sectional view of the dotted line area SP1 in FIG. Figure 2A The portion of the dotted line area SP1 in the Y direction (for example, along Figure 1 An enlarged cross-sectional view of some components of the device (corresponding to the section taken along the line Y-Y').

[0021] Figure 2A and Figure 2B The IC device 100 shown in FIG. Figure 1 1. A portion of an IC device 10 is shown in FIG. The IC device 100 includes a substrate 110 in which a plurality of active areas ACT are defined by an isolation layer 112. The isolation layer 112 is formed in an isolation trench T1 formed in the substrate 110.

[0022] According to some embodiments, the substrate 110 may include silicon, for example, single crystal silicon, polycrystalline silicon, or amorphous silicon. According to some other embodiments, the substrate 110 may include at least one selected from Ge, SiGe, SiC, GaAs, InAs, and InP. According to some embodiments, the substrate 110 may include a conductive region, for example, a well doped with impurities or a structure doped with impurities.

[0023] A plurality of word line trenches T2 extending longitudinally in a first horizontal direction (X direction) are formed in the substrate 110, and a plurality of gate dielectric layers 116, a plurality of word lines 118, and a buried insulating layer 120 are formed in the plurality of word line trenches T2. The plurality of word lines 118 may correspond to Figure 1 A plurality of second recess spaces R2 may be formed in the upper surface of the buried insulating layer 120 .

[0024] The first insulating layer 122, the second insulating layer 124, and the third insulating layer 126 are formed on the substrate 110 in the order stated herein. The width of the third insulating layer 126 in the X direction may be smaller than the width of each of the first insulating layer 122 and the second insulating layer 124 in the X direction. According to some embodiments, each of the first insulating layer 122, the second insulating layer 124, and the third insulating layer 126 may include an oxide layer, a nitride layer, or a combination thereof. For example, the first insulating layer 122 and the third insulating layer 126 may each include a silicon oxide layer, and the second insulating layer 124 may include a silicon nitride layer, but the inventive concept is not limited thereto.

[0025] A plurality of direct contacts DC may be arranged on corresponding portions of a plurality of active regions ACT, respectively. A plurality of line structures including a plurality of conductors may extend along a second horizontal direction (Y direction) on the third insulating layer 126 and the plurality of direct contacts DC. A plurality of conductors included in the plurality of line structures may be a plurality of bit lines BL. A plurality of line structures may include a plurality of bit lines BL and a plurality of insulating cap patterns 136 covering the plurality of bit lines BL. A plurality of conductive plugs 150P and a plurality of insulating fences 144B may be aligned along the Y direction between a pair of line structures adjacent to each other from among the plurality of line structures, each of the pair of line structures including a bit line BL and an insulating cap pattern 136. A plurality of insulating fences 144B may fill a plurality of second recessed spaces R2 formed in the upper surface of the buried insulating layer 120, and may alternate with a plurality of conductive plugs 150P so that one insulating fence 144B is located between two adjacent conductive plugs 150P. The corresponding two sidewalls of the plurality of conductive plugs 150P in the Y direction may be covered by a plurality of insulating fences 144B. The plurality of conductive plugs 150P aligned along the Y direction may be insulated from each other by the plurality of insulating fences 144B. The plurality of conductive plugs 150P may constitute Figure 1 Multiple buried contacts BC.

[0026] A plurality of contact structures each including a conductive plug 150P located between a pair of line structures adjacent to each other from among a plurality of line structures may each extend in a columnar shape in the vertical direction (Z direction). Each of the plurality of contact structures may include a conductive plug 150P, a conductive bonding pad LP, and a metal silicide layer 172 located between the conductive plug 150P and the conductive bonding pad LP. For example, the bottom surface of the metal silicide layer 172 may contact the top surface of the conductive plug 150P, and the top surface of the metal silicide layer 172 may contact the bottom surface of the conductive bonding pad LP.

[0027] A plurality of bit lines BL may be connected to the active area ACT via a direct contact DC. A direct contact DC and a pair of conductive plugs 150P facing each other with the direct contact DC therebetween may be connected to different active areas ACT among the plurality of active areas ACT. According to some embodiments, the direct contact DC may include Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or a combination thereof. According to some embodiments, each direct contact DC may include an epitaxial silicon layer. In some embodiments, the bottom surface of each direct contact DC may have a convex shape relative to the substrate 110.

[0028] Each of the plurality of bit lines BL may include a lower conductive layer 130, an intermediate conductive layer 132, and an upper conductive layer 134, which are formed on the substrate 110 in the order stated herein. For example, the lower conductive layer 130 may be formed on the third insulating layer 126, the intermediate conductive layer 132 may be formed on the lower conductive layer 130, and the upper conductive layer 134 may be formed on the intermediate conductive layer 132. The upper surface of the lower conductive layer 130 and the upper surface of the direct contact DC may extend on the same horizontal plane. Although in Figure 2A Each of the plurality of bit lines BL has a three-layer structure including a lower conductive layer 130, an intermediate conductive layer 132, and an upper conductive layer 134, but the inventive concept is not limited thereto. For example, each of the plurality of bit lines BL may be formed as a single layer, a double layer, or a stack of multiple layers such as four or more layers. According to some embodiments, the lower conductive layer 130 may include conductive polysilicon. Each of the intermediate conductive layer 132 and the upper conductive layer 134 may include TiN, TiSiN, W, silicide W, or a combination thereof. For example, the intermediate conductive layer 132 may include TiN and / or TiSiN, and the upper conductive layer 134 may be tungsten (W). The insulating cap pattern 136 may be a silicon nitride layer.

[0029] The plurality of conductive plugs 150P may each have a columnar shape extending in a vertical direction (Z direction) in a space between the plurality of bit lines BL on the substrate 110. A lower surface of each of the plurality of conductive plugs 150P may contact the active area ACT. A portion of each of the plurality of conductive plugs 150P may be located at a level lower than the upper surface of the substrate 110 to be buried in the substrate 110. The plurality of contact plugs 150P may each include, but are not limited to, a semiconductor material doped with impurities, a metal, a conductive metal nitride, or a combination thereof.

[0030] Multiple insulating fences 144B may each have a columnar shape extending in a vertical direction (Z direction) in a space between multiple bit lines BL on substrate 110. Each of the multiple insulating fences 144B may include a fence base FB and a fence upper FU, the fence base FB having a sidewall covered by a conductive plug 150P, and the fence upper FU protruding above the upper surface of each of the multiple conductive plugs 150P. In the Y direction, the width W1 of the fence base FB may be greater than the width W3 of the fence upper FU. In the X direction, the fence base FB and the fence upper FU may have substantially the same width as each other or similar widths to each other. According to some embodiments, multiple insulating fences 144B may include, but are not limited to, a silicon nitride layer. The sidewalls of the fence base FB and the fence upper FU may be substantially vertical and may be perpendicular to the top surface of substrate 110.

[0031] The IC device 100 may include a plurality of insulating spacers SPC1, which cover the corresponding side walls of a plurality of line structures each including a bit line BL and an insulating cap pattern 136. The plurality of insulating spacers SPC1 may cover the corresponding two side walls of the plurality of bit lines BL, the corresponding two side walls of the plurality of insulating cap patterns 136, and the corresponding two side walls of the plurality of direct contacts DC. For example, the insulating spacer SPC1 may contact the two side walls of the plurality of bit lines BL, the two side walls of the plurality of insulating cap patterns 136, and the two side walls of the plurality of direct contacts DC. The plurality of insulating spacers SPC1 may each extend parallel to the plurality of bit lines BL in the Y direction to cover the corresponding two side walls of the plurality of bit lines BL. The top surface of the insulating spacer SPC1 may be at the same vertical level as the top surface of the plurality of insulating cap patterns 136. Each of the plurality of insulating spacers SPC1 may be an oxide layer, a nitride layer, an air spacer, or a combination thereof. The term "air" used herein may mean a space including atmospheric air or other gases that may be present during the manufacturing process.

[0032] According to some embodiments, Figure 2B As shown in (a-1) of , each of the plurality of insulating spacers SPC1 may include an insulating liner 140, a first insulating spacer 142A, and a second insulating spacer 142B, and the insulating liner 140, the first insulating spacer 142A, and the second insulating spacer 142B cover the sidewalls of each bit line BL in the order stated herein. In some embodiments, the insulating liner 140 may contact all sidewalls of the plurality of bit lines BL, all sidewalls of the plurality of insulating cap patterns 136, and all sidewalls of the plurality of direct contacts DC. The first insulating spacer 142A may be formed on at least a portion of each outer sidewall of the insulating liner 140, and the second insulating spacer 142B may be formed on the first insulating spacer 142A. The insulating liner 140 may be a silicon nitride layer. The first insulating spacer 142A may be a silicon oxide layer or an air spacer. The second insulating spacer 142B may be a silicon nitride layer. The insulating liner 140 , the first insulating spacer 142A, and the second insulating spacer 142B may extend parallel to the bit line BL between the bit line BL and the plurality of conductive plugs 150P and between the bit line BL and the plurality of insulating fences 144B.

[0033] A plurality of conductive plugs 150P aligned in the Y direction may be spaced apart from the bit lines BL in the X direction with insulating spacers SPC1 therebetween. A plurality of insulating fences 144B aligned in the Y direction may be spaced apart from the bit lines BL in the X direction with insulating spacers SPC1 therebetween.

[0034] A plurality of metal silicide layers 172 and a plurality of conductive bonding pads LP may be sequentially formed on the plurality of conductive plugs 150P to constitute a plurality of contact structures. In the plurality of contact structures, the metal silicide layers 172 and the conductive bonding pads LP may be arranged to vertically overlap the conductive plugs 150P.

[0035] A plurality of metal silicide layers 172 may be respectively disposed between the plurality of conductive plugs 150P and the plurality of conductive pads LP and may be spaced apart from the bit lines BL in the X direction with insulating spacers SPC1 therebetween. According to some embodiments, each metal silicide layer 172 may include, but is not limited to, cobalt silicide, nickel silicide, or manganese silicide.

[0036] A plurality of conductive bonding pads LP may be connected to a plurality of conductive plugs 150P via a plurality of metal silicide layers 172, respectively. A plurality of conductive bonding pads LP may extend from the space between the plurality of insulating cap patterns 136 to the space above the plurality of fence upper portions FU to vertically overlap with corresponding portions of the plurality of bit lines BL. Each of the plurality of conductive bonding pads LP may include a conductive barrier layer 174 and a conductive layer 176. The conductive barrier layer 174 may include Ti, TiN, or a combination thereof. The conductive layer 176 may include a metal, a metal nitride, a conductive polysilicon, or a combination thereof. For example, the conductive layer 176 may be tungsten (W).

[0037] The plurality of conductive bonding pads LP may be in the shape of a plurality of island patterns in a plan view. The plurality of conductive bonding pads LP may be electrically insulated from each other by an insulating layer 180 filling insulating spaces 180S around the plurality of conductive bonding pads LP. The insulating layer 180 may include a silicon nitride layer, a silicon oxide layer, or a combination thereof.

[0038] According to some embodiments, the interval between two conductive bonding pads LP adjacent to each other in the Y direction from among the plurality of conductive bonding pads LP may be smaller than the interval between two conductive bonding pads LP adjacent to each other in the X direction from among the plurality of conductive bonding pads LP. Therefore, the depth of the insulating space 180S between two conductive bonding pads LP adjacent to each other in the Y direction (see Figure 2B (a-2)) may be smaller than the depth of the insulating space 180S between two conductive bonding pads LP adjacent to each other in the X direction (see Figure 2A (a)). Therefore, the lower surface level of the insulating layer 180 filling the insulating space 180S may vary depending on the position on the substrate 110. Figure 2B As shown in , a level of a lower surface of a portion of the insulation layer 180 vertically overlapping each insulation fence 144B may be higher than a level of a lower surface of a portion of the insulation layer 180 vertically overlapping each insulation capping pattern 136 .

[0039] A plurality of line structures each including a bit line BL and an insulating capping pattern 136 may be covered by a capping layer 154. The capping layer 154 may include, but is not limited to, silicon nitride (Si 3 N 4 ), silicon carbonitride (SiCN), or a combination thereof. Here, the cap layer 154 may also be referred to as an improper-fraction type cap layer 154.

[0040] like Figure 2A (a) and Figure 2B As shown in (a-1) of FIG. 1 , the pseudo-fractional capping layer 154 may include a first portion 154A disposed between each conductive bonding pad LP and each insulating cap pattern 136. For example, the first portion 154A of the pseudo-fractional capping layer 154 may be formed on the outer sidewall of the wall insulating liner 140 at a position extending above the first insulating spacer 142A and the second insulating spacer 142B in the insulating liner 140. The first portion 154A may contact a portion of the outer sidewall of the insulating liner 140 and the top surface of each insulating cap pattern 136. The first portion 154A of the pseudo-fractional capping layer 154 located between each conductive bonding pad LP and each insulating cap pattern 136 may gradually increase in width in the X direction as the distance from the substrate 110 in the Z direction increases.

[0041] like Figure 2B As shown in (a-2), the pseudo-fractional capping layer 154 may include a second portion 154B disposed between each conductive bonding pad LP and each insulating fence 144B. For example, the second portion 154B may contact a portion of the sidewall and the top surface of each fence upper portion FU. The second portion 154B of the pseudo-fractional capping layer 154 may cover the sidewall of each conductive bonding pad LP in the Y direction, and may gradually increase the width in the Y direction as the distance from the substrate 110 in the Z direction increases.

[0042] like Figure 2A (a) and Figure 2BAs shown in FIG. (a-1), the pseudo-fractional capping layer 154 may include a third portion 154C disposed between each conductive bonding pad LP and each insulating spacer SPC1. For example, the third portion 154C of the pseudo-fractional capping layer 154 may be formed on a portion of the outer sidewall and upper sidewall of the first insulating spacer 142A and the second insulating spacer 142B and may be in contact with the portion. The width of the first portion 154A of the pseudo-fractional capping layer 154 in the X direction may be greater than the width of the third portion 154C of the pseudo-fractional capping layer 154 in the X direction. The third portion 154C of the pseudo-fractional capping layer 154 may be disposed between each bit line BL and each conductive bonding pad LP. A portion of each conductive bonding pad LP may be separated from each bit line BL, and the third portion 154C of the pseudo-fractional capping layer 154 and each insulating spacer SPC1 are located between them.

[0043] At least a portion of each metal silicide layer 172 may be separated from each bit line BL, and the third portion 154C of the pseudo-digital capping layer 154 and each insulating spacer SPC1 may be located therebetween. The third portion 154C of the pseudo-digital capping layer 154 may be separated from each conductive plug 150P, and each metal silicide layer 172 may be located therebetween. The bottom surface of the third portion 154C may be at a vertical height lower than the top surface of the metal silicide layer 172, and may be at a vertical height higher than the bottom surface of the metal silicide layer 172. Some portions of the metal silicide layer 172 may be respectively disposed between the bottom surface of the third portion 154C and the top surface of the fence base FB, and other portions of the metal silicide layer 172 may be respectively disposed between the bottom surface of the third portion 154C and the top surface of the conductive plug 150P.

[0044] Each of the plurality of conductive bonding pads LP may include a portion in which at least one of the widths in the horizontal direction (eg, the width in the X direction and the width in the Y direction) decreases as the distance from the substrate 110 in the Z direction increases. Figure 2A (a) and Figure 2B As shown in (a-1) of FIG. 1 , each of the plurality of conductive bonding pads LP may have a first side wall SW11 facing the first portion 154A of the pseudo-single-element capping layer 154, and a separation distance between the first side wall SW11 and each insulating capping pattern 136 may gradually increase as the distance from the substrate 110 increases. Figure 2B As shown in (a-2), each of the multiple conductive bonding pads LP may have a second side wall SW12 facing the second portion 154B of the pseudo-single-element cover layer 154, and the separation distance between the second side wall SW12 and each insulating fence 144B may gradually increase with increasing distance from the substrate 110.

[0045] exist Figure 2A and Figure 2B In the IC device 100, an insulating structure including each insulating cap pattern 136 and a pseudo-number-type cap layer 154 can be formed on each bit line BL, so it is easy to ensure that the insulating structure covers the upper surface of the bit line BL. The minimum critical dimension (CD) in the horizontal direction required for the upper surface of the bit line BL. Therefore, even when the insulating cap pattern 136 and the pseudo-number-type cap layer 154 are etched in the subsequent process and the insulating cap pattern 136 and the pseudo-number-type cap layer 154 are consumed, because sufficient insulating space between the multiple bit lines BL, the multiple metal silicide layers 172, the multiple conductive bonding pads LP and other conductive patterns is ensured by the insulating cap pattern 136 and the pseudo-number-type cap layer 154, the occurrence of undesired short circuits can be prevented. In addition, because the insulating spacer SPC1 covering the corresponding two side walls of the multiple bit lines BL is covered by the pseudo-number-type cap layer 154, the insulating spacer SPC1 and the pseudo-number-type cap layer 154 can ensure sufficient insulation distance between the multiple conductive bonding pads LP and the bit lines BL adjacent thereto. Therefore, it is possible to prevent the occurrence of an undesirable short circuit between each conductive bonding pad LP and each bit line BL.

[0046] Figure 3A is a cross-sectional view for explaining an IC device according to an example embodiment of the inventive concept, Figure 3B yes Figure 3A Enlarged cross-sectional views of some areas of Figure 3A In the figure, (a) is along Figure 1 A cross-sectional view of some components of the section corresponding to the section taken along the line A-A', (b) is a cross-sectional view of some components of the section corresponding to the section taken along the line A-A', Figure 1 The cross-section taken along the line BB' corresponds to a cross-sectional view of some of the components. Figure 3B In the equation (a-1), Figure 3A The enlarged cross-sectional view of the dotted line area SP2 in (a), (a-2) is Figure 3A The portion of the dotted line area SP2 in the Y direction in (a) (for example, along Figure 1 An enlarged cross-sectional view of some components of the device (corresponding to the section taken along the line Y-Y'). Figure 3A and Figure 3B Zhongyu Figure 2A and Figure 2B The same reference numerals and reference numbers as in FIG. 1 denote the same elements, and thus their description will be omitted here.

[0047] Figure 3A and Figure 3B The IC device 200 shown in FIG. Figure 1 The IC device 200 is a portion of the IC device 10 shown in FIG. Figure 2A and Figure 2B The IC device 100 of the present invention has almost the same structure. However, the IC device 200 includes a plurality of insulating cap patterns 236 covering a plurality of bit lines BL. Each of the plurality of insulating cap patterns 236 includes a peak-shaped cap top 236T having a shape in which the width in the X direction gradually decreases as the distance from the substrate 110 increases. For example, the lower portion of each insulating cap pattern 236 may have a sidewall that is substantially vertical relative to the top surface of the substrate 110, while the peak-shaped cap top 236T may have a sidewall that is angled relative to the top surface of the substrate 110.

[0048] The plurality of line structures including the plurality of bit lines BL and the plurality of insulating capping patterns 236 may be covered by a capping layer 254. The capping layer 254 may include, but is not limited to, silicon nitride (Si 3 N 4 ), silicon carbonitride (SiCN), or a combination thereof. The cap layer 254 may also be referred to as a pseudo-fractional cap layer 254. Figure 3A (a) and Figure 3B As shown in (a-1), the pseudo-fractional capping layer 254 may include a first portion 254A disposed between each conductive bonding pad LP and the peak capping top 236T of each insulating cap pattern 236. For example, the first portion 254A of the pseudo-fractional capping layer 254 may be formed on the outer sidewall of the insulating liner 140 in a position extending above the first insulating spacer 142A and the second insulating spacer 142B in the insulating liner 140. The first portion 254A may contact a portion of the outer sidewall of the insulating liner 140 and the side surface and the top surface of each peak capping top 236T. The first portion 254A of the pseudo-fractional capping layer 254 between the conductive bonding pad LP and the peak capping top 236T may gradually increase the width in the X direction as the distance from the substrate 110 increases.

[0049] like Figure 3B As shown in (a-2) of FIG. 1 , the pseudo-score capping layer 254 may include a second portion 254B disposed between each conductive bonding pad LP and each insulating fence 244B. For example, the second portion 254B may contact a portion of the sidewall and the top surface of each fence upper portion FU. Figure 3A (a) and Figure 3BAs shown in (a-1), the pseudo-fractional capping layer 254 may include a third portion 254C disposed between each conductive bonding pad LP and each insulating spacer SPC1. For example, the third portion 254C of the pseudo-fractional capping layer 254 may be formed on and in contact with portions of the outer sidewalls and upper sidewalls of the first insulating spacer 142A and the second insulating spacer 142B. The width of the first portion 254A of the pseudo-fractional capping layer 254 in the X direction may be greater than the width of the third portion 254C of the pseudo-fractional capping layer 254 in the X direction. The third portion 254C of the pseudo-fractional capping layer 254 may be disposed between each bit line BL and each conductive bonding pad LP. A portion of each conductive bonding pad LP may be separated from each bit line BL, and the third portion 254C of the pseudo-fractional capping layer 254 and each insulating spacer SPC1 are located between them.

[0050] At least a portion of each metal silicide layer 172 may be separated from each bit line BL, and the third portion 254C of the pseudo-number type capping layer 254 and each insulating spacer SPC1 are located therebetween. The third portion 254C of the pseudo-number type capping layer 254 may be separated from each conductive plug 150P, and each metal silicide layer 172 is located therebetween.

[0051] According to some embodiments, each of the plurality of conductive bonding pads LP may include a portion in which at least one of the widths in the horizontal direction (eg, the width in the X direction and the width in the Y direction) decreases as the distance from the substrate 110 in the Z direction increases. Figure 3A (a) and Figure 3B As shown in (a-1) of FIG. 1 , each of the plurality of conductive bonding pads LP may have a first sidewall SW21 facing the first portion 254A of the pseudo-single-element capping layer 254, and a separation distance between the first sidewall SW21 and each insulating capping pattern 236 may gradually increase as the distance from the substrate 110 increases. Figure 3B As shown in (a-2), each of the plurality of conductive bonding pads LP may have a second sidewall SW22 facing the second portion 254B of the pseudo-single-element capping layer 254. The separation distance between the second sidewall SW22 and each insulating fence 244B may be substantially the same or gradually increase as the distance from the substrate 110 increases.

[0052] The detailed structures of the plurality of insulating cap patterns 236, the plurality of insulating fences 244B and the pseudo-score type cap layer 254 are similar to those described above. Figure 2A and Figure 2B The detailed structures of the plurality of insulating capping patterns 136 , the plurality of insulating fences 144B, and the pseudo-number-type capping layer 154 described are almost the same.

[0053] exist Figure 3A and Figure 3B In the IC device 200, an insulating structure including each insulating cover pattern 236 and a pseudo-number-type cover layer 254 can be formed on each bit line BL, so it is easy to ensure the minimum CD in the horizontal direction required by the insulating structure covering the upper surface of the bit line BL. Therefore, sufficient insulating space between multiple bit lines BL, multiple metal silicide layers 172, multiple conductive bonding pads LP and other conductive patterns is ensured by the insulating cover pattern 236 and the pseudo-number-type cover layer 254, so that the occurrence of undesirable short circuits can be prevented. In addition, because the insulating spacer SPC1 covering the corresponding two side walls of the multiple bit lines BL is covered by the pseudo-number-type cover layer 254, the insulating spacer SPC1 and the pseudo-number-type cover layer 254 can ensure sufficient insulation distance between the multiple conductive bonding pads LP and the bit lines BL adjacent thereto. Therefore, the occurrence of undesirable short circuits between each conductive bonding pad LP and each bit line BL can be prevented.

[0054] FIG. 4A to FIG. 4N is a cross-sectional view for explaining a method of manufacturing an IC device according to an exemplary embodiment of the inventive concept. FIG. 4A to FIG. 4N In the figure, (a) is along Figure 1 A cross-sectional view of some components of the section corresponding to the section taken along the line A-A', (b) is a cross-sectional view of some components of the section corresponding to the section taken along the line A-A', Figure 1 The cross-section taken along the line BB' corresponds to a cross-sectional view of some components of the part. FIG. 4A to FIG. 4N To describe manufacturing Figure 2A and Figure 2B Method of the IC device 100.

[0055] Reference Figure 4A An isolation trench T1 is formed in the substrate 110, and an isolation layer 112 is formed in the isolation trench T1. An active area ACT may be defined in the substrate 110 by the isolation layer 112. The isolation layer 112 may include an oxide layer, a nitride layer, or a combination thereof.

[0056] A plurality of word line trenches T2 may be formed in the substrate 110. The plurality of word line trenches T2 may extend parallel to each other in the X direction and may have a line shape extending across the active area ACT. Figure 4AAs shown in the cross-sectional view (b) in FIG. 1 , in order to form the plurality of word line trenches T2 to each have a step at the bottom surface thereof, the isolation layer 112 and the substrate 110 may be etched separately by separate etching processes so that the isolation layer 112 and the substrate 110 have different etching depths. The resulting structure formed with the plurality of word line trenches T2 may be cleaned, and then a gate dielectric layer 116, a word line 118, and a buried insulating layer 120 may be formed in each of the plurality of word line trenches T2 in the order stated below. According to some embodiments, before or after forming the plurality of word lines 118, impurity ions may be implanted into the substrate 110 from both sides of each of the plurality of word lines 118, thereby forming a plurality of source / drain regions 114 in the upper portion of the plurality of active regions ACT.

[0057] The gate dielectric layer 116 may include at least one selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an oxide / nitride / oxide (ONO), or a high-k dielectric layer having a higher dielectric constant than that of the silicon oxide layer. For example, the gate dielectric layer 116 may have a dielectric constant of about 10 to about 25. According to some embodiments, the gate dielectric layer 116 may include, but is not limited to, HfO. 2 、Al 2 O 3 、HfAlO 3 、 2 O 3 、TiO 2 Each of the plurality of word lines 118 may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or a combination thereof. Each of the plurality of buried insulating layers 120 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof.

[0058] An insulating layer structure including a first insulating layer 122 , a second insulating layer 124 , and a third insulating layer 126 is formed on the plurality of buried insulating layers 120 and the substrate 110 .

[0059] Reference Figure 4B , a lower conductive layer 130 is formed on the third insulating layer 126. The lower conductive layer 130 may include doped polysilicon.

[0060] Reference Figure 4C , a mask pattern MP1 is formed on the lower conductive layer 130, and then the lower conductive layer 130 exposed through the opening MH of the mask pattern MP1 is etched, and then a portion of the substrate 110 and a portion of the isolation layer 112 thus exposed are etched, thereby forming a direct contact hole DCH exposing the active area ACT of the substrate 110.

[0061] The mask pattern MP1 may include an oxide layer, a nitride layer, or a combination thereof. The mask pattern MP1 may be formed using a photolithography process.

[0062] Reference Figure 4D , remove the mask pattern MP1 (see Figure 4C ), a direct contact member DC is formed in the direct contact hole DCH.

[0063] In an example of a process for forming a direct contact DC, a conductive layer having a sufficient thickness to fill the direct contact hole DCH may be formed in the direct contact hole DCH and on the lower conductive layer 130, and the conductive layer may be etched back so that the conductive layer remains only in the direct contact hole DCH. The conductive layer for forming the direct contact DC may be doped polysilicon, but is not limited thereto.

[0064] Reference Figure 4E , an intermediate conductive layer 132, an upper conductive layer 134, and an insulating cap layer 136L are formed on the lower conductive layer 130 and the direct contact DC in the order stated below.

[0065] Each of middle conductive layer 132 and upper conductive layer 134 may include TiN, TiSiN, W, W silicide, or a combination thereof. According to some embodiments, middle conductive layer 132 may be TiSiN, and upper conductive layer 134 may be W. Insulating cap layer 136L may be a silicon nitride layer.

[0066] Reference Figure 4F , by using an etching mask (not shown) in Figure 4E In the resultant structure of the structure, each of the insulating capping layer 136L, the upper conductive layer 134, the middle conductive layer 132, the lower conductive layer 130, and the direct contact DC is partially etched to form a plurality of bit lines BL and a plurality of insulating capping patterns 136 covering the plurality of bit lines BL. The plurality of bit lines BL may include respective remaining portions of the lower conductive layer 130, the middle conductive layer 132, and the upper conductive layer 134. Each of the plurality of bit lines BL and the plurality of insulating capping patterns 136 may be formed in a line pattern extending in the Y direction. After the plurality of bit lines BL are formed, the direct contact hole DCH may be partially exposed again around the direct contact DC.

[0067] When etching the lower conductive layer 130 to form a plurality of bit lines BL, the third insulating layer 126 directly below the lower conductive layer 130 may also be etched due to over-etching, so that only the portion of the third insulating layer 126 covered by the plurality of bit lines BL may be retained, and the upper surface of the second insulating layer 124 may be exposed around the plurality of bit lines BL.

[0068] Reference Figure 4GA plurality of insulating spacers SPC1 are formed to cover sidewalls of the plurality of bit lines BL, the plurality of insulating capping patterns 136, and the plurality of direct contacts DC. The plurality of insulating spacers SPC1 may be formed to fill empty spaces of the plurality of direct contact holes DCH.

[0069] Each of the plurality of insulating spacers SPC1 may extend in parallel with the plurality of bit lines BL in the Y direction to cover corresponding two sidewalls of the plurality of bit lines BL.

[0070] FIG. 5A to FIG. 5D It is shown that the Figure 4G A cross-sectional view of a sequential process of a method of forming a plurality of insulating spacers SPC1 is shown in FIG. FIG. 5A to FIG. 5D In the figure, the Figure 4G The area corresponding to the dotted line area "SP1" in FIG.

[0071] Reference Figure 4G and Figure 5A ,exist Figure 4F An insulating liner 140 is formed on the entire surface of the resulting structure to conformally cover Figure 4F The resulting structure includes exposed surfaces of the plurality of bit lines BL, exposed surfaces of the plurality of insulating capping patterns 136, exposed surfaces of the plurality of direct contacts DC, and exposed surfaces of the second insulating layer 124. The insulating liner 140 may include a silicon nitride layer.

[0072] Reference Figure 5B , a lower insulating buried pattern (not shown) is formed on the insulating liner 140 to fill the remaining space of the direct contact hole DCH while covering the corresponding sidewalls of the plurality of direct contacts DC, and then a first insulating spacer layer 142AL is formed covering the lower insulating buried pattern and the sidewalls of the insulating liner 140. The first insulating spacer layer 142AL may cover the plurality of bit lines BL, the plurality of insulating capping patterns 136, the plurality of direct contacts DC, and the second insulating layer 124, with the insulating liner 140 therebetween. The first insulating spacer layer 142AL may be a silicon oxide layer.

[0073] Reference Figure 5C , through Figure 5B The first insulating spacer layer 142AL in the resulting structure is etched back to form a plurality of first insulating spacers 142A covering the respective two sidewalls of the plurality of bit lines BL. While the first insulating spacer layer 142AL is etched back, the second insulating layer 124 (see FIG. 1 ) may be overetched. Figure 4G ) The insulating liner 140 is partially removed on the upper surface. The insulating liner 140 may be retained between each bit line BL and each first insulating spacer 142A and between each insulating cap pattern 136 and the first insulating spacer 142A. Figure 5CHowever, it is also possible to form a second insulating layer 124 (see Figure 4G ) and the plurality of first insulating spacers 142A retain an insulating liner 140.

[0074] Reference Figure 5D , a plurality of insulating spacers SPC1 are obtained by forming a plurality of second insulating spacers 142B on the plurality of first insulating spacers 142A using a method similar to the method of forming the plurality of first insulating spacers 142A. Each of the plurality of second insulating spacers 142B may be a silicon nitride layer.

[0075] Return to reference Figure 4G After forming the plurality of insulating spacers SPC1 , each line space LS extending in the Y direction may be defined on the second insulating layer 124 between the plurality of line structures including the plurality of bit lines BL and the plurality of insulating capping patterns 136 .

[0076] While forming the plurality of insulating spacers SPC1, a portion of the second insulating layer 124 and the first insulating layer 122, a portion of the substrate 110, and a portion of each of the plurality of buried insulating layers 120 may be consumed in the space between the plurality of bit lines BL. Thus, after forming the plurality of insulating spacers SPC1, a portion of the substrate 110 and a portion of each of the plurality of buried insulating layers 120 may be consumed in the line space LS between the plurality of bit lines BL. Figure 4H , a sacrificial layer 143 is formed between the plurality of bit lines BL to fill the plurality of line spaces LS. The sacrificial layer 143 may include a material having an etch selectivity different from that of the plurality of insulating capping patterns 136. For example, the plurality of insulating capping patterns 136 may be a silicon nitride layer, and the sacrificial layer 143 may be a silicon oxide layer. However, the inventive concept is not limited thereto.

[0077] Thereafter, some regions of the sacrificial layer 143 covering the plurality of buried insulating layers 120 are etched using the mask pattern as an etching mask, thereby forming a plurality of fence spaces FS (see FIG. 1 ) exposing the plurality of buried insulating layers 120 between the plurality of bit lines BL. Figure 4H (b)). While etching some areas of the sacrificial layer 143 to form a plurality of fence spaces FS, as shown in FIG. Figure 4H As shown in (b), portions of the plurality of insulating cap patterns 136 and the plurality of insulating spacers SPC1 adjacent to the plurality of fence spaces FS in the X direction may be partially consumed, and thus some regions of the plurality of insulating cap patterns 136 and some regions of the plurality of insulating spacers SPC1 may have a reduced height. In addition, while etching some regions of the sacrificial layer 143 to form the plurality of fence spaces FS, portions of the plurality of buried insulating layers 120 exposed via the plurality of fence spaces FS may be removed, and thus a plurality of recessed spaces R2 may be formed in the upper surface of the plurality of buried insulating layers 120.

[0078] However, if Figure 4H As shown in (a), during the etching process for forming the plurality of fence spaces FS, portions of the plurality of insulating cap patterns 136 and the plurality of insulating spacers SPC1 adjacent to the regions between the plurality of fence spaces FS in the X direction may be protected by the sacrificial layer 143, and thus their heights may be maintained without substantial consumption before the plurality of fence spaces FS are formed. Therefore, the plurality of insulating cap patterns 136 and the plurality of insulating spacers SPC1 have heights that vary in the direction (Y direction) in which each bit line BL extends longitudinally, and thus the upper surfaces of the plurality of insulating cap patterns 136 and the upper surfaces of the plurality of insulating spacers SPC1 may both extend in an uneven shape in the Y direction.

[0079] Thereafter, insulating fences 144 are formed to fill the plurality of fence spaces FS. The insulating fences 144 may be formed to cover the plurality of fence spaces FS and upper surfaces of the plurality of insulating capping patterns 136 adjacent to the plurality of fence spaces FS in the X direction. According to some embodiments, the insulating fences 144 may be a silicon nitride layer.

[0080] After forming the insulating fence 144, the spaces between the plurality of bit lines BL filled with the sacrificial layer 143 may be used as a plurality of contact spaces CS (see Fig. 4I ).

[0081] Reference Fig. 4I ,from Figure 4H The sacrificial layer 143 is removed from the resulting structure to expose the plurality of active areas ACT through the plurality of contact spaces CS defined by the insulating fence 144 between the plurality of bit lines BL, and then the exposed portions of the plurality of active areas ACT are removed to form the plurality of first recessed spaces R1. According to some embodiments, the plurality of first recessed spaces R1 may be formed by anisotropic etching, isotropic etching, or a combination thereof.

[0082] Thereafter, a plurality of preliminary conductive plugs 150 are formed to fill the plurality of first recess spaces R1 and also fill portions of the plurality of contact spaces CS between the plurality of bit lines BL.

[0083] The vertical distance (the distance in the Z direction) from the upper surface of the substrate 110 to the upper surface of each of the plurality of preliminary conductive plugs 150 may be greater than the vertical distance from the upper surface of the substrate 110 to the upper surface of each of the plurality of bit lines BL. Figure 4HAfter removing and forming the plurality of recessed spaces R1 in the resulting structure, a conductive layer filling the plurality of recessed spaces R1 and the plurality of contact spaces CS and covering the upper surfaces of the plurality of insulating cap patterns 136 and the upper surfaces of the plurality of insulating fences 144 is formed, and then the upper portion of the conductive layer is partially removed by etching back, so that the upper surfaces of the plurality of insulating cap patterns 136 and the upper surfaces of the plurality of insulating fences 144 can be exposed, and the respective upper spaces on the entrance side of the plurality of contact spaces CS can be emptied again. The remaining portion of the conductive layer can constitute a plurality of preliminary conductive plugs 150. The plurality of preliminary conductive plugs 150 may include doped polysilicon.

[0084] Figure 6 yes Fig. 4I Magnified cross-sectional views of some areas of the resulting structure. Figure 6 In the equation (a-1), Fig. 4I The enlarged cross-sectional view of the dotted line area SP1 in (a), (a-2) is Fig. 4I The portion of the dotted line area SP1 in the Y direction (for example, along Figure 1 An enlarged cross-sectional view of some components of the device (corresponding to the section taken along the line Y-Y').

[0085] Reference Fig. 4I and Figure 6 , after forming the plurality of preliminary conductive plugs 150 , upper portions of the plurality of insulating fences 144 may partially protrude to be at a level higher than upper surfaces of the plurality of preliminary conductive plugs 150 .

[0086] Reference Figure 4J , partially removed via multiple contact spaces CS (see Fig. 4I ) are formed by exposing a plurality of insulating spacers SPC1 on the respective upper spaces of the preliminary conductive plugs 150 on the entrance side to expand the widths of the plurality of contact spaces CS in the X direction toward both sides between the plurality of insulating cap patterns 136, thereby forming a plurality of upper contact spaces UCS each having an increased width. The width of each of the plurality of upper contact spaces UCS in the X direction may be greater than the width of each preliminary conductive plug 150 in the X direction.

[0087] According to some embodiments, a plurality of upper contact spaces UCS may be formed by partially wet-etching a plurality of insulating spacers SPC1. For example, to form a plurality of upper contact spaces UCS, the second insulating spacer 142B exposed through the plurality of contact spaces CS may be wet-etched, thereby exposing the first insulating spacer 142A, and then the exposed portion of the first insulating spacer 142A may be wet-etched, thereby exposing the insulating liner 140.

[0088] Figure 7 yes Figure 4J Magnified cross-sectional views of some areas of the resulting structure. Figure 7 In the equation (a-1), Figure 4J The enlarged cross-sectional view of the dotted line area SP1 in (a), (a-2) is Figure 4J The portion of the dotted line area SP1 in the Y direction (for example, along Figure 1 An enlarged cross-sectional view of some components of the device (corresponding to the section taken along the line Y-Y').

[0089] Reference Figure 4J and Figure 7 After forming the plurality of upper contact spaces UCS, the insulating liner 140 may be exposed on both sides of the plurality of upper contact spaces UCS in the X direction, and the insulating fence 144 may be exposed on both sides of the plurality of upper contact spaces UCS in the Y direction.

[0090] While the second insulating spacer 142B and the first insulating spacer 142A are etched in the order stated below to form the plurality of upper contact spaces UCS, the surfaces of the plurality of insulating fences 144 exposed under the etching atmosphere may be partially consumed due to the etching atmosphere of the insulating spacer SPC1, so that the size ratio may be obtained. Figure 6 A plurality of insulating fences 144A having a smaller size than the insulating fence 144 as indicated by the dotted line D1. After forming the plurality of upper contact spaces UCS, each of the plurality of insulating fences 144A may include a fence base FB and a fence upper portion FU, the fence base FB having two side walls in the Y direction covered by the plurality of preliminary conductive plugs 150, the fence upper portion FU protruding above the upper surface of each of the plurality of preliminary conductive plugs 150 and having a width W2 in the Y direction that is smaller than the width W1 of the fence base FB. In each of the plurality of insulating fences 144A, the fence base FB and the fence upper portion FU may have the same width as each other in the X direction.

[0091] Reference Figure 4K , the plurality of preliminary conductive plugs 150 exposed through the plurality of upper contact spaces UCS are etched from their respective upper surfaces by a certain thickness to form a plurality of conductive plugs 150P having a lower height than the plurality of preliminary conductive plugs 150. After the plurality of conductive plugs 150P are formed, a landing pad (or “pad”) space LPS may be formed on the upper surface of each of the plurality of conductive plugs 150P between the plurality of insulating cap patterns 136.

[0092] According to some embodiments, a vertical distance (distance in the Z direction) from the upper surface of the substrate 110 to the upper surface of each of the plurality of conductive plugs 150P may be smaller than a vertical distance from the upper surface of the substrate 110 to the upper surface of each of the plurality of bit lines BL.

[0093] Figure 8 yes Figure 4K Magnified cross-sectional views of some areas of the resulting structure. Figure 8 In the equation (a-1), Figure 4K The enlarged cross-sectional view of the dotted line area SP1 in (a), (a-2) is Figure 4K The portion of the dotted line area SP1 in the Y direction (for example, along Figure 1 An enlarged cross-sectional view of some components of the device (corresponding to the section taken along the line Y-Y').

[0094] Reference Figure 4K and Figure 8 While etching the plurality of preliminary conductive plugs 150 to form the plurality of bonding pad spaces LPS, the surfaces of the plurality of insulating fences 144 exposed in the etching atmosphere within the plurality of upper contact spaces UCS may be consumed, thereby obtaining a size ratio of Figure 7 The plurality of insulating fences 144B shown in (a-2) are smaller in size than the plurality of insulating fences 144 shown in FIG. After forming the plurality of bonding pad spaces LPS, each of the plurality of insulating fences 144B may include a fence base FB and a fence upper portion FU, the fence base FB having two side walls in the Y direction covered by the plurality of conductive plugs 150P, the fence upper portion FU protruding higher than the upper surface of each of the plurality of conductive plugs 150P and having a width W3 in the Y direction that is smaller than the width W1 of the fence base FB. In each of the plurality of insulating fences 144B, the fence base FB and the fence upper portion FU may have the same width as each other in the X direction. According to some embodiments, while etching the plurality of preliminary conductive plugs 150 to form the plurality of bonding pad spaces LPS, portions of the plurality of insulating spacers SPC1 exposed under the etching atmosphere may be partially consumed.

[0095] Since each of the plurality of insulating fences 144B includes a fence upper portion FU having a width W3 smaller than the width W1 of the fence base FB, the width of each of the plurality of bonding pad spaces LPS in the X direction can be relatively increased. Figure 4N and Fig.11 The described process of forming the plurality of metal silicide layers 172 helps to reduce contact resistance.

[0096] Reference Figure 4L ,exist Figure 4K A pseudo-number-type capping layer 154 covering the plurality of insulating capping patterns 136 and the plurality of insulating fences 144B is formed on the resultant structure having the plurality of bonding pad spaces LPS formed therein.

[0097] Fig. 9 yes Figure 4L Magnified cross-sectional views of some areas of the resulting structure. Fig. 9 In the equation (a-1), Figure 4L The enlarged cross-sectional view of the dotted line area SP1 in (a), (a-2) is Figure 4L The portion of the dotted line area SP1 in the Y direction (for example, along Figure 1 An enlarged cross-sectional view of some components of the device (corresponding to the section taken along the line Y-Y').

[0098] Reference Figure 4L and Fig. 9 , the pseudo-fractional capping layer 154 may gradually increase the width in the horizontal direction on the sidewalls of the plurality of insulating capping patterns 136 and the sidewalls of the plurality of insulating fences 144B as the distance from the substrate 110 increases. For example, on the sidewall of each of the plurality of insulating capping patterns 136, the pseudo-fractional capping layer 154 may gradually increase the width in the X direction as the distance from the substrate 110 in the Z direction increases. On the sidewall of each of the plurality of insulating fences 144B, the pseudo-fractional capping layer 154 may gradually increase the width in the Y direction as the distance from the substrate 110 in the Z direction increases.

[0099] According to some embodiments, in order to form the pseudo-fractional capping layer 154, the conditions for depositing the insulating material for forming the pseudo-fractional capping layer 154 may be controlled. For example, by adopting a process condition having a relatively degraded step coverage during the process of depositing the insulating material for forming the pseudo-fractional capping layer 154, the pseudo-fractional capping layer 154 may be formed to have a relatively degraded step coverage. Figure 4K The exposed surface of the resulting structure has a relatively small thickness on a portion relatively close to the substrate 110, and the pseudo-score type capping layer 154 is formed to be Figure 4K The exposed surface of the resulting structure has a relatively large thickness on a portion relatively far from the substrate 110. According to some embodiments, the pseudo-integrated cap layer 154 may include, but is not limited to, silicon nitride (Si 3 N 4 ), silicon carbonitride (SiCN), or a combination thereof.

[0100] According to some embodiments, after forming the pseudo-number type capping layer 154, the width of each of some regions of the plurality of bonding pad spaces LPS in the horizontal direction may decrease as the distance from the substrate 110 increases. Fig. 9 As shown in (a-1) of FIG. 1 , the width of each bonding pad space LPS defined by the pseudo-number-type capping layer 154 above the first insulating spacer 142A and the second insulating spacer 142B in the X direction may decrease as the distance from the substrate 110 increases. Fig. 9As shown in (a-2) of FIG. 1 , the width in the Y direction of each bonding pad space LPS defined by the pseudo-number-type capping layer 154 over the conductive plug 150P may decrease as the distance from the substrate 110 increases.

[0101] As from Fig. 9 As can be seen in (a-2), the width in the Y direction of the pseudo-fractional cover layer 154 on the portion of the side wall of each of the multiple insulating fences 144B facing the bonding pad space LPS can increase as the distance from the substrate 110 increases. Therefore, the side wall of the pseudo-fractional cover layer 154 facing the bonding pad space LPS can have an inclined shape with a negative slope that gets closer to the vertical center axis (VCX) of the bonding pad space LPS as the distance from the substrate 110 increases.

[0102] Reference Figure 4M , portions of the pseudo-number-type capping layer 154 covering the plurality of conductive plugs 150P are removed to expose respective upper surfaces of the plurality of conductive plugs 150P through the plurality of bonding pad spaces LPS.

[0103] Fig.10 yes Figure 4M Magnified cross-sectional views of some areas of the resulting structure. Fig.10 In the equation (a-1), Figure 4M The enlarged cross-sectional view of the dotted line area SP1 in (a), (a-2) is Figure 4M The portion of the dotted line area SP1 in the Y direction (for example, along Figure 1 An enlarged cross-sectional view of some components of the device (corresponding to the section taken along the line Y-Y').

[0104] Reference Figure 4M and Fig.10 , a portion of the pseudo-fractional capping layer 154 may be removed using a wet etching process so that the respective upper surfaces of the plurality of conductive plugs 150P may be exposed through the plurality of bonding pad spaces LPS. While etching a portion of the pseudo-fractional capping layer 154 so that the respective upper surfaces of the plurality of conductive plugs 150P may be exposed, the upper surface of the pseudo-fractional capping layer 154 may also be removed by a certain thickness, so that the pseudo-fractional capping layer 154 may have a reduced height.

[0105] According to some embodiments, an annealing process may be performed to repair damage to portions of the upper surfaces of the plurality of conductive plugs 150P exposed via the plurality of bonding pad spaces LPS. The annealing process may use heating, plasma, or laser. The annealing process may be performed at about 600° C. to 1200° C., but the inventive concept is not limited thereto.

[0106] Reference Figure 4N , in the LPS space via multiple bonding pads (see Figure 4M ) A plurality of metal silicide layers 172 are formed on the exposed plurality of conductive plugs 150P, and a plurality of conductive bonding pads LP are formed on the plurality of metal silicide layers 172 to fill the plurality of bonding pad spaces LPS.

[0107] Fig.11 yes Figure 4N Magnified cross-sectional views of some areas of the resulting structure. Fig.11 In the equation (a-1), Figure 4N The enlarged cross-sectional view of the dotted line area SP1 in (a), (a-2) is Figure 4N The portion of the dotted line area SP1 in the Y direction (for example, along Figure 1 An enlarged cross-sectional view of some components of the device (corresponding to the section taken along the line Y-Y').

[0108] Reference Figure 4N and Fig.11 , while filling the plurality of bonding pad spaces LPS over the plurality of metal silicide layers 172, the plurality of conductive bonding pads LP may extend over the plurality of insulating cap patterns 136 and the pseudo-number type capping layer 154 to vertically overlap with a portion of the plurality of bit lines BL and a portion of the pseudo-number type capping layer 154. Each of the plurality of conductive bonding pads LP may include a conductive barrier layer 174 and a conductive layer 176.

[0109] According to some embodiments, in order to form a plurality of conductive bonding pads LP, after the conductive barrier layer 174 and the conductive layer 176 are sequentially formed to cover the entire surface of the resulting structure on which the metal silicide layer 172 is formed, a mask pattern (not shown) exposing corresponding portions of the conductive layer 176 may be formed on the conductive layer 176, and the mask pattern may be used as an etching mask to etch the conductive barrier layer 174, the conductive layer 176, and the insulating layer around the conductive barrier layer 174 and the conductive layer 176. Each of the formed plurality of conductive bonding pads LP includes the remaining portions of the conductive barrier layer 174 and the conductive layer 176. The mask pattern may include, but is not limited to, a hard mask including a nitride layer, an oxide layer, a polysilicon layer, or a combination thereof. The plurality of conductive bonding pads LP may be formed as a plurality of island patterns. When the conductive barrier layer 174, the conductive layer 176, and the insulating layer around the conductive barrier layer 174 and the conductive layer 176 are etched to form the plurality of conductive bonding pads LP, a portion of the pseudo-single-layer capping layer 154, a portion of the plurality of insulating capping patterns 136, and a portion of each of the plurality of insulating spacers SPC1 may also be removed around the plurality of conductive bonding pads LP, so that an insulating space 180S exposing the sidewalls of the plurality of conductive bonding pads LP may be provided around the plurality of conductive bonding pads LP. According to some embodiments, as shown in FIG. Fig.11As shown in , the interval between two conductive bonding pads LP adjacent to each other in the Y direction from among the plurality of conductive bonding pads LP may be smaller than the interval between two conductive bonding pads LP adjacent to each other in the X direction from among the plurality of conductive bonding pads LP. Therefore, the depth of the insulating space 180S between two conductive bonding pads LP adjacent to each other in the Y direction (see Fig.11 (a-2)) may be smaller than the depth of the insulating space 180S between two conductive bonding pads LP adjacent to each other in the X direction (see Figure 4N (a)).

[0110] The insulating space 180S around the plurality of conductive bonding pads LP may be filled with an insulating layer 180 to electrically insulate the plurality of conductive bonding pads LP from each other. The level of the lower surface of the insulating layer 180 may vary depending on the position of the substrate 110. Figure 2B As shown in , a level of a lower surface of a portion of the insulation layer 180 vertically overlapping each insulation fence 144B may be higher than a level of a lower surface of a portion of the insulation layer 180 vertically overlapping each insulation capping pattern 136 .

[0111] Thereafter, a plurality of capacitor lower electrodes that can be electrically connected to the plurality of conductive bonding pads LP may be formed on the insulating layer 180 .

[0112] According to some embodiments, in the above reference Figure 4N and Fig.11 In the described process, after forming a plurality of conductive bonding pads LP and after filling the insulating space 180S with the insulating layer 180, the corresponding portions of the plurality of insulating spacers SPC1 (e.g., the plurality of first insulating spacers 142A) can be removed via wet etching, so that at least a portion of each of the plurality of first insulating spacers 142A can be replaced by an air spacer. Thereafter, the insulating space 180S can be filled with the insulating layer 180 to define the corresponding upper limit of the air spacer. Thus, a structure including an air spacer between the insulating liner 140 and the second insulating spacer 142B can be formed between the bit line BL and the conductive plug 150P and between the bit line BL and the conductive bonding pad LP, respectively.

[0113] According to the above reference FIG. 4A to FIG. 11The method of manufacturing the IC device 100 described above can form an insulating structure including each insulating cap pattern 136 and a pseudo-number-type cap layer 154 on each bit line BL before forming a plurality of metal silicide layers 172 and a plurality of conductive bonding pads LP, so that the minimum CD in the horizontal direction required for the insulating structure to cover the upper surface of the bit line BL can be easily ensured. Therefore, even if a portion of the insulating cap pattern 136 and the pseudo-number-type cap layer 154 is consumed when etching adjacent layers of each of the insulating cap pattern 136 and the pseudo-number-type cap layer 154 in a subsequent process, since sufficient insulating space between the plurality of bit lines BL, the plurality of metal silicide layers 172, the plurality of conductive bonding pads LP, and other conductive patterns is ensured by the insulating cap pattern 136 and the pseudo-number-type cap layer 154, the occurrence of an undesired short circuit can be prevented. In addition, since the pseudo-single-number capping layer 154 is also formed on the insulating spacer SPC1 covering the corresponding two side walls of the plurality of bit lines BL, after forming the plurality of conductive bonding pads LP in the bonding pad space LPS between two adjacent bit lines BL, a sufficient insulation distance between the plurality of conductive bonding pads LP and the bit lines BL adjacent thereto can be ensured. Therefore, the occurrence of an undesirable short circuit between each conductive bonding pad LP and each bit line BL can be prevented.

[0114] FIG. 12A to FIG. 15B are cross-sectional views for explaining methods of manufacturing an IC device according to other embodiments of the inventive concept. Fig. 12A , Fig.13A , Fig.14A and Fig.15A They are respectively along Figure 1 The cross-section taken along the line A-A' corresponds to a cross-sectional view of some components of the part, Fig. 12B , Fig. 13B , Fig. 14B and Fig. 15B Respectively in Fig. 12A , Fig.13A , Fig.14A and Fig.15A Cross-sectional views of some components of the resulting structure obtained in the corresponding process. Fig. 12B , Fig. 13B , Fig. 14B and Fig. 15B In the equation (a-1), Fig. 12A , Fig.13A , Fig.14A and Fig.15A The enlarged cross-sectional view of the dotted line area SP2 in FIG. Fig. 12A , Fig.13A , Fig.14A and Fig.15A The portion of the dotted line area SP2 in the Y direction (for example, along Figure 1Now, reference will be made to the enlarged cross-sectional view of some components of the FIG. 12A to FIG. 15B To describe manufacturing Figure 3A and Figure 3B Method of IC device 200.

[0115] Reference Fig. 12A and Fig. 12B , according to the above reference Figures 4A to 4K as well as Figures 6 to 8 In a method similar to the method described above, a plurality of upper contact spaces UCS having an increased width are formed by partially removing the plurality of insulating spacers SPC1, a plurality of conductive plugs 150P are formed by removing respective portions of the plurality of preliminary conductive plugs 150 exposed through the plurality of upper contact spaces UCS, and a plurality of bonding pad spaces LPS2 are formed on respective upper surfaces of the plurality of conductive plugs 150P. However, in the present embodiment, when performing the Fig. 4I and Figure 6 When the process of etching the second insulating spacer 142B and the first insulating spacer 142A in the resulting structure to form a plurality of upper contact spaces UCS is performed, and when performing Figure 4J and Figure 7 When etching a plurality of preliminary conductive plugs 150 in the resulting structure to form the plurality of bonding pad spaces LPS2, the portions of the insulating liner 140, the insulating cap pattern 136, and the insulating fences 144B exposed through the plurality of upper contact spaces UCS may also be removed by controlling the etching selectivity, thereby forming the insulating cap pattern 236 each having a peak-shaped cap top 236T and the insulating fences 244B each having a peak-shaped fence top 244T. Each of the insulating fences 244B may include a fence base FB, a fence upper portion FU, and a peak-shaped fence top 244T.

[0116] The peak-shaped cap top 236T of the insulating cap pattern 236 may have a shape in which the width in the X direction gradually decreases as the distance from the substrate 110 increases. The peak-shaped fence top 244T of the insulating fence 244B may have a shape in which the width in the Y direction gradually decreases as the distance from the substrate 110 increases. Therefore, the width in the X direction and the width in the Y direction of each of the bonding pad spaces LPS2 defined by the plurality of insulating cap patterns 236 and the plurality of insulating fences 244B may increase in the direction from the substrate 110 to the entrance side.

[0117] Reference Fig.13A and Fig. 13B , according to the above reference Figure 4L and Fig. 9 A similar approach is described in Fig. 12A and Fig. 12BA pseudo-number-type capping layer 254 covering the plurality of insulating capping patterns 236 and the plurality of insulating fences 244B is formed on the resulting structure in which the plurality of bonding pad spaces LPS2 are formed.

[0118] The pseudo-fractional capping layer 254 may increase in width in the horizontal direction on the sidewalls of the plurality of insulating cap patterns 236 and the sidewalls of the plurality of insulating fences 244B as the distance from the substrate 110 increases. For example, on the sidewalls of the peak-shaped cap top 236T of each of the plurality of insulating cap patterns 236, the pseudo-fractional capping layer 254 may increase in width in the X direction as the distance from the substrate 110 increases. On the sidewalls of the peak-shaped fence top 244T of each of the plurality of insulating fences 244B, the pseudo-fractional capping layer 254 may increase in width in the Y direction as the distance from the substrate 110 increases. Detailed description of the formation of the pseudo-fractional capping layer 254 and reference Figure 4L A detailed description of the formation of the pseudo-type capping layer 154 is given to be the same.

[0119] According to this embodiment, Figure 4L and Fig. 9 Different from the embodiments of the present invention, the upper portions of the plurality of peak-type insulating cap patterns 236 and the upper portions of the plurality of peak-type insulating fences 244B decrease in width in the horizontal direction as the distance from the substrate 110 increases. Therefore, even when the width of the pseudo-number-shaped cap layer 254 in the horizontal direction increases as the distance from the substrate 110 increases, the width of each of the plurality of bonding pad spaces LPS2 in the horizontal direction after the pseudo-number-shaped cap layer 254 is formed may not decrease as the distance from the substrate 110 increases. According to some embodiments, according to the width of the upper portions of the plurality of peak-type insulating cap patterns 236 and the upper portions of the plurality of peak-type insulating fences 244B in the horizontal direction, the width of each of the plurality of bonding pad spaces LPS2 in the horizontal direction may not have a substantial change, gradually decrease, or gradually increase as the distance from the substrate 110 increases.

[0120] Reference Fig.14A and Fig. 14B , according to the above reference Figure 4M and Fig.10 In a similar manner to the described method, portions of the pseudo-number-type capping layer 254 covering the plurality of conductive plugs 150P are removed to expose respective upper surfaces of the plurality of conductive plugs 150P through the plurality of bonding pad spaces LPS2 .

[0121] Reference Fig.15A and Fig. 15B , in accordance with the above reference Figure 4N and Fig.11In a method similar to the method described above, a plurality of metal silicide layers 172 are formed on the plurality of conductive plugs 150P exposed through the plurality of bonding pad spaces LPS2, a plurality of conductive bonding pads LP are formed on the plurality of metal silicide layers 172, and an insulating layer 180 is formed to fill the insulating spaces 180S around the plurality of conductive bonding pads LP. Thereafter, a plurality of capacitor lower electrodes electrically connected to the plurality of conductive bonding pads LP may be formed on the insulating layer 180.

[0122] According to the above reference FIG. 12A to FIG. 15B The method of manufacturing the IC device 200 described above forms a pseudo integer type capping layer 254 whose width in the horizontal direction increases with increasing distance from the substrate 110 on the peak type insulating capping pattern 236 even when each peak type insulating capping pattern 236 including a peak type capping top 236T having a width in the X direction smaller than the width of each bit line BL in the X direction, thereby ensuring the minimum CD in the horizontal direction required for the insulating structure to cover the upper surface of the bit line BL. Therefore, even when parts of the pseudo integer type capping layer 254 and the peak type insulating capping pattern 236 are consumed due to etching of adjacent layers of each of the pseudo integer type capping layer 254 and the peak type insulating capping pattern 236 in a subsequent process, since sufficient insulating space is ensured between the peak type insulating capping pattern 236 and a plurality of conductive bonding pads LP around the pseudo integer type capping layer 254 or between other conductive patterns defined by the peak type insulating capping pattern 236 and the pseudo integer type capping layer 254, the occurrence of an undesirable short circuit can be prevented. In addition, since the insulating spacers SPC1 covering the corresponding two side walls of the plurality of bit lines BL are covered by the pseudo-single-type capping layer 254, after forming the plurality of metal silicide layers 172 and the plurality of conductive bonding pads LP in the bonding pad space LPS2 between two adjacent bit lines BL, sufficient insulation distances between the plurality of metal silicide layers 172 and the plurality of conductive bonding pads LP and the bit lines BL adjacent thereto can be ensured. Therefore, the occurrence of an undesirable short circuit between each conductive bonding pad LP and each bit line BL can be prevented.

[0123] While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the claims.

Claims

1. An integrated circuit device, comprising: a wire structure including a conductive line formed on a substrate and an insulating cover pattern covering the conductive line; an insulating spacer covering a side wall of the wire structure; A conductive plug is separated from the conductive wire in a first horizontal direction, and an insulating spacer is located between the conductive plug and the conductive wire; a conductive bonding pad arranged on the conductive plug to vertically overlap the conductive plug; as well as a capping layer including a first portion located between the conductive bonding pad and the insulating capping pattern and a third portion disposed between the conductive bonding pad and the insulating spacer, The first portion of the cover layer has a shape located between the conductive bonding pad and the insulating cover pattern, wherein a width in a first horizontal direction gradually increases as a distance from the substrate in a vertical direction increases.

2. The integrated circuit device according to claim 1, further comprising: an insulating fence, which is separated from the conductive wire in a first horizontal direction and covers the side wall of the conductive plug in a second horizontal direction perpendicular to the first horizontal direction, Wherein, the insulating spacer is formed between the insulating fence and the conductor, The cover layer further includes a second portion disposed between the conductive bonding pad and the insulating fence, and The second portion has a shape in which a width in the second horizontal direction gradually increases as a distance from the substrate in the vertical direction increases.

3. The integrated circuit device according to claim 1, in, The width of the first portion in the first horizontal direction is greater than the width of the third portion in the first horizontal direction.

4. The integrated circuit device according to claim 1, wherein: The conductive bonding pad includes a portion whose width in a horizontal direction gradually decreases as the distance from the substrate increases.

5. The integrated circuit device according to claim 1, further comprising: The metal silicide layer is disposed between the conductive plug and the conductive bonding pad and is separated from the conductive wire. The insulating spacer and the cap layer are located between the metal silicide layer and the conductive line.

6. The integrated circuit device according to claim 5, in, The third portion of the capping layer is separated from the conductive plug, and the metal silicide layer is located between the third portion and the conductive plug.

7. The integrated circuit device according to claim 1, in, The insulating cap pattern includes a peak-type cap top having a shape in which a width in a first horizontal direction gradually decreases as a distance from the substrate in a vertical direction increases, The first part of the cover layer is disposed between the conductive bonding pad and the peak-shaped cover top.

8. An integrated circuit device, the integrated circuit device comprising: a pair of wire structures including a pair of conductive lines extending parallel to each other on a substrate and adjacent to each other in a first horizontal direction and a pair of insulating cover patterns covering the pair of conductive lines; a conductive plug disposed between the pair of wire structures; a conductive bonding pad disposed on the conductive plug between the pair of wire structures; an insulating spacer covering the side walls of the pair of wire structures; as well as a capping layer including a first portion located between one of the pair of line structures and the conductive bonding pad and a third portion disposed between the conductive bonding pad and the insulating spacer, The first portion of the cover layer has a shape located between one of the pair of line structures and the conductive bonding pad, wherein a width in a first horizontal direction gradually increases as a distance from the substrate in a vertical direction increases.

9. The integrated circuit device according to claim 8, in, The conductive bonding pad includes a first sidewall facing the first portion of the cap layer, and Wherein, a separation distance between the first side wall and one of the pair of insulating cover patterns gradually increases as the distance from the substrate in the vertical direction increases.

10. The integrated circuit device according to claim 8, further comprising: an insulating fence, disposed between the pair of line structures and covering a side wall of the conductive plug in a second horizontal direction perpendicular to the first horizontal direction, The cover layer further includes a second portion located between the conductive bonding pad and the insulating fence, and The second portion has a shape in which a width in the second horizontal direction gradually increases as a distance from the substrate in the vertical direction increases.

11. The integrated circuit device according to claim 8, further comprising: an insulating fence disposed between the pair of wire structures and contacting a side wall of the conductive plug, The cover layer further includes a second portion located between the conductive bonding pad and the insulating fence. The conductive bonding pad includes a second side wall facing the second portion of the cover layer, and The separation distance between the second side wall and the insulating fence gradually increases as the distance from the substrate increases in the vertical direction.

12. The integrated circuit device according to claim 8, wherein: an insulating spacer between one of the pair of wire structures and the conductive bonding pad, The width of the first portion in the first horizontal direction is greater than the width of the third portion in the first horizontal direction.

13. The integrated circuit device according to claim 12, wherein: A third portion of the capping layer is disposed between one of the pair of line structures and the conductive bonding pad.

14. The integrated circuit device according to claim 12, wherein: The insulating spacers include oxide layers, nitride layers, air spacers, or a combination thereof.

15. The integrated circuit device according to claim 8, in, Each of the pair of insulating cap patterns includes a peak-shaped cap top having a shape in which a width in a first horizontal direction gradually decreases as a distance from the substrate in a vertical direction increases, and The first part of the cover layer is disposed between the conductive bonding pad and the peak-shaped cover top.

16. The integrated circuit device according to claim 8, wherein: an insulating spacer between one of the pair of line structures and the conductive plug and between one of the pair of line structures and the conductive bonding pad, Each of the pair of conductive lines is separated from the conductive bonding pad, and an insulating spacer and a cover layer are located between each of the pair of conductive lines and the conductive bonding pad.

17. The integrated circuit device according to claim 8, further comprising: an insulating spacer between one of the pair of line structures and the conductive plug and between one of the pair of line structures and the conductive bonding pad, and The metal silicide layer is located between the conductive plug and the conductive bonding pad. Each of the pair of conductive lines is separated from the metal silicide layer, and an insulating spacer and a capping layer are located between each of the pair of conductive lines and the metal silicide layer.

18. An integrated circuit device, the integrated circuit device comprising: a pair of wire structures including a pair of conductive lines extending parallel to each other on a substrate and adjacent to each other in a first horizontal direction and a pair of insulating cover patterns covering the pair of conductive lines; a plurality of contact structures disposed between the pair of line structures and aligned in a second horizontal direction perpendicular to the first horizontal direction; a plurality of insulating fences, alternating with the plurality of contact structures between the pair of line structures such that one insulating fence is located between two adjacent contact structures; an insulating spacer covering the side walls of the pair of wire structures; a capping layer including a first portion located between one of the pair of line structures and one of the plurality of contact structures and a third portion disposed between the conductive bonding pad and the insulating spacer, The first portion of the cover layer has a shape located between one of the pair of line structures and one of the plurality of contact structures, wherein a width in the first horizontal direction gradually increases as a distance from the substrate in a vertical direction increases.

19. The integrated circuit device according to claim 18, in, The cap layer further includes a second portion located between one of the plurality of contact structures and one of the plurality of insulating fences, and The second portion has a shape in which a width in the second horizontal direction gradually increases as a distance from the substrate in the vertical direction increases.

20. The integrated circuit device according to claim 18, in, Each of the plurality of contact structures includes a conductive plug disposed between the pair of conductive lines, a conductive bonding pad disposed between the pair of insulating cap patterns, and a metal silicide layer disposed between the conductive plug and the conductive bonding pad. The conductive bonding pad includes a portion whose width in the second horizontal direction gradually decreases as the distance from the substrate increases.

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