Vertical storage device

Abstract

A vertical storage device includes a gate electrode and a first structure on a substrate. The gate electrodes may be spaced apart from each other in a first direction perpendicular to the upper surface of the substrate. The first structure extends through the gate electrodes in the first direction and includes a channel and a variable resistance structure sequentially stacked in a horizontal direction parallel to the upper surface of the substrate. The variable resistance structure may include quantum dots (QDs).

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2018 - 0166554, filed on December 20, 2018, with the Korean Intellectual Property Office (KIPO), the content of which is incorporated herein by reference in its entirety. Technical field

[0003] The present inventive concept relates to a vertical storage device. Background art

[0004] A VNAND flash memory device including cells stacked in a vertical direction may have a high operating voltage, and as the number of stacked cells increases and the size of each cell decreases, interference between cells may increase. Therefore, a VNAND flash memory device with a low operating voltage and low inter - cell interference is desired.

[0005] Semiconductor nanocrystals, namely quantum dots (QDs), are semiconductor materials having a crystal structure with a size of several nanometers. Different from bulk materials, nanoparticles have physical properties (e.g., bandgap and melting point) depending on the particle size. Quantum dots have a very small size such that they have a large surface area per unit volume and exhibit a quantum confinement effect, and thus have physicochemical properties different from those of bulk materials. Quantum dots can absorb light from an excitation source and can emit light energy corresponding to the bandgap of the quantum dots. In quantum dots, the bandgap can be selected by controlling the size and / or composition of the nanocrystals. Summary of the invention

[0006] Example embodiments provide a vertical storage device with improved characteristics.

[0007] Example embodiments employ quantum dots in a vertical storage device to obtain these improved characteristics.

[0008] According to an aspect of the present inventive concept, a vertical storage device includes a gate electrode and a first structure on a substrate. The gate electrodes may be spaced apart from each other in a first direction perpendicular to the upper surface of the substrate. The first structure extends through the gate electrodes in the first direction and includes a channel and a variable - resistance structure sequentially stacked in a horizontal direction parallel to the upper surface of the substrate. The variable - resistance structure may include quantum dots (QDs).

[0009] According to one aspect of the inventive concept (which may reflect the same or different embodiments from the previously described aspects), a vertical storage device includes a gate electrode and a first structure on a substrate. The gate electrodes are spaced apart from each other in a first direction perpendicular to an upper surface of the substrate. The first structure extends through the gate electrodes in the first direction and includes a channel and a variable resistance structure sequentially stacked in a horizontal direction parallel to the upper surface of the substrate. The variable resistance structure may include a plurality of depletion regions spaced apart from each other in the first direction.

[0010] According to one aspect of the inventive concept (which may reflect the same or different embodiments from the previously described aspects), a vertical storage device includes a gate electrode and a first structure on a substrate. The gate electrodes are spaced apart from each other in a first direction perpendicular to an upper surface of the substrate. The first structure extends through the gate electrodes in the first direction and includes a gate insulating layer, a current path layer, and an information storage layer sequentially stacked in a horizontal direction parallel to the upper surface of the substrate starting from each gate electrode. The information storage layer may include quantum dots (QDs).

[0011] In an exemplary embodiment, instead of a charge storage structure, the vertical storage device may include a variable resistance structure, and thus may be operated with a relatively low operation voltage. In addition, interference between upper and lower cells may be low, and a thickness of the variable resistance structure serving as an information storage structure may be small, such that the vertical storage device may have enhanced integration.

[0012] Quantum dots may be formed in the variable resistance structure such that a conductive filament may be formed with relatively low energy, and thus information may be stored with a relatively low operation voltage. In addition, a plurality of depletion regions may be formed in the variable resistance structure such that the variable resistance structure may have a low resistance distribution. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figures 1 to 3 are a plan view and a cross-sectional view showing a vertical storage device according to an exemplary embodiment;

[0014] Figure 4A and Figure 4B respectively show a conductive filament formation energy and a resistance distribution of a variable resistance structure according to a comparative embodiment and an exemplary embodiment;

[0015] Figures 5 to 14 is a plan view and a cross-sectional view showing a method of manufacturing a vertical storage device according to an exemplary embodiment;

[0016] Figures 15 to 17 is a cross-sectional view showing a variable resistance structure of a vertical storage device according to an exemplary embodiment;

[0017] Figure 18is a cross-sectional view showing a vertical memory device according to an exemplary embodiment;

[0018] Figure 19 and Figure 20 is a cross-sectional view showing a method of manufacturing a vertical memory device according to an exemplary embodiment; and

[0019] Figure 21 is a cross-sectional view showing a vertical memory device according to an exemplary embodiment. DETAILED DESCRIPTION

[0020] Based on the following detailed description with reference to the accompanying drawings, the above and other aspects and features of a vertical memory device and a method of manufacturing the same according to an exemplary embodiment will be readily understood.

[0021] Figures 1 to 3 is a plan view and a cross-sectional view showing a vertical memory device according to an exemplary embodiment. Specifically, Figure 1 is the plan view, Figure 2 is the cross-sectional view taken along line A-A' in Figure 1 and Figure 3 is Figure 2 an enlarged cross-sectional view of the X region in

[0022] Hereinafter, a direction substantially perpendicular to the upper surface of the substrate may be referred to as a first direction, which may be referred to as a vertical direction; two directions substantially parallel to the upper surface of the substrate and intersecting each other may be referred to as a second direction and a third direction, respectively, and may be referred to as horizontal directions. In an exemplary embodiment, the second direction and the third direction may be substantially perpendicular to each other and may also be substantially perpendicular to the first direction. However, it should be understood that ordinal numbers such as "first", "second", "third", etc. may be used merely as labels for certain elements, directions, steps, etc. to distinguish these elements, directions, steps, etc. from each other. Terms not described with "first", "second", etc. in the specification may also be referred to as "first" or "second" in the claims. In addition, a term referred to by a specific ordinal number (e.g., "first" in a specific claim) may be described elsewhere by a different ordinal number (e.g., "second" in the specification or another set of claims).

[0023] Referring to Figures 1 to 3, The vertical memory device may include a gate electrode structure, an insulating pattern structure, and a first structure extending through the gate electrode structure and the insulating pattern structure on a substrate 100. The vertical memory device may further include a common source line (CSL) plate 110, an impurity region 120, pads 230 (e.g., a plurality of pads 230), division layers 260 (e.g., a plurality of division layers 260), contact plugs 280 (e.g., a plurality of contact plugs 280), bit lines 300 (e.g., a plurality of bit lines 300), and first to third interlayer insulating layers 240, 270, and 290 on the substrate 100. Items shown as plural in the figures may be described in the text with reference to only one of them, and that one item may have the same structure and function as the remaining plural items.

[0024] The substrate 100 may be or include silicon, germanium, silicon germanium, or a group III-V compound such as GaP, GaAs, GaSb, etc. In some embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0025] The CSL plate 110 and the impurity region 120 may be sequentially stacked on the substrate 100.

[0026] In an exemplary embodiment, the CSL plate 110 may be a conductive material, such as a metal like tungsten, or a metal silicide such as tungsten silicide. The impurity region 120 may be a conductive material, such as polysilicon doped with an n-type impurity.

[0027] The gate electrode structure may include a plurality of gate electrodes respectively located at multiple levels and spaced apart from each other in a first direction. The gate electrode structure may extend longitudinally in a second direction and a plurality of gate electrode structures may be formed in a third direction. An item, layer, or a part of an item or layer described as extending "longitudinally" in a specific direction has a length in that specific direction and a width perpendicular to that direction, where the length is greater than the width. For example, gate electrode structures each extending in the second direction at the same level may be spaced apart from each other in the third direction by an opening 250.

[0028] In an exemplary embodiment, the division layer 260 may extend longitudinally in the second direction in the opening 250. The division layer 260 may be an insulating layer formed of an insulating material and may be or include an oxide such as silicon oxide.

[0029] Each gate electrode structure may include a plurality of first gate electrodes 142 and at least one second gate electrode 144 sequentially stacked in a first direction.

[0030] In an exemplary embodiment, each first gate electrode 142 may be used as a word line, and the second gate electrode 144 may be used as a string select line (SSL).

[0031] Figure 2It is shown that the first gate electrode 142 is formed in four levels (e.g., vertical levels), and the second gate electrode 144 is formed in one level. However, the inventive concept is not limited thereto, and the second gate electrode 144 may also be formed in multiple levels. In some embodiments, some of the first gate electrodes 142 may be used as dummy word lines.

[0032] Both the first gate electrode 142 and the second gate electrode 144 may be or include a conductive material, such as polysilicon doped with impurities such as n-type impurities. In an exemplary embodiment, the thickness of the second gate electrode 144 in the first direction may be greater than the thickness of the first gate electrode 142 in the first direction.

[0033] The insulating pattern structure may include a plurality of insulating patterns 135 sequentially stacked in the first direction. The insulating patterns 135 may be respectively formed between the impurity region 120 and the first gate electrode 142, between the first gate electrode 142 and the gate electrodes adjacent to each other in the first direction among the first gate electrode 142 and the second gate electrode 144, and on the second gate electrode 144.

[0034] In an exemplary embodiment, at a specific level (e.g., vertical level) in the first direction, each insulating pattern 135 extends longitudinally in the second direction, and a plurality of insulating patterns 135 spaced apart from each other through the opening 250 are formed in the third direction. The insulating pattern 135 may be or include an insulating material, such as an oxide such as silicon oxide.

[0035] The first structure may extend from the upper surface of the impurity region 120 in the first direction through the gate electrode structure and the insulating pattern structure, and may include a channel 175 (e.g., a plurality of channels) and a variable resistance structure 215 (e.g., a plurality of variable resistance structures) sequentially stacked in a horizontal direction substantially parallel to the upper surface of the substrate 100, a gate insulating pattern 160 covering the outer sidewalls and the edge lower surface of the channel 175, and a filling pattern 220 filling the internal space formed by the inner walls of the variable resistance structure 215. The first structure may be provided in a plurality such that a plurality of first structures are formed, and each first structure includes a channel 175, a variable resistance structure 215, a gate insulating pattern 160, and a filling pattern 220.

[0036] In an exemplary embodiment, both the channel 175 and the variable resistance structure 215 may have a cup shape, and the bottom of the channel 175 may contact the upper surface of the impurity region 120. The term "contact" used herein refers to a direct connection, i.e., touching. The gate insulating pattern 160 may have a hollow cylindrical shape, and the filling pattern 220 may have a columnar shape. Therefore, the first structure may have a columnar shape extending in the first direction.

[0037] The gate insulating pattern 160 may be or include an oxide such as silicon oxide.

[0038] The channel 175 may be or include crystalline silicon such as polysilicon or single-crystalline silicon, and the fill pattern 220 may be or include an oxide such as silicon oxide. In an exemplary embodiment, a plurality of channels 175 may be formed in both the second direction and the third direction, and thus a channel array may be defined.

[0039] The variable resistance structure 215 may include a first variable resistance pattern 185 and a second variable resistance pattern 205 stacked in sequence and first quantum dots (QDs) 190 (e.g., a plurality of first quantum dots (QDs) 190) therein.

[0040] In an exemplary embodiment, the first variable resistance pattern 185 and the second variable resistance pattern 205 may include materials whose resistance may vary according to oxygen vacancies or oxygen movement.

[0041] For example, both the first variable resistance pattern 185 and the second variable resistance pattern 205 may be or include perovskite-based materials or transition metal oxides. Perovskite-based materials may include, for example, STO (SrTiO3), BTO (BaTiO3), PCMO (Pr 1-X Ca X MnO3), etc. Transition metal oxides may be or include titanium oxide (TiOx), zirconium oxide (ZrOx), aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), niobium oxide (NbOx), cobalt oxide (CoOx), tungsten oxide (WOx), lanthanum oxide (LaOx), zinc oxide (ZnOx), etc. These may be used alone or in combination.

[0042] Alternatively, both the first variable resistance pattern 185 and the second variable resistance pattern 205 may include materials whose resistance may vary according to their phase change. For example, both the first variable resistance pattern 185 and the second variable resistance pattern 205 may be or include chalcogenide materials, such as chalcogenide materials containing germanium, antimony, and / or tellurium.

[0043] In some embodiments, the first variable resistance pattern 185 and the second variable resistance pattern 205 may include substantially the same material, and thus may be merged with each other. For example, they may form an integral pattern without grain boundaries therebetween.

[0044] In an exemplary embodiment, a plurality of first QDs 190 may be formed to be spaced apart from each other in the first direction in the variable resistance structure 215. Some of the first QDs 190 may be in contact with each other.

[0045] In an exemplary embodiment, the first QD 190 may be formed in the second variable resistance pattern 205. The first QD 190 formed in the second variable resistance pattern 205 may be formed at an interface between the second variable resistance pattern 205 and the first variable resistance pattern 185 and may contact the surface of the first variable resistance pattern 185.

[0046] In an exemplary embodiment, the first QD 190 may be or include a metal, a metal silicide, or a semiconductor material. The metal may include, for example, platinum, tungsten, nickel, etc., the metal silicide may include, for example, tungsten silicide, and the semiconductor material may include, for example, silicon, germanium, silicon germanium, or carbon.

[0047] The pad 230 may be formed on the first structure and may partially extend through the uppermost insulating pattern 135. The pad 230 may be or include, for example, crystalline silicon doped with impurities.

[0048] The contact plug 280 may be formed on the pad 230, and the bit line 300 may be formed on the contact plug 280. The contact plug 280 may extend through the first interlayer insulating layer 240 and the second interlayer insulating layer 270 to contact the upper surface of the pad 230, and the bit line 300 may extend through the third interlayer insulating layer 290 to contact the upper surface of the contact plug 280.

[0049] The contact plug 280 and the bit line 300 may be or include a metal such as copper, aluminum, tungsten, titanium, tantalum, etc. and / or a metal nitride such as titanium nitride, tantalum nitride, tungsten nitride, etc., and the first to third interlayer insulating layers 240, 270, and 290 may be or include an oxide such as silicon oxide.

[0050] Instead of a charge storage structure having, for example, a tunnel insulating pattern, a charge storage pattern, and a blocking pattern, the vertical storage device may include a variable resistance structure 215 having variable resistance patterns 185 and 205. Therefore, it may not be necessary to perform an erase operation on all cells including a plurality of gate electrodes arranged in a first direction, but an erase operation may be performed on each cell including the gate electrodes at each level, so that a high operation voltage may not be required. In addition, the vertical storage device may not be a charge-based storage device but may be a current-based storage device, such that interference between upper and lower cells may be low.

[0051] The thickness of the variable resistance structure 215 serving as an information storage element may be smaller than the thickness of the charge storage structure, so the vertical storage device may have a small area. The variable resistance structure 215 may be referred to as an information storage structure, an information storage layer, or a variable resistance layer, and the first and second variable resistance patterns 185 and 205 may be respectively referred to as the first and second information storage structures or layers, or the first and second variable resistance layers. The channel 175 may be referred to as a current path pattern or a current path layer.

[0052] In the following, the difference between the variable resistance structure 215 including the first QD 190 according to the exemplary embodiment and the variable resistance structure without the QD in the comparative embodiment will be explained in detail.

[0053] Figure 4A and Figure 4B respectively show the conductive filament formation energy and resistance distribution of the variable resistance structures according to the comparative embodiment and the exemplary embodiment.

[0054] Referring to Figure 4A , oxygen vacancies (OVs) are stacked in a given region of the variable resistance structure, and a depletion region (D) is formed therebetween. When an operating voltage higher than a given value is applied to the given region, a conductive filament (F) can be formed in the given region where the depletion region (D) is not formed.

[0055] Referring to Figure 4B , quantum dots (QDs) can be disposed in a given region of the variable resistance structure, for example, arranged adjacent to each other in a first (e.g., vertical) direction with a space therebetween, so that a plurality of depletion regions (D) spaced apart from each other (e.g., in the first direction) can be formed in the given region (e.g., between adjacent second gate electrodes 142 in the on state). When an operating voltage higher than a given value is applied to the given region, a conductive filament (F) can be formed in the given region between the depletion regions (D). Since a plurality of depletion regions (D) are formed in the given region, a plurality of conductive filaments (F) can be formed, and the length of each conductive filament (F) can be less than Figure 4A the length of the conductive filament (F) of

[0056] Thus, in Figure 4B the variable resistance structure, the energy used to form the conductive filament can be less than that in Figure 4A the variable resistance structure, so that information can be stored by a relatively low operating voltage.

[0057] In Figure 4A the variable resistance structure, only one depletion region (D) having a relatively high resistance is formed, and the length of the other regions therein is relatively long, so that the resistance distribution can be large according to the distribution of oxygen vacancies (OVs) in the other regions. However, in Figure 4B the variable resistance structure, a plurality of depletion regions (D) each having a relatively high resistance can be formed, and the length of the other regions therein is relatively short, so that the resistance distribution can be small according to the distribution of oxygen vacancies (OVs) in the other regions.

[0058] Figures 5 to 14 is a plan view and a cross-sectional view showing a method of manufacturing a vertical memory device according to an exemplary embodiment. Specifically,Figure 6 and Figure 13 are plan views, Figure 5 , Figures 7 - 12 and Figure 14 are cross-sectional views taken along line A-A' in the corresponding plan views, respectively. Figure 10 and Figure 11 are Figure 9 magnified cross-sectional views of region X in

[0059] Referring to Figure 5 , CSL plates 110 (also referred to as CSL lines or CSL layers) and impurity regions 120 (also referred to as impurity layers) can be sequentially stacked on substrate 100, and insulating layer 130 and gate electrode layer 140 can be alternately and repeatedly formed along a first direction on impurity region 120.

[0060] Insulating layer 130 and gate electrode layer 140 can be formed by, for example, chemical vapor deposition (CVD) process, plasma enhanced chemical vapor deposition (PECVD) process, atomic layer deposition (ALD) process, etc. Insulating layer 130 can be or include an oxide such as silicon oxide, and gate electrode layer 140 can be or include, for example, polysilicon doped with n-type impurities.

[0061] Figure 5 shows insulating layer 130 and gate electrode layer 140 stacked in six layers and five layers, respectively. However, the present invention is not limited thereto. The thickness of the topmost gate electrode layer 140 can be greater than the thickness of other gate electrode layers 140, and the thickness of the topmost insulating layer 130 can be greater than the thickness of other insulating layers 130.

[0062] Referring to Figure 6 and Figure 7 , channel holes 150 can be formed through insulating layer 130 and gate electrode layer 140 to expose impurity region 120.

[0063] Specifically, a photoresist pattern (not shown) can be formed on the topmost insulating layer 130, and insulating layer 130 and gate electrode layer 140 can be etched using the photoresist pattern as an etching mask to form channel holes 150 exposing the upper surface of impurity region 120. In some embodiments, a part of impurity region 120 can also be etched in this process. In an exemplary embodiment, a plurality of channel holes 150 can be formed in both the second direction and the third direction to form a channel array.

[0064] Referring to Figure 8 , a gate insulating pattern 160 can be formed on the sidewalls of channel holes 150 and a part of the exposed upper surface of impurity region 120.

[0065] Specifically, a gate insulating layer and a spacer layer (not shown) can be conformally formed in sequence on the sidewalls of the channel holes 150, the exposed upper surfaces of the impurity regions 120, and the upper surface of the uppermost insulating layer 130. The spacer layer can be anisotropically etched to form spacers (not shown) on the sidewalls of the channel holes 150, and the gate insulating layer can be etched using the spacers as an etch mask to form a bottom-open cup-shaped gate insulating pattern 160 (commonly also referred to as the gate insulating layer) on the sidewalls of the channel holes 150 and the edges of the exposed upper surfaces of the impurity regions 120. During the etching process, the exposed upper portions of the impurity regions 120 can also be partially removed.

[0066] The gate insulating pattern 160 can be or include an oxide such as silicon oxide, and the spacers can be or include a nitride such as silicon nitride.

[0067] After removing the spacers, a channel layer 170 can be formed on the exposed upper surfaces of the impurity regions 120, the gate insulating pattern 160, and the uppermost insulating layer 130.

[0068] The channel layer 170 can be or include crystalline silicon such as polysilicon or single-crystalline silicon, or amorphous silicon. When the channel layer 170 includes amorphous silicon, the amorphous silicon can be converted into crystalline silicon by the heat generated during the formation process of other layers. Alternatively, a laser epitaxial growth (LEG) process or a solid-phase epitaxy (SPE) process can be further performed so that the amorphous silicon can be converted into crystalline silicon.

[0069] Refer to Figure 9 , a variable resistance structure layer 210 is formed on the channel layer 170, for example, in a conformal manner.

[0070] Reference will be made to Figure 10 and Figure 11 to describe a specific method for forming the variable resistance structure layer 210, Figure 10 and Figure 11 is Figure 9 an enlarged cross-sectional view of the X region in

[0071] Refer to Figure 10 , a first variable resistance layer 180 can be formed on the channel layer 170, and a first quantum dot (QD) 190 can be formed on the first variable resistance layer 180.

[0072] In an exemplary embodiment, the first variable resistance layer 180 can be or include a material whose resistance can vary according to oxygen vacancies or oxygen movement. Alternatively, the first variable resistance layer 180 can include a material whose resistance can vary according to its phase change.

[0073] The first QD 190 can be formed by forming a first QD formation layer on the first variable resistance layer 180 and annealing the first QD formation layer. The size of the first QD 190 can be changed according to the thickness of the first QD formation layer and the annealing temperature. In an exemplary embodiment, as the thickness of the first QD formation layer increases, the size of the first QD 190 increases.

[0074] In an exemplary embodiment, a plurality of first QDs 190 can be formed (e.g., arranged) relative to each other in a first direction, and the plurality of first QDs 190 can be spaced apart from each other or some of the plurality of first QDs 190 can be in contact with each other. Some QDs can also be arranged relative to each other in a horizontal direction.

[0075] Refer to Figure 11 , a second variable resistance layer 200 is formed on the first variable resistance layer 180 to cover the first QD 190.

[0076] In an exemplary embodiment, the second variable resistance layer 200 can be or include a material substantially the same as the material of the first variable resistance layer 180, and thus can be incorporated into the first variable resistance layer 180. In some embodiments, at the interface between the first variable resistance layer 180 and the second variable resistance layer 200, there is no distinct surface, so the combined layer is continuous.

[0077] Hereinafter, the first variable resistance layer 180 and the second variable resistance layer 200 sequentially stacked in a horizontal direction substantially parallel to the upper surface of the substrate 100 and the first QD 190 included therein can be collectively referred to as a variable resistance structure layer 210, or more generally as a variable resistance structure or a variable resistance layer. The variable resistance structure or the variable resistance layer can be described as having a first layer portion (e.g., from the first variable resistance layer 180) and a second layer portion (e.g., from the second variable resistance layer 200 and the first QD 190 therein). The first layer portion can be horizontally adjacent to the second layer portion, and one layer portion can include quantum dots while the other layer portion does not include quantum dots.

[0078] Refer to Figure 12 , a filling layer can be formed on the variable resistance structure layer 210 to fill the remaining portion of the channel hole 150, and the filling layer, the variable resistance structure layer 210, and the channel layer 170 can be planarized until the upper surface of the uppermost insulating layer 130 is exposed to form a filling pattern 220 that fills the remaining portion of the channel hole 150. After planarization, the remaining portions of the variable resistance structure layer 210 and the channel layer 170 can be formed, and these remaining portions can be respectively referred to as a variable resistance structure 215 and a channel 175.

[0079] Accordingly, a first structure can be formed. The first structure includes a gate insulating pattern 160, a channel 175, a variable resistance structure 215, and a filling pattern 220 that are sequentially stacked on the impurity region 120 in the channel hole 150. The variable resistance structure 215 can include a first variable resistance pattern 185 and a second variable resistance pattern 205 (refer to Figure 3 ) and a first QD 190 therein.

[0080] In an exemplary embodiment, both the channel 175 and the variable resistance structure 215 can have a cup shape, and the gate insulating pattern 160 can cover the outer sidewall and the edge lower surface of the channel 175. The filling pattern 220 can have a columnar shape that fills the internal space formed by the inner wall of the variable resistance structure 215.

[0081] The upper part of the first structure can be removed to form a trench, and a pad 230 can be formed to fill the trench.

[0082] In an exemplary embodiment, the pad 230 can be or include crystalline silicon doped with impurities, such as polysilicon or single-crystalline silicon doped with impurities, or amorphous silicon doped with impurities. When the pad 230 includes amorphous silicon doped with impurities, a crystallization process can be further performed on it.

[0083] Refer to Figure 13 and Figure 14 , a first interlayer insulating layer 240 is formed on the topmost insulating layer 130 and the pad 230, and an opening 250 is formed through the first interlayer insulating layer 240, the insulating layer 130, and the gate electrode layer 140 to expose the upper surface of the impurity region 120.

[0084] In an exemplary embodiment, the opening 250 can extend longitudinally in a second direction, and a plurality of openings 250 arranged in a third direction can be formed.

[0085] Due to the formation of the opening 250, the insulating layer 130 becomes an insulating pattern 135 (e.g., a plurality of insulating patterns 135) that extends longitudinally in the second direction, and the gate electrode layer 140 can become a gate electrode (e.g., a plurality of gate electrodes) that extends longitudinally in the second direction.

[0086] The gate electrode can extend in the second direction, and a plurality of gate electrodes can be formed (e.g., arranged) in the third direction at the same level. Accordingly, these plurality of gate electrodes that can each extend longitudinally in the second direction can be spaced apart from each other in the third direction through the opening 250.

[0087] In an exemplary embodiment, a gate electrode may be formed of a plurality of levels spaced apart from each other in a first direction, and each stacked layer of the gate electrode may form a gate electrode structure. A plurality of gate electrode structures spaced apart from each other may be formed in a third direction. Each gate electrode structure may include a plurality of first gate electrodes 142 and at least one second gate electrode 144.

[0088] Figure 14 It is shown that the first gate electrode 142 is formed of four levels and the second gate electrode 144 is formed of one level. However, the present invention is not limited thereto.

[0089] In an exemplary embodiment, the first gate electrode 142 serves as a word line and the second gate electrode 144 serves as an SSL. Some of the first gate electrodes 142 may serve as dummy word lines.

[0090] Referring again to Figures 1 to 3 , a partition layer 260 may be formed to fill the opening 250. A second interlayer insulating layer 270 may be formed on the first interlayer insulating layer 240 and the partition layer 260. A contact plug 280 may be formed through the first interlayer insulating layer 240 and the second interlayer insulating layer 270 to contact the upper surface of the pad 230. The partition layer 260 may also be referred to as a separation layer or an isolation layer.

[0091] A third interlayer insulating layer 290 may be formed on the second interlayer insulating layer 270 and the contact plug 280. A bit line 300 may be formed through the third interlayer insulating layer 290 to contact the upper surface of the contact plug 280.

[0092] In an exemplary embodiment, the bit line 300 extends longitudinally in the third direction, and a plurality of bit lines 300 may be formed (e.g., arranged) in the second direction.

[0093] A vertical memory device may be manufactured by the above process. The vertical memory device may be, for example, a semiconductor chip including an integrated circuit formed on a die.

[0094] Figures 15 to 17 is a cross-sectional view showing a variable resistance structure of a vertical memory device according to an exemplary embodiment. Figures 15 to 17 is Figure 2 an enlarged cross-sectional view of the X region in

[0095] Referring to Figure 15 , a part of each first QD 190 in the variable resistance structure 215 may be exposed (e.g., exposed to the outside of the variable resistance structure 215).

[0096] For example, a part of the first QD 190 in the second variable resistance pattern 205 may be exposed at the surface of the second variable resistance pattern 205, so that the first QD 190 may contact the surface of the filling pattern 220.

[0097] Referring to Figure 16 , in addition to the first variable resistor pattern 185 and the second variable resistor pattern 205, the variable resistor structure 215 may further include a third variable resistor pattern 207, and the second QD 195 may be formed in the third variable resistor pattern 207.

[0098] Therefore, the variable resistor structure 215 may include the first to third variable resistor patterns 185, 205, and 207 arranged in sequence, and the first QD 190 and the second QD 195 may be formed in the second variable resistor pattern 205 and the third variable resistor pattern 207, respectively. The third variable resistor pattern 207 may include a material substantially the same as the materials of the first variable resistor pattern 185 and the second variable resistor pattern 205. A plurality of second QDs 195 may be formed to be spaced apart from each other in a first direction, or some of the second QDs 195 may be in contact with each other.

[0099] Referring to Figure 17 , the variable resistor structure 215 may only include the second variable resistor pattern 205 in which the first QD 190 is provided. In this case, the first QD 190 may be in contact with the surface of the channel 175.

[0100] Figure 18 is a cross-sectional view showing a vertical memory device according to an exemplary embodiment. The vertical memory device may be substantially the same as or similar to the vertical memory device of Figures 1 to 3 , except for the gate electrode. Therefore, the same reference numerals denote the same elements and will not be described herein again.

[0101] Referring to Figure 18 , the second gate electrode 144 may be formed in the first layer and the second layer from top to bottom.

[0102] Each second gate electrode 144 may have a thickness substantially the same as the thickness of each first gate electrode 142.

[0103] In an exemplary embodiment, each of the first gate electrode 142 and the second gate electrode 144 may further include a metal pattern 146. For example, each of the first gate electrode 142 and the second gate electrode 144 may include a polysilicon pattern doped with an n-type impurity and a metal pattern 146, and the polysilicon pattern and the metal pattern 146 may be arranged in sequence in a third direction and may be in contact with each other. The metal pattern 146 may be formed at a portion of each of the first gate electrode 142 and the second gate electrode 144 adjacent to the opening 250 or the partitioning layer 260.

[0104] Each of the first gate electrode 142 and the second gate electrode 144 may include the metal pattern 146 so that its total resistance may be reduced.

[0105] Figure 19 and Figure 20 is a cross-sectional view showing a method of manufacturing a vertical storage device according to an exemplary embodiment. The method may include processes substantially the same as or similar to the processes described with reference to Figures 5 to 14 and Figures 1 to 3 and thus will not be described herein again.

[0106] With reference to Figure 19 , processes substantially the same as or similar to the processes described with reference to Figure 5 may be performed.

[0107] However, the thickness of the topmost gate electrode layer 140 may not be greater than but may be substantially equal to the thickness of the other gate electrode layers 140.

[0108] With reference to Figure 20 , processes substantially the same as or similar to the processes described with reference to Figures 6 to 14 may be performed.

[0109] A portion of the gate electrode layer 140 exposed by the opening 250 may be removed to form a gap, and a metal pattern 146 may be formed to fill the gap.

[0110] In the exemplary embodiment, the gap may be formed by a wet etching process.

[0111] The metal pattern 146 may be or include a metal such as tungsten, titanium, tantalum, etc.

[0112] Processes substantially the same as or similar to the processes described with reference to Figures 1 to 3 may be performed to complete the manufacture of the vertical storage device.

[0113] Figure 21 is a cross-sectional view showing a vertical storage device according to an exemplary embodiment. The vertical storage device may be substantially the same as or similar to the vertical storage device of Figures 1 to 3 except for the gate electrodes. Thus, the same reference numerals denote the same elements and will not be described herein again.

[0114] With reference to Figure 21 , a second gate electrode 144 may be formed on the topmost layer, and its thickness may be greater than the thickness of each first gate electrode 142, as Figures 1 to 3 shown.

[0115] However, each first gate electrode 142 may also include a metal pattern 146, as Figure 18 shown.

[0116] Although example embodiments have been specifically shown and described, those of ordinary skill in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the claims.

[0117] When referring to orientation, layout, position, shape, size, quantity, or other measurements, terms such as "same", "equal", "parallel", or "perpendicular" as used herein do not necessarily mean exactly the same orientation, layout, position, shape, size, quantity, or other measurements, but are intended to encompass nearly the same orientation, layout, position, shape, size, quantity, or other measurements within acceptable variations that may occur, for example, due to manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning. For example, items described as "substantially the same", "substantially equal", "substantially parallel", or "substantially perpendicular" may be exactly the same, equal, parallel, or perpendicular, or may be the same, equal, parallel, or perpendicular within acceptable variations that may occur, for example, due to manufacturing processes.

Claims

1. A vertical storage device, comprising: Gate electrodes on a substrate, the gate electrodes being spaced apart from each other in a first direction substantially perpendicular to the upper surface of the substrate; And A first structure that extends through the gate electrodes in the first direction and includes a channel and a variable resistance structure sequentially stacked in a horizontal direction substantially parallel to the upper surface of the substrate, Wherein the variable resistance structure includes quantum dots, Wherein the quantum dots included in the variable resistance structure are arranged relative to each other in the first direction and have a space therebetween, Wherein the variable resistance structure includes a plurality of depletion regions spaced apart from each other in the first direction, Wherein each of the plurality of depletion regions is disposed in a corresponding space in the space between adjacent quantum dots in the first direction, and Wherein current flows through the quantum dots and the plurality of depletion regions.

2. The vertical storage device according to claim 1, wherein the quantum dots are formed of a metal, a metal silicide, or a semiconductor material.

3. The vertical storage device according to claim 2, wherein the quantum dots are formed of platinum, tungsten, nickel, or tungsten silicide.

4. The vertical storage device according to claim 2, wherein the quantum dots are formed of silicon, germanium, silicon germanium, or carbon.

5. The vertical storage device according to claim 1, wherein some of the quantum dots in the variable resistance structure are arranged relative to each other in the horizontal direction.

6. The vertical storage device according to claim 1, wherein no quantum dots are exposed to the outside of the variable resistance structure.

7. The vertical storage device according to claim 1, wherein some of the quantum dots are formed at the surface of the variable resistance structure to be exposed to the outside of the variable resistance structure.

8. The vertical storage device according to claim 7, wherein the quantum dots contact the surface of the channel.

9. The vertical storage device according to claim 1, wherein the variable resistance structure is formed of a perovskite-based material, a transition metal oxide, or a chalcogenide material.

10. The vertical storage device according to claim 1, wherein the variable resistance structure is a layer conformally formed on the channel.

11. The vertical storage device according to claim 1, wherein the variable resistance structure is a single layer.

12. The vertical storage device according to claim 1, wherein the variable resistance structure includes multiple layers sequentially stacked in the horizontal direction.

13. The vertical storage device according to claim 12, wherein the variable resistance structure includes a first variable resistance pattern and a second variable resistance pattern sequentially stacked in the horizontal direction starting from the channel, such that the first variable resistance pattern is located between the channel and the second variable resistance pattern, and Wherein the quantum dots are formed in the second variable resistance pattern.

14. The vertical storage device according to claim 12, wherein the variable resistance structure includes a first variable resistance pattern, a second variable resistance pattern, and a third variable resistance pattern sequentially stacked in the horizontal direction starting from the channel, and Wherein the quantum dots are formed in each of the second variable resistance pattern and the third variable resistance pattern.

15. The vertical memory device according to claim 1, wherein the first structure further includes a gate insulating pattern, and wherein the gate insulating pattern, the channel, and the variable resistance structure are sequentially stacked in the horizontal direction starting from the sidewalls of each gate electrode.

16. The vertical memory device according to claim 1, wherein both the variable resistance structure and the channel have a cup shape, and wherein the first structure further includes a filling pattern filling an internal space formed by an inner wall of the variable resistance structure.

17. The vertical memory device according to claim 1, wherein each gate electrode includes polysilicon doped with impurities.

18. The vertical memory device according to claim 17, wherein each gate electrode further includes a metal pattern.

19. A vertical memory device, comprising: gate electrodes on a substrate, the gate electrodes being spaced apart from each other in a first direction substantially perpendicular to an upper surface of the substrate; and a first structure extending through the gate electrodes in the first direction and including a channel and a variable resistance structure sequentially stacked in a horizontal direction substantially parallel to the upper surface of the substrate, wherein a plurality of depletion regions spaced apart from each other in the first direction are included in the variable resistance structure, wherein quantum dots are included between the depletion regions in the variable resistance structure, wherein each of the plurality of depletion regions is disposed in a corresponding space in a space between adjacent quantum dots in the first direction, and wherein current flows through the quantum dots and the plurality of depletion regions.

20. A vertical memory device, comprising: gate electrodes on a substrate, the gate electrodes being spaced apart from each other in a first direction substantially perpendicular to an upper surface of the substrate; and a first structure extending through the gate electrodes in the first direction and including a gate insulating pattern, a current path pattern, and an information storage structure sequentially stacked in a horizontal direction substantially parallel to the upper surface of the substrate starting from each gate electrode, wherein quantum dots are included in the information storage structure, wherein the quantum dots included in the information storage structure are arranged relative to each other in the first direction with a space therebetween, wherein a plurality of depletion regions spaced apart from each other in the first direction are included in the information storage structure, wherein each of the plurality of depletion regions is disposed in a corresponding space in the space between adjacent quantum dots in the first direction, and wherein current flows through the quantum dots and the plurality of depletion regions.

21. The vertical memory device according to claim 20, wherein the gate insulating pattern is a gate insulating layer, the current path pattern is a current path layer, and the information storage structure is an information storage layer.

22. The vertical storage device according to claim 21, wherein the information storage layer includes a first information storage portion and a second information storage portion sequentially arranged in the horizontal direction starting from the current path layer, such that the first information storage portion is located between the current path layer and the second information storage portion, and wherein the quantum dots are formed in the second information storage portion.

23. The vertical storage device according to claim 21, wherein the information storage layer includes a first information storage portion, a second information storage portion, and a third information storage portion sequentially arranged in the horizontal direction starting from the current path layer, and wherein the quantum dots are formed in each of the second information storage portion and the third information storage portion.

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