A high and low voltage protection circuit

Abstract

The present invention relates to the field of power management, and discloses a high and low voltage protection circuit, including a voltage conversion module, an undervoltage lockout module, a reference voltage module, an oscillator, a timer, a voltage detection module, a logic control module, a drive circuit and a MOS tube. The voltage conversion module converts the bus voltage into an operating voltage, the undervoltage lockout module outputs a start signal when the operating voltage is higher than a set start voltage, the reference voltage module inputs a reference voltage to the voltage detection module, the voltage detection module detects the bus voltage, and the logic control module controls the MOS tube to turn on or off through the drive circuit. The present invention is novel in design, performs voltage protection when the bus voltage is too high or too low, and disconnects the control circuit system from the bus, thereby preventing the circuit control system from being damaged due to excessive bus voltage fluctuations.

Description

Technical Field

[0001] The invention relates to the field of power management, and in particular to a high and low voltage protection circuit. Background Art

[0002] like Figure 1 As shown in the figure, the input AC voltage range of commonly used AC-DC power adapters or AC-DC control circuit systems is 85V to 300V. However, the grid voltage in some countries or regions is unstable and its amplitude may exceed this range. Generally, the withstand voltage of the input capacitor C1 on the AC-DC bus is 400V. Figure 1 As shown in the figure, when the input AC voltage exceeds 300V, the rectified DC voltage is 424V, which exceeds the withstand voltage of the input capacitor C1 and will cause damage or explosion of the input capacitor C1. If a higher withstand voltage input capacitor C1 is used, the manufacturing cost of the system will increase. In addition, if the bus input AC voltage is too low, it is easy to cause the control chip circuit to be damaged due to excessive stress. Summary of the invention

[0003] In view of the shortcomings of the background technology, the present invention provides a high and low voltage protection circuit, which turns on the protection function when it detects that the input bus AC voltage is too high or too low, thereby protecting the input capacitor and the control chip so that they always operate within the normal bus AC voltage.

[0004] In order to solve the above technical problems, the present invention provides the following technical solutions: a high and low voltage protection circuit, including a voltage conversion module, an undervoltage lockout module, a reference voltage module, an oscillator, a timer, a voltage detection module, a logic control module, a drive circuit and a MOS tube;

[0005] The voltage conversion module converts the bus voltage into an operating voltage;

[0006] The undervoltage lockout module outputs a start signal when the operating voltage is higher than a set start voltage;

[0007] The reference voltage module inputs the reference voltage VUP, the reference voltage VDN and the reference voltage VST to the voltage detection module. The reference voltage VUP is used to determine whether the bus voltage is higher than the high voltage threshold, the reference voltage VDN is used to determine whether the bus voltage is lower than the low voltage threshold, and the reference voltage VST is used to detect whether the bus voltage is lower than the turn-on voltage of the MOS tube at the initial power-on.

[0008] The voltage detection module includes a sampling circuit, a first voltage comparator, a second voltage comparator and a third voltage comparator. The sampling circuit samples the bus voltage and inputs the sampled voltage to the positive input terminal of the first voltage comparator, the negative input terminal of the second voltage comparator and the negative input terminal of the third voltage comparator. The negative input terminal of the first voltage comparator is connected to a reference voltage VUP, the positive input terminal of the second voltage comparator is connected to a reference voltage VDN, the positive input terminal of the third voltage comparator is connected to a reference voltage VST, and the output terminals of the first voltage comparator, the second voltage comparator and the third voltage comparator are all electrically connected to the logic control module;

[0009] The logic control module inputs a driving signal to the driving circuit and a control signal to the oscillator respectively, the output end of the driving circuit is electrically connected to the gate of the MOS tube, the source of the MOS tube is electrically connected to the peripheral circuit, the drain of the MOS tube is grounded, the timer counts according to the output signal of the oscillator, and inputs a timing signal to the logic control module after the timing time is up.

[0010] Furthermore, it also includes an overcurrent detection module, one input end of the overcurrent detection module is electrically connected to one end of the sampling resistor RCS and the drain of the MOS tube, the other input end of the overcurrent detection module is connected to the overcurrent reference voltage, the output end of the overcurrent detection module is electrically connected to the logic module, and the other end of the sampling resistor RCS is grounded.

[0011] Further, the sampling circuit includes a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4 and a resistor R1, the drain of the third NMOS tube is electrically connected to the gate of the third NMOS tube N3, the gate of the fourth NMOS tube N4 and one end of the sampling resistor RUP, the other end of the sampling resistor RUP is connected to the bus, the source of the third NMOS tube N3 is electrically connected to the drain of the first NMOS tube N1 and the gate of the first NMOS tube N1 and the gate of the second NMOS tube N2, the source of the first NMOS tube N1 and the source of the second NMOS tube N2 are both grounded, and the The source of the first PMOS tube P1 and the source of the second PMOS tube P2 are both connected to the power supply, the gate of the first PMOS tube P1 is electrically connected to the gate of the second PMOS tube P2, the drain of the first PMOS tube P1 and the source of the third PMOS tube P3, the drain of the second PMOS tube P2 is electrically connected to the source of the fourth PMOS tube P4, the gate of the third PMOS tube P3 is electrically connected to the gate of the fourth PMOS tube P4, the drain of the third PMOS tube P3 and the drain of the fourth NMOS tube N4, the drain of the fourth PMOS tube P4 is electrically connected to the positive input terminal of the first voltage comparator, the negative input terminal of the second voltage comparator, the negative input terminal of the third voltage comparator and one end of the resistor R1, and the other end of the resistor R1 is grounded.

[0012] Compared with the prior art, the present invention has the following beneficial effects: through the high and low voltage protection circuit, when the power adapter or other control circuit systems are connected to the bus, if the bus voltage fluctuates and is not within the input voltage range of the power adapter, the high and low voltage protection circuit can promptly form a circuit break between the bus and the power adapter, thereby protecting the power adapter from being damaged by the impact of the bus voltage, preventing the input bus capacitor from being damaged or exploding, and also preventing the control chip circuit of the power adapter from being damaged due to excessive stress when the bus voltage is too low. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The present invention has the following accompanying drawings:

[0014] Figure 1 This is the structural diagram of a commonly used AC-DC control system;

[0015] Figure 2 is a system structure diagram of the present invention;

[0016] Figure 3 is a circuit diagram of a voltage detection module of the present invention;

[0017] Figure 4 is an application circuit diagram of the present invention;

[0018] Figure 5 A schematic diagram of the bus voltage for starting the MOS tube of the present invention;

[0019] Figure 6 A schematic diagram of bus voltage for overvoltage protection of the present invention;

[0020] Figure 7 A schematic diagram of bus voltage for low voltage protection of the present invention;

[0021] Figure 8 It is the work flow chart of the present invention. DETAILED DESCRIPTION

[0022] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0023] like Figure 2-3 As shown, a high and low voltage protection circuit includes a voltage conversion module, an undervoltage lockout module, a reference voltage module, an oscillator, a timer, a voltage detection module, a logic control module, a drive circuit, an overcurrent detection module and a MOS tube, wherein the MOS tube is a high voltage MOSFET;

[0024] The voltage conversion module converts the bus voltage into an operating voltage;

[0025] The undervoltage lockout module, namely UVLO, outputs a start signal when the operating voltage is higher than the set start voltage;

[0026] The reference voltage module inputs the reference voltage VUP, the reference voltage VDN and the reference voltage VST to the voltage detection module. The reference voltage VUP is used to determine whether the bus voltage is higher than the high voltage threshold. The reference voltage VDN is used to determine whether the bus voltage is lower than the low voltage threshold. The reference voltage VST is used to detect whether the bus voltage is lower than the turn-on voltage of the MOS tube at the initial power-on. In this embodiment, VUP = 1.05V, VDN = 0.3V, and VST = 0.1V.

[0027] The voltage detection module includes a sampling circuit, a first voltage comparator, a second voltage comparator and a third voltage comparator. The sampling circuit includes a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4 and a resistor R1. The drain of the third NMOS tube is electrically connected to the gate of the third NMOS tube N3, the gate of the fourth NMOS tube N4 and one end of the sampling resistor RUP, and the other end of the sampling resistor RUP is connected to the bus. The source of the third NMOS tube N3 is electrically connected to the drain of the first NMOS tube N1 and the gate of the first NMOS tube N1 and the gate of the second NMOS tube N2, respectively. The source of the first NMOS tube N1 and The source of the second NMOS tube N2 is grounded, the source of the first PMOS tube P1 and the source of the second PMOS tube P2 are connected to the power supply, the gate of the first PMOS tube P1 is electrically connected to the gate of the second PMOS tube P2, the drain of the first PMOS tube P1 and the source of the third PMOS tube P3, the drain of the second PMOS tube P2 is electrically connected to the source of the fourth PMOS tube P4, the gate of the third PMOS tube P3 is electrically connected to the gate of the fourth PMOS tube P4, the drain of the third PMOS tube P3 and the drain of the fourth NMOS tube N4, the drain of the fourth PMOS tube P4 is electrically connected to the positive input terminal of the first voltage comparator, the negative input terminal of the second voltage comparator, the negative input terminal of the third voltage comparator and one end of the resistor R1, and the other end of the resistor R1 is grounded.

[0028] The working principle of the voltage detection module is as follows: the first NMOS tube N1 and the second NMOS tube N2 are a pair of current proportional sources, and their ratio is K1. The first PMOS tube P1 and the second PMOS tube P2 are also proportional current sources, and their ratio is K2. The resistor R1 is also a sampling resistor. The bus voltage is converted into current through the sampling resistor RUP, and a voltage is formed on the resistor R1. The voltage is:

[0029]

[0030] Since VGS can be approximately equal to VT, and the VLN voltage is much larger than the VGS voltage, the impact of the VGS voltage fluctuation on the system can be ignored. Therefore, in this example, VGS=1V is set, and the voltage across the resistor R1 is:

[0031]

[0032] The voltage change of VR1 can characterize the change of bus voltage. The reference voltage VUP, reference voltage VDN and reference voltage VST are respectively the bus voltage detection reference, bus voltage detection reference and startup voltage reference. The voltage detection module compares VR1 with the reference voltage VUP, reference voltage VDN and reference voltage VST to determine whether the bus voltage is too high, too low and whether the MOS tube is allowed to start.

[0033] The logic control module inputs a driving signal to the driving circuit and a control signal to the oscillator respectively, the output end of the driving circuit is electrically connected to the gate of the MOS tube, the source of the MOS tube is electrically connected to the peripheral circuit, the drain of the MOS tube is grounded, the timer counts according to the output signal of the oscillator, and inputs a timing signal to the logic control module after the timing time is up.

[0034] One input end of the overcurrent detection module is electrically connected to one end of the sampling resistor RCS and the drain of the MOS tube, the other input end of the overcurrent detection module is connected to the overcurrent reference voltage, the output end of the overcurrent detection module is electrically connected to the logic module, and the other end of the sampling resistor RCS is grounded.

[0035] At the moment when the system, i.e. the high and low voltage protection circuit, is powered on, the bus voltage may fall on any phase of the AC signal. At this time, if the logic control module turns on the high-voltage MOSFET, the voltage of the bus falling on the capacitor C1 may be the peak voltage. In this case, the current charging the capacitor and the current flowing through the high-voltage MOSFET will be very large, and the transient power consumption of the high-voltage MOSFET will be very large, and it may even damage the high-voltage MOSFET.

[0036] Therefore, at the initial power-on, the high-voltage MOSFET is not turned on, that is, GND and DRN are disconnected, the busbar supplies power to the voltage conversion module through LN, and the VCC voltage rises slowly. When the VCC voltage is greater than the UVLO start voltage (set to 9.5V in this embodiment), the UVLO is turned on, and the system starts to detect the DET pin current and enters the working state, but does not perform overvoltage and overcurrent protection detection until it is detected that the current of the DET pin is equivalent to the voltage on the internal resistor R1 is less than VST (currently set to 1 / 3 of the VDN low-voltage detection), and the logic control module controls the high-voltage MOSFET to turn on. After the high-voltage MOSFET is turned on, there is a path between GND and DRN, and the capacitor C1 is connected to the busbar, and starts to charge from the low voltage. Since the voltage on the capacitor C1 is low, the charging current is small, and the transient power consumption of the high-voltage MOSFET is low, so the high-voltage MOSFET works in a safe area. Figure 5 Point A in the diagram is where the high-voltage MOSFET turns on.

[0037] When the high-voltage MOSFET is turned on, the bus voltage drops to Figure 5 At point A in the circuit, the voltage detection module starts to perform low-voltage UVP detection, and the oscillator starts to oscillate, and the timer starts timing. Within half an AC cycle (10ms), if VR1 is always lower than VDN, the UVP protection is triggered, that is, the logic control module turns off the high-voltage MOSFET and starts timing. After TDELAY is full, the system triggers the UVLO signal and starts re-detection. The timing starts when the bus voltage reaches point A again. If VR1 is not less than VDN within 10ms, the system starts to work normally.

[0038] like Figure 7 As shown, under normal working conditions, if VR1 is less than VDN and continues to be TUVP, the UVP protection is triggered, that is, the logic control module controls the high-voltage MOSFET to disconnect and starts timing. After TDELAY is full, the system triggers the UVLO signal and starts re-detection.

[0039] like Figure 6 As shown in the figure, when the bus detection voltage VR1 exceeds VUP, the system starts OVP detection and starts timing. If VR1 is always higher than VUP during the Tovp time, the OVP protection is triggered. At this time, the system turns off the high-voltage MOSFET and starts timing. After TDELAY is full, the system triggers the UVLO signal and starts re-detection.

[0040] The calculation formula for the maximum and minimum busbar voltages allowed to be connected to the system is as follows:

[0041] The upper resistance of the DET pin is RUP, and the upper voltage of the detection is calculated as follows:

[0042]

[0043]

[0044] In this embodiment, RUP = 5.1M, K1*K2 = 30, R1 = 42K, then the protection range of AC input is 85V ~ 298V, the system works normally within this range, and the system triggers the protection function outside this range. This range is fixed, but can be moved up and down. This range can be adjusted by adjusting RUP.

[0045] The above is based on the present invention as an inspiration. Through the above description, relevant staff can make various changes and modifications without departing from the technical idea of ​​this invention. The technical scope of this invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A high and low voltage protection circuit, characterized in that: It includes a voltage conversion module, an undervoltage lockout module, a reference voltage module, an oscillator, a timer, a voltage detection module, a logic control module, a drive circuit and a MOS tube; The voltage conversion module converts the bus voltage into an operating voltage; The undervoltage lockout module outputs a start signal when the operating voltage is higher than a set start voltage; The reference voltage module inputs a reference voltage VUP, a reference voltage VDN and a reference voltage VST to the voltage detection module, wherein the reference voltage VUP is used to determine whether the bus voltage is higher than the high voltage threshold, the reference voltage VDN is used to determine whether the bus voltage is lower than the low voltage threshold, and the reference voltage VST is used to detect whether the bus voltage is lower than the turn-on voltage of the MOS tube at the initial power-on; The voltage detection module includes a sampling circuit, a first voltage comparator, a second voltage comparator and a third voltage comparator. The sampling circuit samples the bus voltage and inputs the sampled voltage to the positive input terminal of the first voltage comparator, the negative input terminal of the second voltage comparator and the negative input terminal of the third voltage comparator. The negative input terminal of the first voltage comparator is connected to a reference voltage VUP, the positive input terminal of the second voltage comparator is connected to a reference voltage VDN, and the positive input terminal of the third voltage comparator is connected to a reference voltage VST. The output terminals of the first voltage comparator, the second voltage comparator and the third voltage comparator are all electrically connected to the logic control module. The logic control module inputs a driving signal to the driving circuit and a control signal to the oscillator respectively, the output end of the driving circuit is electrically connected to the gate of the MOS tube, the source of the MOS tube is electrically connected to the peripheral circuit, the drain of the MOS tube is grounded, the timer counts according to the output signal of the oscillator, and inputs a timing signal to the logic control module after the timing time is up; It also includes an overcurrent detection module, one input end of the overcurrent detection module is electrically connected to one end of the sampling resistor RCS and the drain of the MOS tube, the other input end of the overcurrent detection module is connected to the overcurrent reference voltage, the output end of the overcurrent detection module is electrically connected to the logic module, and the other end of the sampling resistor RCS is grounded; The sampling circuit includes a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4 and a resistor R1. The drain of the third NMOS tube is electrically connected to the gate of the third NMOS tube N3, the gate of the fourth NMOS tube N4 and one end of the sampling resistor RUP respectively. The other end of the sampling resistor RUP is connected to the bus. The source of the third NMOS tube N3 is electrically connected to the drain of the first NMOS tube N1 and the gate of the first NMOS tube N1 and the gate of the second NMOS tube N2 respectively. The source of the first NMOS tube N1 and the source of the second NMOS tube N2 are both grounded. The source of the first PMOS tube P1 and the source of the second PMOS tube P2 are both connected to the power supply, the gate of the first PMOS tube P1 is electrically connected to the gate of the second PMOS tube P2, the drain of the first PMOS tube P1 and the source of the third PMOS tube P3, the drain of the second PMOS tube P2 is electrically connected to the source of the fourth PMOS tube P4, the gate of the third PMOS tube P3 is electrically connected to the gate of the fourth PMOS tube P4, the drain of the third PMOS tube P3 and the drain of the fourth NMOS tube N4, the drain of the fourth PMOS tube P4 is electrically connected to the positive input terminal of the first voltage comparator, the negative input terminal of the second voltage comparator, the negative input terminal of the third voltage comparator and one end of the resistor R1, and the other end of the resistor R1 is grounded.

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