A packaging method for ultra-thin substrate and chip structure thereof

Abstract

The invention relates to a packaging method of an ultra-thin substrate and a chip structure thereof. The method comprises the following steps: a first step: making a carrier substrate; a second step: high-temperature baking the carrier substrate; a third step: mechanical drilling; a fourth step: circuit manufacturing to obtain a dry film layer cavity; a fifth step: circuit detection; a sixth step: pickling and trimming the copper thickness of the copper foil layer; a seventh step: electroplating the circuit and stripping the film, electroplating the circuit in the dry film layer cavity to form a circuit layer, and peeling off the dry film layer, wherein the circuit layer is arranged on the top surface of the copper foil layer; an eighth step: printing an ink layer and developing it; a ninth step: nickel-plating a gold layer; a tenth step: pasting a chip on the top of the carrier substrate of the ninth step, bonding and interconnecting, and packaging; and an eleventh step: peeling off the carrier substrate to obtain a finished product, and cutting the finished product to obtain a finished chip.

Description

Technical Field

[0001] The invention relates to a substrate packaging method and a chip structure thereof, in particular to a method suitable for manufacturing an ultra-thin chip and a chip structure thereof. Background Art

[0002] In today's information age, with the rapid development of the electronics industry, products such as computers and mobile phones are becoming increasingly popular. People have more and more functional requirements for electronic products and stronger performance requirements, which has prompted electronic products to develop in the direction of multi-function, high performance, miniaturization and lightness. To achieve this goal, the characteristic size of IC chips must be smaller and smaller, and the complexity is increasing. In order to meet this development requirement, ultra-thin packaging substrate technology has emerged. And this technology is still developing in the direction of fine pitch and high-end numbers. However, the current substrate packaging method and structure cannot adapt to ultra-thin and small-sized packaging, which is the main disadvantage of traditional technology. Summary of the invention

[0003] The technical solution adopted by the present invention is: a packaging method for an ultra-thin substrate, which is suitable for packaging chips and includes the following steps.

[0004] The first step: making a carrier substrate, the carrier substrate includes a substrate layer, a copper clad layer and a copper foil layer, wherein the copper clad layer is respectively arranged on the top surface and the bottom surface of the substrate layer, and the copper foil layer is arranged on the top of the copper clad layer on the top surface of the substrate layer.

[0005] The second step: high temperature baking of the carrier substrate, and the third step: mechanical drilling.

[0006] Step 4: Circuit production, obtaining a dry film layer cavity, the specific steps are as follows: Step 1, medium roughening and lamination, setting a dry film layer on top of the copper foil layer, Step 2, circuit exposure, Step 3, development and etching to remove the film.

[0007] The fifth step is to detect the circuit. The sixth step is to pickle and adjust the copper thickness of the copper foil layer. The seventh step is to electroplate the circuit and strip the film. The circuit is electroplated in the cavity of the dry film layer to form a circuit layer, and the dry film layer is peeled off. The circuit layer is arranged on the top surface of the copper foil layer.

[0008] Step 8: Printing and developing the ink layer. Printing the ink layer on the top of the carrier substrate in step 7 and developing the ink layer to form a plurality of openings. The bottom surface of the ink layer is arranged on the top surface of the copper foil layer. At the same time, the ink layer is embedded in the circuit layer. The ink layer includes an embedded portion and a top portion. The top portion is fixedly connected to the top of the embedded portion. The top portion has an opening. The circuit layer is directly below the opening. The embedded portion is embedded in the circuit layer. The circuit layer includes a plurality of circuits. The embedded portion is arranged between any two adjacent circuits. The top portion is pressed on the top of the circuit.

[0009] Step 9: nickel-gold plating. A nickel layer and a gold layer are electroplated on the top of the circuit layer in step 8, respectively. The nickel layer and the gold layer are in the opening, wherein the nickel layer is arranged on the top of the circuit layer, the gold layer is arranged on the top of the nickel layer, and the top surface of the gold layer is flush with the top surface of the ink layer.

[0010] Step 10: Place the chip on top of the carrier substrate in step 9, perform bonding and interconnection, and then perform packaging.

[0011] Step 11: Peel off the carrier substrate to obtain the finished product, and cut the finished product to obtain the finished chip. The eleventh step includes the following steps: step 1, peel off the substrate layer and the copper cladding layer at the same time, and expose the copper foil layer; step 2, micro-etch and peel off the copper foil layer; step 3, perform anti-oxidation treatment on the bottom of the circuit layer to form an anti-oxidation layer; step 4, cut the finished product into several chips to obtain a finished chip.

[0012] An ultra-thin chip structure comprises a circuit layer, an ink layer and a chip, wherein the chip is connected to the top of the circuit layer, the ink layer is embedded in the circuit layer, the ink layer comprises an embedded part and a top part, wherein the top part is fixedly connected to the top of the embedded part, the top part has an opening, the circuit layer is directly below the opening, the embedded part is embedded in the circuit layer, the circuit layer comprises a plurality of circuits, the embedded part is arranged between any two adjacent circuits, the top part is pressed on the top of the circuit, a nickel layer and a gold layer are respectively arranged on the top of the circuit layer, the nickel layer and the gold layer are in the opening, wherein the nickel layer is arranged on the top of the circuit layer, the gold layer is arranged on the top of the nickel layer, the top surface of the gold layer is flush with the top surface of the ink layer, the top of the chip is encapsulated in a black glue layer, the black glue layer covers the chip on the top of the circuit layer, an anti-oxidation layer is arranged on the bottom of the circuit layer, and the anti-oxidation layer is arranged on the bottom of each of the circuits.

[0013] The beneficial effects of the present invention are as follows: during packaging, the carrier substrate is first added, and after the chip packaging is completed, the carrier substrate is peeled off, and the packaging of ultra-thin chips can be achieved through the production method. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic diagram of the first step of the present invention.

[0015] Figure 2 It is a schematic diagram of the fourth step of the present invention.

[0016] Figure 3 It is a schematic diagram of the seventh step of the present invention.

[0017] Figure 4 It is a schematic diagram of the eighth step of the present invention.

[0018] Figure 5 It is a schematic diagram of the ninth step of the present invention.

[0019] Figure 6 It is a schematic diagram of the tenth step of the present invention.

[0020] Figure 7 It is a schematic diagram of the eleventh step of the present invention.

[0021] Figure 8 Schematic diagram of the chip structure of the present invention. DETAILED DESCRIPTION

[0022] like Figures 1 to 7 As shown, a packaging method for an ultra-thin substrate is mainly applicable to the packaging of chips, and includes the following steps.

[0023] like Figure 1 As shown, the first step is to make a carrier substrate 10.

[0024] The carrier substrate 10 includes a substrate layer 11, a copper clad layer 12 and a copper foil layer 13, wherein the copper clad layer 12 is respectively arranged on the top surface and the bottom surface of the substrate layer 11, and the copper foil layer 13 is arranged on the top of the copper clad layer 12 on the top surface of the substrate layer 11. In a specific implementation, the thickness of the copper clad layer 12 is preferably 18um, and the thickness of the copper foil layer 13 is preferably 3um.

[0025] During specific implementation, the carrier substrate 10 is manufactured according to the following steps.

[0026] Step 1: The copper cladding layer 12 is fixedly disposed on the top surface and the bottom surface of the substrate layer 11 respectively.

[0027] Step 2: Roughening the top surface of the copper clad layer 12 on the top surface of the substrate layer 11 and the bottom surface of the copper foil layer 13, that is, roughening the joint surface of the copper foil layer 13 and the copper surface of the copper clad layer 12 to obtain a microscopic rough structure on the copper surface, increase its surface roughness, thereby significantly improving the adhesion between the copper surface and the copper foil, and providing the prerequisite for lower pressing.

[0028] Step 3: Use a hot press to press the copper foil layer 13 onto the top of the copper clad layer 12 on the top surface of the substrate layer 11. Specifically, the principle of high-temperature curing of the resin is used to press the 3um copper foil and the 18um substrate together through the pressure of pressing to obtain the carrier substrate 10.

[0029] Step 2: The carrier substrate 10 is baked at a high temperature. During the baking process, the temperature is controlled at 195°C for 2 hours to remove moisture from the surface of the carrier substrate 10, stabilize the size expansion and contraction of the carrier substrate 10, reduce the deformation of the carrier substrate 10 in subsequent production, and use a copper measuring instrument to clearly mark the 3um copper foil surface to facilitate the subsequent drilling direction.

[0030] The third step: mechanical drilling, specifically described as drilling with the 3um copper foil facing up, checking the drilling size to be qualified, and numbering it.

[0031] like Figure 2 As shown, the fourth step: circuit production, to obtain the dry film layer cavity 15.

[0032] The specific steps are as follows.

[0033] Step 1, medium roughening lamination, setting a dry film layer 14 on the top of the copper foil layer 13, specifically, the medium roughening solution chemical reaction creates a microscopic rough structure on the surface of the copper foil layer 13, improves the bonding force between the dry film and the copper surface, and the laminating machine presses the photosensitive material (dry film layer 14) onto the copper foil layer 13.

[0034] Step 2, circuit exposure, specifically described as, using the principle that the dry film has photosensitivity, using an exposure machine to transfer the circuit film data to the dry film layer 14, the exposure machine exposes the semi-finished board positive film, the front side is aligned, and the back side is exposed to death.

[0035] Step 3, developing and etching, specifically, using developer to remove the unexposed dry film layer 14 to obtain the dry film layer cavity 15, etching away excess copper, retaining the circuit pattern, pickling to clean the copper surface, and then drying the surface to prevent copper foil oxidation.

[0036] Step 5: Detect the circuit. Specifically, the AOI machine uses optical principles to detect whether the circuit is open or short-circuited.

[0037] Step 6: Pickling and trimming the copper thickness of the copper foil layer 13. Specifically, pickling is performed before the board is electrically bonded to remove oxidation on the copper surface, and then the copper foil layer 13 is electrically bonded to the required copper thickness to make it conductive.

[0038] like Figure 3As shown, the seventh step: electroplating the circuit and stripping the film, electroplating the circuit in the dry film layer cavity 15 to form a circuit layer 16, and peeling off the dry film layer 14, the circuit layer 16 is arranged on the top surface of the copper foil layer 13.

[0039] like Figure 4 As shown, the eighth step: printing and developing the ink layer, printing the ink layer 17 on the top of the carrier substrate 10 in the seventh step, and developing the ink layer 17 to form a plurality of openings 173.

[0040] The bottom surface of the ink layer 17 is arranged on the top surface of the copper foil layer 13. At the same time, the ink layer 17 is embedded in the circuit layer 16. The ink layer 17 includes an embedded portion 171 and a top portion 172, wherein the top portion 172 is fixedly connected to the top of the embedded portion 171, and the top portion 172 has an opening 173. In practice, the opening 173 can be an opening, a hole, an open groove or the like.

[0041] The circuit layer 16 is located directly below the opening 173 , and the embedded portion 171 is embedded in the circuit layer 16 .

[0042] In a specific implementation, the circuit layer 16 includes a plurality of circuits 161 , the embedded portion 171 is disposed between any two adjacent circuits 161 , and the top layer portion 172 is pressed on the top of the circuits 161 .

[0043] like Figure 5 As shown, step 9: nickel-gold plating.

[0044] In the eighth step, a nickel layer 181 and a gold layer 182 are electroplated on the top of the circuit layer 16 respectively, and the nickel layer 181 and the gold layer 182 are in the opening 173, wherein the nickel layer 181 is arranged on the top of the circuit layer 16, and the gold layer 182 is arranged on the top of the nickel layer 181, and the top surface of the gold layer 182 is flush with the top surface of the ink layer 17.

[0045] The nickel-gold plating process is performed as follows.

[0046] First, the top surface of the circuit layer 16 is roughened by micro-etching, and then activated by sulfuric acid washing to prevent oxidation of the copper surface. Then, a layer of nickel is plated on the parts that need to be plated with nickel to provide reliability for bonding and welding. Finally, a layer of gold is plated on the parts that need to be plated with gold for bonding or welding.

[0047] In a specific implementation, the thickness of the nickel layer 181 is 2.54-15 um, and the thickness of the gold layer 182 is 0.03-0.5 um.

[0048] In practice, the nickel-gold layer can be a nickel-silver-gold layer, and the thickness of the silver layer is 0.5-2um. The silver layer is located between the nickel layer 181 and the gold layer 182 to reduce the thickness of the precious metal and reduce the product cost.

[0049] In practice, the thickness of the silver coating is preferably 1 μm.

[0050] The nickel plating solution of the invention contains: 70-110 g / L nickel sulfamate, 10-30 g / L nickel chloride, 30-50 g / L boric acid, the nickel plating solution temperature is 55-65 DEG C, and the pH value is 3.8-4.4.

[0051] The present invention directly electroplates a nickel layer on the circuit layer 16 to replace the current copper layer. Even if the thickness of the silver plating layer is 0.1-0.3 μm, it will not change color at high temperature. While ensuring performance requirements, it reduces the use of precious metal silver and saves costs. It solves the current problems of discoloration due to high-temperature baking when the silver plating layer is thin, low yield and high cost when the silver layer is thick.

[0052] In practice, the following work can be done after the ninth step: the molding machine uses the data prepared by CAD, and the milling cutter depth compensation gongs out the required size to obtain the desired size of the finished product and ensure the SET size requirements. The surface of the molded product is cleaned to obtain the final package substrate product.

[0053] like Figure 6 As shown, the tenth step: affix the chip 20 on the top of the carrier substrate 10 in the ninth step, perform bonding interconnection, and perform packaging.

[0054] The specific description is as follows: the carrier substrate 10 with the chip 20 attached thereto is placed into a customized mold, and the chip and the substrate are packaged together using a black glue layer 21 for glue filling, thereby preliminarily completing the BGA packaging.

[0055] like Figure 7 As shown, the eleventh step: peeling off the carrier substrate 10 to obtain a finished product, and cutting the finished product to obtain a finished chip.

[0056] In the specific implementation, the eleventh step includes the following steps.

[0057] Step 1: peel off the substrate layer 11 and the copper cladding layer 12 at the same time, and expose the copper foil layer 13.

[0058] Step 2: micro-etching to peel off the copper foil layer 13. Specifically, micro-etching is used to etch off the copper foil layer 13.

[0059] Step 3, performing anti-oxidation treatment on the bottom of the circuit layer 16 to form an anti-oxidation layer 162 , specifically, performing OSP (anti-oxidation treatment) on the exposed circuit layer 16 to facilitate subsequent tinning of the circuit layer 16 .

[0060] Step 4: Cut the finished product into several chips to obtain finished chips.

[0061] like Figure 8 As shown, an ultra-thin chip structure includes a circuit layer 16, an ink layer 17 and a chip 20. The chip 20 is connected to the top of the circuit layer 16, and the ink layer 17 is embedded in the circuit layer 16.

[0062] The ink layer 17 includes an embedded portion 171 and a top portion 172, wherein the top portion 172 is fixedly connected to the top of the embedded portion 171, and the top portion 172 has an opening 173. In practice, the opening 173 can be an opening, a hole, an open channel or the like.

[0063] The circuit layer 16 is located directly below the opening 173 , and the buried portion 171 is embedded in the circuit layer 16 . In a specific implementation, the circuit layer 16 includes a plurality of circuits 161 , and the buried portion 171 is disposed between any two adjacent circuits 161 . The top layer portion 172 is pressed on top of the circuit 161 .

[0064] A nickel layer 181 and a gold layer 182 are respectively arranged on the top of the circuit layer 16, and the nickel layer 181 and the gold layer 182 are located in the opening 173, wherein the nickel layer 181 is arranged on the top of the circuit layer 16, and the gold layer 182 is arranged on the top of the nickel layer 181, and the top surface of the gold layer 182 is flush with the top surface of the ink layer 17.

[0065] The top of the chip 20 is encapsulated in a black glue layer 21 , and the black glue layer 21 covers the chip 20 on the top of the circuit layer 16 . An anti-oxidation layer 162 is provided at the bottom of the circuit layer 16 , and the anti-oxidation layer 162 is provided at the bottom of each of the circuits 161 .

Claims

1. A packaging method for an ultra-thin substrate, which is suitable for chip packaging, characterized in that: The steps include: Step 1: Make the carrier substrate. The carrier substrate comprises a substrate layer, a copper-clad layer and a copper foil layer, wherein the copper-clad layer is respectively arranged on the top surface and the bottom surface of the substrate layer, and the copper foil layer is arranged on the top of the copper-clad layer on the top surface of the substrate layer. Step 2: High temperature baking of the carrier substrate. Step 3: Mechanical drilling, Step 4: Circuit production, get the dry film layer cavity, The specific steps are as follows: step 1, roughening and laminating, setting a dry film layer on the top of the copper foil layer, step 2, circuit exposure, step 3, developing, etching and stripping the film, Step 5: Test the circuit. Step 6: Pickling and trimming the copper thickness of the copper foil layer. Step 7: Electroplating the circuit and stripping the film. Electroplating the circuit in the cavity of the dry film layer to form a circuit layer, and stripping the dry film layer. The circuit layer is arranged on the top surface of the copper foil layer. Step 8: Print the ink layer and develop it. In the seventh step, an ink layer is printed on the top of the carrier substrate, and the ink layer is developed to form a plurality of openings. The bottom surface of the ink layer is arranged on the top surface of the copper foil layer. At the same time, the ink layer is embedded in the circuit layer. The ink layer includes an embedded part and a top part, wherein the top part is fixedly connected to the top of the embedded part, the top part has an opening, and the circuit layer is directly below the opening. The embedded part is embedded in the circuit layer, and the circuit layer includes a plurality of circuits. The embedded part is arranged between any two adjacent circuits, and the top part is pressed on the top of the circuit. Step 9: Nickel-gold plating, In the eighth step, a nickel layer and a gold layer are electroplated on the top of the circuit layer, respectively, and the nickel layer and the gold layer are in the opening, wherein the nickel layer is arranged on the top of the circuit layer, and the gold layer is arranged on the top of the nickel layer, and the top surface of the gold layer is flush with the top surface of the ink layer. Step 10: Place the chip on top of the carrier substrate in step 9, perform bonding and interconnection, and then package it. Step 11: Peel off the carrier substrate to obtain the finished product, and cut the finished product to obtain the finished chip. The eleventh step includes the following steps, Step 1: peel off the substrate layer and the copper cladding layer at the same time, and expose the copper foil layer. Step 2: Micro-etching to remove the copper foil layer. Step 3: Perform anti-oxidation treatment on the bottom of the circuit layer to form an anti-oxidation layer. Step 4: Cut the finished product into several chips to obtain finished chips.

2. The packaging method of an ultra-thin substrate according to claim 1, characterized in that: In the first step, the thickness of the copper cladding layer is 18 um, and the thickness of the copper foil layer is 3 um.

3. The packaging method of an ultra-thin substrate according to claim 1, characterized in that: In the first step, the carrier substrate is manufactured according to the following steps: Step 1: fix the copper cladding layer on the top surface and the bottom surface of the substrate layer respectively. Step 2: roughening the top surface of the copper-clad layer on the top surface of the substrate layer and the bottom surface of the copper foil layer. Step 3: Use a hot press to press the copper foil layer onto the top of the copper cladding layer on the top surface of the substrate layer.

4. The packaging method of an ultra-thin substrate according to claim 1, characterized in that: In the second step, the temperature is controlled at 195° C. for 2 hours during the baking process to remove moisture from the surface of the carrier substrate, stabilize the dimensional expansion and contraction of the carrier substrate, and reduce deformation of the carrier substrate in subsequent production.

5. The packaging method of an ultra-thin substrate according to claim 1, characterized in that: In the ninth step, the nickel-gold layer is plated according to the following steps: first, the top surface of the circuit layer is roughened by micro-etching, and the top surface is activated by sulfuric acid washing to prevent the copper surface from oxidizing. Then, a layer of nickel is plated on the part where the nickel layer needs to be plated, and finally a layer of gold is plated on the part where the gold layer needs to be plated for bonding or welding.

6. The packaging method of an ultra-thin substrate according to claim 1, characterized in that: In the ninth step, the thickness of the nickel layer is 2.54-15 um, and the thickness of the gold layer is 0.03-0.5 um.

7. The packaging method of an ultra-thin substrate according to claim 1, characterized in that: In the ninth step, the nickel-gold layer is a nickel-silver-gold layer, the thickness of the silver layer is 0.5-2um, the silver layer is between the nickel layer and the gold layer, the thickness of the nickel layer is 2.54-15um, and the thickness of the gold layer is 0.03-0.5um.

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