Half-bridge inverter circuit and electronic device

By sampling and comparing the positive and negative half-peripheral capacitor voltages of the half-bridge inverter circuit, the switching tube operation is controlled, which solves the problem of the continuous increase in the voltage of the half-bridge inverter circuit under the half-wave load, and realizes voltage stability and transient Reduction of mutations.

CN111478615BActive Publication Date: 2025-02-18GUANGZHOU DAOTONG NEW ENERGY CO LTD
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Patent Information

Application Number
CN202010332559.X
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2020-04-24
Publication Date
2025-02-18
Estimated Expiration
2040-04-24

AI Technical Summary

Technical Problem

When the half-bridge inverter circuit is operating under a half-wave load for a long time, the BUS voltage of the half-circumferential bus without load is continuously charged, causing the voltage to rise continuously, causing the UPS failure.

Method used

By sampling the positive and negative half-period capacitor voltages and performing comparison operations, we can determine the half-period that needs to be discharged, and control the switch tube to operate through an external controller to discharge the half-period with lower voltage.

Benefits of technology

It realizes that when the half-bridge inverter power supply is operated with half-wave type load, no abnormality occurs, which improves voltage stability and reduces the distortion and impact of transient sudden changes on the output.

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Abstract

The present invention discloses a half-bridge inverter circuit, comprising: a first capacitor, a second capacitor, a third capacitor, a first inductor, a second inductor, a first switch tube, a second switch tube, a first diode, a second diode and a load; the first capacitor is connected to the first switch tube, the first switch tube is also connected to an external controller and the second inductor, and the second inductor is connected to the third capacitor; the second capacitor is connected to the second switch tube, and the second switch tube is also connected to the first inductor and the external controller; the positive electrode of the first diode is connected to the second capacitor, and the negative electrode of the first diode is connected to the second inductor; the positive electrode of the second diode is connected to the first inductor, and the negative electrode of the second diode is connected to the first capacitor; the load is connected to the third capacitor. The present invention also discloses an electronic device. By adopting the embodiment of the present invention, it can work with a half-wave type load without abnormal operation, and at the same time improve the voltage stability and reduce the distortion and influence of transient mutations on the output.
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Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a half-bridge inverter circuit and electronic equipment. Background Art

[0002] An inverter is a static current conversion device that uses power semiconductor devices to convert DC power from batteries, solar cells or fuel cells into constant voltage and frequency AC power for use by AC loads or for grid-connected power generation. This inverter technology plays a vital role in the development and application of new energy. With the rapid development of power electronics technology, research on traditional circuit structures has gradually deepened, and new circuit structures have been proposed, but they are also facing more and more problems.

[0003] For high-frequency uninterruptible UPS power supply with half-bridge inverter architecture, when related products are used to carry half-wave loads (such as some half-wave printers, half-wave medical equipment, etc.), due to the working characteristics of the half-bridge inverter itself, it will work under half-wave load for a long time, which will eventually cause the unloaded half-cycle bus BUS voltage to be continuously passively charged, causing the voltage to continue to rise, and eventually generate BUS high voltage, causing UPS failure, resulting in UPS abnormality and failure to achieve the purpose of uninterrupted power supply. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a half-bridge inverter circuit and an electronic device that can operate with a half-wave type load without causing abnormal operation, while improving voltage stability and reducing the distortion and impact of transient mutations on the output.

[0005] To achieve the above object, an embodiment of the present invention provides a half-bridge inverter circuit, comprising:

[0006] The first end of the first capacitor is connected to the second end of the first switch tube, the second end of the first capacitor is grounded, the second end of the first switch tube is connected to an external controller, the third end of the first switch tube is connected to the first end of the second inductor, the second end of the second inductor is connected to the first end of the third capacitor, and the second end of the third capacitor is grounded;

[0007] The first end of the second capacitor is grounded, the second end of the second capacitor is connected to the third end of the second switch tube, the first end of the second switch tube is connected to the second end of the first inductor, the second end of the second switch tube is connected to an external controller, and the first end of the first inductor is grounded;

[0008] The anode of the first diode is connected to the second end of the second capacitor, and the cathode of the first diode is connected to the first end of the second inductor; the anode of the second diode is connected to the second end of the first inductor, and the cathode of the second diode is connected to the first end of the first capacitor;

[0009] The first end of the load is connected to the first end of the third capacitor, and the second end of the load is grounded.

[0010] As an improvement of the above solution, the half-bridge inverter circuit further includes a third switch tube; wherein,

[0011] The first end of the third switch tube is connected to the first end of the first capacitor, the second end of the third switch tube is connected to the external controller, and the third end of the third switch tube is connected to the second end of the first inductor.

[0012] As an improvement of the above solution, the half-bridge inverter circuit further includes a fourth switch tube; wherein,

[0013] The first end of the fourth switch tube is connected to the third end of the first switch tube, the second end of the fourth switch tube is connected to an external controller, and the third end of the fourth switch tube is connected to the anode of the first diode.

[0014] As an improvement of the above solution, the half-bridge inverter circuit further includes a third diode; wherein,

[0015] An anode of the third diode is connected to the second end of the second capacitor, and a cathode of the third diode is connected to the second end of the first inductor.

[0016] As an improvement of the above solution, the half-bridge inverter circuit further includes a fourth diode; wherein,

[0017] An anode of the fourth diode is connected to the first end of the second inductor, and a cathode of the fourth diode is connected to the first end of the first capacitor.

[0018] As an improvement of the above solution, the first switch tube is an N-channel MOS tube, the first end of the first switch tube is the drain of the N-channel MOS tube, the second end of the first switch tube is the gate of the N-channel MOS tube, and the third end of the first switch tube is the source of the N-channel MOS tube.

[0019] As an improvement of the above solution, the second switch tube is an N-channel MOS tube, the first end of the second switch tube is the drain of the N-channel MOS tube, the second end of the second switch tube is the gate of the N-channel MOS tube, and the third end of the second switch tube is the source of the N-channel MOS tube.

[0020] As an improvement of the above scheme, the third switch tube is an N-channel MOS tube, the first end of the third switch tube is the drain of the N-channel MOS tube, the second end of the third switch tube is the drain of the N-channel MOS tube, and the third end of the third switch tube is the source of the N-channel MOS tube.

[0021] As an improvement of the above solution, the fourth switch tube is an N-channel MOS tube, the first end of the fourth switch tube is the drain of the N-channel MOS tube, the second end of the fourth switch tube is the gate of the N-channel MOS tube, and the third end of the fourth switch tube is the source of the N-channel MOS tube.

[0022] To achieve the above objective, an embodiment of the present invention further provides an electronic device, comprising the half-bridge inverter circuit described in any one of the above embodiments.

[0023] Compared with the prior art, the half-bridge inverter circuit and electronic device disclosed in the present invention samples the positive and negative half-cycle capacitor voltages, performs comparison operations to determine the corresponding half-cycle that needs to be discharged, and then controls the operation of the switch tube through an external controller to discharge the half-cycle with a lower voltage. It enables the half-bridge inverter power supply to work with a half-wave type load without abnormal operation. When some loading transients and load mutations generate instantaneous high power, the current transient half-cycle usually causes the bus voltage to drop rapidly. After adopting the embodiment of the present invention, after the bus voltage is lowered by a certain amplitude, it can be charged through the bus that is not loaded in the other half cycle, thereby improving voltage stability and reducing the distortion and influence of transient mutations on the output. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a circuit diagram of a half-bridge inverter circuit provided by an embodiment of the present invention;

[0025] Figure 2 is the output waveform of the half-bridge inverter circuit provided by the embodiment of the present invention when operating in the positive half cycle;

[0026] Figure 3 is the output waveform of the half-bridge inverter circuit provided by the embodiment of the present invention when operating in the negative half cycle;

[0027] Figure 4 is a circuit diagram of a PFC circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] See also Figure 1 , Figure 1: is a circuit diagram of a half-bridge inverter circuit provided by an embodiment of the present invention; the half-bridge inverter circuit includes: a first capacitor C1, a second capacitor C2, a third capacitor C3, a first inductor L1, a second inductor L2, a first switch tube Q1, a second switch tube Q2, a first diode D1, a second diode D2 and a load LOAD; wherein,

[0030] The first end of the first capacitor C1 is connected to the second end of the first switch tube Q1, the second end of the first capacitor C1 is grounded, the second end of the first switch tube Q1 is connected to an external controller, the third end of the first switch tube Q1 is connected to the first end of the second inductor L2, the second end of the second inductor L2 is connected to the first end of the third capacitor C3, and the second end of the third capacitor C3 is grounded;

[0031] A first end of the second capacitor C2 is grounded, a second end of the second capacitor C2 is connected to a third end of the second switch tube Q2, a first end of the second switch tube Q2 is connected to a second end of the first inductor L1, a second end of the second switch tube Q2 is connected to an external controller, and a first end of the first inductor L1 is grounded;

[0032] The anode of the first diode D1 is connected to the second end of the second capacitor C2, and the cathode of the first diode D1 is connected to the first end of the second inductor L2; the anode of the second diode D2 is connected to the second end of the first inductor L1, and the cathode of the second diode D2 is connected to the first end of the first capacitor C1;

[0033] A first end of the load LOAD is connected to a first end of the third capacitor C3, and a second end of the load LOAD is grounded.

[0034] Specifically, the half-bridge inverter circuit in the embodiment of the present invention is suitable for a UPS power supply, and the UPS power supply is also provided with an external controller, and the external controller is used to control the working state of the switch tube. Exemplarily, the external controller is a PWM controller. The half-bridge inverter circuit has two working states: a positive half cycle and a negative half cycle. Exemplarily, the positive half cycle, that is, the upper half of the circuit is the main working object, and the positive half wave of the sine wave will be output accordingly, such as Figure 2 As shown; the positive half cycle, that is, the lower half of the circuit is the main working object, corresponding to the negative half wave of the output sine wave, such as Figure 3 shown.

[0035] Specifically, when the half-bridge inverter circuit operates in the positive half cycle, the external controller controls the first switch tube Q1 to turn on, and at this time, the first capacitor C1 forms a loop through the first switch tube Q1, the second inductor L2, and the third capacitor C3 to supply power to the load LOAD, and the first capacitor C1 is in a discharging state. When the first switch tube Q1 is turned off, the second capacitor C2, the first diode D1, the second inductor L2, and the third capacitor C3 form a loop, and in this process, the second inductor L2 discharges, which will have the effect of charging the second capacitor C2.

[0036] At this time, the half-bridge inverter with bus voltage regulation function samples and judges the voltages of the first capacitor C1 and the second capacitor C2. When the voltage of the second capacitor C2 gradually increases, the second switch tube Q2 is controlled to be turned on, and a loop is formed through the first inductor L1, the second switch tube Q2, and the second capacitor C2 to store energy in the first inductor L1. After the second switch tube Q2 is turned on to store energy, the second switch tube Q2 is turned off, and the electric energy stored in the first inductor L1 will form a loop through the second diode D2 and the first capacitor C1 to discharge the first capacitor C1, and the electric energy in the second capacitor C2 is converted and transmitted to the first capacitor C1, so as to achieve the purpose of controlling the bus voltage of the second capacitor C2.

[0037] Optionally, the half-bridge inverter circuit further includes a third switch tube Q3, a fourth switch tube Q4, a third diode D3 and a fourth diode D4; wherein,

[0038] The first end of the third switch tube Q3 is connected to the first end of the first capacitor C1, the second end of the third switch tube Q3 is connected to the external controller, and the third end of the third switch tube Q3 is connected to the second end of the first inductor L1; the first end of the fourth switch tube Q4 is connected to the third end of the first switch tube Q1, the second end of the fourth switch tube Q4 is connected to the external controller, and the third end of the fourth switch tube Q4 is connected to the positive electrode of the first diode D1;

[0039] The anode of the third diode D3 is connected to the second end of the second capacitor C2, and the cathode of the third diode D3 is connected to the second end of the first inductor L1; the anode of the fourth diode D4 is connected to the first end of the second inductor L2, and the cathode of the fourth diode D4 is connected to the first end of the first capacitor C1.

[0040] Further, when the half-bridge inverter circuit operates in the negative half cycle, the external controller controls the fourth switch tube Q4 to turn on, at which time the second capacitor C2 forms a loop through the fourth switch tube Q4, the second inductor L2, and the third capacitor C3 to supply power to the load LOAD, and the second capacitor C2 is in a discharging state. When the fourth switch tube Q4 is turned off, the first capacitor C1, the fourth diode D4, the second inductor L2, and the third capacitor C3 form a loop, and in this process, the second inductor L2 discharges, which will have the effect of charging the first capacitor C1.

[0041] At this time, the half-bridge inverter with bus voltage regulation function samples and judges the voltages of the first capacitor C1 and the second capacitor C2. When the voltage of the first capacitor C1 gradually increases, the third switch tube Q3 is controlled to be turned on, and a loop is formed through the first inductor L1, the third switch tube Q3, and the first capacitor C1 to store energy in the first inductor L1. After the third switch tube Q3 is turned on to store energy, the third switch tube Q3 is turned off, and the electric energy stored in the first inductor L1 will form a loop through the third diode D3 and the second capacitor C2 to discharge the second capacitor C2, and the electric energy in the first capacitor C1 is converted and transmitted to the second capacitor C2, so as to achieve the purpose of controlling the bus voltage of the first capacitor C1.

[0042] It is worth noting that the first switch tube Q1 and the fourth switch tube Q4 are a corresponding group, and the second switch tube Q2 and the third switch tube Q3 are a corresponding group; the control between the two groups of switch tubes is unrelated. The first switch tube Q1 and the fourth switch tube Q4 cannot be turned on at the same time, and the second switch tube Q2 and the third switch tube Q3 cannot be turned on at the same time. When the first switch tube Q1 is turned off, the fourth switch tube Q4 can be turned on or off. The first switch tube Q1 and the fourth switch tube Q4 determine the working mode based solely on the voltage on the first capacitor C1 and the second capacitor C2. When the second switch tube Q2 is turned on, the third switch tube Q3 must be turned off, and the first switch tube Q1 and the fourth switch tube Q4 are not affected, depending on the control of the output waveform requirements.

[0043] Exemplarily, the first switch tube Q1, the second switch tube Q2, the third switch tube Q3 and the fourth switch tube Q4 may all be N-channel MOS tubes. Alternatively, the first switch tube Q1 and the fourth switch tube Q4 adopt a push-pull form, and when the first switch tube Q1 is an N-channel MOS tube, the fourth switch tube Q4 is a P-channel MOS tube. Similarly, the second switch tube Q2 and the third switch tube Q3 may also adopt a push-pull form.

[0044] Optionally, the first switch tube Q1 is an N-channel MOS tube, the first end of the first switch tube Q1 is the drain of the N-channel MOS tube, the second end of the first switch tube Q1 is the gate of the N-channel MOS tube, and the third end of the first switch tube Q1 is the source of the N-channel MOS tube.

[0045] Optionally, the second switch tube Q2 is an N-channel MOS tube, the first end of the second switch tube Q2 is the drain of the N-channel MOS tube, the second end of the second switch tube Q2 is the gate of the N-channel MOS tube, and the third end of the second switch tube Q2 is the source of the N-channel MOS tube.

[0046] Optionally, the third switch tube Q3 is an N-channel MOS tube, the first end of the third switch tube Q3 is the drain of the N-channel MOS tube, the second end of the third switch tube Q3 is the drain of the N-channel MOS tube, and the third end of the third switch tube Q3 is the source of the N-channel MOS tube.

[0047] Optionally, the fourth switch tube Q4 is an N-channel MOS tube, the first end of the fourth switch tube Q4 is the drain of the N-channel MOS tube, the second end of the fourth switch tube Q4 is the gate of the N-channel MOS tube, and the third end of the fourth switch tube Q4 is the source of the N-channel MOS tube.

[0048] Furthermore, the UPS power supply front stage is also provided with a PFC circuit, through which the input mains or battery voltage is converted to the first capacitor C1 and the second capacitor C2. For example, the circuit diagram of the PFC circuit can be referred to Figure 4 The PFC circuit includes a power input terminal Vin, a third inductor L3, a fourth capacitor C4, a fifth capacitor C5, a fifth switch tube Q5, a sixth diode D6, a seventh diode D7, an eighth diode D8, a ninth diode D9 and a tenth diode D10. The specific connection relationship of each device in the PFC circuit can be referred to Figure 4 , I will not go into details here.

[0049] Furthermore, an embodiment of the present invention also provides an electronic device, in which the half-bridge inverter circuit described in the above embodiment is provided. For the specific working process of the half-bridge inverter circuit, please refer to the working process of the half-bridge inverter circuit described in the above embodiment, which will not be repeated here.

[0050] Compared with the prior art, the half-bridge inverter circuit and electronic device disclosed in the present invention samples the positive and negative half-cycle capacitor voltages, performs comparison operations to determine the corresponding half-cycle that needs to be discharged, and then controls the operation of the switch tube through an external controller to discharge the half-cycle with a lower voltage. It enables the half-bridge inverter power supply to work with a half-wave type load without abnormal operation. When some loading transients and load mutations generate instantaneous high power, the current transient half-cycle usually causes the bus voltage to drop rapidly. After adopting the embodiment of the present invention, after the bus voltage is lowered by a certain amplitude, it can be charged through the bus that is not loaded in the other half cycle, thereby improving voltage stability and reducing the distortion and influence of transient mutations on the output.

[0051] The above is a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A half-bridge inverter circuit, characterized in that: include: A first capacitor, a second capacitor, a third capacitor, a first inductor, a second inductor, a first switch tube, a second switch tube, a first diode, a second diode and a load; wherein, The first end of the first capacitor is connected to the first end of the first switch tube, the second end of the first capacitor is grounded, the second end of the first switch tube is connected to an external controller, the third end of the first switch tube is connected to the first end of the second inductor, the second end of the second inductor is connected to the first end of the third capacitor, and the second end of the third capacitor is grounded; The first end of the second capacitor is grounded, the second end of the second capacitor is connected to the third end of the second switch tube, the first end of the second switch tube is connected to the second end of the first inductor, the second end of the second switch tube is connected to an external controller, and the first end of the first inductor is grounded; The anode of the first diode is connected to the second end of the second capacitor, and the cathode of the first diode is connected to the first end of the second inductor; the anode of the second diode is connected to the second end of the first inductor, and the cathode of the second diode is connected to the first end of the first capacitor; The first end of the load is connected to the first end of the third capacitor, and the second end of the load is grounded.

2. The half-bridge inverter circuit according to claim 1, characterized in that: The half-bridge inverter circuit also includes a third switch tube; wherein, The first end of the third switch tube is connected to the first end of the first capacitor, the second end of the third switch tube is connected to the external controller, and the third end of the third switch tube is connected to the second end of the first inductor.

3. The half-bridge inverter circuit according to claim 1, characterized in that: The half-bridge inverter circuit also includes a fourth switch tube; wherein, The first end of the fourth switch tube is connected to the third end of the first switch tube, the second end of the fourth switch tube is connected to an external controller, and the third end of the fourth switch tube is connected to the anode of the first diode.

4. The half-bridge inverter circuit according to claim 1, characterized in that: The half-bridge inverter circuit also includes a third diode; wherein, An anode of the third diode is connected to the second end of the second capacitor, and a cathode of the third diode is connected to the second end of the first inductor.

5. The half-bridge inverter circuit according to claim 1, characterized in that: The half-bridge inverter circuit also includes a fourth diode; wherein, An anode of the fourth diode is connected to the first end of the second inductor, and a cathode of the fourth diode is connected to the first end of the first capacitor.

6. The half-bridge inverter circuit according to claim 1, characterized in that: The first switch tube is an N-channel MOS tube, the first end of the first switch tube is the drain of the N-channel MOS tube, the second end of the first switch tube is the gate of the N-channel MOS tube, and the third end of the first switch tube is the source of the N-channel MOS tube.

7. The half-bridge inverter circuit according to claim 1, characterized in that: The second switch tube is an N-channel MOS tube, the first end of the second switch tube is the drain of the N-channel MOS tube, the second end of the second switch tube is the gate of the N-channel MOS tube, and the third end of the second switch tube is the source of the N-channel MOS tube.

8. The half-bridge inverter circuit according to claim 2, characterized in that: The third switch tube is an N-channel MOS tube, the first end of the third switch tube is the drain of the N-channel MOS tube, the second end of the third switch tube is the drain of the N-channel MOS tube, and the third end of the third switch tube is the source of the N-channel MOS tube.

9. The half-bridge inverter circuit according to claim 3, characterized in that: The fourth switch tube is an N-channel MOS tube, the first end of the fourth switch tube is the drain of the N-channel MOS tube, the second end of the fourth switch tube is the gate of the N-channel MOS tube, and the third end of the fourth switch tube is the source of the N-channel MOS tube.

10. An electronic device, characterized in that: The invention comprises the half-bridge inverter circuit according to any one of claims 1 to 9.

Citation Information

Patent Citations

  • Half-bridge inverter circuit and electronic equipment

    CN211859974U