Semiconductor device including data storage pattern and method of manufacturing the same

Abstract

The present invention relates to a semiconductor device including a data storage pattern and a manufacturing method thereof. The semiconductor device includes: a first wire on a substrate and extending along a first direction; a second wire on the first wire and extending along a second direction; a data storage structure between the first wire and the second wire, wherein each data storage structure includes a lower data storage electrode, a data storage pattern and an upper data storage electrode, wherein the width of the upper portion of the lower data storage electrode is smaller than the width of the lower portion of the lower data storage electrode, the width of the upper portion of the data storage pattern is larger than the width of the lower portion of the data storage pattern, and the width of the upper portion of the lower data storage electrode is different from the width of the lower portion of the data storage pattern.

Description

Technical Field

[0001] Exemplary embodiments of the inventive concepts relate to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a data storage pattern and a method of manufacturing the same. Background Art

[0002] Next generation memory devices such as phase change random access memory (PRAM) have been developed to achieve high performance and operate at low power. Such next generation memory devices are manufactured using data storage materials with variable or maintainable resistance values. For example, some of these devices may have resistance values ​​that change according to current or voltage, while other devices may maintain resistance values ​​when current or voltage is cut off. In order to increase the integration of next generation memory devices, memory cells are arranged in a three-dimensional (3D) structure. However, for example, such a 3D arrangement of memory cells may lead to unexpected defects and reduced reliability. Summary of the invention

[0003] According to an exemplary embodiment of the present invention, a semiconductor device includes: a first conductive line, which is arranged on a substrate and extends in a first direction parallel to an upper surface of the substrate; a second conductive line, which is arranged on the first conductive line and extends in a second direction crossing the first direction and along the upper surface of the substrate; a first data storage structure, which is arranged between the first conductive line and the second conductive line, wherein each first data storage structure includes a first lower data storage electrode, a first data storage pattern on the first lower data storage electrode, and a first upper data storage electrode on the first data storage pattern; and a first etch stop layer, which is adjacent to a lower side surface of the first data storage pattern and extends in the first direction and the second direction, wherein in the second direction, a width of an upper portion of the first lower data storage electrode is smaller than a width of a lower portion of the first lower data storage electrode, in the second direction, a width of an upper portion of the first data storage pattern is larger than a width of a lower portion of the first data storage pattern, and in the second direction, a width of an upper portion of the first lower data storage electrode is different from a width of a lower portion of the first data storage pattern.

[0004] According to an exemplary embodiment of the present invention, a semiconductor device includes: a first conductive line, which is arranged on a substrate and extends in a first direction parallel to an upper surface of the substrate; a second conductive line, which is arranged on the first conductive line and extends in a second direction perpendicular to the first direction and parallel to the upper surface of the substrate; a first data storage structure and a first selector structure, which are arranged between the first conductive line and the second conductive line and are connected in series with each other; and a first etch stop layer, which is adjacent to a lower side surface of the first data storage structure and extends in the first direction and the second direction, wherein the first data storage structure includes a first lower data storage electrode, a first data storage pattern and a first upper data storage electrode, wherein a slope of a side surface of the first lower data storage electrode is different from a slope of a side surface of the first data storage pattern, and a width of an upper portion of the first lower data storage electrode is different from a width of a lower portion of the first data storage pattern.

[0005] According to an exemplary embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a first conductive line extending along a first direction parallel to a surface of the substrate on a substrate; forming a lower data storage electrode on the first conductive line; forming an etch stop layer and a mold insulating layer on the lower data storage electrode; forming a first hard mask pattern on the mold insulating layer, the first hard mask pattern extending along a second direction perpendicular to the first direction and parallel to the surface of the substrate; forming a first spacer on a side surface of the first hard mask pattern, the first spacer extending along the second direction; forming a second hard mask layer on the first hard mask pattern and the first spacer; forming a third hard mask pattern on the second hard mask layer, the third hard mask pattern extending along the first direction; forming a second spacer on a side surface of the third hard mask pattern, the second spacer extending along the first direction; forming a primary hole by etching the first spacer using the second spacer; forming a hole by etching the mold insulating layer exposed by the primary hole; and forming a data storage pattern and an upper data storage electrode in the hole.

[0006] According to an exemplary embodiment of the present invention, a semiconductor device includes: a first conductive line arranged on a substrate; a second conductive line arranged on the substrate; and a data storage structure arranged between the first conductive line and the second conductive line, the data storage structure including a data storage pattern arranged between a first data storage electrode and a second data storage electrode, wherein a width of a lower portion of the data storage pattern is wider than a width of an upper portion of the first data storage electrode, and wherein the data storage pattern gradually becomes thinner in a direction toward the first data storage electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other features of the inventive concept will be more clearly understood by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0008] Figure 1is a diagram showing a semiconductor device according to an exemplary embodiment of the inventive concept as viewed from above;

[0009] Figure 2 including a cross-sectional view showing a semiconductor device according to an exemplary embodiment of the inventive concept;

[0010] Figure 3 Included is shown in enlarged form Figure 2 A cross-sectional view of the local area shown;

[0011] Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment of the inventive concept;

[0012] Figures 9 to 21 is a diagram illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept, wherein Fig. 9 , Fig.11 , Fig.13 , Fig.15 , Fig.17 , Fig.19 , Fig.21 , Fig.23 , Fig.25 and Fig. 27 is a diagram from above showing a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept, Fig.10 , Fig.12 , Fig.14 , Fig.16 , Fig.18 , Fig. 20 , Fig. 22 , Fig.24 , Fig.26 and Fig.28 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept;

[0013] Fig.29 including a cross-sectional view showing a semiconductor device according to an exemplary embodiment of the inventive concept;

[0014] Fig.30 including a cross-sectional view showing a semiconductor device according to an exemplary embodiment of the inventive concept;

[0015] Fig.31 Included is shown in enlarged form Fig.30 A cross-sectional view of the partial area shown; and

[0016] Fig.32 and Fig.33Each includes a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0017] Hereinafter, exemplary embodiments of the present inventive concept will be described in detail with reference to the accompanying drawings.

[0018] Figure 1 is a diagram illustrating a semiconductor device according to an exemplary embodiment of the inventive concept, as viewed from above. Figure 2 A cross-sectional view of a semiconductor device according to an exemplary embodiment of the present inventive concept is included, showing a Figure 1 The cross section taken along the line II' shown in FIG. Figure 1 A cross section taken along line II-II' is shown in FIG. Figure 3 Included is shown in enlarged form Figure 2 A cross-sectional view of a local area is shown.

[0019] refer to Figures 1 to 3 , a semiconductor device according to an exemplary embodiment of the inventive concept may include a first conductive line 10, a second conductive line 75, and a storage area S disposed between the first conductive line 10 and the second conductive line 75. The first conductive line 10, the second conductive line 75, and the storage area S are disposed on a substrate 2. The substrate 2 may be formed of a semiconductor material.

[0020] A peripheral circuit including a circuit wiring 7 and a contact plug 9 may be provided between the substrate 2 and the first conductive line 10. Figure 2 Only one contact plug 9 is shown in each cross-sectional view of the present invention, but the contact plug 9 may be provided under each first conductive line 10. The peripheral circuit may include a transistor provided on the substrate 2. The transistor may be covered by the first base insulating layer 5. The circuit wiring 7 and the contact plug 9 may be surrounded by the second base insulating layer 8. The first base insulating layer 5 and the second base insulating layer 8 may be formed of an insulating material such as silicon oxide or the like. The circuit wiring 7 and the contact plug 9 may be formed of a conductive material such as a metal (e.g., W or the like), a metal nitride (e.g., TiN, WN or the like) and / or a metal silicide (e.g., WSi, TiSi or the like) or the like.

[0021] The first wire 10 may extend on the second base insulating layer 8 along a first direction (X direction) parallel to the upper surface of the substrate 2, and the second wire 75 may extend along a second direction (Y direction) parallel to the upper surface of the substrate 2 and perpendicular to the first direction (X direction). The first wires 10 may be parallel to each other and may be spaced apart from each other in the second direction (Y direction). The second wires 75 may be parallel to each other and may be spaced apart from each other in the first direction (X direction). The first wire 10 and the second wire 75 may be formed of a conductive material such as a metal (e.g., W or the like), a metal nitride (e.g., TiN, WN or the like) and / or a metal silicide (e.g., WSi, TiSi or the like) or the like. The first wire 10 may be a word line, and the second wire 75 may be a bit line. Alternatively, the first wire 10 may be a bit line, and the second wire 75 may be a word line.

[0022] The storage region S may include a data storage structure 50 , a selector structure 69 , first insulating patterns 15 a , second insulating patterns 15 b , third insulating patterns 15 c , spacer insulating patterns 24 , an etch stop layer 32 , a mold insulating layer 51 , and a first interlayer insulating layer 72 .

[0023] The data storage structures 50 may be connected in series to the corresponding selector structures 69. The data storage structures 50 may each include a lower data storage electrode 40, a data storage pattern 45, and an upper data storage electrode 48.

[0024] Each of the lower data storage electrodes 40 may include a first portion 41a in contact with the data storage pattern 45 and a second portion 41b extending from a lower portion of the first portion 41a in the first direction (X direction) and in contact with the first conductive line 10. The second portions 41b of a pair of lower data storage electrodes 40 disposed on the first conductive line 10 and facing each other may be connected to each other. Therefore, a pair of lower data storage electrodes 40 may be formed in a "U" shape. A pair of lower data storage electrodes 40 forming a "U" shape may be repeatedly disposed on the first conductive line 10. In the second direction (Y direction), the width of the upper portion of the lower data storage electrode 40 may be smaller than the width of the lower portion thereof. In the second direction (Y direction), the width of the lower portion of the lower data storage electrode 40 may be the same as the width of the upper portion of the corresponding first conductive line 10. The lower data storage electrode 40 may be formed of a conductive material including TiN, TiAlN, TaN, WN, MoN, TiSiN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TaSiN, TaAlN, TiON, TiAlON, WON or TaON, or a combination thereof, and / or a carbon-based conductive material. The carbon-based conductive material may include C, CN, TiCN or TaCN, or a combination thereof.

[0025] The first insulating pattern 15a may be disposed on the first conductive line 10 alternately with a pair of lower data storage electrodes 40 forming a "U" shape in the first direction (X direction). The spacer insulating pattern 24 may conformally cover the inner side surface of the lower data storage electrode 40 forming the "U" shape. The spacer insulating pattern 24 may have a "U" shape. The second insulating pattern 15b may be disposed on the spacer insulating pattern 24, and the spacer insulating pattern 24 may cover the side surface and the bottom surface of the second insulating pattern 15b. The first pore V1 may be disposed in each second insulating pattern 15b. The first pore V1 may be filled with a gas such as air or the like. The first pore V1 may extend from the inside of the second insulating pattern 15b until the etching stop layer 32. The third insulating pattern 15c may be disposed alternately with the lower data storage electrode 40 in the second direction (Y direction). The third insulating pattern 15c may extend along the first direction (X direction). The second pore V2 may be disposed in each third insulating pattern 15c. The second pore V2 may extend along the first direction (X direction) and may be filled with a gas such as air or the like. The second pores V2 may extend from the inside of the third insulating pattern 15c to the etch stop layer 32. The lower data storage electrode 40 may be disposed between the first insulating patterns 15a and between the third insulating patterns 15c. The first insulating pattern 15a, the second insulating pattern 15b, the third insulating pattern 15c, and the spacer insulating pattern 24 may be made of a material such as SiO x 、Si x N y , SiON, SiCN, SiOCN, TiO, ZrO x MgO x , HfO x 、AlO x or the like.

[0026] The etch stop layer 32 may cover the first insulating pattern 15a, the second insulating pattern 15b, and the third insulating pattern 15c, and the upper end of the first pore V1 and the upper end of the second pore V2 may contact the etch stop layer 32. The first pore V1 and the second pore V2 may be referred to as a first seam and a second seam, respectively. The etch stop layer 32 may be formed of an insulating material different from the insulating material of the first insulating pattern 15a, the second insulating pattern 15b, and the third insulating pattern 15c. The etch stop layer 32 may be formed of an insulating material such as SiO x 、Si x N y , SiON, SiCN, SiOCN, TiO, ZrO x MgO x , HfO x 、AlO x or the like.

[0027] The mold insulating layer 51 may be disposed on the etch stop layer 32. The data storage pattern 45 and the upper data storage electrode 48 may be disposed in a hole H penetrating the mold insulating layer 51 and the etch stop layer 32. The width of the hole H may decrease toward its lower portion. For example, the width of the hole H may decrease close to the etch stop layer 32. For example, the width of the hole H may be 20 nm or less. The data storage pattern 45 may be disposed on the first portion 41 a of the lower data storage electrode 40. The data storage pattern 45 may penetrate the etch stop layer 32 and may contact the first portion 41 a of the lower data storage electrode 40. The upper data storage electrode 48 may be disposed on the data storage pattern 45. The lower surface of the upper data storage electrode 48 may contact the upper surface of the data storage pattern 45.

[0028] The data storage pattern 45 may be configured so that the width of its upper portion may be greater than the width of its lower portion. For example, in the second direction (Y direction), the width of the upper portion of the data storage pattern 45 may be greater than the width of its lower portion. The side surface of the data storage pattern 45 may be inclined relative to the upper surface of the substrate 2. For example, the data storage pattern 45 may have a tapering shape. In the second direction (Y direction), the width of the lower portion of the data storage pattern 45 may be greater than the width of the upper portion of the first portion 41a of the lower data storage electrode 40. The upper data storage electrode 48 may be configured so that the width of its upper portion may be greater than the width of its lower portion. For example, in the second direction (Y direction), the width of the upper portion of the upper data storage electrode 48 may be greater than the width of the lower portion. The side surface of the upper data storage electrode 48 may be inclined relative to the upper surface of the substrate 2. The side surface of the upper data storage electrode 48 may be coplanar with the side surface of the data storage pattern 45. The width of the lower portion of the upper data storage electrode 48 may be the same as the width of the upper portion of the data storage pattern 45. For example, in the second direction (Y direction), the width of the lower portion of the upper data storage electrode 48 may be the same as the width of the upper portion of the data storage pattern 45. For example, the width of the upper portion of the upper data storage electrode 48 may be 20 nm or less.

[0029] The data storage pattern 45 may be formed of a material capable of storing data using a change in resistance. For example, the data storage pattern 45 may be formed of a phase change storage material that can change the phase from an amorphous phase with high resistivity to a crystalline phase with low resistivity or can change the phase from a crystalline phase to an amorphous phase according to the temperature and heating time caused by the applied current. The phase change storage material used as the data storage pattern 45 may include a chalcogenide material containing Ge, Sb and / or Te, or may be a material including at least one element of Te and Se, and at least one element of Ge, Sb, Bi, Pb, Sn, As, S, Si, P, O, N and In. The phase change storage material used as the data storage pattern 45 may be formed of a superlattice material of GeTe-SbTe, In-Sb-Te (IST) material or Bi-Sb-Te (BST) material.

[0030] The upper data storage electrode 48 may be formed of a conductive material including TiN, TiAlN, TaN, WN, MoN, TiSiN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TaSiN, TaAlN, TiON, TiAlON, WON or TaON or a combination thereof, and / or a carbon-based conductive material.

[0031] The selector structures 69 may each include a lower selector electrode 60, a selector pattern 63, an upper selector electrode 66, and a connection pattern 68 stacked in order in a third direction (Z direction) perpendicular to the upper surface of the substrate 2. The lower selector electrode 60 may be in contact with the upper data storage electrode 48. The upper selector electrode 66 may be electrically connected to the second conductive line 75 through the connection pattern 68. In an exemplary embodiment of the present inventive concept, the connection pattern 68 may be omitted, in which case the upper selector electrode 66 may be in contact with the second conductive line 75. The connection pattern 68 may be formed of a conductive material.

[0032] The selector structure 69 can be configured so that the width of its upper portion can be smaller than the width of its lower portion. For example, in the second direction (Y direction), the width of the upper portion of the selector structure 69 can be smaller than the width of the lower portion. The side surface of the selector structure 69 can be inclined relative to the upper surface of the substrate 2. The side surface of the lower selector electrode 60, the side surface of the selector pattern 63, the side surface of the upper selector electrode 66, and the side surface of the connection pattern 68 can be coplanar with each other. In the first direction (X direction) and / or in the second direction (Y direction), the width of the upper portion of the upper data storage electrode 48 can be greater than the width of the lower portion of the selector structure 69, such as the width of the lower selector electrode 60.

[0033] The selector pattern 63 may be formed of a threshold switch material. For example, the selector pattern 63 may be formed of a bidirectional threshold switch material. The selector pattern 63 may be formed of a chalcogenide material different from the chalcogenide material used as the data storage pattern 45. For example, the selector pattern 63 may be formed of a chalcogenide-based bidirectional threshold switch material that can maintain an amorphous phase when the semiconductor device operates.

[0034] The selector pattern 63 may include an alloy material containing at least two or more elements among As, S, Se, Te and Ge, or may include, in addition to the above alloy materials, an additive element (e.g., Si, N or the like) that can maintain an amorphous phase at a high temperature. The selector pattern 63 may be formed of at least one alloy material including an alloy material including Te, As, Ge and Si, an alloy material including Ge, Te and Pb, an alloy material including Ge, Se and Te, an alloy material including Al, As and Te, an alloy material including Se, As, Ge and Si, an alloy material including Se, As, Ge and C, an alloy material including Se, Te, Ge and Si, an alloy material including Ge, Sb, Te and Se, an alloy material including Ge, Bi, Te and Se, an alloy material including Ge, As, Sb and Se, an alloy material including Ge, As, Bi and Te, and an alloy material including Ge, As, Bi and Se. The selector pattern 63 may be made of AsTeGeSiIn, GeTe, SnTe, GeSe, SnSe, AsTeGeSiSbS, AsTeGeSiIP, AsTeGeSi, As 2 Te 3 Ge、As 2 Se 3 Ge、As 25 (Te 90 Ge 10 ) 75 、Te 40 As 35 Si 18 Ge 6.75 In 0.25 、Te 28 As 34.5 Ge 15.5 S 22 、Te 39 As 36 Si 17 Ge 7 P.As 10 Te 21 S 2 Ge 15 Se 50 Sb 2 、Si 5 Te34 As 28 Ge 11 S 21 Se 1 , AsTeGeSiSeNS, AsTeGeSiP, AsSe, AsGeSe, AsTeGeSe, ZnTe, N-treated OTS, TeAsGeSi, GeTePb, GeSeTe, AlAsTe, SeAsGeS i. SeAsGeC, SeTeGeSi, GeSbTeSe, GeBiTeSe, GeAsSbSe, GeAsBiTe, GeAsBiSe, AsSe, AsSeGe, AsSeGeTe, AsGeTeSi and Ge x Se 1-x is formed by at least one material.

[0035] The selector pattern 63 implemented as a threshold switching device may switch from an off state to an on state when a voltage having a magnitude equal to or higher than a threshold voltage is applied.

[0036] The lower selector electrode 60 and the upper selector electrode 66 may be formed of a conductive material including TiN, TiAlN, TaN, WN, MoN, TiSiN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TaSiN, TaAlN, TiON, TiAlON, WON or TaON or a combination thereof, and / or a carbon-based conductive material.

[0037] The second conductive line 75 may contact the connection pattern 68. In an exemplary embodiment of the present inventive concept, in the case where the connection pattern 68 is omitted, the second conductive line 75 may contact the upper selector electrode 66. For example, the second conductive line 75 may directly contact the upper selector electrode 66. The first interlayer insulating layer 72 may be disposed around the selector structure 69. The second interlayer insulating layer 78 may be disposed between the second conductive lines 75. The second interlayer insulating layer 78 may be made of, for example, SiO x 、Si x N y , SiON, SiCN, SiOCN, TiO, ZrO x MgO x , HfO x 、AlO x or the like.

[0038] Figures 4 to 8 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. Figures 4 to 8 Similar to Figure 3 In the following description, most of the differences will be described.

[0039] refer to Figure 4 , the width of the data storage pattern 45 and the upper data storage electrode 48 may be less than Figure 3 In the example shown. In the second direction (Y direction), the width of the lower portion of the data storage pattern 45 may be smaller than the width of the upper portion of the first portion 41a of the lower data storage electrode 40. In addition, the lower portion of the data storage pattern 45 may partially overlap the spacer insulating pattern 24 in the third direction (Z direction). In the first direction (X direction) and / or in the second direction (Y direction), the width of the upper portion of the upper data storage electrode 48 may be smaller than the width of the lower portion of the selector structure 69, for example, the width of the lower selector electrode 60.

[0040] refer to Figure 5 ,and Figure 3 Unlike the example in FIG. 1 , the lower surface of the data storage pattern 45 may be lower than the lower surface of the etch stop layer 32. Thus, the data storage pattern 45 may protrude below the lower surface of the etch stop layer 32 and into the first, second and third insulating patterns 15a, 15b and 15c.

[0041] refer to Figure 6 , and in Figure 3 Unlike the example in FIG. 2 , the spacer insulating pattern 24 may be omitted.

[0042] refer to Figure 7 , the width of the data storage pattern 45 and the upper data storage electrode 48 may be less than Figure 3 In the second direction (Y direction), the width of the lower portion of the data storage pattern 45 may be smaller than the width of the upper portion of the first portion 41a of the lower data storage electrode 40. In the first direction (X direction) and / or in the second direction (Y direction), the width of the upper portion of the upper data storage electrode 48 may be smaller than the width of the lower portion of the selector structure 69, for example, the width of the lower selector electrode 60. The spacer insulating pattern 24 may also be omitted.

[0043] refer to Figure 8 ,and Figure 3 Unlike the example in FIG. 1 , the lower surface of the data storage pattern 45 may be lower than the lower surface of the etch stop layer 32. Thus, the data storage pattern 45 may protrude further downward than the lower surface of the etch stop layer 32. The spacer insulating pattern 24 may also be omitted.

[0044] Figures 9 to 21 is a diagram illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. Fig. 9 , Fig.11 , Fig.13 , Fig.15 , Fig.17 , Fig.19 , Fig.21 , Fig.23 , Fig.25 and Fig. 27 is a diagram from above showing a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept, Fig.10 , Fig.12 , Fig.14 , Fig.16 , Fig.18 , Fig. 20 , Fig. 22 , Fig.24 , Fig.26 and Fig.28 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept.

[0045] refer to Fig. 9 and Fig.10 , a first base insulating layer 5, a circuit wiring 7, a contact plug 9, and a second base insulating layer 8 may be formed on the substrate 2. A transistor may be formed on the substrate 2. The transistor may be covered by the first base insulating layer 5. The circuit wiring 7 and the contact plug 9 may be surrounded by the second base insulating layer 8.

[0046] The first conductive line 10 may be formed on the second base insulating layer 8, the lower data storage electrode 40, the first insulating pattern 15a, the spacer insulating pattern 24 and the second insulating pattern 15b may be formed on the first conductive line 10, and the third insulating pattern 15c extending in the first direction (X direction) may be formed between the first insulating pattern 15a and between the lower data storage electrodes 40 along the second direction (Y direction). The first pore V1 may be formed in each second insulating pattern 15b, and the second pore V2 may be formed in each third insulating pattern 15c. The second pore V2 may extend in the first direction (X direction).

[0047] The lower data storage electrode 40 may be formed of a conductive material including TiN, TiAlN, TaN, WN, MoN, TiSiN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TaSiN, TaAlN, TiON, TiAlON, WON or TaON, or a combination thereof, and / or a carbon-based conductive material.

[0048] The first insulating pattern 15a, the second insulating pattern 15b, the third insulating pattern 15c, and the spacer insulating pattern 24 may be made of, for example, SiO x 、Si x N y , SiON, SiCN, SiOCN, TiO, ZrO x MgO x , HfO x 、AlOx The spacer insulating pattern 24 may be formed of a material different from those of the first insulating pattern 15a, the second insulating pattern 15b, and the third insulating pattern 15c.

[0049] refer to Fig.11 and Fig.12 An etch stop layer 32 , a mold insulating layer 51 , a first hard mask layer 52 and a second hard mask pattern 53 a may be formed on the lower data storage electrode 40 , the first insulating pattern 15 a , the second insulating pattern 15 b , the third insulating pattern 15 c and the spacer insulating pattern 24 .

[0050] After forming the second hard mask layer and the first anti-reflection layer on the first hard mask layer 52, the second hard mask pattern 53a may be formed by patterning the second hard mask layer using a photolithography process and an etching process. The first anti-reflection pattern 54a may be formed on the second hard mask pattern 53a. The second hard mask patterns 53a may be spaced apart from each other in the first direction (X direction) and may extend in the second direction (Y direction).

[0051] The etching stop layer 32 and the mold insulating layer 51 may be made of a material such as SiO x 、Si x N y , SiON, SiCN, SiOCN, TiO, ZrO x MgO x , HfO x 、AlO x The etch stop layer 32 may be formed of a material different from that of the first insulating pattern 15a, the second insulating pattern 15b, the third insulating pattern 15c, the spacer insulating pattern 24, and the mold insulating layer 51. For example, the first hard mask layer 52 may be formed of polysilicon. For example, the second hard mask pattern 53a may be formed of a spin-on hard mask (SOH) material. For example, the first anti-reflection pattern 54a may be formed of SiON.

[0052] refer to Fig.13 and Fig.14 , a first hard mask pattern 52a may be formed on the mold insulation layer 51. The first hard mask pattern 52a may be formed by patterning the first hard mask layer 52 using the second hard mask pattern 53a as an etching mask. The first hard mask patterns 52a may be spaced apart from each other in the first direction (X direction) and may extend in the second direction (Y direction).

[0053] refer to Fig.15 and Fig.16 , a first spacer 55s may be formed on the side surface of the first hard mask pattern 52a. The first spacer 55s may be made of, for example, SiOx 、Si x N y , SiON, SiCN, SiOCN, TiO, ZrO x MgO x , HfO x 、AlO x or the like. The first spacer 55s may be formed of a material having an etch selectivity relative to the first hard mask pattern 52a. For example, the first hard mask pattern 52a and the first spacer 55s may be formed of SiO x form.

[0054] refer to Fig.17 and Fig.18 , a third hard mask layer 56 and a fourth hard mask layer 57 covering the first hard mask pattern 52a and the first spacer 55s may be formed. A second anti-reflection layer 58 for a photolithography process may be formed on the fourth hard mask layer 57. The third hard mask layer 56 may fill the space between the first spacers 55s. The third hard mask layer 56 may be formed of the same material as that of the first hard mask pattern 52a. For example, the fourth hard mask layer 57 may be formed of a spin-on-hard mask (SOH) material. For example, the second anti-reflection layer 58 may be formed of SiON.

[0055] refer to Fig.19 and Fig. 20 , a fourth hard mask pattern 57a ​​may be formed on the third hard mask layer 56. A second anti-reflection pattern 58a may be formed on the fourth hard mask pattern 57a. For example, the second anti-reflection pattern 58a may directly contact the fourth hard mask pattern 57a.

[0056] The fourth hard mask patterns 57a may be formed by patterning the fourth hard mask layer 57 using a photolithography process and an etching process. The fourth hard mask patterns 57a may be spaced apart from each other in the second direction (Y direction) and may extend in the first direction (X direction).

[0057] A second spacer 59s may be formed on a side surface of the fourth hard mask pattern 57a. The second spacers 59s may be spaced apart from each other in the second direction (Y direction) and may extend in the first direction (X direction). The second spacers 59s may be made of a material such as SiO x 、Si x N y , SiON, SiCN, SiOCN, TiO, ZrO x MgO x , HfO x 、AlO xor the like. The second spacer 59s may be formed of a material having an etching selectivity relative to the fourth hard mask pattern 57a. For example, the second spacer 59s may be formed of SiO x form.

[0058] refer to Fig.21 and Fig. 22 , after removing the fourth hard mask pattern 57a ​​and the second anti-reflection pattern 58a, a third hard mask pattern 56a may be formed on the first spacer 55s by patterning the third hard mask layer 56 using the second spacer 59s as an etching mask. The second spacer 59s may remain on the third hard mask pattern 56a. The third hard mask pattern 56a may be spaced apart from each other in the second direction (Y direction) and may extend along the first direction (X direction). A portion of the third hard mask layer 56 may remain so that a gap-filling pattern 56b may be formed between the first spacers 55s.

[0059] refer to Fig.23 and Fig.24 , a primary hole may be formed by etching the first spacer 55s using the third hard mask pattern 56a as an etching mask. A side surface of the primary hole may be provided by the first hard mask pattern 52a, the gap filling pattern 56b, and the first spacer 55s. A hole H penetrating the mold insulating layer 51 may be formed by etching the mold insulating layer 51 exposed by the primary hole.

[0060] refer to Fig.25 and Fig.26 The lower data storage electrode 40 may be exposed by removing the third hard mask pattern 56 a , the first hard mask pattern 52 a , the gap-filling pattern 56 b , and the first spacer 55 s remaining on the mold insulating layer 51 and etching the etch-stop layer 32 exposed through the hole H penetrating the mold insulating layer 51 .

[0061] The width of the hole H obtained in the first direction and the second direction may be narrowed from the upper portion of the hole H toward the lower portion of the hole H. For example, the width of the hole H obtained in the first direction and the width of the hole H obtained in the second direction may be 20 nm or less. The side surface of the hole H may be inclined relative to the upper surface of the substrate 2. The upper end of the lower data storage electrode 40, the upper end of the spacer insulating pattern 24, and a portion of the second insulating pattern 15 b may be exposed through the hole H.

[0062] refer to Fig. 27 and 28 , a data storage pattern 45 and an upper data storage electrode 48 may be formed in the hole H.

[0063] After forming the data storage material layer filling the hole H, the data storage pattern 45 may be formed by performing a planarization process and an etch-back process to remove the data storage material layer from the upper region of the hole H. After forming the data storage material layer filling the upper region of the hole H, the upper data storage electrode 48 may be formed by performing a planarization process.

[0064] Return to reference Figure 2 , a selector structure 69 may be formed on the upper data storage electrode 48. A first interlayer insulating layer 72 filling a peripheral region of the selector structure 69 may be formed.

[0065] A second conductive line 75 may be formed on the selector structure 69. A second interlayer insulating layer 78 filling a peripheral region of the second conductive line 75 may be formed.

[0066] Fig.29 Included are cross-sectional views illustrating a semiconductor device according to an exemplary embodiment of the inventive concept.

[0067] refer to Fig.29 , a first wire 10 extending in a first direction (X direction), a second wire 75 extending in a second direction (Y direction), and a third wire 175 extending in the first direction (X direction) may be disposed on the second base insulating layer 8 on the substrate 2. The first wires 10 may be parallel to each other and may be spaced apart from each other. The second wires 75 may be parallel to each other and may be spaced apart from each other. The third wire 175 may overlap the first wire 10 in a third direction (Z direction).

[0068] The first storage region LS between the first conductive line 10 and the second conductive line 75 may include a first data storage structure 50, a first selector structure 69, a first insulating pattern 15a, a second insulating pattern 15b, a third insulating pattern 15c, a first spacer insulating pattern 24, a first etch stop layer 32, a first mold insulating layer 51, and a first interlayer insulating layer 72. The first data storage structure 50 may be connected in series to the corresponding first selector structure 69. The structure of the first storage region LS may be connected to the first selector structure 69. Figure 2 The first data storage structures 50 may each include a first lower data storage electrode 40, a first data storage pattern 45, and a first upper data storage electrode 48. The first selector structures 69 may each include a first lower selector electrode 60, a first selector pattern 63, a first upper selector electrode 66, and a first connection pattern 68. The first data storage structures 50 and the first selector structures 69 may be the same as those of the reference numerals 14 and 15. Figure 2 and Figure 3 The data storage structure 50 and selector structure 69 described are the same.

[0069] The second storage area US between the second conductive line 75 and the third conductive line 175 may include a second data storage structure 150, a second selector structure 169, a fourth insulation pattern 115a, a fifth insulation pattern 115b, a sixth insulation pattern 115c, a second spacer insulation pattern 124, a second etch stop layer 132, a second mold insulation layer 151 and a third interlayer insulation layer 172.

[0070] The second data storage structures 150 may be connected in series to corresponding second selector structures 169 .

[0071] The second data storage structure 150 may include a second lower data storage electrode 140, a second data storage pattern 145, and a second upper data storage electrode 148. The second lower data storage electrode 140, the second data storage pattern 145, and the second upper data storage electrode 148 may be sequentially arranged.

[0072] The second data storage structure 150 may be the same as the first data storage structure 50 rotated 90 degrees in a direction horizontal to the upper surface of the substrate 2. Thus, the second data storage structure 150 may include a second lower data storage electrode 140 corresponding to the first lower data storage electrode 40, a second data storage pattern 145 corresponding to the first data storage pattern 45, and a second upper data storage electrode 148 corresponding to the first upper data storage electrode 48.

[0073] The second lower data storage electrode 140 may include a first portion in contact with the second data storage pattern 145 and a second portion extending from a lower portion of the first portion in the second direction (Y direction) and in contact with the second conductive line 75. The second portions of a pair of second lower data storage electrodes 140 disposed on the second conductive line 75 and facing each other may be connected to each other. Thus, the pair of second lower data storage electrodes 140 may form a "U" shape. The pair of second lower data storage electrodes 140 forming the "U" shape may be repeatedly disposed on the second conductive line 75. In the first direction (X direction), the width of the upper portion of the second lower data storage electrode 140 may be smaller than the width of the lower portion thereof.

[0074] The fourth insulating pattern 115a may be disposed on the second conductive line 75 alternately with a pair of second lower data storage electrodes 140 forming a "U" shape in the second direction (Y direction). The second spacer insulating pattern 124 may conformally cover the inner side surface of the second lower data storage electrode 140 forming a "U" shape. The second spacer insulating pattern 124 may have a "U" shape. The fifth insulating pattern 115b may be disposed on the second spacer insulating pattern 124, and the second spacer insulating pattern 124 may cover the side surface and the bottom surface of the fifth insulating pattern 115b. The third pore V3 may be disposed in each fifth insulating pattern 115b. The sixth insulating pattern 115c may be disposed alternately with the second lower data storage electrode 140 in the first direction (X direction). The sixth insulating pattern 115c may extend in the second direction (Y direction). The fourth pore V4 may be disposed in each sixth insulating pattern 115c. The fourth pore V4 may extend in the second direction (Y direction). For example, the third pore V3 may be arranged in a row in the first direction (X direction). The second lower data storage electrode 140 may be disposed between the fourth insulating patterns 115 a and between the sixth insulating patterns 115 c .

[0075] The second etch stop layer 132 may cover the fourth, fifth, and sixth insulation patterns 115 a , 115 b , and 115 c , and upper ends of the third and fourth voids V3 and V4 may contact the second etch stop layer 132 .

[0076] The second mold insulating layer 151 may be disposed on the second etch stop layer 132. The second data storage pattern 145 may pass through the second etch stop layer 132 and may contact the second lower data storage electrode 140. For example, the second data storage pattern 145 may directly contact the second lower data storage electrode 140 through the opening in the second etch stop layer 132. The second upper data storage electrode 148 may be disposed on the second data storage pattern 145. A lower surface of the second upper data storage electrode 148 may contact an upper surface of the second data storage pattern 145.

[0077] The second data storage pattern 145 may be configured so that the width of its upper portion may be greater than the width of its lower portion. For example, in the first direction (X direction), the width of the upper portion of the second data storage pattern 145 may be greater than the width of the lower portion thereof. The side surface of the second data storage pattern 145 may be inclined relative to the upper surface of the substrate 2. In the first direction (X direction), the width of the lower portion of the second data storage pattern 145 may be greater than the width of the upper portion of the second lower data storage electrode 140. The side surface of the second upper data storage electrode 148 may be inclined relative to the upper surface of the substrate 2. The side surface of the second upper data storage electrode 148 may be coplanar with the side surface of the second data storage pattern 145. The width of the lower portion of the second upper data storage electrode 148 may be the same as the width of the upper portion of the second data storage pattern 145. For example, in the first direction (X direction), the width of the lower portion of the second upper data storage electrode 148 may be the same as the width of the upper portion of the second data storage pattern 145.

[0078] Each of the second selector structures 169 may include a second lower selector electrode 160, a second selector pattern 163, a second upper selector electrode 166, and a second connection pattern 168 stacked in order in a third direction (Z direction) perpendicular to the upper surface of the substrate 2. The second lower selector electrode 160 may contact the second upper data storage electrode 148. The second upper selector electrode 166 may be electrically connected to the third wire 175 through the second connection pattern 168. In an exemplary embodiment of the inventive concept, the second connection pattern 168 may be omitted, in which case the second upper selector electrode 166 may contact the third wire 175.

[0079] The second selector structure 169 may be configured so that the width of its upper portion may be smaller than the width of its lower portion. The side surface of the second selector structure 169 may be inclined relative to the upper surface of the substrate 2. The side surface of the second lower selector electrode 160, the side surface of the second selector pattern 163, the side surface of the second upper selector electrode 166, and the side surface of the second connection pattern 168 may be coplanar with each other. In the first direction (X direction) and / or in the second direction (Y direction), the width of the upper portion of the second upper data storage electrode 148 may be greater than the width of the lower portion of the second selector structure 169, for example, the width of the second lower selector electrode 160.

[0080] A third interlayer insulating layer 172 may be disposed around the second selector structure 169. A fourth interlayer insulating layer 178 may be disposed between the third conductive lines 175.

[0081] Fig.30 Included are cross-sectional views illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. Fig.31 Included is shown in enlarged form Fig.30 A cross-sectional view of a local area is shown.

[0082] refer to Fig.30 and Fig.31 , different from Figure 2 and Figure 3 In the illustrated example, the storage region S′ disposed between the first conductive line 10 and the second conductive line 75 may have a structure in which the selector structure 69 is disposed below the data storage structure 50 ′.

[0083] The data storage structure 50' may include a lower data storage electrode 40', a data storage pattern 45, and an upper data storage electrode 48. The selector structure 69 may include a lower selector electrode 60, a selector pattern 63, an upper selector electrode 66, and a connection pattern 68 sequentially stacked on the first conductive line 10 in a third direction (Z direction) perpendicular to the upper surface of the substrate 2.

[0084] The lower data storage electrode 40' may be disposed on the selector structure 69. The width of the lower portion of the selector structure 69 may be greater than the width of the upper portion of the selector structure 69. In the second direction (Y direction), the width of the upper portion of the lower data storage electrode 40' may be less than the width of the lower portion of the lower data storage electrode 40'. In the second direction (Y direction), the width of the lower portion of the lower data storage electrode 40' may be the same as the width of the upper portion of the selector structure 69. The side surface of the lower selector electrode 60, the side surface of the selector pattern 63, the side surface of the upper selector electrode 66, the side surface of the connection pattern 68, and the side surface of the lower data storage electrode 40' may be coplanar with each other. The lower data storage electrode 40' may cover the side surface and the lower surface of the gap filling insulating pattern 24'.

[0085] The insulating pattern 71' may be disposed between the first conductive lines 10, and the interlayer insulating layer 72' may be disposed around the selector structure 69. The insulating pattern 71' may protrude into the second base insulating layer 8. The first voids V1' and the second voids V2' may be formed in the interlayer insulating layer 72'.

[0086] The data storage pattern 45 may pass through the etch stop layer 32 disposed on the interlayer insulating layer 72' and may contact the lower data storage electrode 40'. The width of the upper portion of the data storage pattern 45 may be greater than the width of the lower portion of the data storage pattern 45. The width of the lower portion of the data storage pattern 45 may be greater than the width of the upper portion of the lower data storage electrode 40' in the first direction (X direction) and / or the second direction (Y direction).

[0087] The upper data storage electrode 48 may be disposed on the data storage pattern 45, and the side surface of the upper data storage electrode 48 and the side surface of the data storage pattern 45 may be coplanar with each other. The width of the lower portion of the upper data storage electrode 48 may be the same as the width of the upper portion of the data storage pattern 45. The mold insulating layer 51 may be disposed on the etch stop layer 32, and the mold insulating layer 51 may surround the side surface of the upper data storage electrode 48 and the side surface of the data storage pattern 45.

[0088] Fig.32 and Fig.33 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept.

[0089] Fig.32 and Fig.33 Similar to Fig.31 , therefore, most of the differences will be described in the following description.

[0090] refer to Fig.32 , the width of the data storage pattern 45 and the upper data storage electrode 48 may be less than Fig.31 In the second direction (Y direction), the width of the lower portion of the data storage pattern 45 may be smaller than the width of the upper portion of the lower data storage electrode 40'. The width of the upper portion of the upper data storage electrode 48 may be smaller than the width of the lower portion of the selector structure 69, such as the width of the lower selector electrode 60.

[0091] refer to Fig.33 , different from Fig.31 In the example shown, the lower surface of the data storage pattern 45 may be lower than the lower surface of the etch stop layer 32. In other words, the data storage pattern 45 may protrude further downward than the lower surface of the etch stop layer 32.

[0092] According to the above-described exemplary embodiments of the inventive concept, data storage patterns each having a size of 20 nm or less may be formed.

[0093] Furthermore, a bridging defect between upper data storage electrodes formed on the data storage pattern may be reduced or removed.

[0094] Furthermore, a semiconductor device with improved productivity and reliability can be provided.

[0095] While the inventive concept has been shown and described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that modifications and variations may be made thereto without departing from the scope of the inventive concept as defined in the appended claims.

[0096] This application claims the priority benefit of Korean Patent Application No. 10-2019-0010762 filed on January 28, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: A first conductive line is disposed on the substrate and extends along a first direction parallel to an upper surface of the substrate; a second conductive line disposed on the first conductive line and extending along a second direction perpendicular to the first direction and parallel to the upper surface of the substrate; first data storage structures disposed between the first conductive line and the second conductive line, wherein each of the first data storage structures includes a first lower data storage electrode, a first data storage pattern on the first lower data storage electrode, and a first upper data storage electrode on the first data storage pattern; as well as a first etch stop layer adjacent to a lower surface of the first data storage pattern and extending along the first direction and the second direction, wherein in the second direction, the width of the upper portion of the first lower data storage electrode is smaller than the width of the lower portion of the first lower data storage electrode, in the second direction, the width of the upper portion of the first data storage pattern is greater than the width of the lower portion of the first data storage pattern, and in the second direction, the width of the upper portion of the first lower data storage electrode is different from the width of the lower portion of the first data storage pattern.

2. The semiconductor device according to claim 1, wherein in the second direction, a width of an upper portion of the first upper data storage electrode is greater than a width of a lower portion of the first upper data storage electrode, and Wherein in the second direction, the width of the lower portion of the first upper data storage electrode is the same as the width of the upper portion of the first data storage pattern.

3. The semiconductor device according to claim 1, further comprising: A first selector structure is disposed between the first conductive line and the second conductive line and is serially connected to the first data storage structure.

4. The semiconductor device according to claim 3, wherein in the second direction, a width of an upper portion of the first selector structure is smaller than a width of a lower portion of the first selector structure, and Wherein in the second direction, the width of the lower portion of the first selector structure is different from the width of the upper portion of the first upper data storage electrode.

5. The semiconductor device according to claim 1, further comprising: An insulating pattern is disposed under the first etch stop layer, covers side surfaces of the first lower data storage electrode, and includes a pore. The semiconductor device according to claim 5 , wherein the pore is in contact with a lower surface of the first etch stop layer. 7 . The semiconductor device of claim 1 , wherein a lower end of the first data storage pattern is below a lower surface of the first etch stop layer. 8 . The semiconductor device of claim 1 , wherein the width of the lower portion of the first lower data storage electrode is the same as a width of an upper portion of a corresponding one of the first conductive lines in the second direction.

9. The semiconductor device according to claim 1, further comprising: a third conductive line disposed on the second conductive line and extending along the first direction; second data storage structures disposed between the second conductive line and the third conductive line, wherein each of the second data storage structures includes a second lower data storage electrode, a second data storage pattern on the second lower data storage electrode, and a second upper data storage electrode on the second data storage pattern; as well as a second etch stop layer adjacent to a lower surface of the second data storage pattern and extending along the first direction and the second direction, wherein in the first direction, the width of the upper portion of the second lower data storage electrode is smaller than the width of the lower portion of the second lower data storage electrode, in the first direction, the width of the upper portion of the second data storage pattern is greater than the width of the lower portion of the second data storage pattern, and in the first direction, the width of the upper portion of the second lower data storage electrode is different from the width of the lower portion of the second data storage pattern.

10. The semiconductor device according to claim 9, wherein in the first direction, a width of an upper portion of the second upper data storage electrode is greater than a width of a lower portion of the second upper data storage electrode, and Wherein in the first direction, the width of the lower portion of the second upper data storage electrode is the same as the width of the upper portion of the second data storage pattern.

11. The semiconductor device according to claim 9, further comprising: A second selector structure is disposed between the second conductive line and the third conductive line and is serially connected to the second data storage structure.

12. The semiconductor device according to claim 11, wherein in the second direction, a width of an upper portion of the second selector structure is smaller than a width of a lower portion of the second selector structure, and Wherein the width of the lower portion of the second selector structure is different from the width of the upper portion of the second upper data storage electrode.

13. A semiconductor device comprising: A first conductive line is disposed on the substrate and extends along a first direction parallel to an upper surface of the substrate; a second conductive line disposed on the first conductive line and extending along a second direction perpendicular to the first direction and parallel to the upper surface of the substrate; a first data storage structure and a first selector structure, disposed between the first conductive line and the second conductive line and connected in series with each other; as well as a first etch stop layer adjacent to a side surface of the first data storage structure and extending along the first direction and the second direction, wherein the first data storage structure comprises a first lower data storage electrode, a first data storage pattern and a first upper data storage electrode, and The slope of the side surface of the first lower data storage electrode is different from the slope of the side surface of the first data storage pattern, and the width of the upper portion of the first lower data storage electrode is different from the width of the lower portion of the first data storage pattern.

14. The semiconductor device according to claim 13, wherein a slope of a side surface of the first upper data storage electrode is the same as the slope of the side surface of the first data storage pattern, and a width of a lower portion of the first upper data storage electrode is the same as a width of an upper portion of the first data storage pattern.

15. The semiconductor device according to claim 13, wherein each side surface of the first selector structure has a slope, and Wherein a width of a lower portion of the first selector structure is different from a width of an upper portion of the first upper data storage electrode.

16. The semiconductor device according to claim 13, further comprising: An insulating pattern is disposed under the first etch stop layer, covers the side surface of the first lower data storage electrode, and includes a pore. 17 . The semiconductor device according to claim 16 , wherein the pore is in contact with a lower surface of the first etch stop layer.

18. A semiconductor device comprising: A first conductive line disposed on the substrate; a second conductive line disposed on the substrate; as well as a data storage structure disposed between the first conductive line and the second conductive line, wherein the data storage structure comprises a data storage pattern disposed between a first data storage electrode and a second data storage electrode, wherein the first data storage electrode is below the data storage pattern, the second data storage electrode is above the data storage pattern, and Wherein a width of a lower portion of the data storage pattern is greater than a width of an upper portion of the first data storage electrode, and wherein the data storage pattern gradually becomes thinner in a direction toward the first data storage electrode. 19 . The semiconductor device of claim 18 , wherein the lower portion of the data storage pattern directly contacts the upper portion of the first data storage electrode.

20. The semiconductor device of claim 18, further comprising a selector structure directly contacting the second data storage electrode.

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