Switching driver of insulated gate bipolar transistor using first and second pull-down signals

Abstract

A driver of an insulated gate bipolar transistor is switched with first and second pull-down signals. For example, a controller circuit for controlling an insulated gate bipolar transistor (IGBT) is configured to, in response to an IGBT turn-off switching event, disconnect a first switching element to prevent a pull-up signal from flowing to a gate of the IGBT, connect a second switching element to create a channel that allows a first pull-down signal to flow to the gate of the IGBT, and connect a third switching element to create a channel that allows a second pull-down signal to flow to the gate of the IGBT. In response to determining that a collector-emitter voltage at the IGBT does not satisfy a threshold, the controller circuit is configured to disconnect the third switching element to prevent the second pull-down signal from flowing to the gate of the IGBT.

Description

Technical Field

[0001] The present disclosure relates to a circuit arrangement for driving an insulated gate bipolar transistor (IGBT), in particular an IGBT in hard switching applications. Background Art

[0002] Insulated gate bipolar transistors (IGBTs) have desirable characteristics that make them more suitable than metal oxide semiconductor field effect transistors (MOSFETs), particularly for high power and high efficiency applications. For example, IGBTs may be used in many applications such as, but not limited to, variable frequency drives (VFDs), automotive, power converters, light emitting diodes (LEDs), and other applications. As a byproduct of the switching operation, the IGBT may generate waste heat. If the IGBT reaches a temperature that exceeds the rated temperature of the IGBT, the IGBT may deteriorate or permanently fail. Summary of the invention

[0003] In general, the present disclosure is directed to a driver for an insulated gate bipolar transistor (IGBT) having a first pull-down signal that reduces switching losses at the IGBT and a second pull-down signal that reduces switching losses at the IGBT and reduces voltage overshoot at the IGBT. For example, the driver may be configured to allow the first pull-down signal and the second pull-down signal to quickly reduce the current flowing through the IGBT in response to a turn-off switching event, and then allow only the first pull-down signal to reduce the peak turn-off voltage at the IGBT. In this manner, the driver may "decouple" the current rate of change (di / dt) and voltage rate of change (dv / dt) performance of the IGBT, which may reduce switching losses at the IGBT while helping to ensure that the peak turn-off voltage at the IGBT is less than the rated voltage at the IGBT. Reducing switching losses at the IGBT may reduce waste heat generated by the IGBT, which may help protect the IGBT from thermal damage and help improve the reliability of the IGBT.

[0004] In one example, a controller circuit for controlling an IGBT is configured to: in response to an IGBT turn-off switching event, disconnect a first switching element to prevent a pull-up signal from flowing to a gate of the IGBT; in response to the IGBT turn-off switching event, connect a second switching element to create a channel that allows a first pull-down signal to flow to a gate of the IGBT; in response to the IGBT turn-off switching event, connect a third switching element to create a channel that allows a second pull-down signal to flow to a gate of the IGBT; and in response to determining that a collector-emitter voltage at the IGBT does not satisfy a threshold, disconnect the third switching element to prevent the second pull-down signal from flowing to the gate of the IGBT.

[0005] In another example, a method for controlling an IGBT comprises: in response to an IGBT turn-off switching event, disconnecting, by a controller circuit, a first switching element to prevent a pull-up signal from flowing to a gate of the IGBT; in response to the IGBT turn-off switching event, connecting, by the controller circuit, a second switching element to create a channel allowing a first pull-down signal to flow to a gate of the IGBT; in response to the IGBT turn-off switching event, connecting, by the controller circuit, a third switching element to create a channel allowing a second pull-down signal to flow to a gate of the IGBT; and in response to determining that a collector-emitter voltage at the IGBT does not satisfy a threshold, disconnecting, by the controller circuit, the third switching element to prevent the second pull-down signal from flowing to the gate of the IGBT.

[0006] In another example, an IGBT system includes: an IGBT and a controller circuit, the controller circuit being configured to: in response to an IGBT turn-off switching event, disconnect a first switching element to prevent a pull-up signal from flowing to a gate of the IGBT; in response to the IGBT turn-off switching event, connect a second switching element to create a channel allowing a first pull-down signal to flow to a gate of the IGBT; in response to the IGBT turn-off switching event, connect a third switching element to create a channel allowing a second pull-down signal to flow to the gate of the IGBT; and in response to determining that a collector-emitter voltage at the IGBT does not satisfy a threshold, disconnect the third switching element to prevent the second pull-down signal from flowing to the gate of the IGBT.

[0007] Details of these and other examples are set forth in the accompanying drawings and the description that follows. Other features, objects, and advantages will be apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram illustrating a driver circuit arrangement of an insulated gate bipolar transistor (IGBT) with a first pull-down signal and a second pull-down signal according to one or more techniques of this disclosure.

[0009] Figure 2A is a diagram showing a fixed delay according to one or more techniques of the present disclosure. Figure 1 Circuit diagram of a first example of a driver circuit device.

[0010] Figure 2B is a diagram showing a fixed delay according to one or more techniques of the present disclosure. Figure 1 Circuit diagram of a second example of a driver circuit device.

[0011] Figure 3A is a diagram showing a variable delay determined by a controller according to one or more techniques of the present disclosure Figure 1 Circuit diagram of a first example of a driver circuit device.

[0012] Figure 3B is a diagram showing a variable delay determined by a controller according to one or more techniques of the present disclosure Figure 1 Circuit diagram of a second example of a driver circuit device.

[0013] Figure 4A is a diagram showing a variable delay determined by a sensing circuit according to one or more techniques of the present disclosure Figure 1 Circuit diagram of a first example of a driver circuit device.

[0014] Figure 4B is a diagram showing a variable delay determined by a sensing circuit according to one or more techniques of the present disclosure Figure 1 Circuit diagram of a second example of a driver circuit device.

[0015] Figure 5A FIG. 1 is a diagram showing a variable delay and di / dt enhancement function determined by a sensing circuit according to one or more techniques of the present disclosure. Figure 1 Circuit diagram of a first example of a driver circuit device.

[0016] Figure 5B FIG. 1 is a diagram showing a variable delay and di / dt enhancement function determined by a sensing circuit according to one or more techniques of the present disclosure. Figure 1 Circuit diagram of a second example of a driver circuit device.

[0017] Figure 6 is a diagram showing a fixed delay according to one or more techniques of the present disclosure. Figure 1 Detailed circuit diagram of an example of a driver circuit device.

[0018] Figure 7 is a diagram showing an example of a circuit having an external variable delay according to one or more techniques of the present disclosure. Figure 1 Detailed circuit diagram of an example of a driver circuit device.

[0019] Figure 8 is a diagram showing a circuit having an internal variable delay according to one or more techniques of the present disclosure Figure 1 Detailed circuit diagram of an example of a driver circuit device.

[0020] Fig. 9 FIG. 1 is a diagram showing a circuit having internal variable delay and di / dt enhancement capabilities according to one or more techniques of the present disclosure. Figure 1 Detailed circuit diagram of an example of a driver circuit device.

[0021] Fig.10 According to one or more techniques of the present disclosure Figure 1 A first diagram of the performance of a driver circuit arrangement.

[0022] Fig.11 According to one or more techniques of the present disclosure Figure 1 A second diagram of the performance of a driver circuit arrangement.

[0023] Fig.12 According to one or more techniques of the present disclosure Figure 1 A third diagram of the performance of a driver circuit arrangement.

[0024] Fig.13 is a flow chart of a process for driving an IGBT according to one or more techniques of this disclosure.

[0025] Fig.14 is a flow chart of a process for driving an IGBT with current enhancement function according to one or more techniques of this disclosure.

[0026] Fig.15 is a flow chart of a process for driving an IGBT according to one or more techniques of this disclosure. DETAILED DESCRIPTION

[0027] In hard-switched insulated gate bipolar transistor (IGBT) applications, some voltage gate drive techniques use a single turn-on and / or turn-off gate resistor to control the switching speed of the IGBT. To reduce the IGBT turn-off switching losses, such systems may use a reduced turn-off gate resistor. This results in an increase in the IGBT's di / dt and dv / dt response during turn-off due to IGBT turn-off di / dt and dv / dt coupling. Thus, reducing the turn-off gate resistor increases the turn-off di / dt and also results in a corresponding increase in the IGBT turn-off overshoot voltage due to the approximate L between the IGBT turn-off overshoot voltage and the turn-off di / dt. stray *di / dt(where L stray Since each IGBT may be designed to operate reliably up to a certain rated voltage (eg, 650V), this increase in overshoot voltage may have an impact on both the transient and long-term reliability of the IGBT.

[0028] Some drivers are based on applying the lowest possible turn-off gate resistance, which limits the maximum turn-off di / dt, thereby maintaining the turn-off overshoot voltage of the IGBT below the rated breakdown voltage of the IGBT. In such drivers, the IGBT can be driven faster to obtain lower turn-off switching losses if it is not limited by the maximum rated breakdown voltage of the IGBT. Therefore, one disadvantage of such drivers is that the rated breakdown voltage of the IGBT limits the degree to which the turn-off switching losses of the IGBT can be reduced.

[0029] According to one or more techniques described herein, a driver may be configured to "decouple" the turn-off di / dt and dv / dt of an IGBT so that the IGBT turn-off switching losses may be further reduced compared to a driver limited by the rated breakdown voltage of the IGBT. In this manner, the driver may operate the IGBT to turn off at an optimal dv / dt and di / dt (and therefore at a lower overshoot voltage) to help achieve the maximum possible reduction in the IGBT turn-off switching losses. For example, the driver may be configured to allow a first pull-down signal to flow to the gate of the IGBT to reduce the switching losses at the IGBT, and to allow a second pull-down signal to flow to the gate of the IGBT to reduce the voltage overshoot at the IGBT. Thus, such a driver may reduce the switching losses at the IGBT while helping to ensure that the peak turn-off voltage at the IGBT is less than the rated voltage at the IGBT, which may reduce the waste heat generated by the IGBT to help protect the IGBT from thermal damage and improve the long-term reliability of the IGBT.

[0030] Figure 1 is a block diagram illustrating a system 100 for an IGBT 102 with a first pull-down signal 123 and a second pull-down signal 125 , in accordance with one or more techniques of this disclosure. Figure 1 A system 100 is shown, which includes a driver circuit device 106, a gate-on resistor 120, a gate-off resistor 122, a gate-off resistor 124, and an IGBT 102. The driver circuit device 106 may include a controller circuit 104, a gate driver 108, and an enhancement driver 110. The system 100 may include additional components. For example, the system 100 may include a gate-off resistor 126. In some examples, one or more components of the system 100 may be omitted. For example, the gate-off resistor 124 may be omitted, and the enhancement driver 110 may be coupled to the gate-off resistor 122. In some examples, the driver circuit 106 may be implemented as a single or multiple integrated circuit (IC) packages.

[0031] IGBT 102 may refer to a device including alternating PNPN layers controlled by a metal oxide semiconductor (MOS) gate structure. In some examples, IGBT 102 may include a collector, an emitter, and a gate. In this example, the current at the gate may control the conductive path between the collector and the emitter.

[0032] The gate driver 108 may include a first switching element 130 configured to allow a pull-up signal to flow to the gate of the IGBT 102 via the gate-on resistor 120. As shown, the gate driver 108 may include a second switching element 132 configured to allow a first pull-down signal 123 to flow to the gate of the IGBT 102 via the gate-off resistor 122. Examples of switching elements may include, but are not limited to, junction field effect transistors (JFETs), metal oxide semiconductor field effect transistors (MOSFETs), dual-gate MOSFETs, insulated gate bipolar transistors (IGBTs), any other type of FET, or any combination of switching elements. Examples of MOSFETs may include, but are not limited to, p-channel MOSFETs (pMOS), n-channel MOSFETs (nMOS), double diffused MOSFETs (DMOS), or any other type of MOSFETs or any combination thereof. In some examples, the switching element may include a high electron mobility transistor, a GaN-based transistor, or another switching element. Other materials may also be used to implement the switching element.

[0033] More specifically, for example, the gate driver 108 may be configured to turn on the switching element 132 to create a channel so that the first pull-down signal 123 flows to the gate of the IGBT 102 through the gate-on resistor 122. Similarly, the gate driver 108 may be configured to turn off the switching element 132 to prevent the first pull-down signal from flowing to the gate-on resistor 122 coupled to the gate of the IGBT 102. The gate driver 108 may be configured to turn off the switching element 130 to prevent the pull-up signal from flowing to the gate-on resistor 120 coupled to the gate of the IGBT 102. Similarly, the gate driver 108 may be configured to turn on the switching element 130 to create a channel so that the pull-up signal flows to the gate of the IGBT 102 through the gate-on resistor 120.

[0034] The boost driver 110 may include a third switching element 134 configured to allow the second pull-down signal 125 to flow to the gate of the IGBT 102 via the gate turn-off resistor 124. In some examples, the third switching element 134 is configured to allow the second pull-down signal to flow to the gate of the IGBT 102 via the gate turn-off resistor 122. In some examples, the boost driver 110 may include a fourth switching element 136 configured to allow the fourth pull-down signal to flow to the gate of the IGBT 102 via the gate turn-off resistor 126. In some examples, the fourth switching element 136 is configured to allow the fourth pull-down signal to flow to the gate of the IGBT 102 via the gate turn-off resistor 122. In some examples, the fourth switching element 136 may be omitted.

[0035] The enhancement driver 110 may be configured to turn on the switching element 134 to create a channel so that the second pull-down signal flows to the gate of the IGBT 102 through the gate turn-off resistor 124. Similarly, the enhancement driver 110 may be configured to turn off the switching element 134 to prevent the second pull-down signal from flowing to the gate turn-off resistor 124 coupled to the gate of the IGBT 102. The enhancement driver 110 may be configured to turn off the switching element 136 to prevent the pull-down signal from flowing to the gate turn-off resistor 126 coupled to the gate of the IGBT 102. Similarly, the enhancement driver 110 may be configured to turn on the switching element 136 to create a channel so that the pull-down signal flows to the gate of the IGBT 102 through the gate turn-off resistor 126. Figure 1 In the example of , the switching element 134 is coupled to the gate-off resistor 124. However, in other examples, the switching element 134 may be coupled to the gate-off resistor 122, and the gate-off resistor 124 may be omitted.

[0036] The gate driver 108 may be configured to turn on the switching element 132 so that the channel created by the second switching element 132 allows the first pull-down current to flow from the gate of the IGBT 102 to the pull-down source. Similarly, the boost driver 110 may be configured to turn on the third switching element 134 so that the channel created by the switching element 134 allows the second pull-down current to flow from the gate of the IGBT 102 to the pull-down source.

[0037] The power supply 131 may be configured to provide a pull-up signal. For example, the power supply 131 may be configured to provide a charge at the gate of the IGBT 102. In some examples, the power supply 131 may be the output of a power converter, a power inverter, a regulator, or other power conversion circuit device. For example, the power supply 131 may be the output of a direct current (DC)-DC power converter, an alternating current (AC)-DC power converter, a DC-AC power converter, a linear regulator, or other power conversion circuit.

[0038] The power supply 133 may be configured to provide a pull-down signal. For example, the power supply 133 may be configured to discharge the gate of the IGBT 102. In some examples, the power supply 133 may be the output of a power converter, a power inverter, a regulator, or other power conversion circuit device. Although not shown, one or more of the third switching element 134 and the fourth switching element 136 may have a corresponding power supply similar to the power supply 133. In some examples, the power supply 133 may output a voltage having a polarity opposite to the voltage output from the power supply 131. For example, the power supply 131 may output a positive voltage, and the power supply 133 may output a negative voltage.

[0039] The controller circuit 104 may be configured to control the switching of one or more of the first switching element 130, the second switching element 132, the third switching element 134, or the fourth switching element 136. In some examples, the controller circuit 104 may receive a pulse width modulation (PWM) signal and use the PWM signal to determine the IGBT turn-off switching event. In some examples, the controller circuit 104 may be configured to use the voltage indication at the IGBT 102 and / or the current indication at the IGBT 102 to control the switching of one or more of the first switching element 130, the second switching element 132, the third switching element 134, or the fourth switching element 136. The controller circuit 104 may include any suitable arrangement of hardware, software, firmware, or any combination thereof. The controller circuit 104 may include any one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or any other equivalent integrated or discrete logic circuits and any combination of these components. When the controller circuit includes software or firmware, the controller circuit may further include any necessary hardware for storing and executing the software or firmware, such as one or more memories and one or more processors or processing units. In general, the controller circuit may include one or more microprocessors, DSPs, ASICs, FPGAs, or any other equivalent integrated or discrete logic circuits, as well as any combination of these components.

[0040] In operation, the controller circuit 104 may be configured to turn off the first switching element 130 in response to an IGBT turn-off switching event to prevent the pull-up signal from flowing to the gate of the IGBT 102, turn on the second switching element 132 in response to the IGBT turn-off switching event to create a channel that allows the first pull-down signal to flow to the gate of the IGBT 102, and turn on the third switching element 134 in response to the IGBT turn-off switching event to create a channel that allows the second pull-down signal to flow to the gate of the IGBT 102. In response to determining that the collector-emitter voltage at the IGBT 102 does not satisfy the threshold, the controller circuit may be configured to turn off the third switching element 134 to prevent the second pull-down signal from flowing to the gate of the IGBT 102.

[0041] Figure 2A is a diagram showing a fixed delay according to one or more techniques of the present disclosure. Figure 1 1 is a circuit diagram of a first example of a driver circuit device 106. As shown in the figure, the system 200A includes a driver circuit device 206, a gate-on resistor 220, a gate-off resistor 222, a gate-off resistor 224 and an IGBT 202, which can be respectively Figure 1The driver circuit device 206, the gate-on resistor 120, the gate-off resistor 122, the gate-off resistor 124 and the IGBT 102 are examples of the driver circuit device 206. The driver circuit device 206 may include a microcontroller 204, a gate driver 208 and an enhancement driver 210, which may be respectively Figure 1 2 . The controller circuit 104, the gate driver 108 and the boost driver 110 are shown in FIG. 2 . The driver circuit device 206 can be implemented as a single or multiple IC packages. In this example, the boost driver 210 outputs a second pull-down signal (also referred to herein as a "dv / dt boost signal" or simply "boost pull-down signal") to the gate of the IGBT 202 via the gate turn-off resistor 224.

[0042] Figure 2B is a diagram showing a fixed delay according to one or more techniques of the present disclosure. Figure 1 1 is a circuit diagram of a second example of a driver circuit device 106. Similar to the system 200A, the system 200B includes a driver circuit device 206, a gate-on resistor 220, a gate-off resistor 222, and an IGBT 202, which may be Figure 1 1, 2, and 3. The system 200B is an example of a driver circuit device 106, a gate-on resistor 120, a gate-off resistor 122, and an IGBT 102. However, the system 200B omits the gate-off resistor 224. The driver circuit device 206 may include a microcontroller 204, a gate driver 208, and a boost driver 210, which may be Figure 1 The controller circuit 104, the gate driver 108 and the boost driver 110 of FIG. 206 can be implemented as a single or multiple IC packages. In this example, the boost driver 210 outputs a second pull-down signal to the gate of the IGBT 202 via the gate turn-off resistor 222.

[0043] exist Figure 2A and Figure 2B In the example of FIG. 2 , the microcontroller 204 can define a fixed input delay based on the switching characteristics of the IGBT 202 at the maximum load current and bus voltage of the application dedicated to the IGBT 202. The fixed delay can be provided externally by the microcontroller 204 to generate a dv / dt enhancement signal. In this way, the driver circuit device 206 can reduce the turn-off switching loss at high currents of the peak turn-off overshoot voltage (e.g., 30% at 400V / 180A). Compared to a system omitting the enhancement driver 210, Figure 2A The example uses only one additional external component (the additional turn-off gate resistor). However, Figure 2BExamples of use the same external components as systems that omit the boost driver 210. In some examples, the boost driver 210 can be implemented in an integrated circuit including the gate driver circuit device 206 to extend the performance of the existing gate driver circuit device 206. Figure 2A In the example of , if implemented in a gate driver IC, the driver circuit device 206 may use only two additional pins compared to a system omitting the boost driver 210, wherein the additional input pin is configured for setting the fixed delay and the additional output pin is used to connect the boost driver 210 to the gate turn-off resistor 224. However, in Figure 2B In the example of FIG. 1 , the driver circuit 206 may use only one additional pin compared to a system that omits the enhancement driver 210 , where the additional pin is an input pin configured to set a fixed delay. Figure 2A and Figure 2B Examples of may not use additional sensing circuitry compared to systems that omit the boost driver 210 and / or may operate in open loop. Figure 2A and Figure 2B An example can be used for a fixed bus voltage system.

[0044] The external fixed delay may provide the greatest performance improvement at the maximum system current and less improvement at lower currents. However, the external fixed delay may not interfere with normal system operation. Due to the reduced switching losses, the IGBT 202 may have a lower junction temperature during operation, or cooling restrictions on the systems 200A and 200B may be reduced. In addition, reducing the switching losses at the IGBT 202 may improve the electromechanical reliability of the IGBT and / or may accommodate higher conduction losses, which would allow for smaller IGBT active area requirements for implementing products with similar current ratings compared to systems that omit the enhanced driver 210.

[0045] Figure 3A is a diagram showing a variable delay determined by a controller according to one or more techniques of the present disclosure Figure 1 1 is a circuit diagram of a first example of a driver circuit 106. As shown, the system 300A includes a driver circuit device 306, a gate-on resistor 320, a gate-off resistor 322, a gate-off resistor 324, and an IGBT 302, which may be Figure 1 The driver circuit device 306, the gate-on resistor 120, the gate-off resistor 122, the gate-off resistor 124 and the IGBT 102 are examples of the driver circuit device 306. The driver circuit device 306 may include a microcontroller 304, a gate driver 308 and an enhancement driver 310, which may be respectively Figure 1306. The example of the controller circuit 104, the gate driver 108 and the boost driver 110 of FIG. 306 can be implemented as a single or multiple IC packages. In this example, the boost driver 310 outputs a second pull-down signal (also referred to herein as a "dv / dt boost signal" or simply a "pull-down signal") to the gate of the IGBT 302 via the gate turn-off resistor 324.

[0046] exist Figure 3A In the example of , the microcontroller 304 may be configured to calculate a variable delay to reduce losses at the IGBT 302 . Figure 3A An example of can be used for a variable bus voltage system. Figure 3A An example of a system 300A may use bus voltage and current measurement techniques available in the system 300A (e.g., inverter and DC-DC converter). The microcontroller 304 may define input delays based on the switching characteristics of the IGBT 302 at various load currents and bus voltage levels specific to the application of the IGBT 302. Based on the voltage and current levels, the microcontroller 304 of the system 300A may provide a lookup table based variable delay to the boost driver 310.

[0047] Figure 3B is a diagram showing a variable delay determined by a controller according to one or more techniques of the present disclosure Figure 1 1 is a circuit diagram of a second example of a driver circuit device 106. Similar to the system 300A, the system 300B includes a driver circuit device 306, a gate-on resistor 320, a gate-off resistor 322, and an IGBT 302, which may be Figure 1 1 , a gate-on resistor 120, a gate-off resistor 122, and an example of an IGBT 102. However, the system 300B omits the gate-off resistor 324. The driver circuit device 306 may include a microcontroller 304, a gate driver 308, and an enhancement driver 310, which may be Figure 1 3. The controller circuit 104, gate driver 108 and boost driver 110 of FIG. 306 are examples of the controller circuit 104, gate driver 108 and boost driver 110 of FIG. 306. The driver circuit device 306 can be implemented as a single or multiple IC packages. In this example, the boost driver 310 outputs a second pull-down signal to the gate of the IGBT 302 via the gate turn-off resistor 322.

[0048] Figure 4A FIG. 4 is a diagram showing a variable delay determined by sense circuitry 440 in accordance with one or more techniques of this disclosure. Figure 1 1 is a circuit diagram of a first example of a driver circuit 106. As shown, the system 400A includes a driver circuit device 406, a gate-on resistor 420, a gate-off resistor 422, a gate-off resistor 424, and an IGBT 402, which may be respectively Figure 1 The driver circuit device 406, the gate turn-off resistor 120, the gate turn-off resistor 122, the gate turn-off resistor 124 and the IGBT 102 are examples. The driver circuit device 406 may include a microcontroller 404, a gate driver 408 and an enhancement driver 410, which may be respectively Figure 1 4. The embodiment of the controller circuit 104, the gate driver 108 and the boost driver 110 of FIG. 406 are shown in FIG. 406. As shown, the driver circuit device 406 may include a sensing circuit device 440. The driver circuit device 406 may be implemented as a single or multiple IC packages. In this example, the boost driver 410 outputs a second pull-down signal (also referred to herein as a "dv / dt boost signal" or simply a "pull-down signal") to the gate of the IGBT 402 via the gate turn-off resistor 424.

[0049] Figure 4A An example of can be used for a variable bus voltage system. In this example, the microcontroller 404 does not use an external delay input. In this example, the sense circuit device 440 can automatically (e.g., without a delay signal generated by another component outside the microcontroller 404 or the driver circuit device 406) generate a dv / dt pull-down signal.

[0050] Figure 4B FIG. 4 is a diagram showing a variable delay determined by sense circuitry 440 in accordance with one or more techniques of this disclosure. Figure 1 4 is a circuit diagram of a second example of a driver circuit device 106. Similar to the system 400A, the system 400B includes a driver circuit device 406, a gate-on resistor 420, a gate-off resistor 422, and an IGBT 402, which may be Figure 1 1, 2, and 3. The system 400B is an example of a driver circuit device 106, a gate-on resistor 120, a gate-off resistor 122, and an IGBT 102. However, the system 400B omits the gate-off resistor 424. The driver circuit device 406 may include a microcontroller 404, a gate driver 408, and a boost driver 410, which may be Figure 1 4. The controller circuit 104, gate driver 108 and boost driver 110 of FIG. 406 are examples of the controller circuit 104, gate driver 108 and boost driver 110 of FIG. 406 can be implemented as a single or multiple IC packages. In this example, the boost driver 410 outputs a second pull-down signal to the gate of the IGBT 402 via the gate turn-off resistor 422.

[0051] Figure 4BA switching element 442 is shown, which can be configured to provide a resistance in series with the gate driver 408 and the gate turn-off resistor 422. In this example, the switching element 444 is configured to provide a resistance in series with the boost driver 410 and the gate turn-off resistor 422. In this example, the switching element 444 can be configured to have a different resistance than the switching element 442. For example, the switching element 444 can be configured to have a lower or higher resistance than the switching element 442. In this way, the gate turn-off signal output by the switching element 442 can discharge the gate of the IGBT 402 faster or slower than the gate turn-off signal output by the switching element 444.

[0052] Figure 5A FIG. 5 is a diagram showing a variable delay and di / dt enhancement function determined by a sensing circuit 540 according to one or more techniques of the present disclosure. Figure 1 1 is a circuit diagram of a first example of a driver circuit 106. As shown in the figure, the system 500A includes a driver circuit device 506, a gate-on resistor 520, a gate-off resistor 522, a gate-off resistor 524 and an IGBT 502, which can be respectively Figure 1 1 , a gate-on resistor 120, a gate-off resistor 122, a gate-off resistor 124, and an example of an IGBT 102. As shown, the system 500A may also include a gate-off resistor 526. The driver circuit device 506 may include a microcontroller 504, a gate driver 508, and an enhancement driver 510, which may be Figure 1 1. The controller circuit 104, gate driver 108, and boost driver 110 are examples of the same. As shown, the driver circuit device 506 may also include a sensing circuit device 540 and a di / dt enhancement circuit device 550. The driver circuit device 506 may be implemented as a single or multiple IC packages.

[0053] The enhancement driver 510 may be configured to output a second pull-down signal (also referred to herein as a “dv / dt enhancement signal” or simply as a “pull-down signal”) to the gate of the IGBT 502 via the gate turn-off resistor 524. As shown, the di / dt enhancement circuit device 550 may be configured to output a pull-down signal (also referred to herein as a “partial load pull-down signal”) to the gate of the IGBT 502 via the gate turn-off resistor 526. In some examples, the di / dt enhancement circuit device 550 may be configured to provide a partial load pull-down signal via the gate turn-off resistor 526 when the microcontroller 504 determines that the current at the IGBT 502 meets the load current (e.g., is less than the load current threshold).

[0054] Figure 5BFIG. 1 is a diagram showing a circuit having variable delay and current enhancement functions determined by a sensing circuit according to one or more techniques of the present disclosure. Figure 1 1 is a circuit diagram of a second example of a driver circuit device 106. Similar to the system 500A, the system 500B includes a driver circuit device 506, a gate-on resistor 520, a gate-off resistor 522, and an IGBT 502, which may be Figure 1 1 , and an example of a driver circuit device 106 , a gate-on resistor 120 , a gate-off resistor 122 , and an IGBT 102 . As shown, a switching element 530 may be configured to allow current to flow to the gate of the IGBT 502 via the gate-on resistor 520 .

[0055] However, the system 500B omits the gate turn-off resistor 524 and the gate turn-off resistor 526. In this example, the enhancement driver 510 outputs a second pull-down signal to the gate of the IGBT 502 via the gate turn-off resistor 522. In some examples, the di / dt enhancement circuit 550 outputs a partial load pull-down signal to the gate of the IGBT 502 via the gate turn-off resistor 522.

[0056] exist Figure 5B In the example of , the switching element 542 can be configured to provide a resistance in series with the gate driver 508 and the gate turn-off resistor 522. In this example, the switching element 544 is configured to provide a resistance in series with the boost driver 510 and the gate turn-off resistor 522. In this example, the switching element 544 can be configured to have a different resistance than the switching element 542. For example, the switching element 544 can be configured to have a lower or higher resistance than the switching element 542. In this way, the microcontroller 504 can select the node B or the node D as the node X, which is coupled to the gate of the IGBT 502 via the gate turn-off resistor 522 without using an additional pin or an additional external resistor.

[0057] Figure 5A and Figure 5B Examples of can be used for variable bus voltage systems. In these examples, the reduction in turn-off di / dt at IGBT 502 as current decreases can be offset by additional gate resistors, which will speed up the turn-off di / dt at IGBT 502 while keeping the peak overshoot voltage below the IGBT voltage breakdown limit. Microcontroller 504 can be configured to set the drive strength based on the load current of the system.

[0058] Figure 6 is a diagram showing a fixed delay according to one or more techniques of the present disclosure. Figure 1Detailed circuit diagram of an example of a driver circuit device 106. As shown, the system 600 includes a driver circuit device 606, a gate-on resistor 620, a gate-off resistor 622, a gate-off resistor 624, and an IGBT 602, which may be Figure 1 The driver circuit device 606, the gate-on resistor 120, the gate-off resistor 122, the gate-off resistor 124 and the IGBT 102 are examples of the driver circuit device 606. The driver circuit device 606 may include a power supply 631, a power supply 633, a gate driver 608 and a boost driver 610, which may be Figure 1 1 , a power supply 131, a power supply 133, a gate driver 108, and an enhancement driver 110. As shown, the driver circuit device 606 may also include a pulse width modulator (PWM) 604. The driver circuit device 606 may be implemented as a single or multiple IC packages. In this example, the enhancement driver 610 outputs a second pull-down signal (also referred to herein as a "dv / dt enhancement signal") to the gate of the IGBT 602 via a gate turn-off resistor 624. As shown, the power supply 631 outputs a positive voltage to turn on the IGBT 602. In this example, the power supply 633 outputs a negative voltage to turn off the IGBT 602. Figure 6 In the example of , the fixed input delay may be provided (eg, by a microcontroller) based on the switching characteristics of the IGBT 602 at a maximum load current and bus voltage specific to the application of the IGBT 602 .

[0059] Figure 7 is a diagram showing an example of a circuit having an external variable delay according to one or more techniques of the present disclosure. Figure 1 Detailed circuit diagram of an example of a driver circuit device 106. As shown, the system 700 includes a driver circuit device 706, a gate-on resistor 720, a gate-off resistor 722, a gate-off resistor 724, and an IGBT 702, which may be respectively Figure 1 The driver circuit device 706, the gate-on resistor 120, the gate-off resistor 122, the gate-off resistor 124 and the IGBT 102 are examples of the driver circuit device 706. The driver circuit device 706 may include a power supply 731, a power supply 733, a gate driver 708 and a boost driver 710, which may be Figure 1 The example of power supply 131, power supply 133, gate driver 108 and boost driver 110. Driver circuit device 706 also includes PWM 704. Driver circuit device 706 can be implemented as a single or multiple IC packages. Figure 7 In the example of , the microcontroller can be configured to calculate a variable delay to reduce losses at the IGBT 702.

[0060] Figure 8is a diagram showing a circuit having an internal variable delay according to one or more techniques of the present disclosure Figure 1 As shown, the system 800 includes a driver circuit device 806, a gate-on resistor 820, a gate-off resistor 822, a gate-off resistor 824, and an IGBT 802, which can be respectively Figure 1 The driver circuit device 806, the gate-on resistor 120, the gate-off resistor 122, the gate-off resistor 124 and the IGBT 102 are examples of the driver circuit device 806. The driver circuit device 806 may include a power supply 831, a power supply 833, a gate driver 808 and a boost driver 810, which may be Figure 1 The example of power supply 131, power supply 133, gate driver 108 and boost driver 110. The driver circuit device 806 also includes PWM 804. The driver circuit device 806 can be implemented as a single or multiple IC packages. Figure 8 In an example of , sensing circuitry 840 , which may be an example of sensing circuitry 440 of FIG. 4 , may be configured to calculate a variable delay to reduce losses at IGBT 802 .

[0061] Fig. 9 FIG. 1 is a diagram showing a circuit having internal variable delay and di / dt enhancement capabilities according to one or more techniques of the present disclosure. Figure 1 As shown, the system 900 includes a driver circuit device 906, a gate-on resistor 920, a gate-off resistor 922, a gate-off resistor 924, and an IGBT 902, which may be Figure 1 The driver circuit device 906, the gate-on resistor 120, the gate-off resistor 122, the gate-off resistor 124 and the IGBT 102 are examples of the driver circuit device 906. The driver circuit device 906 may include a power supply 931, a power supply 933, a gate driver 908 and a boost driver 910, which may be Figure 1 906. The driver circuit device 906 also includes a PWM 904. The driver circuit device 906 can be implemented as a single or multiple IC packages. Fig. 9 In an example of , sensing circuitry 940 , which may be an example of sensing circuitry 440 of FIG. 4 , may be configured to calculate a variable delay to reduce losses at IGBT 902 .

[0062] As shown, the system 900 may further include a gate turn-off resistor 926, and the driver circuit device may further include a di / dt enhancement circuit 950. In this example, the di / dt enhancement circuit device 950 may be configured to output a pull-down signal (also referred to herein as a "di / dt enhancement signal") to the gate of the IGBT 902 via the gate turn-off resistor 926. For example, the controller circuit 104 may be configured to set the driver strength to high when the current at the IGBT 902 is not less than a load current threshold (e.g., not less than 180 amps), so that the gate driver 908 provides the pull-down signal via the gate turn-off resistor 920. In this example, the controller circuit 104 may be configured to set the driver strength to low when the current at the IGBT 902 is less than the load current threshold (e.g., less than 180 amps), so that the di / dt enhancement circuit device 950 provides the partial load pull-down signal via the gate turn-off resistor 926.

[0063] Fig.10 According to one or more techniques of the present disclosure Figure 1 A first diagram of the performance of the driver circuit arrangement 106 . Fig.10 The abscissa axis (eg, horizontal) of represents time, and Fig.10 The ordinate axis (e.g., vertical) represents a pull-up signal 1002 output by the gate driver 108 to the gate of the IGBT 102 via the gate-on resistor 120, a first pull-down signal 1004 output by the gate driver 108 to the gate of the IGBT 102 via the gate-off resistor 122, a second pull-down signal 1006 output by the boost driver 110 to the gate of the IGBT 102 via the gate-off resistor 124, an IGBT current 1008 at the IGBT 102, a voltage 1010 at the IGBT 102, a reference voltage 1012 of the voltage at the IGBT driven without the second pull-down signal 1006, a power loss 1014 at the IGBT 102, and a reference power loss 1016 of the voltage at the IGBT driven without the second pull-down signal 1006.

[0064] exist Fig.10 In the example of , 400 volts and 180 amps are applied to the IGBT 102 to obtain a peak turn-off overshoot voltage of 560 volts. As shown, in a 400 volt and 180 amp application, the turn-off switching loss of the driver circuit device 106 can be reduced by 30% compared to a system omitting the enhancement driver 110.

[0065] Fig.11 According to one or more techniques of the present disclosure Figure 1 A second diagram of the performance of the driver circuit arrangement 106 is shown. Fig.11The abscissa axis (eg, horizontal) of represents the current of the IGBT 102 , and Fig.11 The ordinate axis (e.g., vertical) represents the “turn-off” switching loss energy 1102 (or simply “energy 1102”) of the system in which the enhancement driver 110 is omitted, the energy 1104 of the system 100 configured with a fixed delay, the energy 110 of the system 100 configured with a variable delay calculated using a sensing circuit device (e.g., sensing circuit device 440), and the energy 1108 of the system 100 configured with a variable delay calculated using a sensing circuit device (e.g., sensing circuit device 540) and a di / dt enhancement circuit device 550.

[0066] Fig.12 According to one or more techniques of the present disclosure Figure 1 A third diagram of the performance of a driver circuit arrangement. Fig.12 The abscissa axis (eg, horizontal) of represents the bus voltage of the IGBT 102 at 180 amperes, and Fig.12 The ordinate axis (e.g., vertical) represents the “off” switching loss energy 1202 (or simply “energy 1202”) of the system in which the enhancement driver 110 is omitted and the energy 1204 of the system 100 configured with a variable delay calculated using a sensing circuit device (e.g., sensing circuit device 440).

[0067] Fig.13 is a flowchart of a process for driving an IGBT according to one or more techniques of the present disclosure. Figures 1 to 9 Described in the context of Fig.13 In operation, the controller circuit 104 initiates an IGBT turn-off switching event (1302), and R g,on The pull-up signal goes low. Gate driver 108 sets node A to high impedance (1304), and R g,off Pull-down signal and R g,off The pull-down / pull-down signal is high. For example, gate driver 108 opens switching element 130 and closes switching elements 132 and 134. Gate driver 108 pulls node B low to discharge IGBT 102, and boost driver 110 pulls node C low to discharge IGBT 102, the collector-emitter voltage at IGBT 102 begins to increase, and the rate of voltage change (dv / dt) increases, which reduces the switching loss at IGBT 102 (1306). The collector-emitter voltage at IGBT 102 reaches the bus voltage, and the sensing circuit (e.g., sensing circuit device 440) generates a signal (1308), which causes R g,offThe pull-up / pull-down signal goes low. Node C becomes high impedance (1310). For example, the boost driver 110 turns on the switching element 134. The collector-emitter current at the IGBT 102 begins to decrease toward zero, and the rate of change of the collector-emitter current and the overshoot voltage at the IGBT 102 is equivalent to a system omitting the boost driver 110 (1312). The IGBT turn-off switching event ends (1314).

[0068] Fig.14 is a flow chart of a process for driving an IGBT 102 with di / dt enhancement functionality according to one or more techniques of the present disclosure. Figures 1 to 9 Described in the context of Fig.14 In operation, the controller circuit 104 initiates an IGBT turn-off switching event (1402), and R g,on The pull-up signal goes low. Gate driver 108 sets node A to high impedance (1404), and R g,off Pull-down signal and R g,off dv / dt The pull-down signal is high. For example, gate driver 108 opens switching element 130 and closes switching element 132 and switching element 134. Although R g,off dv / dt The pull-down signal is referred to as the “pull-down signal” in this article, but R g,off dv / dt The pull-down signal may, for example, be changed from a pull-down signal to a pull-up signal.

[0069] The controller circuit 104 provides a signal (1416) indicating the driver strength based on the current level at the IGBT 102. In other words, for example, the controller circuit 104 is configured to turn on the switching element 132 in response to determining that the current at the IGBT 102 meets the load current to allow the full load pull-down signal to flow to the gate of the IGBT 102. For example, if the current at the IGBT 102 is at a maximum level, the signal specifies that the node X is set to the node B.

[0070] However, in response to determining that the current at the IGBT 102 does not satisfy the load current (eg, the load current is less than the load current threshold), the controller circuit (eg, the microcontroller 504) is configured to turn on the switching element (eg, Figure 5BThe switching element 544 of the IGBT 502 is used to allow a partial load pull-down signal to flow to the gate of the IGBT 502. For example, if the current is not at a maximum level, the signal specifies that the node X is set to the node D. The di / dt enhancement circuit device 550 pulls the node D low to discharge the IGBT 502, and the enhancement driver 510 pulls the node C low to discharge the IGBT 502, and the collector-emitter voltage at the IGBT 502 begins to rise, and the voltage change rate (dv / dt) is enhanced, which reduces the switching loss at the IGBT 502 (1406).

[0071] For example, in response to the signal specifying that node X is set to node B, the gate driver 508 pulls node B low to discharge the IGBT 502, and the di / dt enhancement circuit device 550 does not pull node D low to discharge the IGBT 502. In this example, in response to the signal specifying that node X is set to node D, the gate driver 508 does not pull node B low to discharge the IGBT 502, and the di / dt enhancement circuit device 550 pulls node D low to discharge the IGBT 502.

[0072] The collector-emitter voltage at IGBT 502 reaches the bus voltage, and the sensing circuit (eg, sensing circuit device 440) generates a signal (1408), which causes R g,off The pull-up / pull-down signal goes low. Node C becomes high impedance (1410). For example, the boost driver 510 turns on the switching element 534. The collector-emitter current at the IGBT 502 begins to decrease toward zero, and the rate of change of the collector-emitter current and the overshoot voltage at the IGBT 502 is equivalent to a system omitting the boost driver 510 (1412). The IGBT turn-off switching event ends (1414).

[0073] Fig.15 is a flow chart of a process for driving IGBT 102 according to one or more techniques of the present disclosure. For exemplary purposes only, Figures 1 to 9 Described in the context of Fig.15In operation, the gate driver 108 and the boost driver 110 use the PWM signal to determine that an IGBT turn-off switching event occurs (1502). The gate driver 108 turns off a first switching element (e.g., switching element 130) to prevent the pull-up signal from flowing to the gate of the IGBT 102 (1504). The gate driver 108 turns on a second switching element (e.g., switching element 132) to create a channel that allows the first pull-down signal to flow to the gate of the IGBT 102 (1506). Simultaneously with the gate driver turning on the second switching element, the boost driver 110 turns on a third switching element (e.g., switching element 134) to create a channel that allows the second pull-down signal to flow to the gate of the IGBT 102 (1508).

[0074] The controller circuit 104 determines that the collector-emitter voltage at the IGBT 102 does not meet the threshold value (1510), and turns off the third switching element (e.g., the switching element 134) to prevent the second pull-down signal from flowing to the gate of the IGBT 102 (1512). For example, the controller circuit 104 determines that the collector-emitter voltage at the IGBT 102 does not meet the threshold value in response to the switching element 134 being turned on for a duration exceeding the delay threshold. In some examples, the delay is a fixed delay of the IGBT 102. In some examples, the controller circuit 104 is configured to determine the delay threshold value using a sensed voltage at the IGBT 102 and a sensed current at the IGBT 102. In some examples, the controller circuit 104 is configured to determine that the collector-emitter voltage at the IGBT 102 does not meet the threshold value in response to the collector-emitter voltage at the IGBT 102 being greater than the voltage threshold.

[0075] Although the device has been described with reference to exemplary embodiments, this description is not intended to be interpreted in a limiting sense. Those skilled in the art will understand various modifications and combinations of the exemplary embodiments and other embodiments of the present invention with reference to the description. Therefore, the appended claims include any such modifications or embodiments.

[0076] The following examples may illustrate one or more aspects of the present disclosure.

[0077] Example 1. A controller circuit for controlling an insulated gate bipolar transistor (IGBT), the controller circuit being configured to: in response to an IGBT turn-off switching event, disconnect a first switching element to prevent a pull-up signal from flowing to a gate of the IGBT; in response to the IGBT turn-off switching event, connect a second switching element to create a channel that allows a first pull-down signal to flow to the gate of the IGBT; in response to the IGBT turn-off switching event, connect a third switching element to create a channel that allows a second pull-down signal to flow to the gate of the IGBT; and in response to determining that a collector-emitter voltage at the IGBT does not satisfy a threshold, disconnect the third switching element to prevent the second pull-down signal from flowing to the gate of the IGBT.

[0078] Example 2. The controller circuit of Example 1, wherein the controller circuit is configured to: determine that a collector-emitter voltage at the IGBT does not satisfy a threshold in response to the third switching element being turned on for a duration exceeding a delay threshold.

[0079] Example 3. The controller circuit of any combination of Examples 1-2, wherein the delay threshold is a fixed delay of the IGBT.

[0080] Example 4. The controller circuit of any combination of Examples 1-3, wherein the controller circuit is configured to determine the delay threshold using a sensed voltage at the IGBT and a sensed current at the IGBT.

[0081] Example 5. The controller circuit of any combination of Examples 1-4, wherein the controller circuit is configured to: in response to the collector-emitter voltage at the IGBT being greater than a voltage threshold, determine that the collector-emitter voltage at the IGBT does not satisfy a threshold.

[0082] Example 6. A controller circuit according to any combination of Examples 1-5, wherein the controller circuit is configured to turn on the second switching element in response to determining that the current at the IGBT satisfies the load current, and wherein the controller circuit is configured to: in response to determining that the current at the IGBT satisfies the load current, prevent the fourth switching element from being turned on, thereby preventing the third pull-down signal from flowing to the gate of the IGBT.

[0083] Example 7. A controller circuit according to any combination of Examples 1-6, wherein the first pull-down signal is a partial load pull-down signal; wherein the controller circuit is configured to: in response to determining that the current at the IGBT is less than the load current threshold, determine that the current at the IGBT satisfies the load current threshold; and wherein the third pull-down signal is a full load pull-down signal.

[0084] Example 8. A controller circuit according to any combination of Examples 1-7, wherein the first pull-down signal is a full-load pull-down signal; wherein the controller circuit is configured to: in response to determining that the current at the IGBT is not less than the load current threshold, determine that the current at the IGBT satisfies the load current threshold; and wherein the third pull-down signal is a partial-load pull-down signal.

[0085] Example 9. A controller circuit according to any combination of Examples 1-8, wherein, to disconnect the first switching element, the controller circuit is configured to prevent the pull-up signal from flowing to a gate-on resistor coupled to the gate of the IGBT; and wherein, to connect the second switching element, the controller circuit is configured to create a channel so that the first pull-down signal flows to the gate of the IGBT through the gate-off resistor.

[0086] Example 10. The controller circuit of any combination of Examples 1-9, wherein the gate turn-off resistor is a first gate turn-off resistor, and wherein to turn on the third switching element, the controller circuit is configured to create a channel so that the second pull-down signal flows to the gate of the IGBT through the second gate turn-off resistor.

[0087] Example 11. The controller circuit of any combination of Examples 1-10, wherein to turn on the third switching element, the controller circuit is configured to create a channel such that the second pull-down signal flows to the gate of the IGBT through the gate turn-off resistor.

[0088] Example 12. The controller circuit of any combination of Examples 1-11, wherein the controller circuit is configured to: receive a pulse width modulated (PWM) signal; and determine an IGBT turn-off switching event using the PWM signal.

[0089] Example 13. A controller circuit according to any combination of Examples 1-12, wherein in order to turn on the second switching element, the control circuit is configured to turn on the second switching element so that the channel created by the second switching element allows a first pull-down current to flow from the gate of the IGBT to the pull-down source; and wherein in order to turn on the third switching element, the control circuit is configured to turn on the third switching element so that the channel created by the third switching element allows a second pull-down current to flow from the gate of the IGBT to the pull-down source.

[0090] Example 14. The controller circuit of any combination of Examples 1-13, wherein to turn on the third switching element, the controller circuit is configured to turn on the third switching element simultaneously with the second switching element.

[0091] Example 15. A method for controlling an insulated gate bipolar transistor (IGBT), the method comprising: in response to an IGBT turn-off switching event, disconnecting a first switching element by a controller circuit to prevent a pull-up signal from flowing to a gate of the IGBT; in response to the IGBT turn-off switching event, connecting a second switching element by the controller circuit to create a channel allowing a first pull-down signal to flow to the gate of the IGBT; in response to the IGBT turn-off switching event, connecting a third switching element by the controller circuit to create a channel allowing a second pull-down signal to flow to the gate of the IGBT; and in response to determining that a collector-emitter voltage at the IGBT does not meet a threshold, disconnecting the third switching element by the controller circuit to prevent the second pull-down signal from flowing to the gate of the IGBT.

[0092] Example 16. The method of Example 15, further comprising: in response to the third switching element being turned on for a duration exceeding the delay threshold, determining, by the controller circuit, that the collector-emitter voltage at the IGBT does not satisfy the threshold.

[0093] Example 17. The method of any combination of Examples 15-16, wherein the delay threshold is a fixed delay of the IGBT.

[0094] Example 18 The method of any combination of Examples 15-17, further comprising determining, by the controller circuit, the delay threshold using a sensed voltage at the IGBT and a sensed current at the IGBT.

[0095] Example 19. The method of any combination of Examples 15-18, further comprising: in response to the collector-emitter voltage at the IGBT being greater than a voltage threshold, determining, by the controller circuit, that the collector-emitter voltage at the IGBT does not satisfy a threshold.

[0096] Example 20. An insulated gate bipolar transistor (IGBT) system, comprising an IGBT and a controller circuit, the controller circuit being configured to: in response to an IGBT turn-off switching event, disconnect a first switching element to prevent a pull-up signal from flowing to a gate of the IGBT; in response to the IGBT turn-off switching event, connect a second switching element to create a channel allowing a first pull-down signal to flow to the gate of the IGBT; in response to the IGBT turn-off switching event, connect a third switching element to create a channel allowing a second pull-down signal to flow to the gate of the IGBT; and in response to determining that a collector-emitter voltage at the IGBT does not satisfy a threshold, disconnect the third switching element to prevent the second pull-down signal from flowing to the gate of the IGBT.

[0097] This disclosure describes various aspects. These and other aspects are within the scope of the following claims.

Claims

1. A controller circuit for controlling an insulated gate bipolar transistor (IGBT), the controller circuit being configured as follows: In response to an IGBT turn-off switching event, disconnecting the first switching element to prevent the pull-up signal from flowing to the gate of the IGBT; In response to the IGBT turn-off switching event, turning on a second switching element to create a first channel allowing a first pull-down signal to flow to a gate of the IGBT; In response to the IGBT turn-off switching event, turning on a third switching element to create a second channel allowing a second pull-down signal to flow to the gate of the IGBT; Determine latency thresholds; in response to the third switching element being turned on for a duration exceeding the delay threshold, determining that a collector-emitter voltage at the IGBT does not satisfy a threshold; as well as In response to determining that the collector-emitter voltage at the IGBT does not satisfy the threshold, turning off the third switching element to prevent the second pull-down signal from flowing to the gate of the IGBT. 2 . The controller circuit of claim 1 , wherein the delay threshold is a fixed delay of the IGBT.

3. The controller circuit according to claim 1, wherein: To determine the delay threshold, the controller circuit is configured to: The delay threshold is determined using a sensed voltage at the IGBT and a sensed current at the IGBT.

4. The controller circuit of claim 1 , wherein the controller circuit is configured to turn on the second switching element in response to determining that the current at the IGBT satisfies a load current threshold, and wherein the controller circuit is configured to: In response to determining that the current at the IGBT satisfies the load current threshold, a fourth switching element is prevented from turning on, thereby preventing a third pull-down signal from flowing to a gate of the IGBT.

5. The controller circuit according to claim 4, The controller circuit is configured to: in response to determining that the current at the IGBT is less than the load current threshold, determine that the current at the IGBT satisfies the load current threshold.

6. The controller circuit according to claim 4, The controller circuit is configured to: in response to determining that the current at the IGBT is not less than the load current threshold, determine that the current at the IGBT satisfies the load current threshold.

7. The controller circuit according to claim 1, wherein in order to turn off the first switching element, the controller circuit is configured to prevent the pull-up signal from flowing to a gate-on resistor coupled to a gate of the IGBT; and To turn on the second switching element, the controller circuit is configured to create the first channel so that the first pull-down signal flows to the gate of the IGBT through a gate turn-off resistor.

8. The controller circuit of claim 7 , wherein the gate-off resistor is a first gate-off resistor, and wherein to turn on the third switching element, the controller circuit is configured to create the second channel so that the second pull-down signal flows to the gate of the IGBT through a second gate-off resistor. 9 . The controller circuit of claim 7 , wherein to turn on the third switching element, the controller circuit is configured to create the second channel so that the second pull-down signal flows to the gate of the IGBT through the gate turn-off resistor.

10. The controller circuit of claim 1, wherein the controller circuit is configured to: receiving a pulse width modulation (PWM) signal; and The IGBT turn-off switching event is determined using the PWM signal.

11. The controller circuit according to claim 1, wherein in order to turn on the second switching element, the control circuit is configured to turn on the second switching element so that the first channel created by the second switching element allows a first pull-down current to flow from the IGBT to a pull-down source; and Wherein, in order to turn on the third switching element, the control circuit is configured to turn on the third switching element so that the second channel created by the third switching element allows a second pull-down current to flow from the gate of the IGBT to the pull-down source. 12 . The controller circuit according to claim 1 , wherein to turn on the third switching element, the controller circuit is configured to turn on the third switching element simultaneously with the second switching element.

13. A method for controlling an insulated gate bipolar transistor (IGBT), the method comprising: In response to an IGBT turn-off switching event, disconnecting the first switching element by the controller circuit to prevent the pull-up signal from flowing to the gate of the IGBT; In response to the IGBT turn-off switching event, the controller circuit turns on a second switching element to create a first channel allowing a first pull-down signal to flow to a gate of the IGBT; In response to the IGBT turn-off switching event, the controller circuit turns on a third switching element to create a second channel allowing a second pull-down signal to flow to the gate of the IGBT; determining, by the controller circuit, a delay threshold; In response to the third switching element being turned on for a duration exceeding the delay threshold, determining, by the controller circuit, that a collector-emitter voltage at the IGBT does not satisfy a threshold; In response to determining that the collector-emitter voltage at the IGBT does not satisfy the threshold, the third switching element is turned off by the controller circuit to prevent the second pull-down signal from flowing to the gate of the IGBT. The method of claim 13 , wherein the delay threshold is a fixed delay of the IGBT.

15. The method of claim 13, wherein determining the delay threshold comprises: The delay threshold is determined using a sensed voltage at the IGBT and a sensed current at the IGBT.

16. An insulated gate bipolar transistor (IGBT) system, comprising: IGBT; as well as The controller circuit is configured as: In response to an IGBT turn-off switching event, disconnecting the first switching element to prevent the pull-up signal from flowing to the gate of the IGBT; In response to the IGBT turn-off switching event, turning on a second switching element to create a first channel allowing a first pull-down signal to flow to a gate of the IGBT; In response to the IGBT turn-off switching event, turning on a third switching element to create a second channel allowing a second pull-down signal to flow to the gate of the IGBT; Determine latency thresholds; in response to the third switching element being turned on for a duration exceeding the delay threshold, determining that a collector-emitter voltage at the IGBT does not satisfy a threshold; In response to determining that the collector-emitter voltage at the IGBT does not satisfy the threshold, turning off the third switching element to prevent the second pull-down signal from flowing to the gate of the IGBT.

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