A multi-layer stacked LDMOS power device

Abstract

The present invention discloses a multi-layer stacked LDMOS power device, which utilizes a dual drift region formed by stacking more than two MOS device units, and introduces a P heavily doped region and an N heavily doped region at the top of the lower drift region, which not only adds a new current path and improves the working current in the on state; but also reduces the electric field peaks of the gate and drain of the lower drift region, and introduces two new electric field peaks inside the device, optimizes the internal electric field strength of the device, improves the electric field distribution inside the device, and thus improves the withstand voltage characteristics of the device. In addition, a lightly doped overlapping floating layer is introduced between the dual drift regions to assist depletion, so as to effectively increase the doping concentration of the dual drift regions and further improve the withstand voltage characteristics. Furthermore, the withstand voltage characteristics of the device are further improved by introducing a heavily doped unit buried layer at the bottom of the upper drift region and introducing a heavily doped unit floating layer in the lightly doped region between the dual drift regions.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor devices, and in particular to a multi-layer stacked LDMOS power device. Background Art

[0002] MOSFET is a fairly mature device among power devices. As a voltage-controlled device, MOSFET has the advantages of simple driving, high input impedance, low leakage current, and low noise factor, and has been widely used in the power device market. As a majority carrier conductive device, MOSFET has a very short switching time and can operate at a very high frequency. Compared with bipolar devices that can only be used in low-frequency fields, MOSFET has a wider range of applications.

[0003] In MOSFET power devices, they can be divided into two categories, LDMOS and VDMOS, according to the current flow path during operation. For LDMOS, breakdown voltage (BV) and specific on-resistance (Ron.sp) are two key parameters to measure device performance. Domestic and foreign researchers have been committed to obtaining LDMOS devices with high breakdown voltage (i.e., high withstand voltage) and low specific on-resistance. However, in LDMOS devices, the specific on-resistance of the device increases sharply with the increase of breakdown voltage at the power of 2.5. Therefore, the increase of breakdown voltage will inevitably lead to an increase of specific on-resistance, i.e., a decrease of operating current; the increase of operating current will also reduce the breakdown voltage due to the decrease of specific on-resistance. How to compromise and improve the relationship between the two has always been the focus and hot direction of power device research.

[0004] To this end, researchers have proposed a series of methods to improve this problem. Common improvement methods include RESURF technology (Reduced Surface Field), field plate technology (FP, Field Plate), field limit ring (FLR, Field Limit Ring), lateral doping technology (Variation of Lateral Doping, VLD), junction termination extension (JTE, Junction Termination Extension), etc. These technologies can effectively alleviate the electric field concentration effect near the main junction surface, improve the breakdown voltage of the device, and at the same time improve the specific on-resistance and increase the working current of the device. However, in order to obtain high-voltage and high-current LDMOS power devices, the problem of its specific on-resistance rising sharply with the increase of the device breakdown voltage still exists, that is, to obtain high-voltage LDMOS devices, the drift region length must be increased or the drift region doping concentration must be reduced, which results in a significant increase in the occupied area of ​​high-voltage LDMOS devices without sacrificing the working current, which is inconsistent with the trend of miniaturization of integrated circuits. Summary of the invention

[0005] The present invention aims to solve the problem that the existing LDMOS power device cannot have both high breakdown voltage and low specific on-resistance. A multi-layer stacked LDMOS power device is provided to obtain a high breakdown voltage LDMOS device while obtaining a larger operating current and improving device characteristics.

[0006] To solve the above problems, the present invention is achieved through the following technical solutions:

[0007] A multi-layer stacked LDMOS power device, comprising more than two MOS device units;

[0008] Each MOS device unit is composed of a doping layer, a drift layer, a body region, a first heavily doped region, a second heavily doped region and a third heavily doped region; the drift layer is located directly above the doping layer; the first heavily doped region, the second heavily doped region and the third heavily doped region are distributed from left to right on the top of the drift layer, wherein the first heavily doped region is located on the leftmost side of the top of the drift layer, the second heavily doped region is adjacent to the first heavily doped region, and the third heavily doped region is located on the rightmost side of the top of the drift layer; the body region is located on the upper left side of the drift layer, and the first heavily doped region and the second heavily doped region are both within the body region; the doping polarity of the doping layer, the body region and the first heavily doped region is the same; the doping polarity of the drift layer, the second heavily doped region and the third heavily doped region is the same; the doping polarity of the doping layer and the drift layer is opposite; the top of the first heavily doped region and the second heavily doped region are connected to form the source of the MOS device unit; the top of the body region on the right side of the second heavily doped region forms the gate of the MOS device unit; the top of the third heavily doped region forms the drain of the MOS device unit;

[0009] All MOS device units are stacked in sequence from bottom to top; in every two adjacent stacked MOS device units, the doping layer of the MOS device unit located at a relatively upper layer overlaps with the drift layer of the MOS device unit located at a relatively lower layer, and the total width of the MOS device unit located at a relatively upper layer is less than or equal to the width between the body region and the third heavily doped region of the MOS device unit located at a relatively lower layer;

[0010] After all MOS device units are stacked, the doped layer of the MOS device unit located at the bottom layer forms the substrate of the LDMOS power device; the source electrodes of all MOS device units are connected together through wires to form the source electrode of the LDMOS power device; the gate electrodes of all MOS device units are connected together through wires to form the gate electrode of the LDMOS power device; the drain electrodes of all MOS device units are connected together through wires to form the drain electrode of the LDMOS power device.

[0011] As an improvement, an overlapping floating layer is additionally provided at the overlap of two adjacent stacked MOS device units, i.e., the overlap of the doping layer of the MOS device unit located at the relatively upper layer and the drift layer of the MOS device unit located at the relatively lower layer. The overlapping floating layer is located on the left and / or right side of the above-mentioned overlap.

[0012] In the above solution, the doping polarity of the overlapping floating layer located on the left side of the overlapping portion is opposite to the doping polarity of the overlapping floating layer located on the right side of the overlapping portion.

[0013] As a further improvement, a unit buried layer is additionally provided between the doping layer and the drift layer of at least one MOS device unit, and the unit buried layer is located on the left side of the MOS device unit.

[0014] In the above solution, the doping polarity of the buried layer in the cell is the same as the doping polarity of the body region.

[0015] As a further improvement, a laterally extending intra-unit floating layer is additionally provided in the doping layer of at least one MOS device unit.

[0016] In the above solution, the doping polarity of the floating layer in the cell is the same as the doping polarity of the doping layer, and the doping concentration of the floating layer in the cell is greater than the doping concentration of the doping layer.

[0017] The present invention discloses a multi-layer stacked LDMOS power device. The dual drift regions formed by stacking more than two MOS device units are used to introduce a P heavily doped region and an N heavily doped region at the top of the lower drift region, which not only adds a new current path and improves the working current in the on state; but also reduces the electric field peaks of the gate and drain of the lower drift region, and introduces two new electric field peaks inside the device, optimizes the internal electric field strength of the device, improves the electric field distribution inside the device, and thus improves the withstand voltage characteristics of the device. In addition, by introducing a lightly doped overlapping floating layer between the dual drift regions to assist depletion, the doping concentration of the dual drift regions can be effectively increased, the specific on-resistance can be reduced, and the working current can be further increased. A heavily doped unit buried layer is introduced at the bottom of the upper drift region, thereby introducing a new electric field peak, optimizing the lateral electric field distribution of the device, and improving the lateral withstand voltage characteristics of the device. By introducing a heavily doped unit internal floating layer in the lightly doped region between the dual drift regions, the longitudinal potential distribution of the device is optimized, and the longitudinal withstand voltage characteristics of the device are improved.

[0018] Compared with the prior art, the present invention has the following characteristics:

[0019] 1. The present invention can obtain an LDMOS power device with a higher breakdown voltage and a larger operating current while using the same chip area, thereby improving chip utilization.

[0020] 2. When stacked into two layers, the dual channels of the device can effectively increase the current in the on state, and the introduction of a P lightly doped region between the dual drift regions to assist depletion can effectively increase the concentration of the drift region and reduce the specific on-resistance.

[0021] 3. The stacking structure can be stacked in multiple layers, which can more effectively increase the device current without affecting the withstand voltage, and greatly improve the contradictory relationship between the breakdown voltage BV and the specific on-resistance Ron.sp.

[0022] 4. Under the same size, the breakdown voltage of the present invention is at least about 350V, and the on-state current Ids=4.9×10 - 5 A, while the breakdown voltage of traditional LDMOS is around 250V, and the on-current Ids=2.15×10 -5 A. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of the two-layer stacking structure of the present invention.

[0024] Figure 2 It is a breakdown characteristic curve diagram of the two-layer stacked structure of the present invention.

[0025] Figure 3 It is an on-state current curve diagram of the two-layer stacked structure of the present invention.

[0026] Figure 4 It is another schematic diagram of the structure of the two-layer stacking of the present invention.

[0027] Figure 5 It is a schematic diagram of the three-layer stacking structure of the present invention.

[0028] Figure 6 It is another structural schematic diagram of the three-layer stacking of the present invention. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in combination with specific examples and with reference to the accompanying drawings. It should be noted that the directional terms mentioned in the examples, such as "upper", "lower", "middle", "left", "right", "front", "back", etc., are only referenced to the directions of the accompanying drawings. Therefore, the directions used are only used for illustration and are not used to limit the scope of protection of the present invention.

[0030] A multi-layer stacked LDMOS power device includes more than two MOS device units, which are MOS device units of the same doping polarity, that is, all are P-type MOS device units or all are N-type MOS device units. When all are P-type MOS device units, a P-type LDMOS power device is formed. When all are N-type MOS device units, an N-type LDMOS power device is formed. The number of stacked MOS device units is more than two and is a limited superposition. In a preferred embodiment of the present invention, the number of stacked MOS device units is between 2 and 5.

[0031] Each MOS device unit consists of a doped layer, a drift layer, a body region, a first heavily doped region, a second heavily doped region, and a third heavily doped region. The drift layer is located directly above the doped layer. The first heavily doped region, the second heavily doped region, and the third heavily doped region are distributed from left to right on the top of the drift layer, wherein the first heavily doped region is located on the leftmost side of the top of the drift layer, the second heavily doped region is adjacent to the first heavily doped region, and the third heavily doped region is located on the rightmost side of the top of the drift layer. The body region is located on the upper left side of the drift layer, and both the first heavily doped region and the second heavily doped region are within the body region, that is, at the top of the drift layer, the width of the body region is greater than the sum of the widths of the first heavily doped region and the second heavily doped region. After the tops of the first heavily doped region and the second heavily doped region are connected, the source of the MOS device unit is formed. The top of the body region on the right side of the second heavily doped region forms the gate of the MOS device unit. The top of the third heavily doped region forms the drain of the MOS device unit. The doped layer and the drift layer are lightly doped, and the first heavily doped region, the second heavily doped region, the third heavily doped region, and the body region are heavily doped. The doping polarity of the doping layer, the body region and the first heavily doped region is the same. The doping polarity of the drift layer, the second heavily doped region and the third heavily doped region is the same. The doping polarity of the doping layer and the drift layer is opposite. When the MOS device unit is a P-type MOS device unit, the doping layer is N - Lightly doped, the first heavily doped region and the body region are N + Heavily doped, drift layer is P - Lightly doped, the second and third heavily doped regions are P + When the MOS device unit is an N-type MOS device unit, the doping layer is P - Lightly doped, the first heavily doped region and the body region are P + Heavily doped, drift layer is N - Lightly doped, the second and third heavily doped regions are N + Heavily doped.

[0032] All the above-mentioned MOS device units are stacked in sequence from bottom to top. When stacking, in every two adjacent stacked MOS device units, the doping layer of the MOS device unit located in the relatively upper layer overlaps with the drift layer of the MOS device unit located in the relatively lower layer, and the total width of the MOS device unit located in the relatively upper layer is less than or equal to the width between the body region and the third heavily doped region of the MOS device unit located in the relatively lower layer, that is, the body region, the first heavily doped region, the second heavily doped region and the third heavily doped region of the MOS device unit in the relatively lower layer are not covered by the MOS device unit located in the relatively upper layer. After all the MOS device units are stacked, the doping layer of the MOS device unit located in the lowest layer forms the substrate of the LDMOS power device and is connected to the ground during the later packaging. The source electrodes of all the MOS device units are connected together by wires and form the source electrode of the LDMOS power device during the later packaging. The gate electrodes of all the MOS device units are connected together by wires and form the gate electrode of the LDMOS power device during the later packaging. The drain electrodes of all the MOS device units are connected together by wires and form the drain electrode of the LDMOS power device during the later packaging.

[0033] Before packaging, the present invention utilizes more than two MOS device units for stacking, and the double drift layer formed by the stacking can add a new current path, thereby increasing the operating current in the on state. In addition, by assisting depletion through the doping layer between the double drift layers, the doping concentration of the double drift region can be effectively increased, the specific on-resistance can be reduced, and the operating current can be further increased.

[0034] In order to further improve the withstand voltage characteristics of the present invention, in the present LDMOS power device, an overlapping floating layer is additionally provided at the overlap of two adjacent stacked MOS device units, that is, at the overlap of the doping layer of the MOS device unit located at the relatively upper layer and the drift layer of the MOS device unit located at the relatively lower layer. The overlapping floating layer can be selectively arranged between any one or more groups of adjacent MOS device units in the present LDMOS power device as needed. The overlapping floating layer extends laterally at the overlap of two adjacent stacked MOS device units, and can be arranged only on the left side of the overlap of two adjacent stacked MOS device units, or on the right side of the overlap of two adjacent stacked MOS device units, or can be arranged simultaneously on the left and right sides of the overlap of two adjacent stacked MOS device units. In the preferred embodiment of the present invention, the overlapping floating layer is simultaneously arranged on the left and right sides of the overlap of two adjacent stacked MOS device units. The overlapping floating layer is heavily doped. The doping polarity of the overlapping floating layer located on the left side of the overlap is opposite to the doping polarity of the overlapping floating layer located on the right side of the overlap, wherein the polarity of the overlapping floating layer located on the left side of the overlap is the same as the doping polarity of the doped layer, and the polarity of the overlapping floating layer located on the right side of the overlap is opposite to the doping polarity of the doped layer. The present invention introduces two new electric field peaks inside the device by introducing overlapping floating layers of P heavily doped regions and N heavily doped regions, optimizes the internal electric field strength of the device, improves the electric field distribution inside the device, thereby improving the withstand voltage characteristics (lateral withstand voltage characteristics and longitudinal withstand voltage characteristics) of the device and improving the device performance.

[0035] In order to further enhance the lateral withstand voltage characteristics of the present invention, a unit buried layer is added between the doping layer and the drift layer of at least one MOS device unit of the LDMOS power device. The unit buried layer extends laterally between the doping layer and the drift layer, and is located on the left side of the MOS device unit. The unit buried layer is heavily doped. The unit buried layer is connected to the body region, and the doping polarity of the unit buried layer is the same as the doping polarity of the body region. The unit buried layer can be arranged in any one or more MOS device units of the present LDMOS power device. The present invention introduces a new electric field peak on the surface of the device by introducing a heavily doped unit buried layer, thereby optimizing the surface electric field strength of the device.

[0036] In order to further improve the longitudinal withstand voltage performance of the present invention, a laterally extending intra-unit floating layer is provided in the doping layer of at least one MOS device unit of the LDMOS power device. In the longitudinal direction, the intra-unit floating layer is located in the middle of the doping layer, and it can be located in the lower middle part, the upper middle part, the right side, the left side of the doping layer, or extends from the right side of the doping layer to the left side of the doping layer. In a preferred embodiment of the present invention, the intra-unit floating layer is located in the middle of the right side of the doping layer. The intra-unit floating layer is heavily doped. The doping polarity of the intra-unit floating layer is the same as that of the doping layer, and the doping concentration of the intra-unit floating layer is greater than the doping concentration of the doping layer. The present invention optimizes the longitudinal potential distribution and improves the longitudinal withstand voltage characteristics of the device by introducing the intra-unit floating layer.

[0037] The present invention will be further described below by means of 4 specific embodiments:

[0038] Embodiment 1:

[0039] A two-layer stacked LDMOS power device, such as Figure 1 As shown, the power device includes P arranged in sequence from bottom to top. - The lightly doped semiconductor substrate 1 (the doping layer of the lower MOS device unit) and N - The lightly doped drift region 2 (the drift layer of the lower MOS device unit) - A P-body region 11 (body region of the lower MOS device unit) is disposed at the upper left portion of the lightly doped drift region 2. + The heavily doped region 9 (the first heavily doped region of the lower MOS device unit) and N + The heavily doped region 10 (the second heavily doped region of the lower MOS device unit) is provided with a portion of P-body region 11 on the right side. + Floating layer 7 (overlapping floating layer), the N - The upper right part of the lightly doped drift region 2 is provided with N + The heavily doped region 12 (the third heavily doped region of the lower MOS device unit) is + The left part of the heavily doped region 12 is provided with a portion of N + Floating layer 8 (overlapping floating layer), the N - The upper part of the lightly doped drift region 2 is provided with a P - The lightly doped region 3 (the doping layer of the upper MOS device unit) is - The lightly doped region 3 is provided with a portion of P + Floating layer 6 (floating layer in the unit), the P - The upper portion of the lightly doped region 3 is provided with N - The lightly doped drift region 4 (the drift layer of the upper MOS device unit) is -A P buried layer 5 (buried layer in the unit) is disposed at the upper left portion of the lightly doped region 3, a P-body region 15 (body region of the upper MOS device unit) is disposed on the upper portion of the P buried layer 5, and a P + The heavily doped region 13 (the first heavily doped region of the upper MOS device unit) and N + The heavily doped region 14 (the second heavily doped region of the upper MOS device unit) has N - The upper right portion of the lightly doped drift region 4 is provided with N + The heavily doped region 16 (the third heavily doped region of the upper MOS device unit).

[0040] When the power device is working in the blocking state, by adding the P buried layer 5, part of the P + Floating layer 7 and part N + The floating layer 8 introduces new electric field peaks to the surface and inside of the device, effectively improving the surface lateral electric field strength and the electric field strength inside the device, optimizing the electric field distribution, and at the same time - Part of P is introduced into the lightly doped region 3 + The floating layer 6 improves the potential distribution in the longitudinal direction of the device and improves the withstand voltage characteristics of the device. - Lightly doped drift region 2 and N - The lightly doped drift region 4 increases the current path and at the same time - Part of P is introduced into the lightly doped region 3 + Floating layer 6 enhanced P - Lightly doped region 3 to N - Lightly doped drift region 2 and N - The auxiliary depletion effect of the lightly doped drift region 4 increases the N - Lightly doped drift region 2 and N - The doping concentration of the lightly doped drift region 4 can effectively increase the operating current when the device is turned on.

[0041] Under the same size and optimized parameters, the breakdown characteristic curve of the new LDMOS power device with multi-layer stacking technology (taking a two-layer stacking structure as an example) is as follows: Figure 2 As shown in FIG. 1 , the reverse breakdown voltage of the structure is about 350V, which is 40% better than the 250V of the conventional LDMOS structure and 16% better than the 300V of the conventional LDMOS with buried layer structure. The working current of the structure when it is turned on (taking the two-layer stacked structure as an example) is shown in FIG. Figure 3 As shown, its operating current is 4.9×10 -5 A, compared to 2.15×10 of the conventional LDMOS structure -5 A is increased by about 2.3 times, compared with 2.4×10 -5A is increased by about two times. This shows that the effect achieved by this structure is quite obvious.

[0042] Embodiment 2:

[0043] Another two-layer stacked LDMOS power device, such as Figure 4 As shown, the power device includes P arranged in sequence from bottom to top. - The lightly doped semiconductor substrate 1 (the doping layer of the lower MOS device unit) and N - The lightly doped drift region 2 (the drift layer of the lower MOS device unit) - A P-body region 6 (body region of the lower MOS device unit) is disposed at the upper left portion of the lightly doped drift region 2. + The heavily doped region 7 (the first heavily doped region of the lower MOS device unit) and N + The heavily doped region 8 (the second heavily doped region of the lower MOS device unit) is - The upper right part of the lightly doped drift region 2 is provided with N + The heavily doped region 9 (the third heavily doped region of the lower MOS device unit) is - The upper part of the lightly doped drift region 2 is provided with a P - The lightly doped region 3 (the doping layer of the upper MOS device unit) is - The upper portion of the lightly doped region 3 is provided with N - The lightly doped drift region 4 (the drift layer of the upper MOS device unit) is - A P buried layer 5 (buried layer in the unit) is disposed at the upper left portion of the lightly doped region 3, a P-body region 10 (body region of the upper MOS device unit) is disposed on the upper portion of the P buried layer 5, and a P + The heavily doped region 11 (the first heavily doped region of the upper MOS device unit) and N + The heavily doped region 12 (the second heavily doped region of the upper MOS device unit) is - The upper right portion of the lightly doped drift region 4 is provided with N + Heavily doped region 13 (the third heavily doped region of the upper MOS device unit).

[0044] Embodiment 3:

[0045] A three-layer stacked LDMOS power device, such as Figure 5 As shown, the power device includes P arranged in sequence from bottom to top. - The lightly doped semiconductor substrate 1 (the doping layer of the lower MOS device unit) and N - The lightly doped drift region 2 (the drift layer of the lower MOS device unit) -A P-body region 13 (body region of the lower MOS device unit) is disposed at the upper left portion of the lightly doped drift region 2. + The heavily doped region 14 (the first heavily doped region of the lower MOS device unit) and N + The heavily doped region 15 (the second heavily doped region of the lower MOS device unit) is provided with a portion of P-body region 13 on the right side. + Floating layer 11 (overlapping floating layer), the N - The upper right part of the lightly doped drift region 2 is provided with N + The heavily doped region 16 (the third heavily doped region of the lower MOS device unit) is + A portion of the N floating layer 12 (overlapping floating layer) is disposed on the left side of the heavily doped region 16. - The upper part of the lightly doped drift region 2 is provided with a P - The lightly doped region 3 (the doped layer of the middle MOS device unit) - The lightly doped region 3 is provided with a portion of P + The floating layer 10 (floating layer in the unit), the P - The upper portion of the lightly doped region 3 is provided with N - The lightly doped drift region 4 (the drift layer of the middle MOS device unit) - A P buried layer 9 (buried layer in the unit) is disposed at the upper left portion of the lightly doped region 3, a P-body region 17 (body region of the middle-layer MOS device unit) is disposed on the upper portion of the P buried layer 9, and a P + The heavily doped region 18 (the first heavily doped region of the middle MOS device unit) and N + The heavily doped region 19 (the second heavily doped region of the middle MOS device unit) is - The upper right portion of the lightly doped drift region 4 is provided with N + The heavily doped region 20 (the third heavily doped region of the middle MOS device unit) is - The upper part of the lightly doped drift region 4 is provided with a P - The lightly doped region 5 (the doped layer of the upper MOS device unit) is - The lightly doped region 5 is provided with a portion of P + Floating layer 8 (floating layer in the unit), the P - The upper portion of the lightly doped region 5 is provided with N - The lightly doped drift region 6 (the drift layer of the upper MOS device unit) is - A P buried layer 7 (buried layer in the unit) is disposed at the upper left portion of the lightly doped region 5, a P-body region 21 (body region of the upper MOS device unit) is disposed on the upper portion of the P buried layer 7, and a P +The heavily doped region 22 (the first heavily doped region of the lower MOS device unit) and N + The heavily doped region 23 (the second heavily doped region of the lower MOS device unit) has N - The upper right part of the lightly doped drift region 6 is provided with N + The heavily doped region 24 (the third heavily doped region of the lower MOS device unit).

[0046] Embodiment 4:

[0047] Another three-layer stacked LDMOS power device, such as Figure 6 As shown, the power device includes P arranged in sequence from bottom to top. - The lightly doped semiconductor substrate 1 (the doping layer of the lower MOS device unit) and N - The lightly doped drift region 2 (the drift layer of the lower MOS device unit) - A P-body region 11 (body region of the lower MOS device unit) is disposed at the upper left portion of the lightly doped drift region 2. + The heavily doped region 12 (the first heavily doped region of the lower MOS device unit) and N + The heavily doped region 13 (the second heavily doped region of the lower MOS device unit) is - The upper right part of the lightly doped drift region 2 is provided with N + The heavily doped region 14 (the third heavily doped region of the lower MOS device unit) - The upper part of the lightly doped drift region 2 is provided with a P - The lightly doped region 3 (the doped layer of the middle MOS device unit) - The lightly doped region 3 is provided with a portion of P + The floating layer 10 (floating layer in the unit), the P - The upper portion of the lightly doped region 3 is provided with N - The lightly doped drift region 4 (the drift layer of the middle MOS device unit) - A P buried layer 9 (buried layer in the unit) is disposed at the upper left portion of the lightly doped region 3, a P-body region 15 (body region of the middle-layer MOS device unit) is disposed on the upper portion of the P buried layer 9, and a P + The heavily doped region 16 (the first heavily doped region of the middle MOS device unit) and N + The heavily doped region 17 (the second heavily doped region of the middle MOS device unit) is - The upper right portion of the lightly doped drift region 4 is provided with N + The heavily doped region 18 (the third heavily doped region of the middle MOS device unit) is - The upper part of the lightly doped drift region 4 is provided with a P -The lightly doped region 5 (the doped layer of the upper MOS device unit) is - The lightly doped region 5 is provided with a portion of P + Floating layer 8 (floating layer in the unit), the P - The upper portion of the lightly doped region 5 is provided with N - The lightly doped drift region 6 (the drift layer of the upper MOS device unit) is - A P buried layer 7 (buried layer in the unit) is disposed at the upper left portion of the lightly doped region 5, a P-body region 19 (body region of the upper MOS device unit) is disposed on the upper portion of the P buried layer 7, and a P + The heavily doped region 20 (the first heavily doped region of the lower MOS device unit) and N + The heavily doped region 21 (the second heavily doped region of the lower MOS device unit) is - The upper right part of the lightly doped drift region 6 is provided with N + The heavily doped region 22 (the third heavily doped region of the lower MOS device unit).

[0048] It should be noted that although the embodiments of the present invention described above are illustrative, this is not a limitation of the present invention, and therefore the present invention is not limited to the above specific embodiments. For example, the device can be stacked not only in two or three layers, but also in multiple layers, as long as the substrate layer, drift region, and source, gate, and drain electrodes of the device to be stacked can be accommodated on top of the stacked device. Another example is adding some buried layers and other voltage-resistant structures to the inside of the device. Without departing from the principles of the present invention, any other implementations obtained by those skilled in the art under the enlightenment of the present invention are deemed to be within the protection of the present invention.

Claims

1. A multi-layer stacked LDMOS power device, characterized in that: Includes more than 2 MOS device units; Each MOS device unit is composed of a doped layer, a drift layer, a body region, a first heavily doped region, a second heavily doped region, and a third heavily doped region; the drift layer is located directly above the doped layer; The first heavily doped region, the second heavily doped region and the third heavily doped region are distributed on the top of the drift layer from left to right, wherein the first heavily doped region is located on the leftmost side of the top of the drift layer, the second heavily doped region is adjacent to the first heavily doped region, and the third heavily doped region is located on the rightmost side of the top of the drift layer; the body region is located on the upper left side of the drift layer, and the first heavily doped region and the second heavily doped region are both within the body region; the doping polarity of the doping layer, the body region and the first heavily doped region is the same; The drift layer, the second heavily doped region and the third heavily doped region have the same doping polarity; the doping layer and the drift layer have opposite doping polarities; the tops of the first heavily doped region and the second heavily doped region are connected to form a source of the MOS device unit; The top of the body region on the right side of the second heavily doped region forms the gate of the MOS device unit; The top of the third heavily doped region forms the drain of the MOS device unit; A heavily doped unit buried layer is added between the doping layer and the drift layer of at least one MOS device unit, the unit buried layer is located on the left side of the MOS device unit, and the doping polarity of the unit buried layer is the same as the doping polarity of the body region; A heavily doped floating layer extending laterally is added to the doping layer of at least one MOS device unit, the doping polarity of the floating layer in the unit is the same as the doping polarity of the doping layer, and the doping concentration of the floating layer in the unit is greater than the doping concentration of the doping layer; All MOS device units are stacked in sequence from bottom to top; in every two adjacent stacked MOS device units, the doping layer of the MOS device unit located at a relatively upper layer overlaps with the drift layer of the MOS device unit located at a relatively lower layer, and the total width of the MOS device unit located at a relatively upper layer is less than or equal to the width between the body region and the third heavily doped region of the MOS device unit located at a relatively lower layer; A heavily doped overlapping floating layer is added at the overlap of two adjacent stacked MOS device units, the overlapping floating layer is located on the left and / or right side of the overlap, and the doping polarity of the overlapping floating layer located on the left side of the overlap is opposite to the doping polarity of the overlapping floating layer located on the right side of the overlap; After all MOS device units are stacked, the doped layer of the MOS device unit located at the bottom layer forms the substrate of the LDMOS power device; the source electrodes of all MOS device units are connected together through wires to form the source electrode of the LDMOS power device; The gates of all MOS device units are connected together through a wire to form the gate of the LDMOS power device; the drains of all MOS device units are connected together through a wire to form the drain of the LDMOS power device.

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