Thin film transistor, display panel and method for manufacturing the same

Abstract

The embodiment of the present application discloses a thin film transistor, a display panel and a method for manufacturing the same, wherein the thin film transistor comprises: a gate, a gate insulating layer, an active layer, a first electrode, an interlayer insulating layer and a second electrode; the first electrode is arranged on a side of the active layer away from the gate; the interlayer insulating layer is arranged between the first electrode and the active layer, a first via hole penetrating the interlayer insulating layer and extending to the surface of the first electrode is provided on the interlayer insulating layer, the active layer is connected to the first electrode through the first via hole, the thickness of the interlayer insulating layer is greater than the thickness of the gate insulating layer; the second electrode is connected to the active layer. The present application realizes that the thickness of the gate insulating layer and the thickness of the interlayer insulating layer can be adjusted independently, and the withstand voltage characteristics between the gate and the first electrode are increased and the capacitance between the gate and the first electrode is reduced by increasing the thickness of the interlayer insulating layer while thinning the thickness of the gate insulating layer, thereby improving the comprehensive electrical performance of the thin film transistor.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a thin film transistor, a display panel and a method for preparing the same. Background Art

[0002] In existing back channel etched (BCE) thin film transistors, in order to improve the electrical performance, the Vgs voltage needs to be reduced as much as possible. This can be achieved by thinning the thickness of the gate insulating layer. However, reducing the thickness of the gate insulating layer will not only cause the voltage resistance between the gate and the drain to decrease, but also increase the capacitance between the gate and the source and drain, affecting the comprehensive electrical performance of the thin film transistor. Summary of the invention

[0003] The embodiments of the present application provide a thin film transistor, a display panel and a method for manufacturing the same, which can effectively improve the comprehensive electrical performance of the thin film transistor.

[0004] An embodiment of the present application provides a thin film transistor, including: a gate; a gate insulating layer, arranged on one side of the gate; an active layer, arranged on a side of the gate insulating layer away from the gate, the active layer being arranged opposite to the gate; a first electrode, arranged on a side of the active layer away from the gate; an interlayer insulating layer, arranged between the first electrode and the active layer to insulate the first electrode and the active layer, a first via hole penetrating the interlayer insulating layer and extending to a surface of the first electrode is provided on the interlayer insulating layer, the active layer is connected to the first electrode through the first via hole, the thickness of the interlayer insulating layer is greater than the thickness of the gate insulating layer; and a second electrode, connected to the active layer, the second electrode and the active layer are located on the same layer.

[0005] Optionally, in some specific embodiments of the present application, the thin film transistor further includes: an auxiliary electrode, arranged opposite to the active layer, and the interlayer insulating layer is arranged between the auxiliary electrode and the active layer.

[0006] Optionally, in some specific embodiments of the present application, the first electrode and the auxiliary electrode are located in the same layer, and the active layer is connected to the first electrode through the first via hole.

[0007] Optionally, in some specific embodiments of the present application, the active layer includes a semiconductor part and a first electrode contact part, the conductivity of the first electrode contact part is less than the conductivity of the first electrode, and the conductivity of the first electrode contact part is greater than the conductivity of the semiconductor part; the first electrode contact part is connected to the first electrode through the first via.

[0008] An embodiment of the present application also provides a display panel, comprising: a first electrode, located on a first metal layer; an interlayer insulating layer, arranged on the first electrode, and a first via hole penetrating the interlayer insulating layer and extending to the surface of the first electrode is opened on the interlayer insulating layer; an active layer, arranged on the interlayer insulating layer, and the active layer is connected to the first electrode through the first via hole; a second electrode, connected to the active layer; a gate insulating layer, arranged on the active layer; and a gate, located on a second metal layer arranged on the gate insulating layer, and arranged opposite to the active layer; the thickness of the interlayer insulating layer is greater than the thickness of the gate insulating layer.

[0009] Optionally, in some specific embodiments of the present application, the display panel also includes: an auxiliary electrode, arranged opposite to the active layer, the interlayer insulating layer is arranged between the auxiliary electrode and the active layer; the first electrode is a drain, and the second electrode is a source; and / or the first electrode is a source, and the second electrode is a drain.

[0010] Optionally, in some specific embodiments of the present application, the auxiliary electrode is located in the first metal layer, and the interlayer insulating layer covers the first electrode and the auxiliary electrode.

[0011] Optionally, in some specific embodiments of the present application, the active layer includes a semiconductor part and a first electrode contact part, the conductivity of the first electrode contact part is less than the conductivity of the first electrode, and the conductivity of the first electrode contact part is greater than the conductivity of the semiconductor part; the first electrode contact part is connected to the first electrode through the first via.

[0012] Optionally, in some specific embodiments of the present application, a pixel electrode is further included, wherein the pixel electrode is arranged in the same layer as the active layer, the pixel electrode is electrically connected to the active layer, and the active layer includes a metal oxide semiconductor.

[0013] Optionally, in some specific embodiments of the present application, the display panel also includes: a substrate, the first metal layer is arranged on the substrate, and the first metal layer also includes a data line; a scan line, located in the second metal layer, the scan line intersects with the data line to define a plurality of sub-pixel units, the gate, the second electrode, the first electrode, the thin film transistor composed of the active layer, and the pixel electrode connected to the thin film transistor are all located in the sub-pixel unit; a passivation layer, arranged on the second metal layer, covering the gate and the pixel electrode; a common electrode, arranged on the passivation layer, and the common electrode is arranged opposite to the pixel electrode.

[0014] Optionally, in some specific embodiments of the present application, side edges of the gate, the gate insulating layer, and the semiconductor portion of the active layer are flush.

[0015] Optionally, in some specific embodiments of the present application, the thickness of the interlayer insulating layer is greater than or equal to twice the thickness of the gate insulating layer.

[0016] Optionally, in some specific embodiments of the present application, the first metal layer also includes a touch signal line; the display panel also includes: a first touch electrode, the first touch electrode is arranged in the same layer as the active layer, and the first touch electrode is connected to the active layer; and a second touch electrode, the second touch electrode is insulated from the first touch electrode and is arranged opposite to each other.

[0017] The present application also provides a method for preparing a display panel, including:

[0018] B1. Provide a substrate;

[0019] B2. forming a first metal layer on the substrate, and patterning the first metal layer to form a first electrode;

[0020] B3, disposing an interlayer insulating layer on the first metal layer, and patterning the interlayer insulating layer to form a first via hole;

[0021] B4, providing a patterned active layer on the interlayer insulating layer, wherein the active layer is connected to the first electrode through the first via hole, and the active layer includes a metal oxide semiconductor;

[0022] B5. Form a gate insulating layer and a second metal layer on the active layer, wherein the thickness of the interlayer insulating layer is greater than or equal to twice the thickness of the gate insulating layer; pattern the second metal layer to form a gate, so that the gate is arranged opposite to the active layer; use the patterned gate as a mask to pattern the gate insulating layer to expose the active layer located above the first electrode; use the patterned gate as a mask to metallize the exposed active layer to form a second electrode connected to the active layer and a first electrode contact portion, and the first electrode contact portion is connected to the first electrode through the first via.

[0023] The beneficial effects of the present application are as follows: the first electrode and the gate of the thin film transistor are arranged on both sides of the active layer, and the gate insulating layer between the gate and the active layer and the interlayer insulating layer between the first electrode and the active layer are independently arranged, so that the thickness of the gate insulating layer between the gate and the active layer and the thickness of the interlayer insulating layer between the first electrode and the active layer can be adjusted independently, and the withstand voltage characteristics between the gate and the drain (first electrode) can be increased by increasing the thickness of the interlayer insulating layer while thinning the thickness of the gate insulating layer to reduce Vgs, and the increase in the thickness of the interlayer insulating layer can also reduce the capacitance between the gate and the drain (first electrode), which can significantly improve the various electrical properties of the thin film transistor.

[0024] In addition, in the method for manufacturing the display panel of the present application, the patterning of the gate insulation layer and the metallization treatment of the active layer are completed through a gate self-alignment process, which reduces two photomasks and reduces production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 is a cross-sectional schematic diagram of a specific embodiment of a thin film transistor provided by the present application;

[0027] Figure 2 is a cross-sectional schematic diagram of a display area of ​​a display panel in a first embodiment provided by the present application;

[0028] Figure 3 is a cross-sectional schematic diagram of a display area of ​​a display panel in a second embodiment provided by the present application;

[0029] FIG. 4A to FIG. 4G Shows Figure 2 Schematic diagram of the structure of the display panel during the preparation process. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0031] The present application provides a thin film transistor, comprising a gate, a gate insulating layer, an active layer, an auxiliary electrode, an interlayer insulating layer, a first electrode and a second electrode. The gate insulating layer is arranged on one side of the gate. The active layer is arranged on the side of the gate insulating layer away from the gate. The active layer is arranged opposite to the gate. The auxiliary electrode is arranged opposite to the active layer. The interlayer insulating layer is arranged between the auxiliary electrode and the active layer to insulate the auxiliary electrode from the active layer. The thickness of the interlayer insulating layer is greater than the thickness of the gate insulating layer. The first electrode and the auxiliary electrode are located on the same layer. A first via hole penetrating the interlayer insulating layer and extending to the surface of the first electrode is provided on the interlayer insulating layer. The active layer is connected to the first electrode through the first via hole. The second electrode is connected to the active layer. The second electrode and the active layer are located on the same layer.

[0032] Specifically, Figure 1 As shown, the thin film transistor is arranged on a substrate 1 .

[0033] The substrate 1 is an array substrate. The substrate 1 is a rigid substrate. The rigid substrate 1 can be made of glass. It is understandable that the substrate 1 can also be a flexible substrate. The flexible substrate 1 can be made of organic insulating materials such as polyimide (PI) and / or polyethylene terephthalate (PET) that can isolate water vapor and oxygen, and is not specifically limited here.

[0034] The first metal layer 2 is disposed on the substrate 1. The first metal layer 2 forms a first electrode 21 and an auxiliary electrode 22 of a thin film transistor through a patterning process. The first metal layer 2 can be made of one or more of common conductive metals or alloys such as Mo, Al, Ti, and Cu. The first metal layer 2 can be a single-layer conductive layer structure composed of a single metal, or a multi-layer conductive layer structure composed of multiple metals, which is not specifically limited here. The first electrode 21 is a source electrode or a drain electrode. In this embodiment, the first electrode 21 is a drain electrode connected to a data line.

[0035] The interlayer insulating layer 3 is disposed on the first metal layer 2. The interlayer insulating layer 3 covers the first electrode 21 and the auxiliary electrode 22. The interlayer insulating layer 3 is provided with a first via hole 31 penetrating the interlayer insulating layer 3 and extending to the surface of the first electrode 21. The interlayer insulating layer 3 is generally formed by depositing or sputtering one or more common inorganic materials such as SiNx, SiOx, Al2O3, etc. that can isolate water vapor and oxygen. The interlayer insulating layer 3 can also be prepared by an organic insulating layer to obtain a flat surface.

[0036] The active layer 4 is disposed on the interlayer insulating layer 3. The active layer 4 can be made of common semiconductor materials such as metal oxide, amorphous silicon and polycrystalline silicon. The middle region of the active layer 4 is disposed corresponding to the auxiliary electrode 22. The active layer 4 includes a semiconductor portion 41 and a first electrode contact portion 42. The conductivity of the first electrode contact portion 42 is less than the conductivity of the first electrode 21. The conductivity of the first electrode contact portion 42 is greater than the conductivity of the semiconductor portion 41. The first electrode contact portion 42 is connected to the first electrode 21 through the first via 31.

[0037] The second electrode 5 is connected to the active layer 4. The second electrode 5 is connected to the semiconductor portion 41. The second electrode 5 is a drain or a source. In this embodiment, the second electrode 5 is a source connected to a pixel electrode or other circuits. The second electrode 5 and the active layer 4 are located in the same layer. The second electrode 5 and the first electrode contact portion 42 are respectively arranged on both sides of the semiconductor portion 41.

[0038] The gate insulating layer 6 is disposed on the active layer 4. The gate insulating layer 6 covers the semiconductor portion 41. The gate insulating layer 6 is generally formed by depositing or sputtering one or more common inorganic materials such as SiNx, SiOx, Al2O3, etc. that can isolate water vapor and oxygen. Under normal circumstances, a single-layer insulating layer can meet the yield requirements of the display panel, but in a display panel using polysilicon or metal oxide as an active layer, in order to improve the yield, a structure in which multiple insulating layers are overlapped is also used to ensure effective isolation of water vapor and oxygen. In this embodiment, the gate insulating layer 6 is a single-layer SiO2 or single-layer SiNx structure.

[0039] The gate 71 is disposed on the gate insulating layer 6. The gate 71 is disposed opposite to the semiconductor portion 41. The gate 71 can be made of one or more of common conductive metals or alloys such as Mo, Al, Ti, and Cu. The gate 71 can be a single-layer conductive layer structure composed of a single metal, or a multi-layer conductive layer structure composed of multiple metals, which is not specifically limited here.

[0040] The auxiliary electrode 22 is an auxiliary gate and / or a light-shielding electrode. The auxiliary electrode 22 is arranged opposite to the semiconductor portion 41. When the auxiliary electrode 22 is used as an auxiliary gate, the auxiliary electrode 22 can be made of a conductive material such as metal or ITO. The auxiliary electrode 22 and the semiconductor portion 41 can effectively improve the electrical performance of the thin film transistor. When the auxiliary electrode 22 is made of metal or other opaque materials, it can be used as a light-shielding electrode. The auxiliary electrode 22 and the semiconductor portion 41 can prevent light from irradiating the semiconductor portion 41 and affecting the electrical performance of the thin film transistor.

[0041] The thin film transistor provided in this embodiment arranges the first electrode 21 and the gate 71 on both sides of the active layer 4, the first electrode 21 and the active layer 4 are insulated by the interlayer insulating layer 3, and the gate 71 and the active layer 4 are insulated by the gate insulating layer 6. By independently arranging the insulating layer between the gate 71 and the active layer 4 and the insulating layer between the source and drain electrodes and the active layer 4, the thickness of the gate insulating layer 6 between the gate 71 and the active layer 4 and the thickness of the interlayer insulating layer 3 between the source and drain electrodes and the active layer 4 can be adjusted independently, which can avoid the prior art that when the gate and the source and drain electrodes are arranged on the same side of the active layer, the thickness of the gate insulating layer is thinned to reduce Vgs, while reducing other electrical properties of the thin film transistor.

[0042] The thickness of the interlayer insulating layer 3 is set to be greater than the thickness of the gate insulating layer 6. The thickness of the gate insulating layer 6 is thinned according to the Vgs target setting value of the thin film transistor. Since the thickness of the interlayer insulating layer 3 can be kept constant or increased at the same time, it can not only ensure that the withstand voltage characteristics between the gate 71 and the drain (first electrode 21) are not affected by the thinning of the gate insulating layer 6, but also reduce the capacitance between the gate 71 and the drain (first electrode 21) by appropriately increasing the thickness of the interlayer insulating layer 3. Through the above design, various electrical properties of the thin film transistor can be greatly improved.

[0043] Optionally, the thickness of the interlayer insulating layer 3 is greater than or equal to twice the thickness of the gate insulating layer 6. When the thickness of the gate insulating layer 6 is one third of the thickness of the interlayer insulating layer 3, the overall electrical performance of the thin film transistor is better.

[0044] Optionally, the side edges of the gate 71, the gate insulating layer 6 and the semiconductor portion 41 in the active layer 4 are flush. This structure can reduce the number of masks for the thin film transistor. Specifically, the active layer 4 includes a metal oxide semiconductor, such as IGZO or IGZTO. The gate insulating layer 6 is patterned using the patterned gate 71 as a mask to expose the active layer 4 located above the first electrode 21. The exposed active layer 4 is metallized using the patterned gate 71 as a mask to form a second electrode 5 and a first electrode contact portion 42 connected to the active layer 4. The first electrode contact portion 42 is connected to the first electrode 21 through the first via 31. The patterning of the gate insulating layer 6 and the metallization of the active layer 4 are completed by a self-alignment process of the gate 71, which reduces two masks and reduces production costs.

[0045] like Figure 2 As shown, the present application also provides a first embodiment of a display panel. The display panel includes a substrate 1 and a first metal layer 2, an interlayer insulating layer 3, an active layer 4, a second electrode 5, a gate insulating layer 6, a second metal layer 7, a pixel electrode 8, a passivation layer 9 and a common electrode layer 10 arranged on the substrate 1.

[0046] The substrate 1 is an array substrate. The substrate 1 is a rigid substrate. The rigid substrate 1 can be made of glass. It is understood that the substrate 1 can also be a flexible substrate. The flexible substrate 1 can be made of an organic insulating material such as polyimide and / or polyethylene terephthalate that can isolate water vapor and oxygen, which is not specifically limited here.

[0047] The first metal layer 2 is disposed on the substrate 1. The first metal layer 2 forms a data line (not shown in the figure), a first electrode 21 and an auxiliary electrode 22 of a thin film transistor, and a common electrode line 23 through a patterning process. The first metal layer 2 can be made of one or more of common conductive metals or alloys such as Mo, Al, Ti, and Cu. The first metal layer 2 can be a single-layer conductive layer structure composed of a single metal, or a multi-layer conductive layer structure composed of multiple metals, which is not specifically limited here. The first electrode 21 is a source electrode or a drain electrode. In this embodiment, the first electrode 21 is a drain electrode connected to the data line.

[0048] The auxiliary electrode 22 is an auxiliary gate and / or a light-shielding electrode. The auxiliary electrode 22 is arranged opposite to the semiconductor portion 41. When the auxiliary electrode 22 is used as an auxiliary gate, the auxiliary electrode 22 can be made of a conductive material such as metal or ITO. The auxiliary electrode 22 and the semiconductor portion 41 can effectively improve the electrical performance of the thin film transistor. When the auxiliary electrode 22 is made of metal or other opaque materials, it can be used as a light-shielding electrode. The auxiliary electrode 22 and the semiconductor portion 41 can prevent light from irradiating the semiconductor portion 41 and affecting the electrical performance of the thin film transistor.

[0049] The interlayer insulating layer 3 is arranged on the first metal layer 2. The interlayer insulating layer 3 covers the data line, the first electrode 21, the auxiliary electrode 22 and the common electrode line 23. The interlayer insulating layer 3 is provided with a first via hole 31 that penetrates the interlayer insulating layer 3 and extends to the surface of the first electrode 21. The interlayer insulating layer 3 is generally formed by deposition or sputtering of one or more common inorganic materials such as SiNx, SiOx, Al2O3, etc. that can isolate water vapor and oxygen. Normally, a single-layer insulating layer can meet the yield requirements of the display panel, but in a display panel using polysilicon or metal oxide as an active layer, in order to improve the yield, a structure in which multiple insulating layers are overlapped is also used to ensure effective isolation of water vapor and oxygen. In this embodiment, the interlayer insulating layer 3 is a single-layer SiO2 or single-layer SiNx structure.

[0050] The active layer 4 is arranged on the interlayer insulating layer 3. The active layer 4 can be made of common semiconductor materials such as metal oxide, amorphous silicon and polycrystalline silicon. In the present embodiment, the active layer 4 is made of metal oxide semiconductor. The middle area of ​​the active layer 4 is arranged corresponding to the auxiliary electrode 22. The active layer 4 includes a semiconductor portion 41 and a first electrode contact portion 42. The conductivity of the first electrode contact portion 42 is less than the conductivity of the first electrode 21. The conductivity of the first electrode contact portion 42 is greater than the conductivity of the semiconductor portion 41. The first electrode contact portion 42 is connected to the first electrode 21 through the first via 31.

[0051] The second electrode 5 is connected to the active layer 4. The second electrode 5 is connected to the semiconductor portion 41. The second electrode 5 is a drain or a source. The second electrode 5 and the active layer 4 are located in the same layer. The second electrode 5 and the first electrode contact portion 42 are respectively arranged on both sides of the semiconductor portion 41.

[0052] The gate insulating layer 6 is disposed on the active layer 4. The gate insulating layer 6 covers the semiconductor portion 41. The gate insulating layer 6 is generally formed by depositing or sputtering one or more common inorganic materials such as SiNx, SiOx, Al2O3, etc. that can isolate water vapor and oxygen. Under normal circumstances, a single-layer insulating layer can meet the yield requirements of the display panel, but in a display panel using polysilicon or metal oxide as an active layer, in order to improve the yield, a structure in which multiple insulating layers are overlapped is also used to ensure effective isolation of water vapor and oxygen. In this embodiment, the gate insulating layer 6 is a single-layer SiO2 or single-layer SiNx structure.

[0053] The second metal layer 7 is disposed on the gate insulating layer 6. The second metal layer 7 forms a gate 71 and a scan line (not shown) of the thin film transistor through a patterning process. The gate 71 is disposed opposite to the semiconductor portion 41. The second metal layer 7 can be made of one or more of common conductive metals or alloys such as Mo, Al, Ti, and Cu. The second metal layer 7 can be a single-layer conductive layer structure composed of a single metal, or a multi-layer conductive layer structure composed of multiple metals, which is not specifically limited here.

[0054] The pixel electrode 8 is disposed on the interlayer insulating layer 3. The pixel electrode 8 is disposed in the same layer as the active layer 4 and the second electrode 5. The pixel electrode 8 and the second electrode 5 are formed by metal doping the active layer 4. The pixel electrode 8 and the second electrode 5 are integrally formed. One end of the second electrode 5 is connected to the semiconductor portion 41. The other end of the second electrode 5 is connected to the pixel electrode 8. The pixel electrode 8 and the second electrode 5 are both obtained by metal doping the oxide semiconductor layer. In some specific embodiments, the second electrode 5 may be omitted or may be regarded as a part of the pixel electrode 8, which is specifically determined according to the pattern of the pixel electrode 8.

[0055] The passivation layer 9 is arranged on the second metal layer 7. The passivation layer 9 covers the gate 71, the scanning line, the first electrode contact portion 42, the second electrode 5 and the pixel electrode 8. The passivation layer 9 is provided with a second via hole 91 that penetrates the passivation layer 9 and the interlayer insulating layer 3 and extends to the surface of the common electrode line 23. The passivation layer 9 is generally formed by deposition or sputtering of one or more common inorganic materials such as SiNx, SiOx, Al2O3, etc. that can isolate water vapor and oxygen. Normally, a single-layer insulating layer can meet the yield requirements of the display panel, but in a display panel using polysilicon or metal oxide as the active layer, in order to improve the yield, a structure in which multiple insulating layers are overlapped is also used to ensure effective isolation of water vapor and oxygen.

[0056] The common electrode 10 is arranged on the passivation layer 9. The common electrode 10 can be made of transparent ITO material. The common electrode 10 is connected to the common electrode line 23 through the second via 91. The display panel in this embodiment is an FFS display panel, which is stacked up and down by the planar pixel electrode 8 and the patterned common electrode 10 to generate a horizontal edge electric field to drive the liquid crystal deflection. In order to ensure the display quality, it is necessary to set the interlayer insulating layer 3 under the pixel electrode 8 as a flat layer of organic insulation to ensure that the pixel electrode 8 is formed on the same horizontal plane as much as possible. The common electrode 10 and the pixel electrode 8 are arranged relative to each other to generate a horizontal electric field to drive the liquid crystal. It can be understood that the common electrode 10 can be other patterns such as "rice" shape, comb shape, etc., which are not specifically limited here.

[0057] The first alignment layer (not shown in the figure) is disposed on the common electrode 10 to adjust the deflection angle of the liquid crystal.

[0058] The display panel further includes a substrate 11 and a color filter layer 12 , a light shielding layer 13 and a second alignment layer (not shown in the figure) arranged on the color filter substrate 11 .

[0059] The substrate 11 is arranged opposite to the base plate 1. The material of the substrate 11 is the same as that of the base plate 1, and will not be described in detail here.

[0060] The color filter layer 12 includes a plurality of color filters 121. A color filter 121 is disposed in each sub-pixel region. The color filter 121 is disposed opposite to the pixel electrode 8.

[0061] The light shielding layer 13 is disposed between two adjacent filters 121 to prevent color mixing. The light shielding layer 13 is generally made of black resin material.

[0062] The second alignment layer covers the color filter layer 12 and the light shielding layer 13 to adjust the deflection angle of the liquid crystal.

[0063] The display panel further includes a liquid crystal layer (not shown in the figure) and a spacer (not shown in the figure) disposed between the substrate 1 and the underlay 11 .

[0064] The display area of ​​the display panel is provided with a plurality of scan lines extending along a first direction and a plurality of data lines extending substantially along a second direction. The scan lines and the data lines intersect to define a plurality of sub-pixel areas arranged in an array. The gate 71, the second electrode 5, the first electrode 21, the thin film transistor composed of the active layer 4 and the pixel electrode 8 connected to the thin film transistor are all located in the sub-pixel unit.

[0065] The auxiliary electrode 22 is an auxiliary gate and / or a light-shielding electrode. The auxiliary electrode 22 is arranged opposite to the semiconductor portion 41. When the auxiliary electrode 22 is used as an auxiliary gate, the auxiliary electrode 22 can be made of a conductive material such as metal or ITO. The auxiliary electrode 22 and the semiconductor portion 41 can effectively improve the electrical performance of the thin film transistor. When the auxiliary electrode 22 is made of metal or other opaque materials, it can be used as a light-shielding electrode. The auxiliary electrode 22 and the semiconductor portion 41 can prevent light from irradiating the semiconductor portion 41 and affecting the electrical performance of the thin film transistor.

[0066] In the display panel provided in this embodiment, the first electrode 21 and the gate 71 of the thin film transistor are arranged on both sides of the active layer 4, the first electrode 21 and the active layer 4 are insulated by the interlayer insulating layer 3, and the gate 71 and the active layer 4 are insulated by the gate insulating layer 6. By independently arranging the insulating layer between the gate 71 and the active layer 4 and the insulating layer between the source and drain electrodes and the active layer 4, the thickness of the gate insulating layer 6 between the gate 71 and the active layer 4 and the thickness of the interlayer insulating layer 3 between the source and drain electrodes and the active layer 4 can be adjusted independently, which can avoid the prior art that when the gate and the source and drain electrodes are arranged on the same side of the active layer, the thickness of the gate insulating layer is thinned to reduce Vgs, while reducing other electrical properties of the thin film transistor.

[0067] The thickness of the interlayer insulating layer 3 is set to be greater than the thickness of the gate insulating layer 6. The thickness of the gate insulating layer 6 is thinned according to the Vgs target setting value of the thin film transistor. Since the thickness of the interlayer insulating layer 3 can be kept constant or increased at the same time, it can not only ensure that the withstand voltage characteristics between the gate 71 and the drain (first electrode 21) are not affected by the thinning of the gate insulating layer 6, but also reduce the capacitance between the gate 71 and the drain (first electrode 21) by appropriately increasing the thickness of the interlayer insulating layer 3. Through the above design, various electrical properties of the thin film transistor can be greatly improved.

[0068] Optionally, the thickness of the interlayer insulating layer 3 is greater than or equal to twice the thickness of the gate insulating layer 6. When the thickness of the gate insulating layer 6 is one third of the thickness of the interlayer insulating layer 3, the overall electrical performance of the thin film transistor is better.

[0069] Optionally, the side edges of the gate 71, the gate insulating layer 6 and the semiconductor portion 41 in the active layer 4 are flush. This structure can reduce the number of masks for the thin film transistor. Specifically, the gate insulating layer 6 is patterned using the patterned gate 71 as a mask to expose the active layer 4 located above the first electrode 21. The exposed active layer 4 is metallized using the patterned gate 71 as a mask to form a second electrode 5 and a first electrode contact portion 42 connected to the active layer 4. The first electrode contact portion 42 is connected to the first electrode 21 through the first via 31. The patterning of the gate insulating layer 6 and the metallization of the active layer 4 are completed by the self-alignment process of the gate 71, which reduces two masks and reduces the production cost.

[0070] like Figure 3 As shown, the present application also provides a second embodiment of a display panel. The differences between this embodiment and the first embodiment include:

[0071] The first metal layer 2 further includes a touch signal line. The first metal layer 2 is patterned to form a first electrode 21, an auxiliary electrode 22, a common electrode line 23 and a touch signal line 24.

[0072] The passivation layer 9 is provided with a second via hole 91 penetrating the passivation layer 9 and the interlayer insulating layer 3 and extending to the surface of the common electrode line 23 , and a third via hole 92 penetrating the passivation layer 9 and the interlayer insulating layer 3 and extending to the surface of the touch signal line 24 .

[0073] When the display panel is a mutual capacitance touch structure, it also includes a first touch electrode 14 and a second touch electrode 15. The first touch electrode 14 is arranged in the same layer as the active layer 4. The first touch electrode 14 is connected to the active layer 4. The second touch electrode 15 is insulated from the first touch electrode 14 and arranged opposite to it. The second touch electrode 15 is located in the same layer as the common electrode 10. The second touch electrode 15 is connected to the touch signal line 24 through the third via 92.

[0074] When the display panel is a self-capacitive touch structure, it only includes a layer of second touch electrodes 15 located on the same layer as the common electrode. The second touch electrodes 15 are connected to the touch signal lines 24 through the third vias 92 .

[0075] The other structures of this embodiment are the same as those of the first embodiment and will not be described again here.

[0076] like FIG. 4A to FIG. 4G As shown, the present application also provides a specific embodiment of a method for preparing a display panel. The method for preparing a display panel includes:

[0077] B1. Provide a substrate 1.

[0078] B2, such as Figure 4AAs shown, a first metal layer 2 is formed on a substrate 1. The first metal layer 2 is patterned to form a first electrode 21.

[0079] Optionally, step B2 includes forming a first metal layer 2 on the substrate 1. The first metal layer 2 is patterned to form a first electrode 21, an auxiliary electrode 22, a common electrode line 23 and a data line (not shown in the figure).

[0080] B3, such as Figure 4B As shown, an interlayer insulating layer 3 is disposed on the first metal layer 2. The interlayer insulating layer 3 is patterned to form a first via hole 31. The first via hole 31 penetrates the interlayer insulating layer 3 and extends to the surface of the first electrode 21.

[0081] B4, such as Figure 4C As shown, a patterned active layer 4 is disposed on the interlayer insulating layer 3. The active layer 4 is connected to the first electrode 21 through a first via hole 31. The active layer 4 is an oxide semiconductor layer.

[0082] B5. Figure 4D As shown, a gate insulating layer 6 and a second metal layer 7 are formed on the active layer 4. The thickness of the interlayer insulating layer 3 is greater than or equal to twice the thickness of the gate insulating layer 6. The second metal layer 7 is patterned to form a gate 71 and a scan line (not shown in the figure), so that the gate 71 is arranged opposite to the active layer 4. Optionally, the gate 71 is arranged opposite to the auxiliary electrode 22.

[0083] The gate insulating layer 6 is patterned using the patterned gate 71 as a mask to expose the active layer 4 above the first electrode 21, so that the side edges of the gate 71 and the gate insulating layer 6 are flush. Using the gate 71 as a mask to pattern the gate insulating layer 6 can save one photomask.

[0084] The exposed active layer 4 is subjected to metallization doping treatment using the patterned gate 71 as a mask to form a pixel electrode 8, a second electrode 5 connected to the semiconductor portion 41, and a first electrode contact portion 42, so that the side edges of the gate 71, the gate insulating layer 6, and the semiconductor portion 41 are flush. The first electrode contact portion 42 is connected to the first electrode 21 through the first via hole 31.

[0085] The second electrode 5 is connected to the active layer 4. The second electrode 5 is connected to the semiconductor portion 41. The second electrode 5 is a drain or a source. The second electrode 5 and the semiconductor portion 41 are located in the same layer. The second electrode 5 and the first electrode contact portion 42 are respectively arranged on both sides of the semiconductor portion 41.

[0086] The second electrode 5 and the pixel electrode 8 have the same material. The pattern of the pixel electrode 8 is planar. The second electrode 5 and the pixel electrode 8 are integrally formed. Both the pixel electrode 8 and the second electrode 5 are obtained by metal doping the oxide semiconductor layer. In some specific embodiments, the second electrode 5 can be omitted or can be regarded as a part of the pixel electrode 8, which is specifically determined according to the pattern of the pixel electrode 8.

[0087] B6, such as Figure 4E As shown, a passivation layer 9 is formed on the second metal layer 7. The passivation layer 9 covers the gate 71, the scan line, the first electrode contact portion 42, the second electrode 5 and the pixel electrode 8. The passivation layer 9 is patterned to open a second via hole 91 on the passivation layer 9 that penetrates the passivation layer 9 and the interlayer insulating layer 3 and extends to the surface of the common electrode line 23.

[0088] B7, such as Figure 4F As shown, a common electrode layer is formed on the passivation layer 9. The common electrode layer is patterned to form a common electrode 10. The common electrode 10 can be made of a transparent ITO material. The common electrode 10 is a comb-shaped pattern. The planarly laid pixel electrode 8 and the patterned common electrode 10 are stacked up and down to generate a horizontal edge electric field to drive the liquid crystal to deflect. The common electrode 10 is connected to the common electrode line 23 through the second via hole 91.

[0089] B8, such as Figure 4G As shown, a color filter substrate 11 is placed above the common electrode 10 , and the liquid crystal is sealed between the common electrode 10 and the color filter 121 on the color filter substrate 11 .

[0090] The present application proposes to arrange the first electrode 21 and the gate 71 of the thin film transistor on both sides of the active layer 4, and to independently arrange the gate insulating layer 6 between the gate 71 and the active layer 4 and the interlayer insulating layer 3 between the first electrode 21 and the active layer 4, so that the thickness of the gate insulating layer 6 between the gate 71 and the active layer 4 and the thickness of the interlayer insulating layer 3 between the first electrode 21 and the active layer 4 can be adjusted independently, respectively, and while the thickness of the gate insulating layer 6 is thinned to reduce Vgs, the withstand voltage characteristics between the gate 71 and the drain (first electrode 21) can be increased by increasing the thickness of the interlayer insulating layer 3, and the increase in the thickness of the interlayer insulating layer 3 can also reduce the capacitance between the gate 71 and the drain (first electrode 21), which can significantly improve the various electrical properties of the thin film transistor.

[0091] In addition, in the method for manufacturing the display panel of the present application, the patterning of the gate insulating layer 6 and the metallization of the active layer 4 are completed by a gate 71 self-alignment process, thereby reducing two photomasks and lowering the production cost.

[0092] The above is a detailed introduction to a thin film transistor, a display panel and a preparation method thereof provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A thin film transistor, characterized in that: include: Gate; A gate insulating layer, disposed on one side of the gate; An active layer is arranged on a side of the gate insulating layer away from the gate, and the active layer is arranged opposite to the gate; A first electrode is arranged on a side of the active layer away from the gate; an interlayer insulating layer, arranged between the first electrode and the active layer to insulate the first electrode from the active layer, the interlayer insulating layer being provided with a first via hole penetrating the interlayer insulating layer and extending to a surface of the first electrode, the active layer being connected to the first electrode through the first via hole, and the thickness of the interlayer insulating layer being greater than or equal to twice the thickness of the gate insulating layer; as well as a second electrode connected to the active layer, wherein the second electrode and the active layer are located in the same layer; The thickness of the gate insulating layer is reduced to reduce the voltage difference between the gate and the second electrode in the thin film transistor.

2. The thin film transistor according to claim 1, characterized in that: Also includes: The auxiliary electrode is arranged opposite to the active layer, and the interlayer insulating layer is arranged between the auxiliary electrode and the active layer.

3. The thin film transistor according to claim 2, characterized in that: The first electrode and the auxiliary electrode are located in the same layer, and the active layer is connected to the first electrode through the first via hole.

4. The thin film transistor according to claim 1, characterized in that: The active layer includes a semiconductor portion and a first electrode contact portion, the conductivity of the first electrode contact portion is smaller than the conductivity of the first electrode, and the conductivity of the first electrode contact portion is greater than the conductivity of the semiconductor portion; The first electrode contact portion is connected to the first electrode through the first via hole.

5. A display panel comprising a thin film transistor, characterized in that: The thin film transistor comprises: A first electrode, located on the first metal layer; an interlayer insulating layer, disposed on the first electrode, wherein the interlayer insulating layer is provided with a first via hole penetrating the interlayer insulating layer and extending to a surface of the first electrode; an active layer, disposed on the interlayer insulating layer, wherein the active layer is connected to the first electrode through the first via hole; a second electrode connected to the active layer; a gate insulating layer, disposed on the active layer; and A gate, located on a second metal layer disposed on the gate insulating layer and disposed opposite to the active layer; The thickness of the interlayer insulating layer is greater than or equal to twice the thickness of the gate insulating layer; The thickness of the gate insulating layer is reduced to reduce the voltage difference between the gate and the second electrode in the thin film transistor.

6. The display panel according to claim 5, characterized in that: Also includes: an auxiliary electrode disposed opposite to the active layer, wherein the interlayer insulating layer is disposed between the auxiliary electrode and the active layer; The first electrode is a drain electrode, and the second electrode is a source electrode; And / or, the first electrode is a source electrode, and the second electrode is a drain electrode.

7. The display panel according to claim 6, characterized in that: The auxiliary electrode is located in the first metal layer, and the interlayer insulating layer covers the first electrode and the auxiliary electrode.

8. The display panel according to claim 5, characterized in that: The active layer includes a semiconductor portion and a first electrode contact portion, the conductivity of the first electrode contact portion is smaller than the conductivity of the first electrode, and the conductivity of the first electrode contact portion is greater than the conductivity of the semiconductor portion; The first electrode contact portion is connected to the first electrode through the first via hole.

9. The display panel according to claim 5, characterized in that: It also includes a pixel electrode, which is arranged in the same layer as the active layer, and is electrically connected to the active layer, and the active layer includes a metal oxide semiconductor.

10. The display panel according to claim 9, characterized in that: Also includes: A substrate, the first metal layer is disposed on the substrate, and the first metal layer further includes a data line; A scan line is located in the second metal layer, the scan line intersects the data line to define a plurality of sub-pixel units, the gate, the second electrode, the first electrode, a thin film transistor composed of the active layer, and the pixel electrode connected to the thin film transistor are all located in the sub-pixel unit; A passivation layer, disposed on the second metal layer, covering the gate and the pixel electrode; as well as The common electrode is disposed on the passivation layer, and the common electrode is disposed opposite to the pixel electrode.

11. The display panel according to any one of claims 5 to 10, characterized in that: Side edges of the gate, the gate insulating layer, and the semiconductor portion of the active layer are flush.

12. The display panel according to claim 5, characterized in that: The first metal layer further includes a touch signal line; and the display panel further includes: a first touch electrode, wherein the first touch electrode is disposed in the same layer as the active layer, and the first touch electrode is connected to the active layer; and The second touch control electrode is insulated from and arranged opposite to the first touch control electrode.

13. A method for preparing a display panel according to any one of claims 5 to 12, characterized in that: include: B1. Provide a substrate; B2. forming a first metal layer on the substrate, and patterning the first metal layer to form a first electrode; B3, disposing an interlayer insulating layer on the first metal layer, and patterning the interlayer insulating layer to form a first via hole; B4, providing a patterned active layer on the interlayer insulating layer, wherein the active layer is connected to the first electrode through the first via hole, and the active layer includes a metal oxide semiconductor; B5. forming a gate insulating layer and a second metal layer on the active layer, wherein the thickness of the interlayer insulating layer is greater than or equal to twice the thickness of the gate insulating layer; patterning the second metal layer to form a gate, so that the gate is arranged opposite to the active layer; Using the patterned gate as a mask to pattern the gate insulating layer to expose the active layer above the first electrode; The exposed active layer is metallized using the patterned gate as a mask to form a second electrode connected to the active layer and a first electrode contact portion, wherein the first electrode contact portion is connected to the first electrode through the first via hole.

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