Clock circuits, computing chips, computing boards, and data processing equipment

Abstract

This disclosure relates to clock circuits, computing chips, computing boards, and data processing devices. The clock circuit includes M series-connected clock drive circuits, where M is an integer not less than 2. Each stage of the M-stage clock drive circuit has N series-connected inverters between its input and output terminals, where N is an odd number not less than 3. This clock circuit can provide a high-performance clock signal.

Description

Technical Field

[0001] This disclosure relates to the field of electronic circuits, and more specifically to clock circuits and computing chips, computing boards and data processing devices that use the clock circuits. Background Technology

[0002] Many computing chips include pipelined architectures. A pipelined architecture can include cascaded (or series-connected) multi-stage pipelined circuits for performing data processing tasks. Typically, each stage of a multi-stage pipelined circuit requires a clock signal. Clocking circuits can be used to provide these required clock signals. Clocking circuits can include multiple stages of clock driver circuits. An initial clock signal provided by a clock source can propagate along these clock driver circuits stage by stage and be output to each stage of the pipelined circuit.

[0003] As computing chips become more complex, the number of pipeline stages also increases significantly. For example, a computing chip used to perform data processing tasks may have dozens or even hundreds of pipeline stages. In this case, it is desirable for the clock signal provided by the clock circuit to each stage of the pipeline to maintain a certain signal amplitude and duty cycle. At the same time, it is also desirable for such clock circuits to have a simple structure and low cost. Summary of the Invention

[0004] The embodiments disclosed herein are intended to provide and apply clock signals with good performance.

[0005] According to a first aspect of this disclosure, a clock circuit is provided, the clock circuit comprising M series-connected clock driving circuits, where M is an integer not less than 2, and N series-connected inverters are provided between the input and output terminals of each of the M series-connected clock driving circuits, where N is an odd number not less than 3.

[0006] According to this aspect of the disclosure, the output of each stage of the clock driving circuit in the M-stage clock driving circuit provides a clock signal to the corresponding stage of the pipeline circuit in the pipeline structure used to perform data processing tasks.

[0007] According to this aspect of the disclosure, a corresponding load balancing and phase adjustment module is provided between the output terminal of each stage of the clock driving circuit in the M-stage clock driving circuit and the clock signal input terminal of the corresponding stage of the pipeline circuit in the pipeline structure. The load balancing and phase adjustment module constitutes part of the output port capacitive load of the stage clock driving circuit and adjusts the phase of the clock signal output by the stage clock driving circuit.

[0008] According to this aspect of the disclosure, the load balancing and phase adjustment module has an inverter and a buffer, and the load balancing and phase adjustment module is configured according to one of the following two configuration modes: a first configuration mode, wherein the input terminal of the inverter and the input terminal of the buffer are both connected to the output terminal of the corresponding first-stage clock drive circuit, the output terminal of the inverter is connected to the clock signal input terminal of the corresponding first-stage pipeline circuit of the pipeline structure, and the output terminal of the buffer is unloaded; or a second configuration mode, wherein the input terminal of the inverter and the input terminal of the buffer are both connected to the output terminal of the corresponding first-stage clock drive circuit, the output terminal of the buffer is connected to the clock signal input terminal of the pipeline circuit of the pipeline structure, and the output terminal of the inverter is unloaded.

[0009] According to this aspect of the disclosure, the two load balancing and phase adjustment modules corresponding to two adjacent clock driving circuits in the M-level clock driving circuit each have a different configuration mode selected from the first configuration mode and the second configuration mode.

[0010] According to this aspect of the disclosure, the load balancing and phase adjustment modules corresponding to each stage of the clock drive circuit in the M-stage clock drive circuit have the same input port capacitance.

[0011] According to this aspect of the disclosure, the inverters in all load balancing and phase adjustment modules have the same input port capacitance, and the buffers in all load balancing and phase adjustment modules have the same input port capacitance.

[0012] According to this aspect of the disclosure, the Kth inverter in each of the N inverters in the M-stage clock drive circuit has the same input port capacitance, where 1≤K≤N.

[0013] According to this aspect of the disclosure, the N inverters in each stage of the clock drive circuit in the M-stage clock drive circuit are inverters of the same type.

[0014] According to this aspect of the disclosure, the output of the M-th stage clock drive circuit is connected to an additional load element, which has the same input port capacitance as the first inverter among the N inverters in each stage clock drive circuit.

[0015] According to this aspect of the disclosure, the input of the first-stage clock drive circuit in the M-stage clock drive circuit is connected to an external clock source to receive an initial clock signal.

[0016] According to this aspect of the disclosure, the initial clock signal is a square wave signal with a duty cycle of 50%.

[0017] According to this aspect of the disclosure, the data processing task includes performing the SHA-256 algorithm.

[0018] According to this aspect of the disclosure, the pipeline circuit includes at least one of a storage circuit and a computation circuit for performing the SHA-256 algorithm.

[0019] According to a second aspect of this disclosure, a computing chip is provided, the computing chip including a clock circuit as described in any of the preceding aspects.

[0020] According to a third aspect of this disclosure, a computing board is provided, including the computing chip as described in the preceding aspect.

[0021] According to a fourth aspect of this disclosure, a data processing device is provided, including a computing board as described in the preceding aspect.

[0022] According to various aspects of this disclosure, high-performance clock signals can be provided with simple circuit structures and low cost. Other features and advantages of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0023] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0024] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:

[0025] Figure 1 A schematic diagram of a clock circuit is shown.

[0026] Figures 2A-2C It shows the relationship with Figure 1 Exemplary waveforms of the various clock signals associated with the clock circuit.

[0027] Figure 3 A schematic diagram of a clock circuit according to an embodiment of the present disclosure is shown.

[0028] Figures 4A-4C It shows the relationship with Figure 3 Exemplary waveforms of the various clock signals associated with the clock circuit.

[0029] Figures 5A-5B Two exemplary configuration modes of the load balancing and phase adjustment module according to embodiments of the present disclosure are shown.

[0030] Figure 6 A schematic diagram of a pipeline structure that can be used to implement the SHA-256 algorithm is shown.

[0031] Figure 7 A schematic block diagram of a computing chip according to an embodiment of the present disclosure is shown.

[0032] Figure 8 A schematic block diagram of a computing board according to an embodiment of the present disclosure is shown.

[0033] Figure 9 A schematic block diagram of a data processing apparatus according to an embodiment of the present disclosure is shown.

[0034] Note that in the embodiments described below, the same reference numerals are sometimes used across different figures to denote the same parts or parts having the same function, and repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0035] For ease of understanding, the positions, dimensions, and extents of the structures shown in the accompanying drawings and other materials may not represent their actual positions, dimensions, and extents. Therefore, the disclosed content is not limited to the positions, dimensions, and extents disclosed in the accompanying drawings and other materials. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components. Detailed Implementation

[0036] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0037] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the scope of this disclosure or its application or use. That is, the circuits and methods for implementing hash algorithms herein are shown in an exemplary manner to illustrate different embodiments of the circuits or methods in this disclosure, and are not intended to be limiting. Those skilled in the art will understand that they merely illustrate exemplary ways that can be used to implement this disclosure, and not exhaustive ways.

[0038] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0039] Figure 1 A schematic diagram of a clock circuit 100 is shown. The clock circuit 100 is coupled to a clock source 200 and a pipeline structure 300. The clock circuit 100 is configured to receive an initial clock signal from the clock source 200 and to provide clock signals to the various stages of the pipeline circuits 310, 320, and 330 of the pipeline structure 300.

[0040] like Figure 1 As shown, the clock circuit 100 may include multiple stages of clock drive circuits 110, 120, and 130 connected in series. An initial clock signal provided by the clock source 200 can be provided to the first-stage clock drive circuit 110. The output clock signal of the first-stage clock drive circuit 110 can be provided to the second-stage clock drive circuit 120. The output clock signal of the second-stage clock drive circuit 120 can be provided to the third-stage clock drive circuit 130. Each subsequent stage of the clock drive circuit generates a new clock signal based on the clock signal from the preceding stage. The output clock signal of each stage of the clock drive circuits 110, 120, and 130 is also provided as a clock signal to the corresponding stage of the pipeline circuits 310, 320, and 330 in the pipeline structure 300.

[0041] In clock circuit 100, each stage of clock drive circuitry is configured to include an even number of inverters. This configuration is intended to provide in-phase clock signals to each stage of pipeline circuits 310, 320, and 330 in pipeline structure 300. Figure 1 In the example, each of the clock drive circuits 110, 120, and 130 includes two inverters. These inverters are shown as 111, 112, 121, 122, 131, and 132. Those skilled in the art will understand that the output signal of an inverter has opposite phase to its input signal. That is, in response to a high-level input signal, the output signal of the inverter will be low-level; and in response to a low-level input signal, the output signal of the inverter will be high-level. Therefore, when the clock drive circuit includes an even number of inverters connected in series, the output clock signal obtained by inverting the input clock signal an even number of times is in phase with respect to the input clock signal. Clock circuit 100 is composed of multiple such clock drive circuits connected in series, therefore the output clock signals of each stage of the clock drive circuit of clock circuit 100 will be in phase with each other.

[0042] The applicant of this disclosure recognizes that although the clock driving circuits of the clock circuit 100 at each stage can output output clock signals that are in phase with each other, the duty cycle of these output clock signals will gradually deviate from the initial clock signal's duty cycle as the number of stages of the clock driving circuit increases. This will be discussed below in conjunction with... Figure 2A-2C This needs to be discussed.

[0043] Figures 2A-2C Exemplary waveforms of the various clock signals associated with clock circuit 100 are shown. Figure 2A The waveform of the initial clock signal CLK1 provided to the clock drive circuit 110 is shown, which is a square wave including four states P1-P4. Figure 2BThe waveform of the clock signal CLK2, which is output by the clock drive circuit 110 and provided to the clock drive circuit 120, is shown. It is a square wave including four states P1'-P4' corresponding to states P1-P4. Figure 2C The waveform of clock signal CLK3, output by clock drive circuit 120 and provided to clock drive circuit 130, is shown. It is a square wave comprising four states P1'-P4' corresponding to states P1'-P4'. In this text, the "correspondence" between two states of two clock signals can mean that one state of one clock signal is generated in response to another state of the other clock signal. For example, state P1' of clock signal CLK2 is generated by clock drive circuit 110 in response to clock signal CLK1 being input to clock drive circuit 110 in state P1.

[0044] exist Figure 2A In the example, the clock signal CLK1 is a square wave with a 50% duty cycle. This square wave consists of two clock cycles, where the first clock cycle includes a high-level state P1 and a low-level state P2, and the second clock cycle includes a high-level state P3 and a low-level state P4. The duty cycle in this paper can be described as the proportion of the duration of the high-level state to the total duration of a single clock cycle. In a 50% duty cycle square wave, states P1, P2, P3, and P4 have the same duration, assumed to be 0.5 units of time.

[0045] according to Figure 1Clock signal CLK1 is provided to clock drive circuit 110. After passing through clock drive circuit 110, clock signal CLK2 is obtained. The duty cycle of clock signal CLK2 will differ from that of clock signal CLK1. This difference can be caused by various factors. For example, the inverters 111 and 112 in clock drive circuit 110 are not perfectly ideal; the rise time (time to transition from low to high) and fall time (time to transition from high to low) of the output signal of each inverter will not be strictly the same. This causes the duration of the high-level state (or low-level state) of the input signal of the inverter to change after passing through the inverter. Furthermore, the output port capacitive load of the first inverter 111 in clock drive circuit 110 is associated with inverter 112, while the output port capacitive load of the last inverter 112 in clock drive circuit 110 is associated with both the first inverter 121 of the next stage clock drive circuit 120 and the corresponding pipeline circuit 310. This load imbalance will also cause the duration of the high-level (or low-level) state of the output signal of inverter 111 to change after passing through inverter 112. As a result of the overall effect of clock drive circuit 110, the high-level state of clock signal CLK1 will be prolonged (or shortened) after passing through clock drive circuit 110. Accordingly, the duty cycle of the resulting clock signal CLK2 will be different from the duty cycle of clock signal CLK1.

[0046] For the purposes of this discussion, it can be assumed that the high-level states P1 and P3 of the clock signal CLK1 are prolonged after passing through the clock drive circuit 110, while the low-level states P2 and P4 are shortened after passing through the clock drive circuit 110. For example... Figure 2B As shown, the duration of states P1' and P3' corresponding to the high-level states P1 and P3 is extended to 0.51 units of time, while the duration of states P2' and P4' corresponding to the low-level states P2 and P4 is shortened to 0.49 units of time.

[0047] Since the clock drive circuit 110 includes an even number of inverters, the states P1'-P4' of the clock signal CLK2 are in phase with the states P1-P4 of the clock signal CLK1. That is, the states P1' and P3' corresponding to the high-level states P1 and P3 are still high-level states, and the states P2' and P4' corresponding to the low-level states P2 and P4 are still low-level states. It can be calculated that the duty cycle of the clock signal CLK2 is 51%, which is greater than the 50% duty cycle of the initial clock signal CLK1.

[0048] according to Figure 1The clock signal CLK2 output by clock drive circuit 110 is then provided to clock drive circuit 120. Clock signal CLK3 is obtained after passing through clock drive circuit 120. Since clock drive circuit 120 has the same structure as clock drive circuit 110, the effect of clock drive circuit 120 on clock signal CLK2 is the same as the effect of clock drive circuit 110 on clock signal CLK1; that is, it prolongs the state corresponding to the high-level state in the input signal and shortens the state corresponding to the low-level state in the input signal. Figure 2C As shown, the duration of states P1” and P3” corresponding to the high-level states P1’ and P3’ of clock signal CLK3 is extended to 0.52 units of time, while the duration of states P2” and P4” corresponding to the low-level states P2’ and P4’ is shortened to 0.48 units of time.

[0049] Similarly, since the clock drive circuit 120 includes an even number of inverters, the states P1”-P4” of the clock signal CLK3 are in phase with the states P1'-P4’ of the clock signal CLK2. That is, the states P1” and P3” corresponding to the high-level states P1’ and P3’ are still high-level states, and the states P2” and P4” corresponding to the low-level states P2’ and P4’ are still low-level states. It can be calculated that the duty cycle of the clock signal CLK3 increases to 52%, which is greater than the duty cycle of the clock signal CLK2 (51%), and further deviates from the initial clock signal CLK1 in the direction of increasing duty cycle.

[0050] The clock signal CLK3 output by the clock driving circuit 120 is provided to the clock driving circuit 130. Based on a similar analysis, the duty cycle of the clock signal (not shown) output by the clock driving circuit 130 will be greater than that of the clock signal CLK3, and will further deviate from the initial clock signal CLK1 in the direction of increasing duty cycle.

[0051] although Figure 2A-2C The illustration shows an example where the high-level state of the clock signal is prolonged after passing through each stage of the clock drive circuit. However, in other examples, the high-level state of the clock signal may also be shortened after passing through each stage of the clock drive circuit. In this case, the clock signal output by each stage of the clock drive circuit will gradually deviate from the initial clock signal in the direction of decreasing (rather than increasing) duty cycle.

[0052] As the above analysis shows, for clock circuit 100, as the number of clock drive circuit stages increases, the duty cycle of the clock signal output by the clock drive circuit will deviate further and further from the initial clock signal's duty cycle. That is, the duty cycle deviation accumulates with the increase in the number of clock drive circuit stages. Even if the deviation of the duty cycle of each stage of the clock drive circuit relative to the duty cycle of the previous stage is small, after dozens or hundreds of stages of clock drive circuits, the accumulated deviation becomes significant. This accumulated deviation makes the duty cycle of the clock signal output by later clock drive circuits significantly different from the duty cycle of the clock signal output by earlier clock drive circuits.

[0053] To maintain a stable duty cycle, a conventional approach is to add a duty cycle detection circuit and an adjustment circuit to each stage of the clock drive circuit. The duty cycle detection circuit can be configured to detect the duty cycle of the clock signal and activate the adjustment circuit when the duty cycle deviates to a certain extent. The duty cycle adjustment circuit can adjust the clock signal to reduce the duty cycle deviation. However, such duty cycle detection and adjustment circuits are often complex, have high design and manufacturing costs, and occupy a large area.

[0054] The applicant of this disclosure recognizes that providing an odd number of inverters in each stage of the clock drive circuit can advantageously maintain the duty cycle of the clock signal without significantly increasing the complexity of the clock circuit. According to embodiments of this disclosure, the clock circuit may include M stages of clock drive circuits connected in series, where M can be an integer not less than 2. Each stage of the M-stage clock drive circuit may have N inverters connected in series between its input and output, where N is an odd number not less than 3.

[0055] Figure 3 A schematic diagram of a clock circuit 1000 according to an embodiment of the present disclosure is shown. For the sake of simplicity, Figure 1 The clock circuit 1000 shown includes three clock drive circuits 1100, 1200, and 1300. These three clock drive circuits 1100, 1200, and 1300 are connected in series. The clock circuit 1000 can be coupled to a clock source 2000 and is configured to receive an initial clock signal from the clock source 2000. The initial clock signal provided by the clock source 2000 can be provided to the first-stage clock drive circuit 1100. The output clock signal of the first-stage clock drive circuit 1100 can be provided to the second-stage clock drive circuit 1200. The output clock signal of the second-stage clock drive circuit 1200 can be provided to the third-stage clock drive circuit 1300.

[0056] It should be noted that, although Figure 3The diagram shows three clock drive circuits connected in series, but clock circuit 1000 may include more or fewer clock drive circuits, such as 2, 10, 50 or more than 100 clock drive circuits. Figure 3 The additional module 1400, which receives the output clock signal of the clock drive circuit 1300, is indicated by a box with an ellipsis. This additional module 1400 may represent multiple clock drive circuits not specifically shown or may represent a tail load element.

[0057] Each of the clock drive circuits 1100, 1200, and 1300 of clock circuit 1000 is shown as comprising three (N=3) inverters connected in series. Specifically, clock drive circuit 1100 includes inverters 1110, 1120, and 1130 connected in series; clock drive circuit 1200 includes inverters 1210, 1220, and 1230 connected in series; and clock drive circuit 1300 includes inverters 1310, 1320, and 1330 connected in series. If the additional module 1400 represents a plurality of clock drive circuits not specifically shown, each of these plurality of clock drive circuits will also include three inverters connected in series.

[0058] It should be noted that, although Figure 3 The diagram shows that each clock drive stage may include three inverters connected in series. However, in other embodiments, each clock drive stage may include more inverters connected in series, provided the number of inverters is odd and the number of inverters in each clock drive stage is equal. For example, each clock drive stage may include five, seven, nine, or more inverters connected in series. Using more inverters can be advantageous. Because inverters are active devices, more inverters ensure that the clock signal maintains a certain amplitude after passing through dozens of clock drive stages. However, more inverters may also increase power consumption and footprint. A trade-off may need to be made between the number of inverters and power consumption and footprint. Preferably, each clock drive stage includes three inverters connected in series.

[0059] The applicant of this disclosure recognizes that placing an odd number of inverters in each stage of the clock drive circuit can advantageously maintain the duty cycle of the clock signal. This will be discussed below in conjunction with... Figures 4A-4C This needs to be discussed.

[0060] Figures 4A-4C Exemplary waveforms of the various clock signals associated with clock circuit 1000 are shown. Figure 4A The waveform of the clock signal CLK4 provided to the clock drive circuit 1100 is shown, which is a square wave including four states P1-P4. Figure 4BThe waveform of the clock signal CLK5, which is output by the clock drive circuit 1100 and provided to the clock drive circuit 1200, is shown. It is a square wave including four states P1'-P4' corresponding to states P1-P4. Figure 4C The waveform of the clock signal CLK6, which is output by the clock drive circuit 1200 and provided to the clock drive circuit 1300, is shown. It is a square wave including four states P1”-P4” corresponding to states P1'-P4'.

[0061] exist Figure 4A In the diagram, clock signal CLK4 is a square wave with a 50% duty cycle. This square wave consists of two clock cycles, where the first clock cycle includes a high-level state P1 and a low-level state P2, and the second clock cycle includes a high-level state P3 and a low-level state P4. In the 50% duty cycle square wave, states P1, P2, P3, and P4 have the same duration, assumed to be 0.5 units of time. Clock signal CLK4 can be analogous to... Figure 2A The clock signal CLK1 is described.

[0062] according to Figure 3 The clock signal CLK4 is provided to the clock drive circuit 1100. After passing through the clock drive circuit 1100, the clock signal CLK5 is obtained. As discussed earlier, due to various undesirable factors, the high-level state of the clock signal CLK4 will be prolonged or shortened after passing through the clock drive circuit 1100. (This is related to the previous discussion...) Figures 2A-2C The assumptions used in the discussion are consistent; here it is assumed that the high-level state of clock signal CLK4 will be prolonged after passing through clock drive circuit 1100. For example... Figure 4B As shown, the duration of states P1' and P3' corresponding to the high-level states P1 and P3 of clock signal CLK5 is extended to 0.51 units of time, while the duration of states P2' and P4' corresponding to the low-level states P2 and P4 is shortened to 0.49 units of time.

[0063] Note that since the clock drive circuit 1100 includes an odd number of inverters, the states P1'-P4' of the clock signal CLK5 are inverted compared to the states P1-P4 of the clock signal CLK4. That is, states P1' and P3' corresponding to the high-level states P1 and P3 transition to the low-level state, while states P2' and P4' corresponding to the low-level states P2 and P4 transition to the high-level state. It can be calculated that the duty cycle of the clock signal CLK5 is 49%, which is a decrease compared to the initial 50% duty cycle of the clock signal CLK4.

[0064] according to Figure 3The clock signal CLK5 output by clock drive circuit 1100 is provided to clock drive circuit 1200. After passing through clock drive circuit 1200, clock signal CLK6 is obtained. Clock drive circuit 1200 has the same structure as clock drive circuit 1100; therefore, the effect of clock drive circuit 1200 on clock signal CLK5 is the same as the effect of clock drive circuit 1100 on clock signal CLK4—that is, extending the state corresponding to the high-level state in the input signal and shortening the state corresponding to the low-level state in the input signal. Accordingly, as... Figure 4C As shown, the duration of states P2” and P4” corresponding to the high-level states P2’ and P4’ of clock signal CLK6 is extended from 0.49 units of time to 0.5 units of time. Furthermore, the duration of states P1” and P3” corresponding to the low-level states P1’ and P3’ is shortened from 0.51 units of time to 0.5 units of time.

[0065] Note that because the clock drive circuit 1200 includes an odd number of inverters, the states P1”-P4” of clock signal CLK6 are inverted compared to the states P1'-P4’ of clock signal CLK5. That is, states P1” and P3” corresponding to low-level states P1' and P3' transition to high-level states, and states P2” and P4” corresponding to high-level states P2' and P4' transition to low-level states. It can be calculated that the duty cycle of clock signal CLK6 is 50%, which is an increase compared to the 49% duty cycle of clock signal CLK5.

[0066] Based on the above analysis, it can be concluded that... Figure 3 In the clock circuit 1000 shown, the duty cycle of clock signal CLK5 decreases relative to clock signal CLK4, while the duty cycle of clock signal CLK6 increases relative to clock signal CLK5. The duty cycle of clock signal CLK6 then returns to the same level as that of clock signal CLK4. This is due to (i) the uniformity of the effect of each stage of the clock drive circuit on the clock signal and (ii) the inversion between the input and output signals. In this case, the deviations in duty cycles caused by adjacent stages of the clock drive circuit can cancel each other out to some extent rather than accumulate. This ensures that the duty cycle of the clock signal output by each stage of the clock drive circuit always fluctuates around the duty cycle of the initial clock signal. Therefore, even if the clock circuit 1000 contains dozens or even hundreds of stages of clock drive circuits, the duty cycle of the output clock signal of a later clock drive circuit will not deviate significantly from the duty cycle of the output clock signal of an earlier clock drive circuit.

[0067] It is also noted that the clock circuit 1000 does not use complex duty cycle detection and adjustment circuits, but only a specific number (i.e., an odd number) of inverters. Inverters are simple electronic components, and their complexity and cost are far lower than those of duty cycle detection and adjustment circuits. Therefore, the clock circuit 1000 can provide a clock signal with a stable duty cycle with a simple structure and low cost.

[0068] It should be understood that Figures 4A-4C The clock signals given are merely exemplary. In alternative embodiments, the clock signals may have different properties or parameters. For example, the duty cycle of the initial clock signal CLK4 provided to the clock drive circuit 1100 may not be limited to 50%, but may be smaller or larger. Furthermore, each stage of the clock drive circuit may shorten the states corresponding to high-level states in the input signal and lengthen the states corresponding to low-level states in the input signal. Moreover, the extent to which each state is shortened or lengthened may not be limited to the specific values ​​given above. Figures 4A-4C The description is merely to better illustrate the basic principles of the embodiments of this disclosure and is not intended to be limiting. It is understood that even if the clock signal employs different properties or parameters, it does not violate... Figures 4A-4C The fundamental principles embodied.

[0069] According to embodiments of this disclosure, each stage of the clock driving circuit in the M-stage clock driving circuit of the clock circuit 1000 can provide a clock signal for a corresponding stage of the pipeline circuit in the pipeline structure used to perform data processing tasks.

[0070] Return to Figure 3 The output of clock driver circuit 1100 can be coupled to the corresponding first-stage pipeline circuit 3100 in pipeline structure 3000, the output of clock driver circuit 1200 can be coupled to the corresponding first-stage pipeline circuit 3200 in pipeline structure 3000, and the output of clock driver circuit 1300 can be coupled to the corresponding first-stage pipeline circuit 3300 in pipeline structure 3000. Pipeline circuits 3100, 3200, and 3300 can perform various data processing tasks under the drive of corresponding clock signals.

[0071] According to embodiments of this disclosure, a corresponding load balancing and phase adjustment module may be optionally provided between the output terminal of each stage of the clock drive circuit in the M-stage clock drive circuit of the clock circuit 1000 and the clock signal input terminal of the corresponding stage of the pipeline circuit in the pipeline structure 3000. For example... Figure 3As shown, a load balancing and phase adjustment module 4000-1 can be provided between the clock drive circuit 1100 and the corresponding first-stage pipeline circuit 3100. A load balancing and phase adjustment module 4000-2 can be provided between the clock drive circuit 1200 and the corresponding first-stage pipeline circuit 3200, and a load balancing and phase adjustment module 4000-3 can be provided between the clock drive circuit 1300 and the corresponding first-stage pipeline circuit 3300.

[0072] It should be noted that each load balancing and phase adjustment module 4000 in Figure 3 The dashed box shown within the clock drive circuit 1000 indicates that the load balancing and phase adjustment module 4000 is optional. In some embodiments, the load balancing and phase adjustment module 4000 may be internal to the clock circuit 1000. In other embodiments, the load balancing and phase adjustment module 4000 may be external to the clock circuit 1000.

[0073] According to embodiments of this disclosure, the load balancing and phase adjustment module can form part of the output port capacitive load of the corresponding first-stage clock drive circuit. For example, the load balancing and phase adjustment module 4000-1 can form part of the output port capacitive load of the clock drive circuit 1100 (specifically, inverter 1130). Furthermore, the load balancing and phase adjustment module 4000-1 isolates the clock drive circuit 1100 from the corresponding first-stage pipeline circuit 3100, thereby making the pipeline circuit 3100 have almost no effect on the output port capacitive load of the clock drive circuit 1100. This load isolation can be advantageous, as it ensures that the state of the pipeline structure 3100 does not affect the clock drive circuit 1100. The output port capacitive load of the clock drive circuit 1100 is primarily associated with the input port capacitance of both the load balancing and phase adjustment module 4000-1 and the next-stage clock drive circuit 1200 (specifically, inverter 1210). Similarly, the load balancing and phase adjustment module 4000-2 and the load balancing and phase adjustment module 4000-3 can respectively constitute part of the output port capacitive load of the corresponding first-level clock drive circuits 1200 and 1300.

[0074] It should be noted that in this article, "an electronic component has an input port capacitance c" means that when the input terminal of the electronic component is connected to the output terminal of another electronic component, it exhibits a load with a capacitance value c on the other electronic component. On the other hand, "an electronic component has an output port capacitance load c" means that the various other electronic components connected to the output terminal of the electronic component exhibit a load with a capacitance value c on the electronic component as a whole.

[0075] Because each stage of the clock drive circuit uses an odd number of inverters, the clock signals output by adjacent stages will be out of phase (e.g., CLK4 and CLK5, or CLK5 and CLK6). Some pipeline architectures allow the use of multiple clock signals with inconsistent phases. However, in certain pipeline architectures, it is desirable that the clock signals used by each stage of the pipeline circuit be in phase. According to embodiments of this disclosure, a load balancing and phase adjustment module can be configured to adjust the phase of the clock signal output by the corresponding stage of the clock drive circuit to ensure that the clock signals provided to each stage of the pipeline circuit are in phase. The phase-adjusted clock signal can then be output to the corresponding stage of the clock drive circuit.

[0076] To provide in-phase clock signals to each stage of the pipeline circuits, load balancing and phase adjustment modules 4000-1, 4000-2, and 4000-3 can be configured. As an example, load balancing and phase adjustment module 4000-2 can be configured to invert the output clock signal (e.g., CLK5) of clock driver circuit 1200 and provide the inverted clock signal to pipeline circuit 3200. Load balancing and phase adjustment modules 4000-1 and 4000-3 may not invert the output clock signal. As a result, the clock signals provided to pipeline circuits 3100, 3200, and 3300 will be in phase. As an alternative example, load balancing and phase adjustment modules 4000-1 and 4000-3 may be configured to invert the output clock signals (e.g., CLK4 and CLK6) of clock driver circuits 1100 and 1300, respectively, while load balancing and phase adjustment module 4000-2 may not invert the output clock signal. As a result, the clock signals supplied to pipeline circuits 3100, 3200, and 3300 will be in phase. It should be noted that each load balancing and phase adjustment module 4000 only adjusts the clock signals to be supplied to the pipeline circuits and does not affect the clock signals supplied to the next stage clock drive circuit.

[0077] To achieve the aforementioned functions, the load balancing and phase adjustment module 4000 can have various configurations. Figures 5A-5B Two exemplary configuration modes of the load balancing and phase adjustment module according to embodiments of the present disclosure are shown.

[0078] In such Figure 5AIn the first configuration mode shown, the load balancing and phase adjustment module 4000 may have an inverter 4300 and a buffer 4400. The inputs of both the inverter 4300 and the buffer 4400 are connected to the input 4100 of the load balancing and phase adjustment module 4000. Input 4100 can be connected to the output of the corresponding first-stage clock drive circuit to receive the output clock signal. The output of the inverter 4300 is connected to the output 4200 of the load balancing and phase adjustment module 4000, while the output of the buffer 4400 is unloaded. "Unloaded" means that the output of the circuit unit is floating and not connected to any other circuit unit. Output 4200 can be connected to the clock signal input of the corresponding first-stage pipeline circuit. In this configuration mode, the input port capacitance of the load balancing and phase adjustment module 4000 depends on both the inverter 4300 and the buffer 4400. Furthermore, the output signal of the load balancing and phase adjustment module 4000 will be the inverted version of its input signal.

[0079] In such Figure 5B In the second configuration mode shown, the load balancing and phase adjustment module 4000 can have an inverter 4300 and a buffer 4400. The inputs of both the inverter 4300 and the buffer 4400 are connected to the input 4100 of the load balancing and phase adjustment module 4000. Input 4100 can be connected to the output of the corresponding first-stage clock drive circuit to receive the output clock signal. The output of the buffer 4400 is connected to the output 4200 of the load balancing and phase adjustment module 4000, while the output of the inverter 4300 is unloaded. Output 4200 can be connected to the clock signal input of the corresponding first-stage pipeline circuit. In this configuration mode, the input port capacitance of the load balancing and phase adjustment module 4000 also depends on both the inverter 4300 and the buffer 4400. However, since the buffer does not invert the input signal, the output signal of the load balancing and phase adjustment module 4000 will be in phase with its input signal.

[0080] exist Figures 5A-5B In both configuration modes shown, the load balancing and phase adjustment module 4000 uses inverters and buffers. Inverters and buffers are simple, basic circuit components, offering advantages such as low cost and ease of use. Furthermore, the load balancing and phase adjustment module 4000 has an extremely simple circuit structure, which does not significantly increase the cost and complexity of the circuit.

[0081] According to embodiments of this disclosure, the two load balancing and phase adjustment modules corresponding to adjacent clock driving circuits in the M-stage clock driving circuit of clock circuit 1000 can each have different configuration modes selected from a first configuration mode and a second configuration mode. As an example, load balancing and phase adjustment module 4000-2 corresponding to clock driving circuit 1200 can have the first configuration mode, while load balancing and phase adjustment modules 4000-1 and 4000-3 corresponding to clock driving circuits 1100 and 1300 respectively can have the second configuration mode. As an alternative example, load balancing and phase adjustment module 4000-2 can have the second configuration mode, while load balancing and phase adjustment modules 4000-1 and 4000-3 can have the first configuration mode. In this way, it can be ensured that the clock signals provided to pipeline circuits 3100, 3200, and 3300 will be in phase with each other.

[0082] Furthermore, in order to ensure that the effects of adjacent clock drive circuits on the duty cycle of the clock signal can cancel each other out as much as possible, the electrical structures of each stage of the clock drive circuit in the clock circuit 1000 can be made as identical as possible. Accordingly, the electronic components associated with the clock circuit 1000 can be selected in a specific manner.

[0083] According to embodiments of this disclosure, in each of the N inverters in the M-stage clock driving circuit of the clock circuit, the Kth inverter can have the same input port capacitance, where 1 ≤ K ≤ N. Specifically, Figure 3 In the clock drive circuits of each stage, the first inverters 1110, 1210, and 1310 can have the same input port capacitor c1, the second inverters 1120, 1220, and 1320 can have the same input port capacitor c2, and the third inverters 1130, 1230, and 1330 can have the same input port capacitor c3. In this configuration, each stage of the clock drive circuit can have the same electrical structure and therefore the same input port capacitor. Preferably, the inverters 1110, 1120, 1130, 1210, 1220, 1230, 1310, 1320, and 1330 can be the same type of inverter, for example, the same model of inverter device, which further reduces the complexity of the clock circuit.

[0084] According to embodiments of this disclosure, the load balancing and phase adjustment modules corresponding to each stage of the clock driving circuit in the M-stage clock driving circuit of the clock circuit can have the same input port capacitance. Specifically, load balancing and phase adjustment modules 4000-1, 4000-2, and 4000-3 can have the same input port capacitance. Preferably, the inverters in all load balancing and phase adjustment modules 4000 can have the same input port capacitance, and the buffers in all load balancing and phase adjustment modules 4000 have the same input port capacitance. Specifically, regardless of the method adopted... Figures 5A-5B In which configuration mode can the inverter 4300 of the load balancing and phase adjustment module have a specified input port capacitor c4, and the buffer 4400 have a specified input port capacitor c5? The inverter 4300 can be the same as or different from inverters 1110, 1120, 1130, 1210, 1220, 1230, 1310, 1320, and 1330.

[0085] Additionally, considering that the last stage clock driver circuit in the M-stage clock driver circuit is no longer connected to the next stage clock driver circuit, it is necessary to specially configure the output port capacitive load of this last stage clock driver circuit so that it has the same output port capacitive load as the other clock driver circuits. For this purpose, the output of the M-stage clock driver circuit can be connected to an additional load element that has the same input port capacitance as the first inverter among the N inverters in each stage clock driver circuit. For example, suppose... Figure 3 The clock circuit 1000 shown includes only 3 clock drive circuits (M=3), so the additional module 1400 can have the same input port capacitor c1 as the inverters 1110, 1210, and 1310. This ensures that the clock drive circuit 1300 has the same output port capacitor load as the clock drive circuits 1100 and 1200.

[0086] According to one embodiment of this disclosure, the clock source 2000 providing the initial clock signal to the clock circuit 1000 may be located outside the clock circuit 1000. The input of the first-stage clock drive circuit in the M-stage clock drive circuit of the clock circuit 1000 may be connected to the clock source to receive the initial clock signal. According to another embodiment of this disclosure, the clock source 2000 may also be located inside the clock circuit 1000 as part of the clock circuit 1000. The clock source 2000 is any component capable of providing a clock signal, including an oscillator that generates the original clock waveform, or another clock circuit driven by the clock waveform to output a clock signal.

[0087] According to embodiments of this disclosure, the initial clock signal provided to the clock circuit 1000 by the clock source 2000 can be a square wave clock signal with a specific duty cycle. The duty cycle of the clock signals output by each stage of the clock drive circuit of the clock circuit 1000 will be maintained near this specific duty cycle. That is, each stage of the clock drive circuit of the clock circuit 1000 can maintain the duty cycle of the output clock signal near the duty cycle of the initial clock signal. Preferably, this specific duty cycle is 50%.

[0088] The clock circuit 1000 according to embodiments of this disclosure can be used in conjunction with the pipeline structure 3000. Driven by various clock signals provided by the clock circuit 1000, each stage of the pipeline circuit of the pipeline structure 3000 can perform various data processing tasks. These data processing tasks include, but are not limited to, data storage, data computation, etc.

[0089] According to embodiments of this disclosure, the data processing task performed by the pipeline structure 3000 includes performing a hash algorithm. Specifically, the hash algorithm may be the SHA-256 algorithm.

[0090] A hash algorithm is an algorithm that takes variable-length data as input and produces a fixed-length hash value as output. In a hash algorithm, input data of arbitrary length is padded so that the padded data length is an integer multiple of a fixed length (e.g., 512 bits), meaning the padded data can be divided into multiple data blocks of the aforementioned fixed length. The padded bits contain information about the bit length of the original data. The hash algorithm then performs operations on each fixed-length data block individually, including multiple rounds of operations such as data expansion and / or compression. After all data blocks have been used, the final fixed-length hash value is obtained.

[0091] Since 1993, the National Institute of Standards and Technology (NIST) has designed and released several versions of the Secure Hash Algorithm (SHA), with SHA-256 being one of them, featuring a hash length of 256 bits.

[0092] For hash algorithms involving multiple rounds of computation (such as the SHA-256 algorithm), a pipelined structure with multiple computation stages can be used to achieve high-speed computation. For example, when executing the SHA-256 algorithm, since 64 rounds of repeated computation are required for each 512-bit data block, a 64-stage pipelined structure can be used to process 64 sets of data in parallel.

[0093] Figure 6 A schematic diagram of a pipeline architecture 6000 that can be used to implement the SHA-256 algorithm is shown. Pipeline architecture 6000 can be a specific use case of the pipeline architecture 3000 described earlier. For example... Figure 6 As shown, the pipelined architecture 6000 is divided into three operation stages: the t-th, t+1-th, and t+2-th. Each operation stage may include multiple registers A to H for storing intermediate values ​​and multiple registers R0 to R15 for storing extended data. Furthermore, each operation stage may also include arithmetic logic. Each operation stage can be implemented using a corresponding pipelined circuit. This pipelined circuit may include storage circuits for implementing the various registers and arithmetic circuits for implementing the arithmetic logic, etc. During the execution of the SHA-256 algorithm, the registers in each pipelined circuit of the pipelined architecture 6000 update the data stored therein based on the corresponding clock signal. Because the pipelined architecture 6000 contains a large number of stages, it has very strict requirements on the duty cycle of each clock signal. The clock signal for the pipelined architecture 6000 can be provided by the clock circuit 1000 described above. The clock signals provided by the clock circuit 1000 have stable duty cycles, making them particularly suitable for the pipelined architecture 6000 used to implement the SHA-256 algorithm.

[0094] The clock circuit according to embodiments of this disclosure can be included in various devices, including but not limited to computing chips, computing boards, and data processing devices. Because of the clock circuit according to embodiments of this disclosure, these devices can obtain multiple clock signals with stable duty cycles at low cost and with a simple circuit structure, thereby ensuring the performance of these devices when performing specific computing tasks.

[0095] Figure 7 A schematic block diagram of a computing chip 7000 according to an embodiment of the present disclosure is shown. The computing chip 7000 may include a clock circuit 7100, a clock source 7200, and a pipeline structure 7300. The clock circuit 7100 may be a specific embodiment of the clock circuit 1000 described above. The clock source 7200 may be a specific embodiment of the clock source 2000 described above. The pipeline structure 7300 may be a specific embodiment of the pipeline structure 3000 or 6000 described above. The clock circuit 7100 may be coupled to the clock source 7200 and the pipeline structure 7300. The clock circuit 7100 may receive an initial clock signal from the clock source 7200 and generate a plurality of clock signals accordingly. These plurality of clock signals may be provided to the pipeline structure 7300 to perform a specific computational task. This specific computational task may, for example, be performing the SHA-256 algorithm. Figure 7 In the diagram, clock source 7200 is shown with a dashed box, indicating that clock source 7200 can also be located outside computing chip 7000.

[0096] Figure 8A schematic block diagram of a computing board 8000 according to an embodiment of the present disclosure is shown. The computing board 8000 may include one or more computing chips 8100. The computing chip 8100 may be a specific embodiment of the computing chip 7000. Multiple computing chips 8100 can perform computing tasks in parallel.

[0097] Figure 9 A schematic block diagram of a data processing device 9000 according to an embodiment of the present disclosure is shown. The data processing device 9000 can be configured to execute the SHA-256 algorithm. The data processing device 9000 may include one or more computing boards 9100. The computing board 9100 may be a specific embodiment of a computing board 8000. Multiple computing boards 9100 can perform computational tasks in parallel, such as executing the SHA-256 algorithm.

[0098] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0099] The terms “front,” “back,” “top,” “bottom,” “above,” “below,” etc., used in the specification and claims, if present, are for descriptive purposes and are not necessarily used to describe unchanging relative positions. It should be understood that such terms are interchangeable where appropriate, so that embodiments of this disclosure described herein can, for example, operate on orientations different from those shown or otherwise described herein.

[0100] As used herein, the term "exemplary" means "serving as an example, instance, or illustration," and not as a "model" to be precisely copied. Any implementation described herein by example is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, this disclosure is not limited to any theory expressed or implied as given in the foregoing technical field, background, summary of invention, or detailed description.

[0101] As used herein, the term "substantially" means any minor variation resulting from design or manufacturing defects, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for differences from the perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in the actual implementation.

[0102] The above description may refer to elements, nodes, or features that are “connected” or “coupled” together. As used herein, unless otherwise expressly stated, “connected” means that one element / node / feature is directly connected (or directly communicates) with another element / node / feature electrically, mechanically, logically, or otherwise. Similarly, unless otherwise expressly stated, “coupled” means that one element / node / feature can be directly or indirectly connected to another element / node / feature mechanically, electrically, logically, or otherwise to allow interaction, even if the two features may not be directly connected. That is, “coupled” is intended to include both direct and indirect connections of elements or other features, including connections using one or more intermediate elements.

[0103] It should also be understood that when the term “including / contains” is used herein, it indicates the presence of the indicated feature, whole, step, operation, unit and / or component, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, units and / or components and / or combinations thereof.

[0104] Those skilled in the art will recognize that the boundaries between the above operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed among additional operations, and operations may be performed with at least partial overlap in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in various other embodiments. However, other modifications, variations, and substitutions are equally possible. Therefore, this specification and the accompanying drawings should be considered illustrative rather than restrictive.

[0105] While specific embodiments of this disclosure have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. The various embodiments disclosed herein can be combined in any way without departing from the spirit and scope of this disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A clock circuit, characterized in that, The clock circuit includes M-stage clock drive circuits connected in series, where M is an integer not less than 2. Each stage of the clock drive circuit in the M-stage clock drive circuit has N inverters connected in series without intermediate components between its input and output terminals, where N is an odd number not less than 3. The output of each stage of the M-stage clock drive circuit provides a clock signal to the corresponding stage of the pipeline circuit in the pipeline structure used to perform data processing tasks.

2. The clock circuit as described in claim 1, characterized in that, A corresponding load balancing and phase adjustment module is provided between the output terminal of each stage of the clock driving circuit in the M-stage clock driving circuit and the clock signal input terminal of the corresponding stage of the pipeline circuit in the pipeline structure. The load balancing and phase adjustment module constitutes part of the output port capacitive load of the stage clock driving circuit and adjusts the phase of the clock signal output by the stage clock driving circuit.

3. The clock circuit as described in claim 2, characterized in that, The load balancing and phase adjustment module has an inverter and a buffer, and the load balancing and phase adjustment module is configured according to one of the following two configuration modes: In the first configuration mode, the input terminal of the inverter and the input terminal of the buffer are both connected to the output terminal of the corresponding first-stage clock drive circuit, the output terminal of the inverter is connected to the clock signal input terminal of the corresponding first-stage pipeline circuit of the pipeline structure, and the output terminal of the buffer is unloaded. or In the second configuration mode, the input terminal of the inverter and the input terminal of the buffer are both connected to the output terminal of the corresponding first-level clock drive circuit, the output terminal of the buffer is connected to the clock signal input terminal of the pipeline circuit of the pipeline structure, and the output terminal of the inverter is unloaded.

4. The clock circuit as described in claim 3, characterized in that, The two load balancing and phase adjustment modules corresponding to the two adjacent clock driving circuits in the M-level clock driving circuit each have different configuration modes selected from the first configuration mode and the second configuration mode.

5. The clock circuit as described in claim 3, characterized in that, The load balancing and phase adjustment modules corresponding to each stage of the clock drive circuit in the M-stage clock drive circuit have the same input port capacitance.

6. The clock circuit as described in claim 5, characterized in that, The inverters in all load balancing and phase adjustment modules have the same input port capacitance, and the buffers in all load balancing and phase adjustment modules have the same input port capacitance.

7. The clock circuit as described in claim 1, characterized in that, In the M-stage clock drive circuit, the Kth inverter among the N inverters in each stage of the clock drive circuit has the same input port capacitance, where 1≤K≤N.

8. The clock circuit as described in claim 7, characterized in that, In the M-level clock drive circuit, the N inverters in each level of the clock drive circuit are all of the same type.

9. The clock circuit as described in claim 7, characterized in that, The output of the M-stage clock drive circuit is connected to an additional load element, which has the same input port capacitance as the first inverter among the N inverters in each stage of the clock drive circuit.

10. The clock circuit as described in any one of claims 1-9, characterized in that, The input terminal of the first-stage clock driving circuit in the M-stage clock driving circuit is connected to an external clock source to receive the initial clock signal.

11. The clock circuit as described in claim 10, characterized in that, The initial clock signal is a square wave signal with a 50% duty cycle.

12. The clock circuit as described in claim 1, characterized in that, The data processing task includes executing the SHA-256 algorithm.

13. The clock circuit as described in claim 12, characterized in that, The pipeline circuit includes at least one of a storage circuit and a computation circuit for executing the SHA-256 algorithm.

14. A clock circuit, characterized in that, The clock circuit includes M-stage clock drive circuits connected in series, where M is an integer not less than 2. Each stage of the clock drive circuit in the M-stage clock drive circuit has N inverters connected in series without intermediate components between its input and output terminals, where N is an odd number not less than 3. In the M-stage clock driving circuit, the Kth inverter among the N inverters in each stage of the clock driving circuit has the same input port capacitance, where 1≤K≤N.

15. The clock circuit as described in claim 14, characterized in that, In the M-level clock drive circuit, the N inverters in each level of the clock drive circuit are all of the same type.

16. The clock circuit as described in claim 14, characterized in that, The output of the M-stage clock drive circuit is connected to an additional load element, which has the same input port capacitance as the first inverter among the N inverters in each stage of the clock drive circuit.

17. A computing chip, characterized in that, The computing chip includes a clock circuit as described in any one of claims 1-16.

18. A computing board, characterized in that, Includes the computing chip as described in claim 17.

19. A data processing device, characterized in that, Including the computing board as described in claim 18.

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