Correlated double sampling circuit, method for changing its output signal and image sensor

Abstract

Provided are a correlated double sampling circuit, a method for changing an output signal thereof, and an image sensor. The correlated double sampling (CDS) circuit includes a comparator, the comparator including: a signal input unit, the signal input unit including a first transistor configured to receive a ramp signal and a second transistor configured to receive a pixel signal; and an offset generating unit, the offset generating unit connected to the signal input unit, the offset generating unit including at least two transistors, wherein in the offset generating unit, the width-to-length ratio of the at least two transistors in an auto-zero adjustment period is different from the width-to-length ratio of the at least two transistors in a pixel signal decoding period.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2019-0015566 filed on February 11, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the inventive concept relate to a correlated double sampling (CDS) circuit, an image sensor including the CDS circuit, and a method of changing an output signal of the CDS circuit. Background Art

[0004] The image sensor may employ a correlated double sampling (CDS) scheme. CDS is a method of measuring electrical values ​​such as voltage or current that facilitates the removal of undesired offsets. The image sensor outputs a digital signal by counting the difference between the signals sampled in the CDS scheme (e.g., between a reset signal and a pixel signal).

[0005] In high-resolution products, the CDS circuit processes a large number of pixel signals. However, when the sampling time is concentrated in a short period of time, the CDS circuit consumes too much current instantaneously. When this happens, the VDD voltage and VSS voltage applied to the CDS circuit may experience IR drop / rise (IR-drop / rise) phenomenon.

[0006] This IR drop / rise phenomenon in the CDS circuit may reduce noise margins, which may slow down image sensor processing or prevent signal processing from being properly performed for certain pixels. Summary of the invention

[0007] According to an exemplary embodiment of the inventive concept, a correlated double sampling (CDS) circuit includes a comparator, the comparator including: a signal input unit, the signal input unit including a first transistor for receiving a ramp signal and a second transistor for receiving a pixel signal; and an offset generation unit, the offset generation unit connected to the signal input unit, the offset generation unit including at least two transistors. In the offset generation unit, the width-to-length ratio of the at least two transistors in an auto-zero period and the width-to-length ratio of the at least two transistors in a pixel signal decoding period can be different from each other.

[0008] According to an exemplary embodiment of the present invention, an image sensor includes: a pixel array including a plurality of pixels, each of the plurality of pixels being used to output a pixel signal; a ramp signal generator, the ramp signal generator being used to output a ramp signal; and a CDS circuit. The CDS circuit includes a comparator, the comparator including: a first transistor for receiving the ramp signal, a second transistor for receiving at least one pixel signal, and a third transistor connected to the first transistor or the second transistor. The width-to-length ratio of the third transistor in a first time period and the width-to-length ratio of the third transistor in a second time period may be different from each other.

[0009] According to an exemplary embodiment of the present invention, an image sensor includes: a pixel array, the pixel array including a plurality of pixels, the plurality of pixel arrays connected to a plurality of column lines; a ramp signal generator, the ramp signal generator for outputting a ramp signal; a CDS circuit unit, the CDS circuit unit configured to compare a pixel signal output from the pixel array with the ramp signal and output a compared output signal according to a result of the comparison; and a signal delay unit, the signal delay unit configured to provide different signal delays to at least two column lines among the plurality of column lines.

[0010] According to an exemplary embodiment of the present invention, a method for changing an output signal of a CDS circuit can be provided, the CDS circuit comprising a signal input unit and an offset generating unit, the signal input unit comprising at least two transistors and configured to receive a ramp signal and a pixel signal, the offset generating unit comprising at least two transistors and connected to the signal input unit, the method comprising: forming a first width-to-length ratio of the at least two transistors included in the offset generating unit to perform automatic zeroing; storing an offset component generated by the automatic zeroing; and forming a second width-to-length ratio of the at least two transistors included in the offset generating unit to perform signal decoding, the second width-to-length ratio being different from the first width-to-length ratio.

[0011] According to an exemplary embodiment of the present invention, a CDS circuit is provided, the CDS circuit including a comparator, wherein the comparator includes: a first circuit including a first transistor receiving a ramp signal and a second transistor receiving a pixel signal; and a second circuit including a third transistor connected to the first transistor and a fourth transistor connected to the second transistor, wherein a width-to-length ratio of the third transistor and the fourth transistor in an automatic zeroing time period is different from a width-to-length ratio of the third transistor and the fourth transistor in a pixel signal decoding time period. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other features of the present inventive concept will be more clearly understood by describing in detail exemplary embodiments of the present inventive concept with reference to the accompanying drawings, in which:

[0013] Figure 1 is a timing diagram showing the operation of a correlated double sampling (CDS) circuit;

[0014] Figure 2 , Figure 3 and Figure 4 is a circuit diagram showing the operation of a CDS circuit;

[0015] Figure 5 is a circuit diagram illustrating a CDS circuit according to an exemplary embodiment of the inventive concept;

[0016] Figure 6 , Figure 7 , Figure 8 and Fig. 9 is a circuit diagram illustrating the operation of a CDS circuit according to an exemplary embodiment of the inventive concept;

[0017] Fig.10 , Fig.11 , Fig.12 , Fig.13 and Fig.14 are circuit diagrams illustrating a portion of an image sensor according to an exemplary embodiment of the inventive concept;

[0018] Fig.15 Is shown when applied and not applied Figures 5 to 9 An exemplary embodiment of the inventive concept is a bar graph of a reset code;

[0019] Fig.16 Is shown when applied and not applied Figures 5 to 9 An exemplary embodiment of the inventive concept of the present invention is a bar graph of a difference between an image signal and a reset signal;

[0020] Fig.17 is a diagram showing changes in a VDD voltage and a VSS voltage when a CDS circuit according to an exemplary embodiment of the inventive concept is not applied;

[0021] Fig.18 is a diagram showing changes in a VDD voltage and a VSS voltage when a CDS circuit according to an exemplary embodiment of the inventive concept is applied;

[0022] Fig.19 is a flowchart illustrating a method of changing an output signal of a CDS circuit according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0023] Hereinafter, exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals may represent the same elements.

[0024] Figure 1 is a timing diagram showing the operation of a correlated double sampling (CDS) circuit, Figures 2 to 4 is a circuit diagram illustrating the operation of the CDS circuit. In the accompanying drawings, VDD and VSS may represent a positive power supply voltage and a ground voltage, respectively. Figure 2 In the figure, Vos,N may represent a negative offset voltage, and Vos,P may represent a positive offset voltage.

[0025] Reference Figure 2 The CDS circuit includes a comparator and a peripheral circuit. For example, the comparator includes: a first transistor TR1 for receiving a ramp signal RAMP, a second transistor TR2 for receiving a pixel signal, a third transistor TR3 connected to the first transistor TR1, and a fourth transistor TR4 connected to the second transistor TR2. Figure 3 and Figure 4 , the CDS circuit may include a first switch SW1, a second switch SW2, and a capacitor C as peripheral circuits.

[0026] The comparator compares the pixel signal PIX with the ramp signal RAMP and outputs a comparison signal COMP corresponding to the comparison result. However, before performing these operations, auto-zeroing is performed to remove the offset of the comparator. Figure 1 The timing diagram shown and Figure 3 , Figure 4 To describe the process, Figure 3 The operation of turning on the first switch SW1 and the second switch SW2 corresponds to Figure 1 The waveform AZSW is shown in the interval between t1 and t2.

[0027] The offset voltage obtained by performing the auto-zero adjustment is expressed by the following Equation 1.

[0028] [Formula 1]

[0029]

[0030] In the above formula 1, V OS，AZ Indicates the offset voltage when performing auto-zeroing, V GSN express Figures 2 to 4 The gate-source voltage of the n-type metal oxide semiconductor (NMOS) transistor shown in GSP express Figures 2 to 4 The gate-source voltage of the p-type metal oxide semiconductor (PMOS) transistor shown in FIG.

[0031] V THN express Figures 2 to 4 The threshold voltage of the NMOS transistor shown in THP express Figures 2 to 4 The threshold voltage of the PMOS transistor shown in . In addition, ΔV THN represents the threshold voltage mismatch between the first transistor TR1 and the second transistor TR2, ΔV THP represents the threshold voltage mismatch between the third transistor TR3 and the fourth transistor TR4.

[0032] W / L represents the aspect ratio of the transistor, which is the ratio of the width W to the length L of the transistor channel region. (W / L) N represents the width-to-length ratio of the first transistor TR1 and the width-to-length ratio of the second transistor TR2, (W / L) P，AZ represents the width-to-length ratio of the third transistor TR3 and the width-to-length ratio of the fourth transistor TR4. In addition, Δ(W / L) N represents the mismatch between the width-to-length ratio of the first transistor TR1 and the second transistor TR2, Δ(W / L) P，AZ It represents the mismatch degree of the aspect ratio between the third transistor TR3 and the fourth transistor TR4.

[0033] In addition, g mN represents the transconductance of the first transistor TR1 and the second transistor TR2, g mP，AZ represents the transconductance of the third transistor TR3 and the fourth transistor TR4.

[0034] In Equation 1, as described above, the offset voltage V when performing auto-zeroing is OS，AZ It is represented as the sum of two terms, wherein the first term represents the offset generated by the first transistor TR1 and the second transistor TR2, and the second term represents the offset generated by the third transistor TR3 and the fourth transistor TR4. In addition, according to the conventional CDS circuit described above, the offset voltage V when performing automatic zeroing is OS，AZ And the offset voltage V when decoding the pixel signal OS，OP Therefore, the final offset voltage V OS，OP -V OS，AZ Equal to 0, accordingly, by performing automatic zeroing, the process of decoding the pixel signal will not be affected by the offset voltage of the comparator.

[0035] However, in the process of decoding the pixel signal, specifically, when decoding the reset signal ( Figure 1At t5 in FIG. 1 , a peak current may flow instantaneously. Since no light enters the image sensor when the reset signal is decoded, decoding is performed for a specific color (for example, usually black). Therefore, the peak current may be consumed instantaneously, and accordingly, the VDD voltage and the VSS voltage applied to the data bus may experience an IR drop / rise phenomenon. For high-resolution products with a relatively large number of pixel signals to be decoded, this IR drop / rise phenomenon is more serious.

[0036] To address this IR drop / rise phenomenon inside the data bus caused by the peak current, a decoupling capacitor may be installed. This can mitigate the effects of the IR drop / rise phenomenon to a certain extent; however, the decoupling capacitor may increase the surface area of ​​the CDS circuit. In addition, the peak current and the IR drop caused by the peak current may be difficult to compensate because the peak current may be generated by an inductive component present on the path used to refill the decoupling capacitor after it instantly consumes a large amount of charge.

[0037] According to an exemplary embodiment of the inventive concept, a method of changing a signal decoding time is provided to prevent a peak current and a subsequent IR drop / rise of a voltage inside a data bus.

[0038] Figure 5 is a circuit diagram illustrating a CDS circuit according to an exemplary embodiment of the inventive concept, Figures 6 to 9 is a circuit diagram illustrating the operation of a CDS circuit according to an exemplary embodiment of the inventive concept.

[0039] Reference Figure 5 , a CDS circuit according to an exemplary embodiment of the inventive concept includes a comparator including a signal input unit 20 and an offset generating unit 10 .

[0040] The signal input unit 20 includes a first transistor TR1 for receiving a ramp signal RAMP and a second transistor TR2 for receiving a pixel signal PIX. The first transistor TR1 may be connected to a first capacitor C1, and the second transistor TR2 may be connected to a second capacitor C2.

[0041] The offset generating unit 10 includes transistors, which are connected to the signal input unit 20. The transistors of the offset generating unit 10 may be connected to the third switch SW3 and the fourth switch SW4. In addition, the CDS circuit according to the present embodiment is controlled so that the width-to-length ratio of the transistors included in the offset generating unit 10 in the auto-zero period and the width-to-length ratio in the pixel signal decoding period are different from each other.

[0042] Still refer to Figure 5, the offset generating unit 10 may include a third transistor TR3 connected to the first transistor TR1 and a fourth transistor TR4 connected to the second transistor TR2. The offset generating unit 10 may also include a first auxiliary transistor TR_SUB1 connected in parallel with the third transistor TR3 and a second auxiliary transistor TR_SUB2 connected in parallel with the fourth transistor TR4. In addition, a comparison node of the comparator is formed at a connection point of the first transistor TR1 and the third transistor TR3, and an output node of the comparator is formed at a connection point of the second transistor TR2 and the fourth transistor TR4.

[0043] The CDS circuit according to the present embodiment is controlled so that in the auto-zero period, the first auxiliary transistor TR_SUB1 and the second auxiliary transistor TR_SUB2 and the third transistor TR3 and the fourth transistor TR4 are turned on. Subsequently, in the pixel signal decoding period, the CDS circuit is controlled so that the third transistor TR3 and the fourth transistor TR4 are turned on, while the first auxiliary transistor TR_SUB1 and the second auxiliary transistor TR_SUB2 are turned off.

[0044] However, when the CDS circuit is controlled as described above, the offset voltage value of the offset generating unit 10 in the auto-zero period is different from the offset voltage value of the offset generating unit 10 in the pixel signal decoding period. In this case, the offset voltage is not removed. This can be described with reference to the following equations 2, 3, and 4.

[0045] Equation 2 generates an offset voltage within an auto-zero period during which the third transistor TR3 , the fourth transistor TR4 , the first auxiliary transistor TR_SUB1 , and the second auxiliary transistor TR_SUB2 are all turned on in the CDS circuit according to example embodiments of the inventive concepts.

[0046] [Formula 2]

[0047]

[0048] In this case, V OS，AZ V represents an offset voltage in an auto-zero period when the third transistor TR3, the fourth transistor TR4, the first auxiliary transistor TR_SUB1, and the second auxiliary transistor TR_SUB2 are all turned on according to an exemplary embodiment of the inventive concept; V GSN express Figure 5 The gate-source voltage of the NMOS transistor shown in GSP，AZ It represents the gate-source voltage of the third transistor TR3, the fourth transistor TR4, the first auxiliary transistor TR_SUB1 and the second auxiliary transistor TR_SUB2 when they are operating.

[0049] V THNexpress Figure 5 The threshold voltage of the first transistor TR1 and the second transistor TR2 shown in FIG. THP express Figure 5 The threshold voltages of the third transistor TR3, the fourth transistor TR4, the first auxiliary transistor TR_SUB1 and the second auxiliary transistor TR_SUB2 shown in FIG. THN represents the threshold voltage mismatch between the first transistor TR1 and the second transistor TR2, ΔV THP，AZ represents the threshold voltage mismatch degree of the third transistor TR3, the fourth transistor TR4, the first auxiliary transistor TR_SUB1 and the second auxiliary transistor TR_SUB2.

[0050] (W / L) N represents the width-to-length ratio of the first transistor TR1 and the second transistor TR2, (W / L) P，AZ represents the width-to-length ratio of the third transistor TR3, the fourth transistor TR4, the first auxiliary transistor TR_SUB1, and the second auxiliary transistor TR_SUB2. In addition, Δ(W / L) N represents the mismatch between the width-to-length ratio of the first transistor TR1 and the second transistor TR2, Δ(W / L) P，AZ It represents the mismatch degree of the width-to-length ratio of the third transistor TR3 , the fourth transistor TR4 , the first auxiliary transistor TR_SUB1 , and the second auxiliary transistor TR_SUB2 .

[0051] In addition, g mN represents the transconductance of the first transistor TR1 and the second transistor TR2, g mP，AZ represents the transconductance of the third transistor TR3, the fourth transistor TR4, the first auxiliary transistor TR_SUB1 and the second auxiliary transistor TR_SUB2.

[0052] Equation 3 generates an offset voltage in a pixel signal decoding period when only the third transistor TR3 and the fourth transistor TR4 are turned on in the CDS circuit according to an example embodiment of the inventive concept.

[0053] [Formula 3]

[0054]

[0055] According to an exemplary embodiment of the present inventive concept, in Formula 3, V OS，OP Represents the offset voltage during the pixel signal decoding period, V GSP，OP represents the gate-source voltage of the third transistor TR3 and the fourth transistor TR4 when the third transistor TR3 and the fourth transistor TR4 are turned on. THP，OP represents the threshold voltage mismatch between the third transistor TR3 and the fourth transistor TR4.

[0056] (W / L) P，OP represents the width-to-length ratio of the third transistor TR3 to the fourth transistor TR4; Δ(W / L) P，OP g represents the mismatch between the width-to-length ratio of the third transistor TR3 and the fourth transistor TR4; mP，OP The other parameters in Formula 3 can refer to the description of Formula 2.

[0057] Equation 4 yields the final offset voltage. Figure 5 When the embodiment shown in , as shown in Equation 4, the final offset voltage can be expressed as a difference generated by subtracting the offset voltage in the auto-zero period from the offset voltage in the pixel signal decoding period.

[0058] [Formula 4]

[0059]

[0060] Referring to Formula 2-4, the final offset component does not include the offset component present in the signal input unit 20. In addition, the offset component present in the offset generating unit 10 remains in the final offset component. In other words, this case is different from applying Figures 2 to 4 The CDS circuit shown in and the final offset voltage is equal to 0.

[0061] According to an exemplary embodiment of the inventive concept, the sizes of transistors included in the offset generating unit 10 (eg, their width-to-length ratio W / L) may be changed so that a final offset component is preserved.

[0062] In order to perform such control as described above, the CDS circuit according to the exemplary embodiment of the inventive concept further includes a first switch SW1 connecting the gate of the first transistor TR1 and the comparison node of the comparator and a second switch SW2 connecting the gate of the second transistor TR2 and the output node of the comparator. The start time and the end time of the auto-zero period can be determined based on the on / off switching operation of the first switch SW1 and the second switch SW2.

[0063] Reference Figures 6 to 9 , the process in which the CDS circuit operates according to the exemplary embodiment of the inventive concept will be described in more detail.

[0064] Reference Figures 6 to 9, the CDS circuit according to an exemplary embodiment of the inventive concept may further include a first capacitor C1 connected to the gate of the first transistor TR1 and a second capacitor C2 connected to the gate of the second transistor TR2. In addition, when the auto-zero period ends, at least one of the first capacitor C1 and the second capacitor C2 may store an offset component formed by the third transistor TR3, the fourth transistor TR4, the first auxiliary transistor TR_SUB1, and the second auxiliary transistor TR_SUB2. The node INP is located between the first transistor TR1 and the first capacitor C1, and the node INN is located between the second transistor TR2 and the second capacitor C2. The node OUTN is located between the first transistor TR1 and the third transistor TR3, and the node OUTP is located between the second transistor TR2 and the fourth transistor TR4.

[0065] Reference Figures 6 to 9 , the CDS circuit according to the exemplary embodiment of the inventive concept may further include a third switch SW3 and a fourth switch SW4, the third switch SW3 is used to connect the gate terminal of the third transistor TR3 and the gate terminal of the first auxiliary transistor TR_SUB1, and the fourth switch SW4 is used to connect the gate terminal of the fourth transistor TR4 and the gate terminal of the second auxiliary transistor TR_SUB2. The third switch SW3 and the fourth switch SW4 are turned on during the automatic zero adjustment period ( Figure 6 ), disconnected at the end of the auto-regulation zero period ( Figure 8 and Fig. 9 ). A signal OTA1_CONT is provided to a gate of the third switch SW3, and a signal OTA1_CONT is provided to a gate of the fourth switch SW4.

[0066] like Figure 6 As shown, when the first switch SW1 and the second switch SW2 are turned on and the auto-zero period starts, the third switch SW3 and the fourth switch SW4 are also turned on, thereby controlling the first auxiliary transistor TR_SUB1 and the second auxiliary transistor TR_SUB2 to be in a conducting state.

[0067] like Figure 7 As shown, when the first switch SW1 and the second switch SW2 are disconnected and the automatic zero adjustment period ends, the mismatch offsets of the third transistor TR3, the fourth transistor TR4, the first auxiliary transistor TR_SUB1 and the second auxiliary transistor TR_SUB2 that are in the on state during the automatic zero adjustment period are stored in at least one of the first capacitor C1 and the second capacitor C2.

[0068] The CDS circuit according to an exemplary embodiment of the inventive concept may further include a fifth switch SW5 and a sixth switch SW6, wherein the fifth switch SW5 is used to connect the gate terminal of the first auxiliary transistor TR_SUB1 with the voltage source VDD of the comparator, and the sixth switch SW6 is used to connect the gate terminal of the second auxiliary transistor TR_SUB2 with the voltage source VDD of the comparator. The signal OTA1_CONTB is provided to the gate of the fifth switch SW5, and the signal OTA1_CONTB is provided to the gate of the sixth switch SW6.

[0069] like Figure 8 As shown, when the first switch SW1 and the second switch SW2 are turned off and the auto-zero time period ends, the third switch SW3 and the fourth switch SW4 are also turned off, and the third transistor TR3 and the fourth transistor TR4 are controlled to be in the on state, while the first auxiliary transistor TR_SUB1 and the second auxiliary transistor TR_SUB2 are controlled to be in the off state. In this way, the first auxiliary transistor TR_SUB1 and the second auxiliary transistor TR_SUB2 can be isolated from the third transistor TR3 and the fourth transistor TR4.

[0070] like Fig. 9 As shown, after the third switch SW3 and the fourth switch SW4 are turned off, by turning on the fifth switch SW5 and the sixth switch SW6 , the voltage VDD of the voltage source of the comparator is supplied to the gate terminal of the first auxiliary transistor TR_SUB1 and the gate terminal of the second auxiliary transistor TR_SUB2 .

[0071] In addition, if Figure 5 As shown, the first transistor TR1 and the second transistor TR2 may be NMOS transistors, and the third transistor TR3, the fourth transistor TR4, the first auxiliary transistor TR_SUB1 and the second auxiliary transistor TR_SUB2 may be PMOS transistors. Figures 6 to 9 As shown, the first switch SW1 to the sixth switch SW6 may be PMOS transistors.

[0072] The image sensor may include a ramp signal generator configured to output a ramp signal RAMP and a pixel array having a plurality of pixels, wherein the pixel array includes a plurality of column lines, each of the plurality of column lines being connected to a CDS circuit. For each of the plurality of column lines, the size of the transistor included in the offset generating unit 10 (in other words, the third transistor TR3, the fourth transistor TR4, the first auxiliary transistor TR_SUB1, and the second auxiliary transistor TR_SUB2) may have slightly different values. Accordingly, the offset values ​​of the CDS circuits connected to the column lines are also different from each other. Therefore, it is possible to prevent the reset signal decoding time of the respective column lines from being concentrated at one time point (for example, Figure 1t5) in the figure, thereby preventing the peak current from flowing when the reset signal is decoded, and further, preventing the IR drop / rise phenomenon from occurring in the VDD voltage and the VSS voltage applied to the data bus.

[0073] According to exemplary embodiments of the present inventive concept, Figures 5 to 9 A method using mismatch between transistors included in a plurality of CDS circuits is shown. Alternatively, according to another exemplary embodiment of the inventive concept, by placing a signal delay unit in each of a plurality of CDS circuits respectively connected to a plurality of column lines, control can be performed so that different signal delays can be provided to at least two column lines among the plurality of column lines.

[0074] Figures 10 to 14 2 are circuit diagrams illustrating a portion of an image sensor according to an exemplary embodiment of the inventive concept.

[0075] Reference Figures 10 to 14 , an image sensor according to an exemplary embodiment of the inventive concept may include: a pixel array including a plurality of pixels connected to a plurality of column lines, a ramp signal generator outputting a ramp signal RAMP, a plurality of CDS circuit units 100' and a signal delay unit (200, 201, 202, 203, 204). The sixth transistor TR6 may be connected between the CDS circuit unit 100' and the signal delay unit (200, 201, 202, 203). The capacitor Cx and the transistor TRx may be connected between the CDS circuit unit 100' and the signal delay unit (200, 201, 202, 203).

[0076] The plurality of CDS circuit units 100' are respectively connected to a plurality of column lines of the pixel array, compare the pixel signal PIX output from the pixel array with the ramp signal RAMP, and output a compared output signal based on the comparison result. Figures 10 to 14 In FIG. 1 , the output signal of the CDS circuit unit 100 ′ can be represented by OUT1_OUT. Figures 10 to 13 In the exemplary embodiment of the inventive concept described in , the switch S4 may be an auto-zero switch. The switch S4 may be turned on during the auto-zero period.

[0077] The signal delay unit 200 provides different signal delays to at least two column lines among the plurality of column lines. Figures 10 to 14 1 and 2 are various configurations of a signal delay unit according to an exemplary embodiment of the inventive concept. Figures 10 to 14 In the exemplary embodiment of the inventive concept described in , a user sets a delay time using a separately provided signal delay unit to manually control a signal processing time of each CDS circuit unit 100 ′.

[0078] For example, in Figures 10 to 13 In the circuit configuration shown, each of the signal delay units 200, 201, 202, and 203 is connected to the output terminal of the CDS circuit unit 100' to delay the compared output signal. The delayed output signal can be represented as CDS_OUT. For example, the plurality of columns can be divided into two groups (e.g., even columns and odd columns), as shown in FIG. Fig.10 or Fig.12 The signal delay unit 200 or 202 (including switches SWa and SWb) shown can control the signal processing time of each CDS circuit to be different from each other by turning on or off each group. Fig.11 The signal delay unit 201 (including at least one switch SW) shown in FIG. 1 controls the signal processing time of each CDS circuit to be different from each other by controlling each switch SW to be in a low state or a high state. Fig.13 In the embodiment, each even-numbered column among the plurality of columns may be connected to a delay buffer (Buffer) 203 to delay the output signal after comparison, and each odd-numbered column may not be connected to the delay buffer 203. The output of the delay buffer 203 may be provided to the multiplexer together with the signal OTA2_OUT. Therefore, a bypass may be provided for the output signal after comparison in the odd-numbered column, thereby controlling the signal processing time of each CDS circuit to be different from each other. As another example, in Fig.14 In the circuit configuration shown, a signal delay unit (Buffer) 204 including a delay buffer is provided at the input end of the CDS circuit unit to delay the ramp signal RAMP. The ramp signal RAMP may be provided to the signal delay unit 204, and the ramp signal RAMP may pass through a switch S before being delayed. Fig.12 In the embodiment, a plurality of transistors TRa, TRb and TRc may also be connected between the CDS circuit unit 100 ′ and the signal delay unit 202 .

[0079] Exemplary embodiments of the present invention include a case where a plurality of columns are divided into two groups (e.g., even columns and odd columns). In addition, exemplary embodiments of the present invention also include a scheme in which a plurality of column lines are divided into N groups, and the time of turning on or off the switch SW is controlled to change the signal processing time of the CDS circuit. In this scheme, the plurality of column lines include a first column line to an Nth column line, and the signal delay includes a first delay to a Tth delay that are all greater than or equal to 0 and different from each other. In addition, the plurality of column lines can be grouped into T groups, and the signal delay unit (200 to 204) can generate a first delay to a Tth delay, each delay being used for a corresponding one of the T groups. N and T are both integers greater than or equal to 2, and N is greater than or equal to T.

[0080] like Figures 10 to 12As shown, for each of the T groups, the signal delay unit (200 to 202) including the delay switch SW is turned on or off at different times, thereby changing the signal processing time in the CDS circuit. Fig.13 and Fig.14 As shown, the signal delay unit (203 and 204) including delay buffers provides different delays to each of the T groups and can be manufactured to include buffers of different sizes.

[0081] Fig.15 Included shows when to apply and not apply Figures 5 to 9 A bar graph of reset codes according to an exemplary embodiment of the inventive concept shown in FIG. Fig.16 Included shows when to apply and not apply Figures 5 to 9 An exemplary embodiment of the inventive concept is a bar graph of a code representing a difference between an image signal and a reset signal.

[0082] Fig.15 The bar graph on the left shows the Figures 5 to 9 The reset code of the embodiment of the present invention. Fig.15 As can be observed from the bar graph on the left side of FIG, when the CDS circuit is operated by performing auto-zeroing to cancel the offset voltage of the comparator in the conventional manner, the time period in which the signal is concentrated is 0.559 LSB, and most signals need to be processed in a short time period. Therefore, a peak current and subsequent IR drop may occur when decoding the reset signal.

[0083] Fig.15 The bar chart on the right shows the Figures 5 to 9 The reset code of the embodiment of the present invention. Fig.15 As can be observed from the bar graph on the right side of FIG, when the exemplary embodiment of the inventive concept is applied, the time period for processing most signals is increased to 3.13 LSB. Therefore, the peak current and the subsequent IR drop can be prevented from occurring when the reset signal is decoded.

[0084] Fig.16 The bar graph on the left shows the Figures 5 to 9 The exemplary embodiment of the inventive concept shown in FIG. 1 is a code representing a difference between an image signal and a reset signal; Fig.16 The bar graph on the right shows the Figures 5 to 9 The exemplary embodiment of the inventive concept shown in FIG. 1 is a code representing the difference between an image signal and a reset signal. Fig.15 and Fig.16 In which m is the code ( Fig.15 The reset code and Fig.16The difference between the reset code and the signal code in the code) is the average value, s is the standard deviation value, and the range is the difference between the maximum and minimum values ​​of the code. Fig.16 It is observed that, similar to the scheme when the exemplary embodiment of the inventive concept is not applied, when the scheme according to the exemplary embodiment of the inventive concept is applied, the difference between the image signal and the reset signal is close to 0 (1.64mLSB and 3.64mLSB). This means that the exemplary embodiment of the inventive concept can be applied without causing problems in the signal decoding function of the CDS circuit.

[0085] Fig.17 is a diagram illustrating a change in a VDD voltage and a change in a VSS voltage when a CDS circuit according to an exemplary embodiment of the inventive concept is not applied, and Fig.18 is a diagram showing a change in a VDD voltage and a change in a VSS voltage when a CDS circuit according to an exemplary embodiment of the inventive concept is applied. Fig.17 and Fig.18 In the figure, the upper graph shows the change of VDD, and the lower graph shows the change of VSS.

[0086] like Fig.17 As shown in FIG. 1 , when the CDS circuit of the present invention is not applied, the internal voltage of the data bus drops and rises by 86 mV and 106 mV respectively, thus showing a total IR drop value of 192 mV. Fig.18 As shown, when the CDS circuit of the present invention is applied, the voltage inside the data bus drops and rises by 42 mV and 63 mV respectively, thus generating a total IR drop value of 105 mV. In other words, it can be confirmed that the IR drop is less severe when the CDS circuit of the present invention is applied than when the CDS circuit of the present invention is not applied.

[0087] Fig.19 is a flowchart of a method of changing an output signal of a CDS circuit according to an exemplary embodiment of the inventive concept.

[0088] According to an exemplary embodiment of the present invention, a method of changing an output signal of a CDS circuit may include: operation S100: forming a first width-to-length ratio of at least two transistors included in an offset generating unit to perform automatic zeroing; operation S200: storing an offset component generated by performing automatic zeroing; and operation S300: forming a second width-to-length ratio of at least two transistors included in the offset generating unit to perform signal decoding, the second width-to-length ratio being different from the first width-to-length ratio.

[0089] As reference Figures 5 to 9As described, the first width-to-length ratio in operation S100 may represent the width-to-length ratio formed by the third transistor TR3, the fourth transistor TR4, the first auxiliary transistor TR_SUB1, and the second auxiliary transistor TR_SUB2; the second width-to-length ratio in operation S300 represents the width-to-length ratio formed by the third transistor TR3 and the fourth transistor TR4. As described above, in the method of changing the output signal of the CDS circuit according to the exemplary embodiment of the inventive concept, during the auto-zero period and during the pixel signal decoding period, by changing the size of the transistor included in the offset generating unit 10, in other words, by changing the width-to-length ratio (W / L) of the transistor included in the offset generating unit 10, the final offset component may be controlled to be retained, thereby preventing the peak current and the subsequent IR drop phenomenon from occurring when decoding the reset signal.

[0090] Exemplary embodiments of the inventive concept provide a CDS circuit capable of preventing an IR drop / rise phenomenon that may occur in a high-resolution product, an image sensor including the CDS circuit, and a method of changing an output signal of the CDS circuit.

[0091] As used herein, the term "unit", in other words, "module" can represent, but is not limited to, software or hardware components such as field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs), and can perform specific tasks. A module can be configured to reside on an addressable storage medium and can be configured to execute on one or more processors. Therefore, as an example, a module can include components (such as software components, object-oriented software components, class components, and task components), processes, functions, attributes, processes, subroutines, program code segments, drivers, firmware, microcodes, circuits, data, databases, data structures, tables, arrays, and variables. The functions provided in components and modules can be combined into fewer components and modules, or can be further separated into additional components and modules. In addition, components and modules can be implemented to execute on one or more CPUs inside the device.

[0092] While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as set forth in the following claims.

Claims

1. A correlated double sampling circuit, the correlated double sampling circuit comprising a comparator, in, The comparator comprises: a signal input unit, the signal input unit comprising a first transistor configured to receive a ramp signal and a second transistor configured to receive a pixel signal; an offset generating unit connected to the signal input unit, the offset generating unit comprising at least two transistors, the at least two transistors comprising a third transistor connected to the first transistor, a first auxiliary transistor connected in parallel with the third transistor, a fourth transistor connected to the second transistor, and a second auxiliary transistor connected in parallel with the fourth transistor; a third switch, the third switch being configured to connect a gate of the third transistor and a gate of the first auxiliary transistor; and a fourth switch, the fourth switch being used to connect the gate of the fourth transistor and the gate of the second auxiliary transistor, In which, in the offset generating unit, the width-to-length ratio of the at least two transistors in the automatic zeroing time period is different from the width-to-length ratio of the at least two transistors in the pixel signal decoding time period, the third switch and the fourth switch are turned on in the automatic zeroing time period, and when the automatic zeroing time period ends, the third switch and the fourth switch are turned off.

2. The correlated double sampling circuit according to claim 1, wherein: During the automatic zero adjustment period, the third transistor, the fourth transistor, the first auxiliary transistor and the second auxiliary transistor are turned on.

3. The correlated double sampling circuit according to claim 2, wherein: During the pixel signal decoding period, the third transistor and the fourth transistor are turned on, and the first auxiliary transistor and the second auxiliary transistor are turned off.

4. The correlated double sampling circuit according to claim 1, wherein: A comparison node of the comparator is provided at a connection point between the first transistor and the third transistor, and an output node of the comparator is provided at a connection point between the second transistor and the fourth transistor.

5. The correlated double sampling circuit according to claim 4, wherein: The correlated double sampling circuit also includes a first switch and a second switch, the first switch is used to connect the gate of the first transistor and the comparison node, and the second switch is used to connect the gate of the second transistor and the output node, wherein the automatic zero adjustment time period is determined by the on / off switching operation of the first switch and the second switch.

6. The correlated double sampling circuit according to claim 1, further comprising: a first capacitor connected to a gate of the first transistor; as well as a second capacitor connected to a gate of the second transistor, Wherein, when the auto-zero period ends, the offset component generated by the third transistor, the fourth transistor, the first auxiliary transistor and the second auxiliary transistor is stored in at least one of the first capacitor and the second capacitor.

7. The correlated double sampling circuit according to claim 5, further comprising: a fifth switch, the fifth switch being used to connect the gate of the first auxiliary transistor and a voltage source of the comparator; as well as A sixth switch is used to connect the gate of the second auxiliary transistor and the voltage source of the comparator.

8. The correlated double sampling circuit according to claim 7, wherein: After the third switch and the fourth switch are turned off, the fifth switch and the sixth switch are turned on to supply the voltage of the voltage source of the comparator to the gate of the first auxiliary transistor and the gate of the second auxiliary transistor.

9. The correlated double sampling circuit according to claim 7, wherein: The first transistor and the second transistor are n-type metal oxide semiconductor transistors, and the third transistor, the fourth transistor, the first auxiliary transistor, the second auxiliary transistor, and the first to sixth switches are p-type metal oxide semiconductor transistors.

10. An image sensor, comprising: A pixel array, the pixel array comprising a plurality of pixels, each of the plurality of pixels being configured to output a pixel signal; A ramp signal generator, the ramp signal generator is used to output a ramp signal; as well as Correlated double sampling circuit, The correlated double sampling circuit includes a comparator, wherein the comparator includes: a first transistor for receiving the ramp signal, a second transistor for receiving at least one pixel signal of the plurality of pixel signals, a third transistor connected to the first transistor, a fourth transistor connected to the second transistor, a first auxiliary transistor connected in parallel with the third transistor, a second auxiliary transistor connected in parallel with the fourth transistor, a first switch connected to a gate of the third transistor and a gate of the first auxiliary transistor, and a second switch connected to a gate of the fourth transistor and a gate of the second auxiliary transistor. wherein the width-to-length ratio of the third transistor in the automatic zero adjustment period is different from the width-to-length ratio of the third transistor in the pixel signal decoding period, and The first switch and the second switch are turned on during the automatic zero adjustment period, and the first switch and the second switch are turned off when the automatic zero adjustment period ends.

11. A method for changing an output signal of a correlated double sampling circuit, the correlated double sampling circuit comprising a signal input unit and an offset generating unit, the signal input unit comprising at least two transistors and configured to receive a ramp signal and a pixel signal, the offset generating unit comprising at least two transistors and connected to the signal input unit, the method comprising: forming a first width-to-length ratio of the at least two transistors included in the offset generating unit to perform auto-zeroing; storing an offset component generated by the automatic zeroing; as well as A second width-to-length ratio of the at least two transistors included in the offset generating unit is formed to perform signal decoding, the second width-to-length ratio being different from the first width-to-length ratio so that an offset component present in the offset generating unit is retained in a final offset voltage generated by subtracting an offset voltage in the auto-zero time period from an offset voltage in the pixel signal decoding time period.

12. A correlated double sampling circuit, the correlated double sampling circuit comprising a comparator, in, The comparator comprises: a first circuit including a first transistor receiving a ramp signal and a second transistor receiving a pixel signal; and a second circuit including a third transistor connected to the first transistor and a fourth transistor connected to the second transistor, wherein a width-to-length ratio of the third transistor and the fourth transistor in an automatic zeroing time period is different from a width-to-length ratio of the third transistor and the fourth transistor in a pixel signal decoding time period, so that an offset component present in the second circuit is retained in a final offset voltage generated by subtracting an offset voltage in the automatic zeroing time period from an offset voltage in the pixel signal decoding time period.

13. The correlated double sampling circuit according to claim 12, wherein: The comparator further comprises: a first switch connected to a gate of the first transistor and a first node between the first transistor and the third transistor; and A second switch is connected to the gate of the second transistor and a second node between the second transistor and the fourth transistor.

14. The correlated double sampling circuit according to claim 13, wherein: The comparator further comprises: a first auxiliary transistor connected to the third transistor; a second auxiliary transistor connected to the fourth transistor; a third switch connected to the first node, the first auxiliary transistor, and a gate of the third transistor and a gate of the fourth transistor; and a fourth switch connected to the second node, the second auxiliary transistor and the fourth transistor, The second node is an output node of the comparator.

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