An overcurrent protection circuit for a switching transistor

Abstract

The present invention discloses an overcurrent protection circuit for a switching transistor, which solves the problems in the prior art that the overcurrent protection circuit has a complex circuit structure, high manufacturing cost, and cannot use a conventional delay circuit for precise delay control. The circuit includes a power transistor Qn, a DC pulse generator connected to the gate terminal of the power transistor Qn, a signal conversion circuit, an overload protection switch, and a frequency divider. The signal conversion circuit outputs a DC level signal at the signal output terminal in the normal state of the power transistor Qn, and outputs a DC pulse signal at the signal output terminal in the overcurrent state of the power transistor Qn; the frequency divider performs timing according to the DC pulse signal output by the signal output terminal and outputs a delay signal. The circuit of the present invention has a simple structure, is suitable for the design of integrated circuits, and can perform precise delay control on overcurrent signals.

Description

Technical Field

[0001] The present invention relates to the technical field of overcurrent protection, and particularly to an overcurrent protection circuit for a switching transistor. Background Art

[0002] An overcurrent protection circuit protects components in a circuit by limiting the current when the current in the circuit exceeds a predetermined maximum value, and is currently widely used in various electrical circuits. For example, in the prior art, a portable power tool uses a lithium battery as a power source and is controlled by a debugging switch. The internal circuit is essentially: a direct current pulse modulation signal (PWM) drives a power transistor, and the rotation speed of a direct current motor is changed by changing the duty cycle of the driving signal to achieve smooth starting of the motor. In order to protect the lithium battery, the motor, and the power transistor itself from being damaged by overload, overcurrent protection is required. In the prior art, a commonly used overcurrent protection circuit adopts a structure as shown in Figure 1 which is composed of two power transistors Qn' and Q1' connected in series. Among them, the transistor Qn' is driven by a direct current pulse modulation signal output by a dedicated speed control chip 1' to achieve the purpose of adjusting the speed of the direct current motor; the transistor Q1' obtains an overcurrent signal according to the magnitude of its saturation voltage drop by a comparator BG' inside a lithium battery protection integrated circuit, that is, the lithium battery protection chip 2' in the figure, so as to achieve overcurrent protection for the battery power supply circuit. However, this protection circuit has disadvantages: it requires two relatively high-power transistors Qn' and Q1', and is controlled by two dedicated integrated circuits respectively. Not only is the circuit complex, but the manufacturing cost is also high.

[0003] Therefore, a Chinese invention patent with the patent number ZL200810162438.4 and the name of an overload protection circuit for a switching-type transistor designs an overcurrent protection circuit that can be achieved with only a single transistor for the above problems. In actual use, the circuit of the above patent is indeed effective and reliable when the pulse duty cycle is certain. However, when the duty cycle of the pulse signal changes within a large range (such as multi-stage speed regulation of a power tool), it is very difficult to accurately delay the overcurrent signal by using a conventional RC delay circuit in the circuit of the above patent. Moreover, there are multiple capacitors and resistors in the circuit of the above patent, which is not suitable for integrated circuit design. Summary of the Invention

[0004] The present invention mainly solves the problems that the existing overcurrent protection circuit has a complex circuit structure, a high manufacturing cost, and cannot use a conventional delay circuit for accurate delay control, and provides an overcurrent protection circuit for a switching transistor.

[0005] The above technical problems of the present invention are mainly solved by the following technical solutions: An overcurrent protection circuit for a switching transistor includes a power transistor Qn connected to a power supply circuit and a DC pulse generator connected to the gate terminal of the power transistor Qn to drive its operation, and includes a signal conversion circuit, an overload protection switch, and a frequency divider. The signal conversion circuit includes a signal input terminal, a signal output terminal, and a signal control terminal. The signal input terminal is connected to the line between the power transistor Qn and the power supply, the signal output terminal is connected to the control terminal of the overload protection switch after connecting to the frequency divider, and the signal control terminal is connected to the line between the gate of the power transistor Qn and the DC pulse generator. The input terminal of the overload protection switch is connected to the line between the power transistor and the DC pulse generator, and the output terminal of the overload protection switch is grounded;

[0006] The signal conversion circuit outputs a DC level signal at the signal output terminal in the normal state of the power transistor Qn, and outputs a DC pulse signal at the signal output terminal in the overcurrent state of the power transistor Qn;

[0007] The frequency divider times according to the DC pulse signal output by the signal output terminal of the signal conversion circuit and outputs a delay signal.

[0008] The circuit structure of the present invention is simpler. Compared with the existing circuit, it does not need to use multiple capacitors and resistors, and is more suitable for the design of integrated circuits. The signal conversion circuit of the present invention can output a DC level signal and a DC pulse signal respectively according to the overcurrent state of the power transistor, and cooperate with the frequency divider to accurately control the delay of the overcurrent signal. In the present invention, the frequency divider adopts a pulse timing circuit in the prior art, and different ratios of frequency dividers can be used to obtain delay signals of different times. The starting level of the signal output by the frequency divider can be set according to requirements.

[0009] As a preferred solution, the signal conversion circuit includes a first comparator BG1, a first reference voltage source E01, a first resistor R1, a first field-effect transistor Q1, and a first inverter F1; the non-inverting input terminal of the first comparator GB1 serves as the signal input terminal, the inverting input terminal of the first comparator GB1 is connected to the positive electrode of the first reference voltage source E01, the negative electrode of the first reference voltage source E01 is grounded, the output terminal of the first comparator GB1 is connected to the first end of the resistor R1, the second end of the resistor R1 serves as the signal output terminal, the drain of the first field-effect transistor Q1 is connected to the second end of the resistor R1, the source of the first field-effect transistor Q1 is grounded, and the gate of the first field-effect transistor Q1 is connected to the first inverter F1 and then serves as the signal control terminal. In this solution, a comparator is used to detect the over-current state of the power transistor. When the power transistor is conducting, the voltage signal on the power transistor is collected through the non-inverting input terminal of the first comparator BG1 and compared with the reference voltage on the inverting input terminal to detect whether the power transistor is in an over-current state. In the over-current state, the output terminal of the first comparator BG1 outputs a high level, and at the same time, the on-off of the first field-effect transistor Q1 is controlled by cooperating with the pulse signal input at the signal control terminal, so as to control the change of the output level of the output terminal of the first comparator BG1, that is, the signal output terminal, and the signal output terminal outputs a DC pulse signal to enable the frequency divider to delay the output signal. The signal conversion circuit only uses one resistor, which is more suitable for integrated circuit design and can cooperate with the frequency divider to accurately control the delay of the over-current signal. By selecting different reference voltage sources E01, over-current values of power transistors Qn with different voltages can be obtained.

[0010] As a preferred solution, the signal conversion circuit includes a second field-effect transistor Q2, a third field-effect transistor Q3, a second resistor R2, a third resistor R3, a second inverter F2, and a third inverter F3. The gate of the second field-effect transistor Q2 serves as the signal input terminal, the source of the second field-effect transistor Q2 is grounded, the drain of the second field-effect transistor Q2 is respectively connected to the first end of the second resistor R2 and the input terminal of the second inverter F2. The second end of the second resistor R2 is connected to the power supply. The output terminal of the second inverter F2 is connected to the first end of the third resistor R3. The second end of the third resistor R3 serves as the signal output terminal. The drain of the field-effect transistor Q3 is connected to the second end of the third resistor R3, the source of the field-effect transistor Q3 is grounded, and the gate of the field-effect transistor Q3 is connected to the signal control terminal after passing through the third inverter F3. In this solution, a field-effect transistor is used to detect the overcurrent state of the power transistor. When the power transistor is conducting, the gate of the second field-effect transistor Q2 collects the voltage signal on the power transistor, and whether the power transistor is in an overcurrent state is detected according to whether the second field-effect transistor Q2 is conducting. Here, the turn-on voltage of the second field-effect transistor Q2 is equivalent to the reference voltage. In the overcurrent state, the second field-effect transistor Q2 conducts, and a level signal is output at the signal output terminal. At the same time, the on-off of the third field-effect transistor Q3 is controlled by cooperating with the pulse signal input at the signal control terminal, so as to control the change of the level signal at the signal output terminal. The signal output terminal outputs a DC pulse signal, so that the frequency divider delays the output signal. The signal conversion circuit uses fewer resistors, is suitable for integrated circuit design, and can cooperate with the frequency divider to accurately control the delay of the overcurrent signal. In addition, the resistor R2 can also be replaced by a constant current source.

[0011] As a preferred solution, the signal conversion circuit includes a fourth field effect transistor Q4, a fifth field effect transistor Q5, and a fourth resistor R4. The gate of the fourth field effect transistor Q4 serves as the signal input terminal, the source of the fourth field effect transistor Q4 is grounded, the drain of the fourth field effect transistor Q4 is connected to the source of the fifth field effect transistor Q5, the gate of the fifth field effect transistor Q5 serves as the signal control terminal, the drain of the fifth field effect transistor Q5 is divided into two paths, one path is connected to the first end of the fourth resistor R4, and the other path serves as the signal output terminal. The second end of the fourth resistor R4 is connected to the power supply. In this solution, a field effect transistor is also used to detect the overcurrent state of the power transistor. When the power transistor is conducting, the voltage signal on the power transistor is collected at the gate of the fourth field effect transistor Q4. Whether the power transistor is in an overcurrent state is detected according to whether the fourth field effect transistor Q4 is conducting. Here, the turn-on voltage of the fourth field effect transistor Q4 is equivalent to the reference voltage. In the overcurrent state, the fourth field effect transistor Q4 conducts. The level of the signal at the signal output terminal is determined by the conduction of the circuit composed of the resistor R4, the fifth field effect transistor Q5, and the fourth field effect transistor Q4. The on-off of the fifth field effect transistor Q5 is controlled by the pulse signal input through the signal control terminal, so as to control the change of the level signal at the signal output terminal. The signal output terminal outputs a DC pulse signal to enable the frequency divider to delay the output signal. The signal conversion circuit only uses one resistor, which is more suitable for integrated circuit design and can cooperate with the frequency divider to accurately control the delay of the overcurrent signal. In addition, the resistor R4 can also be replaced by a constant current source.

[0012] As a preferred solution, the signal conversion circuit includes a second comparator BG2, a second reference voltage source E02, a sixth field effect transistor Q6, and a constant current source ID. The inverting input terminal of the second comparator BG2 serves as the signal input terminal. The non-inverting input terminal of the second comparator BG2 is connected to the positive electrode of the second reference voltage source E02, and the negative electrode of the second reference voltage source E02 is grounded. The output terminal of the second comparator BG2 is connected to the source electrode of the sixth field effect transistor Q6. The gate electrode of the sixth field effect transistor Q6 serves as the signal control terminal. The drain electrode of the sixth field effect transistor Q6 is divided into two paths. One path serves as the signal output terminal, and the other path is connected to the constant current source ID. In this solution, a comparator is used to detect the overcurrent state of the power transistor. When the power transistor conducts and operates, the voltage signal on the power transistor is collected through the inverting input terminal of the second comparator BG2 and compared with the reference voltage on the non-inverting input terminal to detect whether the power transistor is in an overcurrent state. In the overcurrent state, the output terminal of the second comparator BG2 outputs a low level. The level signal of the signal output terminal is determined by the operating state of the sixth field effect transistor Q6. The on / off of the sixth field effect transistor Q6 is controlled by the pulse signal input through the signal control terminal, thereby controlling the change of the level signal of the signal output terminal. The signal output terminal outputs a DC pulse signal so that the frequency divider delays the output signal. The signal conversion circuit only uses one resistor, which is more suitable for integrated circuit design and can cooperate with the frequency divider to accurately control the delay of the overcurrent signal. By selecting different reference voltage sources E02, overcurrent values of power transistors Qn with different voltages can be obtained.

[0013] As a preferred solution, the signal conversion circuit includes a third comparator BG3, a third reference voltage source E03, a NOR gate, and a fourth inverter F4. The inverting input terminal of the third comparator BG3 serves as the signal input terminal. The non-inverting input terminal of the third comparator BG3 is connected to the positive electrode of the third reference voltage source E03, and the negative electrode of the third reference voltage source E03 is grounded. The output terminal of the third comparator BG3 is connected to the first input terminal of the NOR gate. The second input terminal of the NOR gate serves as the signal control terminal after being connected to the fourth inverter F4, and the output terminal of the NOR gate serves as the signal output terminal. In this solution, the signal conversion circuit adopts a combination of a comparator, a NOR gate, and an inverter. The comparator is used to detect the overcurrent state of the power transistor. When the power transistor is conducting, the voltage signal on the power transistor is collected through the inverting input terminal of the third comparator BG3 and compared with the reference voltage on the non-inverting input terminal to detect whether the power transistor is in an overcurrent state. In the overcurrent state, the third comparator BG3 outputs a low level, which is input into the NOR gate together with the signal of the signal control terminal. The level of the output terminal of the NOR gate, that is, the level of the signal output terminal, is controlled by the pulse signal input to the signal control terminal, so that the signal output terminal outputs a DC pulse signal, and then the frequency divider delays the output signal. The signal conversion circuit does not need to use resistors and capacitors, is more suitable for integrated circuit design, and can cooperate with the frequency divider to accurately control the delay of the overcurrent signal. By selecting different reference voltage sources E03, overcurrent values of power transistors Qn with different voltages can be obtained.

[0014] As a preferred solution, the signal conversion circuit includes a fourth comparator BG4, a fourth reference voltage source E04, and a NAND gate. The non-inverting input terminal of the fourth comparator BG4 serves as the signal input terminal. The inverting input terminal of the fourth comparator BG4 is connected to the positive electrode of the fourth reference voltage source E04, and the negative electrode of the fourth reference voltage source E04 is grounded. The output terminal of the fourth comparator BG4 is connected to the first input terminal of the NAND gate. The second input terminal of the NAND gate serves as the signal control terminal, and the output terminal of the NAND gate serves as the signal output terminal. In this solution, the signal conversion circuit adopts a combination of a comparator and a NAND gate. The comparator is used to detect the overcurrent state of the power transistor. When the power transistor is conducting, the voltage signal on the power transistor is collected through the non-inverting input terminal of the fourth comparator BG4 and compared with the reference voltage on the inverting input terminal to detect whether the power transistor is in an overcurrent state. In the overcurrent state, the fourth comparator BG4 outputs a high level, which is input into the NAND gate together with the signal of the signal control terminal. The level of the output terminal of the NAND gate, that is, the level of the signal output terminal, is controlled by the pulse signal input to the signal control terminal, so that the signal output terminal outputs a DC pulse signal, and then the frequency divider delays the output signal. The signal conversion circuit does not need to use resistors and capacitors, is more suitable for integrated circuit design, and can cooperate with the frequency divider to accurately control the delay of the overcurrent signal. By selecting different reference voltage sources E04, overcurrent values of power transistors Qn with different voltages can be obtained.

[0015] As a preferred solution, the overload protection switch is an overload protection transistor Qt. The drain of the overload protection transistor Qt is connected to the line between the power transistor Qn and the DC pulse generator. The source of the overload protection transistor Qt is grounded. The gate of the overload protection transistor Qt is connected to the signal output terminal through a frequency divider.

[0016] As a preferred solution, the signal conversion circuit is integrated in an integrated chip. The signal input terminal and the signal control terminal respectively form two pins of the integrated chip. Resistors and capacitors are not used or less used in the signal conversion circuit, making it more suitable for integrated circuit design. The design with fewer pins reduces the manufacturing cost of the integrated chip.

[0017] Therefore, the advantages of the present invention are as follows: The circuit structure is simpler. Compared with the existing circuit, multiple capacitors and resistors are not required, making it more suitable for the design of integrated circuits. The signal conversion circuit can output a DC level signal and a DC pulse signal respectively according to the overcurrent state of the power transistor, and a conventional delay circuit can be used to accurately delay and control the overcurrent signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic diagram of a circuit structure of a common overcurrent protection circuit for power tools in the background art of the present invention;

[0019] Figure 2 is a circuit principle block diagram of the present invention;

[0020] Figure 3 is a schematic diagram of the first circuit structure of the present invention;

[0021] Figure 4 is a schematic diagram of the second circuit structure of the present invention;

[0022] Figure 5 is a schematic diagram of the third circuit structure of the present invention;

[0023] Figure 6 is a schematic diagram of the fourth circuit structure of the present invention;

[0024] Figure 7 is a schematic diagram of the fifth circuit structure of the present invention;

[0025] Figure 8 is a schematic diagram of the sixth circuit structure of the present invention.

[0026] 1 - Signal conversion circuit 2 - Overload protection switch 3 - Frequency divider 4 - DC pulse generator. DETAILED DESCRIPTION OF THE INVENTION

[0027] The technical solutions of the present invention will be further specifically described below through embodiments and in conjunction with the drawings.

[0028] Embodiment 1

[0029] An overcurrent protection circuit for a switching transistor, as Figure 2 shown, includes a load RL, a power transistor Qn, a signal conversion circuit 1, an overload protection switch 2, a frequency divider 3, and a DC pulse generator 4. One end of the load RL is connected to a power supply, the other end of the load RL is connected to the drain of the power transistor Qn, the source of the power transistor Qn is grounded, and the gate of the power transistor Qn is connected to the DC pulse generator. The signal conversion circuit includes a signal input end, a signal output end, and a signal control end. The signal input end is connected to the line between the power transistor Qn and the power supply. The signal output end is connected to the control end of the overload protection switch after connecting to the frequency divider. The signal control end is connected to the line between the power transistor Qn and the DC pulse generator. The input end of the overload protection switch is connected to the line between the power transistor Qn and the DC pulse generator, and the output end of the overload protection switch is grounded.

[0030] In this embodiment, the overload protection switch uses an overload protection transistor Qt. The drain of the overload protection transistor Qt is connected to the line between the power transistor Qn and the DC pulse generator. The source of the overload protection transistor Qt is grounded, and the gate of the overload protection transistor Qt is connected to the signal output end through the frequency divider 3.

[0031] The signal conversion circuit outputs a DC level signal at the signal output end in the normal state of the power transistor Qn, and outputs a DC pulse signal at the signal output end in the overcurrent state of the power transistor Qn;

[0032] The frequency divider performs timing according to the DC pulse signal output by the signal output end and outputs a delay signal. This frequency divider is the pulse timing circuit in the prior art, which is driven by the DC pulse signal. The starting level of the signal output by the frequency divider can be set according to requirements. In the present invention, the set starting level is a low level.

[0033] The signal conversion circuit, the frequency divider, the overload protection switch, and the DC pulse generator are all integrated on an integrated chip, and the signal input end and the signal control end of the signal conversion circuit respectively form two pins of the integrated chip.

[0034] The present invention uses a signal conversion circuit that can output a DC level signal and a DC pulse signal respectively according to the overcurrent state of the power transistor Qn. When ensuring the normal operation of the power transistor Qn, the signal output end of the signal conversion circuit always outputs a stable DC level signal, and always outputs a low level signal after passing through the frequency divider. The overload protection transistor Qt is always in the cut-off state to ensure the normal operation of the power transistor Qn. When the power transistor Qn is cut off, whether the signal output end of the signal conversion circuit outputs a high level or a low level has no impact on the power transistor Qn itself.

[0035] When overcurrent, short - circuit and other overload situations occur, the signal output end of the signal conversion circuit outputs a DC pulse signal, and the frequency of this DC pulse signal is the same as that of the pulse output by the pulse generator. The DC pulse signal triggers the frequency divider. When the number of trigger pulses of the frequency divider reaches the set value, the frequency divider outputs a high - level signal to drive the overload protection transistor Qt to conduct, thereby controlling the power transistor Qn to cut off, so as to achieve the overload protection of the power transistor Qn.

[0036] The signal conversion circuit can be implemented through various circuit structures. For example, Figure 3 As shown, the first circuit structure of the present invention is given. The signal conversion circuit includes a first comparator BG1, a first reference voltage source E01, a first resistor R1, a first field - effect transistor Q1, and a first inverter F1. The non - inverting input terminal of the first comparator GB1 serves as the signal input terminal. The inverting input terminal of the first comparator GB1 is connected to the positive electrode of the first reference voltage source E01, the negative electrode of the first reference voltage source E01 is grounded. The output terminal of the first comparator GB1 is connected to the first end of the resistor R1, and the second end of the resistor R1 serves as the signal output terminal. The drain of the first field - effect transistor Q1 is connected to the second end of the resistor R1, the source of the first field - effect transistor Q1 is grounded, and the gate of the first field - effect transistor Q1 is used as the signal control terminal after being connected to the first inverter F1.

[0037] The working principle of this embodiment is as follows:

[0038] 1. When in the normal working state and the DC pulse generator outputs a high - level signal

[0039] The power transistor Qn is in the normal conducting state, the power supply circuit is conducting, the voltage at the signal input terminal, that is, the non - inverting input terminal of the comparator BG1, is 0. The voltage at the non - inverting input terminal of the comparator BG1 is less than the voltage of the first reference voltage source E01 input at the inverting input terminal, and the output terminal of the comparator BG1 outputs a low - level signal. At the same time, the high - level signal output by the DC pulse generator is converted by the first inverter F1 and outputs a low - level signal to the gate of the first field - effect transistor Q1, and the first field - effect transistor Q1 cuts off. The signal output end of the signal conversion circuit finally outputs a low - level signal.

[0040] 2. When in the normal working state and the DC pulse generator outputs a low - level signal

[0041] If the power transistor Qn is in the cut-off state, the voltage at the signal input terminal, i.e., the non-inverting input terminal of the comparator BG1, increases. When the voltage at the non-inverting input terminal of the comparator BG1 is higher than the voltage of the first reference voltage source E01 input to the inverting input terminal, the output terminal of the comparator BG1 outputs a high level. At the same time, the low level output by the DC pulse generator is converted to a high level by the first inverter F1 and output to the gate of the first field-effect transistor Q1. The first field-effect transistor Q1 conducts, pulling down the output level signal of the comparator BG1 to a low level, and the signal output terminal of the signal conversion circuit finally outputs a low level.

[0042] In the normal operating state, during the process of the DC pulse generator outputting high and low levels, the signal output terminal of the signal conversion circuit always outputs a low level, i.e., a DC level signal. Since there is no trigger pulse signal input to the frequency divider, its output terminal always remains at the initially set low level state, and the overload protection transistor Qt is cut off. That is, in the normal operating state, regardless of the signal output by the DC pulse generator, the overload protection transistor Qt remains cut off and does not affect the state of the power transistor Qn.

[0043] 3. When in the overload state and the DC pulse generator outputs a high level signal

[0044] The power transistor Qn is in the conducting state. Due to the existence of the internal resistance, the voltage potential at the signal input terminal, i.e., the non-inverting input terminal of the comparator BG1, increases. When the voltage at the non-inverting input terminal of the comparator BG1 is higher than the voltage at the inverting input terminal, the output terminal of the comparator BG1 outputs a high level. At the same time, the high level output by the DC pulse generator is converted to a low level by the first inverter F1 and input to the gate of the first field-effect transistor Q1. The first field-effect transistor Q1 is cut off; the signal output terminal of the signal conversion circuit outputs a high level.

[0045] 4. When in the overload state and the DC pulse generator outputs a low level signal

[0046] The power transistor Qn is in the cut-off state. In the overload state, the voltage potential at the signal input terminal, i.e., the non-inverting input terminal of the comparator BG1, increases. When the voltage at the non-inverting input terminal of the comparator BG1 is higher than the voltage at the inverting input terminal, the output terminal of the comparator BG1 outputs a high level. At the same time, the low level output by the DC pulse generator is converted to a high level by the first inverter F1 and input to the gate of the first field-effect transistor Q1. The first field-effect transistor Q1 conducts, pulling down the output level signal of the comparator BG1 to a low level, and the signal output terminal of the signal conversion circuit finally outputs a low level.

[0047] During the process of the DC pulse generator outputting high and low levels, the signal output terminal of the signal conversion circuit outputs corresponding high and low levels, that is, a DC pulse signal of the same frequency is output. The frequency divider is triggered to work when the DC pulse signal is input. After a delay, a high level is output to the gate of the overload protection transistor Qt. The overload protection transistor Qt conducts, pulling down the gate of the power transistor Qn to a low level, controlling the power transistor Qn to cut off and turn off, playing an overload protection role.

[0048] Embodiment 2

[0049] This embodiment gives a second circuit structure of the overcurrent protection circuit of the switching transistor. The difference from Embodiment 1 is that the signal conversion circuit adopts the second circuit structure, and other structures are the same as those in Embodiment 1.

[0050] As Figure 4 shown, the signal conversion circuit 1 includes a second field-effect transistor Q2, a third field-effect transistor Q3, a second resistor R2, a third resistor R3, a second inverter F2, and a third inverter F3. The gate of the second field-effect transistor Q2 is used as the signal input terminal. The source of the second field-effect transistor Q2 is grounded. The drain of the second field-effect transistor Q2 is respectively connected to the first end of the second resistor R2 and the input terminal of the second inverter F2. The second end of the second resistor R2 is connected to the power supply. The output terminal of the second inverter F2 is connected to the first end of the third resistor R3. The second end of the third resistor R3 is used as the signal output terminal. The drain of the field-effect transistor Q3 is connected to the second end of the third resistor R3. The source of the field-effect transistor Q3 is grounded. The gate of the field-effect transistor Q3 is used as the signal control terminal after being connected to the third inverter F3.

[0051] The working principle of this embodiment is as follows:

[0052] 1. When in the normal working state and the DC pulse generator outputs a high-level signal

[0053] The power transistor Qn is in the normal conduction state, the power supply circuit is conducting, the voltage at the signal input terminal, that is, the gate of the second field-effect transistor Q2, is 0. The second field-effect transistor Q2 is cut off. The drain of the second field-effect transistor Q2 is at a high level under the influence of the power supply and is converted to a low level after passing through the second inverter F2. At the same time, the high level output by the DC pulse generator is converted by the third inverter F3 and a low level is output to the gate of the third field-effect transistor Q3. The third field-effect transistor Q3 is cut off. The signal output terminal of the signal conversion circuit finally outputs a low level.

[0054] 2. When in the normal working state and the DC pulse generator outputs a low-level signal

[0055] The power transistor Qn is in the cut-off state. Under the influence of the power supply, the voltage at the signal input terminal, i.e., the gate voltage of the second field-effect transistor Q2, increases, and the second field-effect transistor Q2 conducts. Since the drain of the second field-effect transistor Q2 is grounded, the voltage is 0. After being converted by the second inverter F2, a high level is output. At the same time, the low level output by the DC pulse generator is converted by the third inverter F3 and a high level is output to the gate of the third field-effect transistor Q3. The third field-effect transistor Q3 conducts and pulls down the high level output by the second inverter F2 to a low level. Finally, a low level is output at the signal output terminal of the signal conversion circuit.

[0056] In the normal operating state, during the process of the DC pulse generator outputting high and low levels, the signal output terminal of the signal conversion circuit always outputs a low level, i.e., a DC level signal. Since there is no trigger pulse signal input to the frequency divider, its output terminal always remains at the low level set at the beginning. The overload protection transistor Qt is cut off. That is, in the normal operating state, no matter what signal the DC pulse generator outputs, the overload protection transistor Qt remains cut off and does not affect the state of the power transistor Qn.

[0057] 3. When in the overload state and the DC pulse generator outputs a high level signal

[0058] The power transistor Qn is in the conducting state. In the overload state, the voltage at the signal input terminal, i.e., the gate voltage of the second field-effect transistor Q2, increases, and the second field-effect transistor Q2 conducts. Since the drain of the second field-effect transistor Q2 is grounded, the voltage is 0. After being converted by the second inverter F2, a high level is output. At the same time, the high level output by the DC pulse generator is converted by the third inverter F3 and a low level is output to the gate of the third field-effect transistor Q3. The third field-effect transistor Q3 is cut off. Finally, a high level is output at the signal output terminal.

[0059] 4. When in the overload state and the DC pulse generator outputs a low level signal

[0060] The power transistor Qn is in the cut-off state. In the overload state, the voltage at the signal input terminal, i.e., the gate voltage of the second field-effect transistor Q2, increases, and the second field-effect transistor Q2 conducts. Since the drain of the second field-effect transistor Q2 is grounded, the voltage is 0. After being converted by the second inverter F2, a high level is output. At the same time, the low level output by the DC pulse generator is converted by the third inverter F3 and a high level is output to the gate of the third field-effect transistor Q3. The third field-effect transistor Q3 conducts and pulls down the high level output by the second inverter F2 to a low level. Finally, a low level is output at the signal output terminal of the signal conversion circuit.

[0061] During the process of the DC pulse generator outputting high and low levels, the signal output terminal of the signal conversion circuit outputs corresponding high and low levels, that is, a DC pulse signal of the same frequency is output. The frequency divider is triggered when a DC pulse signal is input. When the number of triggers of the frequency divider to the pulse signal reaches the set value, the frequency divider outputs a high level to the gate of the overload protection transistor Qt. The overload protection transistor Qt conducts, pulling down the gate of the power transistor Qn to a low level, controlling the power transistor Qn to cut off and turn off, playing an overload protection role.

[0062] Embodiment 3

[0063] This embodiment gives a third circuit structure of the overcurrent protection circuit for the switching transistor. The difference from Embodiment 1 is that the signal conversion circuit adopts the third circuit structure, and other structures are the same as those in Embodiment 1.

[0064] As Figure 5 shown, the signal conversion circuit 1 includes a fourth field-effect transistor Q4, a fifth field-effect transistor Q5, and a fourth resistor R4. The gate of the fourth field-effect transistor Q4 is used as the signal input terminal, the source of the fourth field-effect transistor Q4 is grounded, the drain of the fourth field-effect transistor Q4 is connected to the source of the fifth field-effect transistor Q5, the gate of the fifth field-effect transistor Q5 is used as the signal control terminal, the drain of the fifth field-effect transistor Q5 is divided into two paths, one path is connected to the first end of the fourth resistor R4, and the other path is used as the signal output terminal. The second end of the fourth resistor R4 is connected to the power supply.

[0065] The working principle of this embodiment is as follows:

[0066] 1. When in the normal working state and the DC pulse generator outputs a high-level signal

[0067] The power supply circuit is turned on. The voltage of the signal input terminal, that is, the gate of the fourth field-effect transistor Q4, is 0, and the fourth field-effect transistor Q4 is cut off; at the same time, the high level output by the DC pulse generator reaches the gate of the fifth field-effect transistor Q5, and the fifth field-effect transistor Q5 conducts. The circuit composed of the resistor R4, the fifth field-effect transistor Q5, and the fourth field-effect transistor Q4 is not turned on. Then, the drain of the fifth field-effect transistor Q5 is at a high level affected by the power supply, and the signal output terminal of the signal conversion circuit outputs a high level.

[0068] 2. When in the normal working state and the DC pulse generator outputs a low-level signal

[0069] The power transistor Qn is in the cut-off state. Under the influence of the power supply, the voltage at the gate of the signal input terminal, i.e., the fourth field-effect transistor Q4, increases, and the fourth field-effect transistor Q4 conducts; at the same time, the low level output by the DC pulse generator reaches the gate of the fifth field-effect transistor Q5, and the fifth field-effect transistor Q5 is cut off. The circuit composed of the resistor R4, the fifth field-effect transistor Q5, and the fourth field-effect transistor Q4 is not conducting, so the drain of the fifth field-effect transistor Q5 is at a high level under the influence of the power supply, and the signal output terminal of the signal conversion circuit outputs a high level.

[0070] In the normal operating state, during the process of the DC pulse generator outputting high and low levels, the signal output terminal of the signal conversion circuit always outputs a high level, i.e., a DC level signal. Since there is no trigger pulse signal input to the frequency divider, its output terminal is always in the low level state set at the beginning, and the overload protection transistor Qt is cut off. That is, in the normal operating state, no matter what signal the DC pulse generator outputs, the overload protection transistor Qt remains cut off and does not affect the state of the power transistor Qn.

[0071] 3. When in the overload state and the DC pulse generator outputs a high level signal

[0072] The power transistor Qn is in the conducting state. In the overload state, the voltage at the gate of the signal input terminal, i.e., the fourth field-effect transistor Q4, increases, and the fourth field-effect transistor Q4 conducts; at the same time, the high level output by the DC pulse generator reaches the gate of the fifth field-effect transistor Q5, and the fifth field-effect transistor Q5 conducts. The drain of the fifth field-effect transistor Q5 is grounded, so the voltage is 0, and the signal output terminal of the signal conversion circuit outputs a low level.

[0073] 4. When in the overload state and the DC pulse generator outputs a low level signal

[0074] The power transistor Qn is in the cut-off state. In the overload state, the voltage at the gate of the signal input terminal, i.e., the fourth field-effect transistor Q4, increases, and the fourth field-effect transistor Q4 conducts; at the same time, the low level output by the DC pulse generator reaches the gate of the fifth field-effect transistor Q5, and the fifth field-effect transistor Q5 is cut off. The circuit composed of the resistor R4, the fifth field-effect transistor Q5, and the fourth field-effect transistor Q4 is not conducting, so the drain of the fifth field-effect transistor Q5 is at a high level under the influence of the power supply, and the signal output terminal of the signal conversion circuit outputs a high level.

[0075] During the process of the DC pulse generator outputting high and low levels, the signal output terminal of the signal conversion circuit correspondingly outputs high and low levels, that is, it outputs a DC pulse signal of the same frequency. The frequency divider is triggered to work when a DC pulse signal is input. When the number of trigger pulses from the frequency divider reaches the set value, the frequency divider outputs a high level to the gate of the overload protection transistor Qt, and the overload protection transistor Qt conducts, pulling the gate of the power transistor Qn down to a low level, controlling the power transistor Qn to cut off and turn off, playing an overload protection role.

[0076] Embodiment 4

[0077] This embodiment provides a fourth circuit structure of the overcurrent protection circuit for a switching transistor. The difference from Embodiment 1 lies in that the signal conversion circuit adopts a fourth circuit structure, and other structures are the same as those in Embodiment 1.

[0078] As Figure 6 shown, the signal conversion circuit 1 includes a second comparator BG2, a second reference voltage source E02, a sixth field-effect transistor Q6, and a constant current source ID. The inverting input terminal of the second comparator BG2 serves as the signal input terminal. The non-inverting input terminal of the second comparator BG2 is connected to the positive electrode of the second reference voltage source E02, and the negative electrode of the second reference voltage source E02 is grounded. The output terminal of the second comparator BG2 is connected to the source electrode of the sixth field-effect transistor Q6. The gate electrode of the sixth field-effect transistor Q6 serves as the signal control terminal. The drain electrode of the sixth field-effect transistor Q6 is divided into two paths. One path serves as the signal output terminal, and the other path is connected to the constant current source ID.

[0079] The working principle of this embodiment is as follows:

[0080] 1. When in the normal working state and the DC pulse generator outputs a high-level signal

[0081] The power transistor Qn is in the normal conducting state, the power supply circuit is conducting, the voltage at the signal input terminal, i.e., the inverting input terminal of the comparator BG2, is 0. The voltage at the non-inverting input terminal of the comparator BG2 is greater than the voltage of the second reference voltage source E02 input to the inverting input terminal, and the output terminal of the comparator BG2 outputs a high level. At the same time, the high-level signal output by the DC pulse generator reaches the gate electrode of the sixth field-effect transistor Q6, the sixth field-effect transistor Q6 conducts, and the signal output terminal of the signal conversion circuit outputs a high level.

[0082] 2. When in the normal working state and the DC pulse generator outputs a low-level signal

[0083] The power transistor Qn is in the cut-off state, then the voltage at the signal input terminal, i.e., the inverting input terminal of the comparator BG2, rises. When the voltage at the inverting input terminal of the comparator BG2 is higher than the voltage of the second reference voltage source E02 input to the non-inverting input terminal, the output terminal of the comparator BG2 outputs a low level. At the same time, the low-level signal output by the DC pulse generator reaches the gate electrode of the sixth field-effect transistor Q6, the sixth field-effect transistor Q6 is cut off, and the drain electrode of the sixth field-effect transistor Q6 is at a high level under the influence of the constant current source ID, and the signal output terminal finally outputs a high level.

[0084] In the normal working state, during the process of the DC pulse generator outputting high and low levels, the signal output terminal of the signal conversion circuit always outputs a high level, that is, a DC level signal. Since there is no trigger pulse signal input to the frequency divider, it outputs a low level to the gate of the overload protection transistor Qt, and the overload protection transistor Qt is cut off. That is, in the normal working state, no matter what signal the DC pulse generator outputs, the overload protection transistor Qt remains cut off and does not affect the state of the power transistor Qn.

[0085] 3. When in the overload state and the DC pulse generator outputs a high-level signal

[0086] The power transistor Qn is in the conducting state. In the overload state, due to the internal resistance of the power transistor Qn, the voltage potential at the signal input terminal, that is, the inverting input terminal of the comparator BG2, increases. When the voltage at the inverting input terminal of the comparator BG2 is higher than the voltage at the non-inverting input terminal, the output terminal of the comparator BG2 outputs a low level. At the same time, the high level output by the DC pulse generator reaches the gate of the sixth field-effect transistor Q6, and the sixth field-effect transistor Q6 conducts, then the drain voltage of the sixth field-effect transistor Q6 is pulled down to a low level, and the signal output terminal finally outputs a low level.

[0087] 4. When in the overload state and the DC pulse generator outputs a low-level signal

[0088] The power transistor Qn is in the cut-off state. In the overload state, the voltage potential at the signal input terminal, that is, the inverting input terminal of the comparator BG2, increases. When the voltage at the inverting input terminal of the comparator BG2 is higher than the voltage at the non-inverting input terminal, the output terminal of the comparator BG2 outputs a low level. At the same time, the low level output by the DC pulse generator reaches the gate of the sixth field-effect transistor Q6, and the sixth field-effect transistor Q6 is cut off, then the drain of the sixth field-effect transistor Q6 is affected by the power supply and is at a high level, and the signal output terminal finally outputs a high level.

[0089] During the process of the DC pulse generator outputting high and low levels, the signal output terminal of the signal conversion circuit correspondingly outputs low and high levels, that is, it outputs a DC pulse signal of the same frequency. The frequency divider is triggered to work when input with a DC pulse signal. When the number of trigger pulses of the frequency divider reaches the set value, the frequency divider outputs a high level to the gate of the overload protection transistor Qt, and the overload protection transistor Qt conducts; the gate of the power transistor Qn is pulled down to a low level, controlling the power transistor Qn to cut off and turn off, playing an overload protection role.

[0090] Embodiment 5

[0091] This embodiment provides a fifth circuit structure of the overcurrent protection circuit for the switching transistor. The difference from Embodiment 1 is that the signal conversion circuit adopts the fifth circuit structure, and other structures are the same as those in Embodiment 1.

[0092] Such as Figure 7As shown, the signal conversion circuit 1 includes a third comparator BG3, a third reference voltage source E03, a NOR gate, and a fourth inverter F4. The inverting input terminal of the third comparator BG3 serves as the signal input terminal. The non-inverting input terminal of the third comparator BG3 is connected to the positive electrode of the third reference voltage source E03, and the negative electrode of the third reference voltage source E03 is grounded. The output terminal of the third comparator BG3 is connected to the first input terminal of the NOR gate. The second input terminal of the NOR gate serves as the signal control terminal after being connected to the fourth inverter F4, and the output terminal of the NOR gate serves as the signal output terminal.

[0093] The working principle of this embodiment is as follows:

[0094] 1. When in the normal working state and the DC pulse generator outputs a high-level signal

[0095] The power supply circuit is turned on. The voltage at the signal input terminal, i.e., the inverting input terminal of the comparator BG3, is 0. The voltage of the third reference voltage source E03 input to the non-inverting input terminal of the comparator BG3 is greater than the voltage at the inverting input terminal. The output terminal of the comparator BG3 outputs a high level to the first terminal of the NOR gate. At the same time, the high level output by the DC pulse generator is converted by the fourth inverter F4 and then outputs a low level to the second terminal of the NOR gate. The output terminal of the NOR gate outputs a low level, and the signal output terminal of the signal conversion circuit outputs a low level.

[0096] 2. When in the normal working state and the DC pulse generator outputs a low-level signal

[0097] The power transistor Qn is in the cut-off state, so the voltage at the signal input terminal, i.e., the inverting input terminal of the comparator BG3, rises. When the voltage at the inverting input terminal of the comparator BG3 is higher than the voltage of the third reference voltage source E03 input to the non-inverting input terminal, the output terminal of the comparator BG3 outputs a low level to the first terminal of the NOR gate. At the same time, the low level output by the DC pulse generator is converted by the fourth inverter F4 and then outputs a high level to the second terminal of the NOR gate. The output terminal of the NOR gate outputs a low level, and the signal output terminal of the signal conversion circuit outputs a low level.

[0098] In the normal working state, during the process of the DC pulse generator outputting high and low levels, the signal output terminal of the signal conversion circuit always outputs a low level, i.e., a DC level signal. Since there is no trigger pulse signal input to the frequency divider, its output terminal always remains at the initially set low level state, and the overload protection transistor Qt is cut off. That is, in the normal working state, regardless of the signal output by the DC pulse generator, the overload protection transistor Qt remains cut off and does not affect the state of the power transistor Qn.

[0099] 3. When in the overload state and the DC pulse generator outputs a high-level signal

[0100] The power transistor Qn is in the conducting state. Under the overload condition, the voltage potential at the signal input terminal, i.e., the inverting input terminal of the comparator BG3, increases. When the voltage at the inverting input terminal of the comparator BG3 is higher than the voltage at the non-inverting input terminal, the output terminal of the comparator BG3 outputs a low level to the first terminal of the NOR gate; meanwhile, the high level output by the DC pulse generator is converted by the fourth inverter F4 and then outputs a low level to the second terminal of the NOR gate; the output terminal of the NOR gate outputs a high level, and the signal output terminal of the signal conversion circuit outputs a high level.

[0101] 4. When in the overload condition and the DC pulse generator outputs a low level signal

[0102] The power transistor Qn is in the cut-off state. Under the overload condition, the voltage potential at the signal input terminal, i.e., the inverting input terminal of the comparator BG3, increases. When the voltage at the inverting input terminal of the comparator BG3 is higher than the voltage at the non-inverting input terminal, the output terminal of the comparator BG3 outputs a low level to the first terminal of the NOR gate; meanwhile, the low level output by the DC pulse generator is converted by the fourth inverter F4 and then outputs a high level to the second terminal of the NOR gate; the output terminal of the NOR gate outputs a low level, and the signal output terminal of the signal conversion circuit outputs a low level.

[0103] During the process of the DC pulse generator outputting high and low levels, the signal output terminal of the signal conversion circuit correspondingly outputs high and low levels, that is, a DC pulse signal of the same frequency is output. The frequency divider is triggered to work when a DC pulse signal is input. When the number of trigger pulses of the frequency divider reaches the set value, the frequency divider outputs a high level to the gate of the overload protection transistor Qt, and the overload protection transistor Qt conducts, pulling the gate of the power transistor Qn low to a low level, controlling the power transistor Qn to cut off and turn off, playing an overload protection role.

[0104] Embodiment 6

[0105] This embodiment provides a sixth circuit structure of the overcurrent protection circuit for the switching transistor. The difference from Embodiment 1 is that the signal conversion circuit adopts the sixth circuit structure, and other structures are the same as those in Embodiment 1.

[0106] As Figure 8 shown, the signal conversion circuit 1 includes a fourth comparator BG4, a fourth reference voltage source E04, and a NAND gate. The non-inverting input terminal of the fourth comparator BG4 serves as the signal input terminal. The inverting input terminal of the fourth comparator BG4 is connected to the positive electrode of the fourth reference voltage source E04, the negative electrode of the fourth reference voltage source E04 is grounded, the output terminal of the fourth comparator BG4 is connected to the first input terminal of the NAND gate, the second input terminal of the NAND gate serves as the signal control terminal, and the output terminal of the NAND gate serves as the signal output terminal.

[0107] The working principle of this embodiment is as follows:

[0108] 1. When in the normal working state and the DC pulse generator outputs a high-level signal

[0109] The power transistor Qn is in the normal conduction state, the power supply circuit is conducting, the voltage at the signal input terminal, i.e., the non-inverting input terminal of the comparator BG4, is 0, the voltage at the non-inverting input terminal of the comparator BG4 is less than the voltage of the fourth reference voltage source E04 input to the inverting input terminal, the output terminal of the comparator BG4 outputs a low level to the first terminal of the NAND gate; at the same time, the high level output by the DC pulse generator reaches the second terminal of the NAND gate; the output terminal of the NAND gate outputs a high level, and the signal output terminal of the signal conversion circuit outputs a high level.

[0110] 2. When in the normal working state and the DC pulse generator outputs a low-level signal

[0111] The power transistor Qn is in the cut-off state, then the voltage at the signal input terminal, i.e., the non-inverting input terminal of the comparator BG4, rises. When the voltage at the non-inverting input terminal of the comparator BG4 is higher than the voltage input to the inverting input terminal of the fourth reference voltage source E04, the output terminal of the comparator BG4 outputs a high level to the first terminal of the NAND gate; at the same time, the low level output by the DC pulse generator reaches the second terminal of the NAND gate; the output terminal of the NAND gate outputs a high level, and the signal output terminal of the signal conversion circuit outputs a high level.

[0112] In the normal working state, during the process of the DC pulse generator outputting high and low levels, the signal output terminal of the signal conversion circuit always outputs a high level, i.e., a DC level signal. Since there is no trigger pulse signal input to the frequency divider, its output terminal always remains at the initially set low level state, and the overload protection transistor Qt is cut off. That is, in the normal working state, regardless of the signal output by the DC pulse generator, the overload protection transistor Qt remains cut off and does not affect the state of the power transistor Qn.

[0113] 3. When in the overload state and the DC pulse generator outputs a high-level signal

[0114] The power transistor Qn is in the conduction state. In the overload state, the voltage potential at the signal input terminal, i.e., the non-inverting input terminal of the comparator BG4, rises. When the voltage at the non-inverting input terminal of the comparator BG4 is higher than the voltage at the inverting input terminal, the output terminal of the comparator BG4 outputs a high level to the first terminal of the NAND gate; at the same time, the high level output by the DC pulse generator reaches the second terminal of the NAND gate; the output terminal of the NAND gate outputs a low level, and the signal output terminal of the signal conversion circuit outputs a low level.

[0115] 4. When in the overload state and the DC pulse generator outputs a low-level signal

[0116] The power transistor Qn is in the cut-off state. In the overload state, the voltage potential at the signal input end, i.e., the non-inverting input end of the comparator BG4, increases. When the voltage at the non-inverting input end of the comparator BG4 is higher than the voltage at the inverting input end, the output end of the comparator BG4 outputs a high level to the first end of the NAND gate; at the same time, the low level output by the DC pulse generator reaches the second end of the NAND gate; the output end of the NAND gate outputs a high level, and the signal output end of the signal conversion circuit outputs a high level.

[0117] During the process of the DC pulse generator outputting high and low levels, the signal output end of the signal conversion circuit correspondingly outputs low and high levels, that is, a DC pulse signal of the same frequency is output. The frequency divider is triggered to work when a DC pulse signal is input. When the number of trigger pulses of the frequency divider reaches the set value, the frequency divider outputs a high level to the gate of the overload protection transistor Qt. The overload protection transistor Qt conducts, pulling down the gate of the power transistor Qn to a low level, controlling the power transistor Qn to cut off and turn off, playing an overload protection role. The gate of the power transistor Qn is at a low level, always keeping the power transistor Qn cut off and turned off.

[0118] The specific embodiments described herein are merely illustrative of the spirit of the present invention. Those skilled in the art to which the present invention pertains can make various modifications or supplements to the described specific embodiments or use similar ways to substitute, but will not deviate from the spirit of the present invention or exceed the scope defined by the appended claims.

[0119] Although terms such as signal conversion circuit, overload protection switch, frequency divider, DC pulse generator, etc. are used more in this article, the possibility of using other terms is not excluded. Using these terms is only to more conveniently describe and explain the essence of the present invention; interpreting them as any additional limitation is contrary to the spirit of the present invention.

Claims

1. An overcurrent protection circuit for a switching transistor, comprising a power transistor Qn connected to a power supply circuit and a DC pulse generator connected to the gate terminal of the power transistor Qn to drive its operation, characterized in that: It includes a signal conversion circuit (1), an overload protection switch (2), and a frequency divider (3). The signal conversion circuit includes a signal input terminal, a signal output terminal, and a signal control terminal. The signal input terminal is connected to the line between the power transistor Qn and the power supply. The signal output terminal is connected to the control terminal of the overload protection switch after connecting to the frequency divider. The signal control terminal is connected to the line between the gate of the power transistor Qn and the DC pulse generator (4). The input terminal of the overload protection switch is connected to the line between the power transistor Qn and the DC pulse generator, and the output terminal of the overload protection switch is grounded; For the signal conversion circuit, when the power transistor Qn is in the normal state, the DC pulse generator outputs high and low levels, and the signal output terminal outputs a DC level signal. When the power transistor Qn is in the overcurrent state, the DC pulse generator outputs high and low levels, and the signal output terminal outputs a DC pulse signal; For the frequency divider, when no trigger pulse signal is input, the output terminal is in the low level state, and the overload protection switch is cut off; when a DC pulse signal is input to trigger its operation, it outputs a high level after a delay, and the overload protection switch is turned on.

2. The overcurrent protection circuit for a switching transistor according to claim 1, characterized in that The signal conversion circuit (1) includes a first comparator BG1, a first reference voltage source E01, a first resistor R1, a first field effect transistor Q1, and a first inverter F1; the non-inverting input terminal of the first comparator GB1 is used as the signal input terminal, the inverting input terminal of the first comparator GB1 is connected to the positive pole of the first reference voltage source E01, the negative pole of the first reference voltage source E01 is grounded, the output terminal of the first comparator GB1 is connected to the first end of the resistor R1, the second end of the resistor R1 is used as the signal output terminal, the drain of the first field effect transistor Q1 is connected to the second end of the resistor R1, the source of the first field effect transistor Q1 is grounded, and the gate of the first field effect transistor Q1 is used as the signal control terminal after being connected to the first inverter F1.

3. The overcurrent protection circuit for a switching transistor according to claim 1, characterized in that The signal conversion circuit (1) includes a second field effect transistor Q2, a third field effect transistor Q3, a second resistor R2, a third resistor R3, a second inverter F2, and a third inverter F3. The gate of the second field effect transistor Q2 is used as the signal input terminal, the source of the second field effect transistor Q2 is grounded, the drain of the second field effect transistor Q2 is respectively connected to the first end of the second resistor R2 and the input terminal of the second inverter F2, the second end of the second resistor R2 is connected to the power supply, the output terminal of the second inverter F2 is connected to the first end of the third resistor R3, the second end of the third resistor R3 is used as the signal output terminal, the drain of the field effect transistor Q3 is connected to the second end of the third resistor R3, the source of the field effect transistor Q3 is grounded, and the gate of the field effect transistor Q3 is used as the signal control terminal after being connected to the third inverter F3.

4. The overcurrent protection circuit for a switching transistor according to claim 1, characterized in that The signal conversion circuit (1) includes a fourth field effect transistor Q4, a fifth field effect transistor Q5, and a fourth resistor R4. The gate of the fourth field effect transistor Q4 is used as the signal input terminal, the source of the fourth field effect transistor Q4 is grounded, the drain of the fourth field effect transistor Q4 is connected to the source of the fifth field effect transistor Q5, the gate of the fifth field effect transistor Q5 is used as the signal control terminal, the drain of the fifth field effect transistor Q5 is divided into two paths, one path is connected to the first end of the fourth resistor R4, and the other path is used as the signal output terminal, and the second end of the fourth resistor R4 is connected to the power supply.

5. The overcurrent protection circuit for a switching transistor according to claim 1, characterized in that The signal conversion circuit (1) includes a second comparator BG2, a second reference voltage source E02, a sixth field effect transistor Q6, and a constant current source ID. The inverting input terminal of the second comparator BG2 serves as the signal input terminal. The non-inverting input terminal of the second comparator BG2 is connected to the positive electrode of the second reference voltage source E02. The negative electrode of the second reference voltage source E02 is grounded. The output terminal of the second comparator BG2 is connected to the source electrode of the sixth field effect transistor Q6. The gate electrode of the sixth field effect transistor Q6 serves as the signal control terminal. The drain electrode of the sixth field effect transistor Q6 is divided into two paths. One path serves as the signal output terminal, and the other path is connected to the constant current source ID.

6. The overcurrent protection circuit for a switching transistor according to claim 1, characterized in that The signal conversion circuit (1) includes a third comparator BG3, a third reference voltage source E03, an OR-NOT gate, and a fourth inverter F4. The inverting input terminal of the third comparator BG3 serves as the signal input terminal. The non-inverting input terminal of the third comparator BG3 is connected to the positive electrode of the third reference voltage source E03. The negative electrode of the third reference voltage source E03 is grounded. The output terminal of the third comparator BG3 is connected to the first input terminal of the OR-NOT gate. The second input terminal of the OR-NOT gate is used as the signal control terminal after being connected to the fourth inverter F4. The output terminal of the OR-NOT gate serves as the signal output terminal.

7. The overcurrent protection circuit for a switching transistor according to claim 1, characterized in that The signal conversion circuit (1) includes a fourth comparator BG4, a fourth reference voltage source E04, and a NAND gate. The non-inverting input terminal of the fourth comparator BG4 serves as the signal input terminal. The inverting input terminal of the fourth comparator BG4 is connected to the positive electrode of the fourth reference voltage source E04. The negative electrode of the fourth reference voltage source E04 is grounded. The output terminal of the fourth comparator BG4 is connected to the first input terminal of the NAND gate. The second input terminal of the NAND gate serves as the signal control terminal. The output terminal of the NAND gate serves as the signal output terminal.

8. The overcurrent protection circuit for a switching transistor according to any one of claims 2 - 7, characterized in that The overload protection switch (2) is an overload protection transistor Qt. The drain electrode of the overload protection transistor Qt is connected to the line between the power transistor Qn and the DC pulse generator. The source electrode of the overload protection transistor Qt is grounded. The gate electrode of the overload protection transistor Qt is connected to the signal output terminal through a frequency divider (3).

9. The overcurrent protection circuit for a switching transistor according to any one of claims 2 - 7, characterized in that The signal conversion circuit (1) is integrated in an integrated chip. The signal input terminal and the signal control terminal respectively form two pins of the integrated chip.

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