Once-readable memory and its operating method

Abstract

A memory controller scrambles input data and stores the scrambled data in a memory. Subsequently, only the stored data is allowed to be read out of the memory once. The memory controller includes a true random number generator for generating a true random number, and a pseudo-random number generator for using the true random number as a seed to generate a pseudo-random number. A linear feedback shift register receives the pseudo-random number and shifts it, and then scrambles the input data using the shift number from the linear feedback shift register. The scrambled data is then stored in the memory, and the seed is stored in one of the same or different memories. In response to a read request, the seed is read out and used to regenerate the shifted numbers to descramble the stored data. The stored seed is invalidated to prevent other attempts to read the data.

Description

Technical Field

[0001] The present invention relates to data memories. Specifically, the present invention relates to a memory in which the stored data can only be read out once. Background Art

[0002] For security or efficiency reasons, data in a system is set to be processed only once in some cases. For example, in edge computing applications, for privacy protection, the locally collected data must be processed to remove specific identification information before it can be stored in the cloud. After the locally collected data is processed, it is cleared from the processor memory. In secure content distribution applications, content such as video or audio data distributed using network protocols is received and stored for access for decoding and playback. Once the data is played, the distributed content must be cleared or invalidated to meet the requirements of copyright protection. Similar application scenarios include communication between modules in a semiconductor system. For example, communication between a processing core and a security root typically includes instructions and requests that should be deleted or cleared after being known.

[0003] It is advantageous to provide a system that ensures that data is securely stored and read out only once. Summary of the Invention

[0004] The present summary is provided to introduce a selected simplified portion of the concepts described in detail in the following detailed description. The present summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0005] According to one embodiment, a memory system is provided that is configured to receive input data in response to a write request, store the data in a memory, and provide the stored data in response to a read request. The memory system includes:

[0006] A digital generator that generates a random number sequence;

[0007] A scrambler connected to the digital generator, the scrambler receiving the random number sequence and performing a scrambling operation on the input data using the random number sequence in response to a write request;

[0008] A memory controller connected to the scrambler, the memory controller receiving the scrambled data from the scrambler and storing the scrambled data in the memory; and

[0009] A descrambler connected to the memory controller to receive the stored data from the memory, the descrambler connected to the digital generator to receive a regenerated random number sequence, wherein the descrambler uses the regenerated random number sequence to descramble the stored data in response to a read request;

[0010] Wherein the digital generator regenerates a random number sequence to be the same as the random number sequence provided to the scrambler to generate scrambled data.

[0011] Exemplarily, the scrambler is configured to perform an operation on each word in the input data with a corresponding random number in the random number sequence to generate scrambled data.

[0012] Exemplarily, the descrambler is configured to perform an operation on each word in the scrambled data with a corresponding random number in the random number sequence to descramble the stored data.

[0013] Exemplarily, the digital generator includes a first digital generator that uses a seed to generate a random number sequence.

[0014] Exemplarily, the digital generator further includes a storage device that stores the seed and provides the seed to the descrambler in response to a read request.

[0015] Exemplarily, the storage device is configured to invalidate the seed stored therein after the seed is provided to the descrambler in response to a read request.

[0016] Exemplarily, the first digital generator is a linear feedback shift register.

[0017] Exemplarily, the digital generator further includes a random number generator that generates a random number as the seed.

[0018] Exemplarily, the random number generator includes:

[0019] A second digital generator configured to generate true random numbers; and

[0020] A third digital generator connected to the second digital generator to receive the true random numbers, the third digital generator using the true random numbers to generate pseudo-random numbers;

[0021] Wherein the pseudo-random numbers are provided to the first digital generator as the seed.

[0022] Exemplarily, the second digital generator is a true random number generator and the third digital generator is a pseudo-random number generator.

[0023] According to another embodiment, a memory protector is provided that stores data in a memory and only allows the stored data to be read out of the memory once. The memory protector includes:

[0024] A first digital generator that uses a seed to generate a random number sequence;

[0025] A scrambler connected to a first digital generator, the scrambler receiving a random number sequence, scrambling input data using the random number sequence in response to a write request, and providing the scrambled data to a memory for storage;

[0026] A storage device that stores a seed in response to a write request and provides the stored seed to the first digital generator in response to a read request; and

[0027] A descrambler connected to the first digital generator to receive a random number sequence generated using the seed provided by the storage device, wherein the descrambler descrambles the stored scrambled data using the random number sequence in response to a read request; and

[0028] Wherein the storage device is configured to invalidate the seed after the seed is provided to the first digital generator.

[0029] Exemplarily, the memory protector further includes:

[0030] A second digital generator that generates a second random number; and

[0031] A third digital generator that uses the second random number to generate a third random number as a seed.

[0032] Exemplarily, the second digital generator is a true random number generator and the second random number is a true random number.

[0033] Exemplarily, the third digital generator is a pseudo-random number generator and the third random number is a pseudo-random number.

[0034] Exemplarily, the storage device provides the seed to the first digital generator in response to a read request to reproduce the random number sequence used for scrambling the data.

[0035] Exemplarily, the first digital generator is a linear feedback shift register.

[0036] According to another embodiment, a method of storing data in a memory and subsequently allowing the stored data to be read out of the memory only once is provided. The method includes:

[0037] Receiving input data;

[0038] Receiving a seed;

[0039] In response to a write request to store the input in the memory, generating a random number sequence using the seed;

[0040] Scrambling the input data using the random number sequence;

[0041] Storing the scrambled input data in the memory;

[0042] Storing the seed corresponding to the input data;

[0043] In response to a read request for reading stored data, a random number sequence is regenerated using a stored seed; and

[0044] The stored data is descrambled using the regenerated random number sequence.

[0045] Exemplarily, the method further includes:

[0046] Generating a true random number using a true random number generator; and

[0047] Generating a pseudo-random number using a pseudo-random number generator as a seed, wherein the pseudo-random number is generated using the true random number.

[0048] Exemplarily, generating a random number sequence using a seed includes generating a random number sequence using a linear feedback shift register.

[0049] Exemplarily, the method further includes: invalidating the seed in response to the stored seed being provided according to the read request. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] To enable the foregoing content of the present invention to be understood in a more specific manner, a further detailed description of the present invention may be obtained by referring to the embodiments, some of which are shown by the accompanying drawings. The accompanying drawings only show typical embodiments of the present invention, and since the present invention may have other equally effective embodiments, the accompanying drawings should not be construed as limiting the scope of the present invention. The drawings are drawn for ease of understanding rather than for measuring the present invention. For those skilled in the art, after reading this description and in combination with the accompanying drawings, the benefits of the claimed inventive subject matter will be readily understood. In the drawings, like reference numerals are used to indicate like elements, and:

[0051] Figure 1 is a block diagram of a memory system according to an exemplary embodiment of the present invention;

[0052] Figure 2 is Figure 1 a block diagram of the memory protector in;

[0053] Figure 3 is a flowchart of a method for writing data into a memory according to an exemplary embodiment of the present invention; and

[0054] Figure 4 is a flowchart of a method for reading data from a memory according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0055] Figure 1FIG. 0 is a block diagram of a memory system 100 according to an exemplary embodiment of the present invention. The memory system 100 includes memories 102 and / or 103 to store data and to retrieve data therefrom. The memory system 100 further includes a memory controller 104 to write data into and to read data from the memories 102 and / or 103. The memory system 100 includes a memory protector 106, which is connected to the memory controller 104. The memory protector 106 scrambles the data before the data is stored in the memories 102 and / or 103 and only allows the data stored in the memories 102 and / or 103 to be read out once. In Figure 1 FIG. 1, the “OTRP” of the memory protector 106 means one-time readable protector. In various implementations of the present invention, the memory 102, the memory controller 104, and the memory protector 106 may be configured to be integrated in a single chip, and then the memory 102 is an “on-chip” memory. In this case, the present invention only uses the on-chip memory 102 and does not have an off-chip memory 103. In some embodiments, the chip may be connected to the off-chip memory 103. For simplicity of description, the present invention will only describe storing data in the memory 103. However, it should be understood that the data may also be stored only using the memory 102 or stored together with the memory 102.

[0056] In operation, the memory protector 106 receives input data from a one-time data source 108. In response to a write request, the memory protector 106 scrambles the input data to generate scrambled data. The scrambled data is provided to the memory controller 104. The memory controller 104 then writes the scrambled data into the memory 103. Subsequently, the memory 103 provides the stored data to the memory controller 104 in response to a read request. The stored data is provided to the memory protector 106 to be descrambled. Thus, the retrieved data is provided to a one-time data sink 110.

[0057] Memory protector 106 uses random numbers to scramble and descramble data. In this preferred embodiment, the data is processed word by word. Memory protector 106 generates a random number for each word of the data and performs a scrambling and / or descrambling operation on each word using the corresponding random number. Thus, for multi-word data to be stored in memory 103, memory protector 106 generates a sequence of random numbers for scrambling. In this preferred embodiment, the random numbers for the data stored in memory 103 are not available after the data is read out and descrambled. This allows the stored data to be restored only once and prevents the stored data from being restored a second time. Making the random numbers unavailable means that memory protector 106 cannot generate the same sequence of random numbers for the data, either by not causing memory protector 106 to generate the random numbers for the data or by clearing the sequence of random numbers stored somewhere. Additionally, the data can be prevented from being descrambled by memory protector 106 by decoupling the correspondence between the scrambled data and its sequence of random numbers.

[0058] Figure 2 shows Figure 1 A block diagram of memory protector 106 in []. Memory protector 106 includes a digital generator 202 that generates a sequence of random numbers for scrambling and / or descrambling data. Digital generator 202 supplies the sequence of random numbers to a scrambler 204, which also receives input data. Scrambler 204 scrambles the input data using the random numbers in response to a write request to write the input data to memory 103. The scrambled data generated by scrambler 204 is supplied to memory controller 104 and then stored in memory 103. In the currently preferred embodiment, scrambler 204 performs a scrambling operation on each word of the input data using a corresponding number in the sequence of random numbers generated by digital generator 202. The algorithm used for scrambling is known and available and will not be described in detail here.

[0059] Digital generator 202 is further connected to a descrambler 206, which further receives the stored data from memory controller 104. In response to a read request to read the stored data from memory 103, digital generator supplies the sequence of random numbers corresponding to the stored data read from memory 103 to descrambler 206. Descrambler 206 uses the sequence of random numbers to perform a descrambling operation on the data to generate descrambled data and supplies the descrambled data to a primary data sink 110. The sequence of random numbers supplied by digital generator 202 to descrambler 206 to descramble the data is the same as the sequence of random numbers used to scramble the same data to ensure that the scrambled data is correctly descrambled. Similar to scrambler 204, descrambler 206 performs a descrambling operation on the scrambled data word by word using a corresponding one from the sequence of random numbers from digital generator 202.

[0060] The digital generator 202 is a three-stage random number generator, which includes a first digital generator L1, a second digital generator L2, and a third digital generator L3. The first digital generator L1 is a true random number generator (TRNG), which generates true random numbers to be used as the seeds for the second digital generator L2. The second digital generator L2 is a pseudo random number generator (PRNG), which uses the seeds from the TRNG L1 to generate pseudo random numbers to be used as the seeds for the third digital generator L3. The third digital generator L3 is a linear feedback shift register (LFSR), which uses the seeds from the PRNG L2 to generate pseudo random numbers. The pseudo random numbers generated by the LFSR L3 are provided to the scrambler 204 and the descrambler 206 as the random number sequences for scrambling and descrambling data.

[0061] The digital generator 202 further includes a storage device 208, which stores the seeds provided by the PRNG L2 to the LFSR L3 and associates the seeds with the write requests. Subsequently, during a read operation in response to a read request that matches a previous write request for the same data, the storage device 208 provides the stored seeds associated with the read request to the LFSR L3, so that the LFSR L3 uses the seeds to generate the same random number sequence for descrambling the data. After the seeds are provided to the LFSR L3 in response to the read request, the storage device 208 invalidates the seeds by clearing or overwriting them. The invalidation of the seeds in the storage device 208 means that the LFSR L3 cannot generate the random number sequence again. Thus, the data stored in the memory 103 cannot be correctly descrambled to restore the pure data, and therefore the data is only allowed to be read once. It can be understood that the storage device 208 may include a memory, a dedicated storage location in the memory, a register, or a dedicated location in a register bank, etc.

[0062] Figure 3 FIG. is a flowchart of a method for writing data to a memory according to an exemplary embodiment of the present invention. The method will be described in conjunction with Figure 1 the memory system 100 in Figure 2The memory protector 106 in it is described. In step 302, the memory system 100 receives a write request for writing data to the memory 103, which includes that the memory protector 106 receives a request for generating a random number sequence, and the scrambler 204 receives input data from the primary data source 108. In step 304, in response to the write request, the LFSR L3 receives a pseudo-random number as a seed. The pseudo-random number is generated by the PRNG L2 using the true random number from the TRNG L1 as a seed. In step 306, the LFSR L3 shifts using the seed from the PRNG L2 and generates a pseudo-random number for each word in the input data. In step 308, the scrambler 204 receives the random number and scrambles the input data word to generate scrambled data. The scrambled data is provided to the memory controller 104 and stored in the memory 103.

[0063] In step 310, it is checked whether all the input data related to the write request has been scrambled and sent to the memory controller 104. If the write request is not completed, step 306 is continued to generate the next random number for scrambling; otherwise, the method executes step 312 to store the seed from the PRNG L2 in the storage device 208 and waits for a subsequent read request.

[0064] Figure 4 A flowchart of a method for reading data from a self-memory according to an exemplary embodiment of the present invention. The method will be described in conjunction with Figure 1 the memory system 100 in Figure 2 the memory protector 106 in Figure 3 and the process of writing to the memory in

[0065] In step 410, it is checked whether all the data read out from the memory 103 have been descrambled. If the read request is not completed, step 406 is continued to generate the next random number for descrambling. If the read request is completed, the method proceeds to step 412 to clear the LFSR L3 to prevent the generation of redundant random numbers.

[0066] The memory system 100 and method of the present invention scramble the data from the primary data source 108 and store the scrambled data in the memory 103. The scrambling operation uses a three-stage random number generator 202 to ensure the security of the data. On the other hand, the scrambled data read out from the memory 103 must be descrambled using the random number sequence used to scramble the same data, so that the read operation is secure and not vulnerable to attacks. Once the data is read out and descrambled, the seed used to generate the random number sequence for descrambling becomes invalid, so that the scrambled data cannot be descrambled again. The data is thus only allowed to be read out once to protect privacy and security.

[0067] The embodiments of the various examples have been described herein with reference to specific, illustrated examples. The examples of the examples are chosen to assist those skilled in the art in forming a clear understanding of the various embodiments and in implementing them. However, the scope of systems, structures, and devices that may be constructed to include one or more embodiments, and the scope of methods implemented in accordance with one or more embodiments, are not limited by the exemplary examples shown. On the contrary, those skilled in the art can understand from this specification that many other configurations, structures, and methods can be implemented in accordance with the various embodiments.

[0068] It should be understood that with respect to the various positional indications used in the foregoing description of the present invention, such as top, bottom, upper, lower, etc., those indications are given only with reference to the corresponding drawings, and when the orientation of the device changes during manufacturing or operation, other positional relationships may instead be had. As described above, those positional relationships are described only for clarity and are not restrictive.

[0069] The foregoing description of the present specification is with reference to specific embodiments and specific drawings, but the present invention should not be limited thereto, but should be given by the claims. The various drawings described are exemplary and not restrictive. In the drawings, for the purpose of illustration, the sizes of the various elements may be enlarged and may not be drawn to a specific scale. The present specification should also include discontinuous transformations of the various elements and the working modes in terms of tolerances and properties. It should also include various weakened embodiments of the present invention.

[0070] As used in this specification and the claims, the term "comprising" does not exclude other elements or steps. Unless specifically stated otherwise, when using the singular form such as "a" or "an" to refer to a defined or undefined element, the plural of that element shall be included. Thus, the term "comprising" should not be construed as being limited to the items listed thereafter, and should not be construed as excluding other elements or steps; the scope of the description "the device comprises items A and B" should not be limited to devices that only include elements A and B. This description means that, for the purposes of this specification, only elements A and B of the device are relevant. "Connected", "coupled", and "coupling" all indicate that there is an electrical connection between the coupled or connected elements, and do not imply that there are no intermediate elements therebetween. When describing a transistor and its connections, the terms gate, drain, and source are interchangeable with gate electrode, drain electrode, source electrode, and gate terminal, drain terminal, source terminal.

[0071] Those skilled in the art can make various specific changes without departing from the scope of the claims of the present invention.

Claims

1. A memory system configured to receive input data in response to a write request, store the data in a memory, and provide the stored data in response to a read request, characterized in that, the memory system comprises: a digital generator that generates a random number sequence; a scrambler connected to the digital generator, the scrambler receiving the random number sequence and performing a scrambling operation on the input data using the random number sequence in response to a write request; a memory controller connected to the scrambler, the memory controller receiving the scrambled data from the scrambler and storing the scrambled data in the memory; and a descrambler connected to the memory controller to receive the stored data from the memory, the descrambler being connected to the digital generator to receive a re-generated random number sequence, wherein the descrambler uses the re-generated random number sequence to descramble the stored data in response to a read request; wherein the digital generator re-generates the random number sequence to be the same as the random number sequence provided to the scrambler to generate the scrambled data; wherein the digital generator includes a first digital generator that uses a seed to generate a random number sequence; the digital generator further includes a storage device that stores the seed and provides the seed to the descrambler in response to a read request; the storage device is configured to invalidate the seed stored therein after the seed is provided to the descrambler in response to a read request.

2. The memory system according to claim 1, characterized in that: the scrambler is configured to perform an operation on each word in the input data with a corresponding random number in the random number sequence to generate the scrambled data.

3. The memory system according to claim 1, characterized in that: the descrambler is configured to perform an operation on each word in the scrambled data with a corresponding random number in the random number sequence to descramble the stored data.

4. The memory system according to claim 1, characterized in that: the first digital generator is a linear feedback shift register.

5. The memory system according to claim 1, characterized in that: the digital generator further includes a random number generator that generates a random number as the seed.

6. The memory system according to claim 5, characterized in that, the random number generator includes: a second digital generator configured to generate true random numbers; and a third digital generator connected to the second digital generator to receive the true random numbers, the third digital generator using the true random numbers to generate pseudo-random numbers; wherein the pseudo-random numbers are provided to the first digital generator as the seed.

7. The memory system according to claim 6, characterized in that: the second digital generator is a true random number generator and the third digital generator is a pseudo-random number generator.

8. A memory protector that stores data in a memory and only allows the stored data to be read out of the memory once, characterized in that, the memory protector comprises: a first digital generator that uses a seed to generate a random number sequence; a scrambler connected to the first digital generator, the scrambler receiving the random number sequence, scrambling the input data using the random number sequence in response to a write request, and providing the scrambled data to the memory for storage; A storage device that stores a seed in response to a write request and provides the stored seed to a first digital generator in response to a read request; and A descrambler connected to the first digital generator to receive a random number sequence generated using the seed provided by the storage device, wherein the descrambler descrambles the stored scrambled data using the random number sequence in response to a read request; and wherein the storage device is configured to invalidate the seed after the seed is provided to the first digital generator.

9. The memory protector according to claim 8, wherein: further comprising: a second digital generator that generates a second random number; and a third digital generator that uses the second random number to generate a third random number as the seed.

10. The memory protector according to claim 9, wherein: The second digital generator is a true random number generator, and the second random number is a true random number.

11. The memory protector according to claim 9, wherein: The third digital generator is a pseudo-random number generator, and the third random number is a pseudo-random number.

12. The memory protector according to claim 8, wherein: The storage device provides the seed to the first digital generator in response to a read request to regenerate the random number sequence for the scrambled data.

13. The memory protector according to claim 8, wherein: The first digital generator is a linear feedback shift register.

14. A method for storing data in a memory and subsequently allowing only the stored data to be read out of the memory once, wherein: the method comprises: receiving input data; receiving a seed; in response to a write request to store the input in the memory, generating a random number sequence using the seed; scrambling the input data using the random number sequence; storing the scrambled input data in the memory; storing the seed corresponding to the input data; in response to a read request to read the stored data, regenerating the random number sequence using the stored seed; descrambling the stored data using the regenerated random number sequence; and invalidating the seed in response to the stored seed being provided according to the read request.

15. The method according to claim 14, wherein: further comprising: generating a true random number using a true random number generator; and generating a pseudo-random number as the seed using a pseudo-random number generator, wherein the pseudo-random number is generated using the true random number.

16. The method according to claim 14, wherein: Generating a random number sequence using the seed includes generating a random number sequence using a linear feedback shift register.

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