Image sensor

Abstract

The image sensor includes a polarizer array and a depth pixel array. The polarizer array may include first to fourth unit pixels arranged in first and second directions intersecting each other, and may include polarization gratings respectively provided in the first to fourth unit pixels. The polarization gratings of the first to fourth unit pixels may have different polarization directions. The depth pixel array may include depth pixels corresponding to the first to fourth unit pixels, respectively. Each of the depth pixels may include a photoelectric conversion device and a first readout circuit and a second readout circuit commonly connected to the photoelectric conversion device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2019-0024003 filed on February 28, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to an image sensor, and in particular, to an image sensor capable of realizing a three-dimensional image. Background Art

[0004] Image sensors are electronic devices that convert optical images into electrical signals. With the recent development of the computer and communications industries, there is an increasing demand for high-performance image sensors in various applications such as digital cameras, video cameras, personal communication systems, game consoles, security cameras, medical miniature cameras, and / or robotics. Furthermore, image sensors that can achieve three-dimensional and / or color images are being developed. Summary of the Invention

[0005] Embodiments of the inventive concept provide an image sensor configured to easily obtain a signal containing information about a polarization state and a depth relative to an object from light emitted toward and reflected by the object.

[0006] According to an embodiment of the present invention, an image sensor may include a polarizer array including first to fourth unit pixels arranged in first and second directions intersecting each other, the polarizer array including polarization gratings respectively disposed in the first to fourth unit pixels. The polarization gratings of the first to fourth unit pixels have different polarization directions. The image sensor further includes a depth pixel array including depth pixels corresponding to the first to fourth unit pixels, respectively. Each of the depth pixels may include a photoelectric conversion device and a first readout circuit and a second readout circuit commonly connected to the photoelectric conversion device.

[0007] According to an embodiment of the present inventive concept, an image sensor may include: a semiconductor substrate having a first surface and a second surface opposing each other and including a plurality of pixel regions; a photoelectric conversion region located in each pixel region of the semiconductor substrate; a first readout circuit and a second readout circuit located on the first surface of the semiconductor substrate in each pixel region; and a polarizer array located on the second surface of the semiconductor substrate. The polarizer array may include polarization gratings disposed in each pixel region. The polarization gratings in the pixel regions may have different polarization directions.

[0008] According to an embodiment of the present inventive concept, an image sensor may include: a polarizer array including first to fourth unit pixels arranged two-dimensionally and including polarization gratings disposed in the first to fourth unit pixels and having different polarization directions; a depth pixel array including depth pixels corresponding to the first to fourth unit pixels, each of the depth pixels including a photoelectric conversion device and first to fourth readout circuits connected to the photoelectric conversion device; and a microlens array including microlenses corresponding to the first to fourth unit pixels, respectively. The polarizer array may be disposed between the microlens array and the depth pixel array. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments will be more clearly understood through the following brief description in conjunction with the accompanying drawings.

[0010] The accompanying drawings represent non-limiting example embodiments described herein.

[0011] Figure 1 is a diagram schematically illustrating an image sensor system according to an embodiment of the inventive concept.

[0012] Figure 2 is a block diagram illustrating an image sensor according to an embodiment of the inventive concept.

[0013] Figure 3 is a block diagram schematically illustrating an active pixel sensor array of an image sensor according to an embodiment of the inventive concept.

[0014] Figure 4 is a circuit diagram illustrating a depth pixel of a 4-tap structure provided in a depth pixel array according to an embodiment of the inventive concept.

[0015] Figure 5 is a schematic plan view illustrating a depth pixel array of an image sensor according to an embodiment of the inventive concept.

[0016] Figure 6 is a plan view illustrating a depth pixel array of an image sensor according to an embodiment of the inventive concept.

[0017] Figure 7 is a plan view illustrating a polarizer array of an image sensor according to an embodiment of the inventive concept.

[0018] Figure 8A 、 Figure 8B and Figure 8C It is along Figure 5 and Figure 7 1 is a cross-sectional view taken along line II′ of FIG. 1 , illustrating an image sensor according to an embodiment of the inventive concept.

[0019] Figure 9 It shows Figure 4 FIG. 1 is a timing diagram of example operations of a depth pixel in an image sensor of FIG.

[0020] Figure 10A is a diagram schematically illustrating an active pixel sensor array of an image sensor according to an embodiment of the inventive concept.

[0021] Figure 10B It shows Figure 10A A plan view of the depth pixel array of the image sensor shown in FIG.

[0022] Figure 11 is a circuit diagram illustrating a depth pixel of a 2-tap structure provided in a depth pixel array of an image sensor according to an embodiment of the inventive concept.

[0023] Figure 12A 、 Figure 13A and Figure 14A Each is a diagram schematically illustrating an active pixel sensor array of an image sensor according to an embodiment of the inventive concept.

[0024] Figure 12B 、 Figure 13B 、 Figure 14B and Figure 14C Each of the Figure 12A 、 Figure 13A and Figure 14A is a plan view of a depth pixel array of a corresponding one of the image sensors shown in .

[0025] Figure 15 It shows Figure 11 A timing diagram of an example operation of a depth pixel in an image sensor is shown in FIG.

[0026] It should be noted that these figures are intended to illustrate the general characteristics of the methods, structures and / or materials utilized in specific example embodiments and are intended to supplement the written description provided below. However, these figures are not necessarily drawn to scale and may not accurately reflect the exact structure or performance characteristics of any given embodiment and should not be interpreted as defining or limiting the range of values ​​or properties encompassed by the example embodiments. For example, the relative thickness and positioning of molecules, layers, regions and / or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numerals in the various figures is intended to indicate the presence of similar or identical elements or features. DETAILED DESCRIPTION

[0027] Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.

[0028] Image sensing can use a time-of-flight (ToF) image sensor and a polarization sensor. Conventional techniques have been proposed to combine images obtained from a ToF sensor and a polarization sensor to provide an accurate depth map. However, this technique uses two cameras, and since this technique requires two cameras, the overall size of the system increases. In addition, for image matching, it may be necessary to calibrate the two cameras. Therefore, some examples are discussed below to address these issues.

[0029] Figure 1 is a diagram schematically illustrating an image sensor system according to an embodiment of the inventive concept.

[0030] Reference Figure 1 , an image sensor system according to an embodiment of the inventive concept is configured to emit light toward an object O, sense light reflected from the object O, and calculate an optical depth or distance D relative to the object O. The image sensor system may include a light source 1 that emits light toward the object O, an image sensor 2 that senses light reflected from the object O, and a timing controller 3 that provides synchronization pulses to the light source 1 and the image sensor 2.

[0031] The light source 1 is configured to emit a light signal EL toward an object O, the light signal EL being provided as a pulse wave. In an embodiment, the light source 1 may be configured to emit infrared light, microwaves, or visible light. For example, a light generator such as a light emitting diode (LED), a laser diode (LD), or an organic light emitting diode (OLED) may be used as the light source 1.

[0032] The image sensor 2 is formed to sense light reflected from the object O and output information about the optical depth to the object O. The optical depth information obtained by the image sensor 2 can be used to estimate a three-dimensional image, such as in an infrared camera. In addition, the image sensor 2 may include depth pixels and visible light pixels, and in this case, a three-dimensional color image can be realized.

[0033] The timing controller 3 may control operations of the light source 1 and the image sensor 2. For example, the timing controller 3 may be configured to synchronize a light emitting operation of the light source 1 with a light receiving operation of the image sensor 2.

[0034] Figure 2 is a block diagram illustrating an image sensor according to an embodiment of the inventive concept.

[0035] Reference Figure 2 , the image sensor may include an active pixel sensor array (APS array) 10, a row decoder 20, a row driver 30, a column decoder 40, a controller 50, a correlated double sampler (CDS) 60, an analog-to-digital converter (ADC) 70, and an input / output buffer (I / O buffer) 80.

[0036] The active pixel sensor array 10 includes a plurality of unit pixels arranged two-dimensionally and can be used to convert optical signals into electrical signals. The active pixel sensor array 10 is driven by a plurality of driving signals (e.g., pixel selection signals, reset signals, and charge transfer signals) sent from the row driver 30. The electrical signals converted by the active pixel sensor array 10 can be provided to the correlated double sampler 60.

[0037] The row driver 30 is configured to generate a driving signal for driving the unit pixel based on the information decoded by the row decoder 20, and then transmit the driving signal to the active pixel sensor array 10. When the unit pixels are arranged in a matrix form (i.e., a plurality of rows and a plurality of columns), the driving signal may be provided to each row.

[0038] The controller 50 controls the overall operation of the image sensor and provides timing signals and control signals to the row decoder 20 and the column decoder 40 .

[0039] The CDS 60 is configured to receive the electrical signal generated by the active pixel sensor array 10 and then perform a hold and sampling operation on the received electrical signal. For example, the CDS 60 may perform a double sampling operation on a specific noise level and signal level of the electrical signal and then output a difference level corresponding to the difference between the noise level and the signal level.

[0040] The ADC 70 is configured to convert an analog signal containing information on the difference level output from the CDS 60 into a digital signal and then output the digital signal.

[0041] The I / O buffer 80 is configured to latch digital signals based on information decoded by the column decoder 40 and then sequentially output the latched digital signals to an image signal processing unit (not shown).

[0042] Figure 3 is a block diagram schematically illustrating an active pixel sensor array of an image sensor according to an embodiment of the inventive concept.

[0043] Reference Figure 3 , the active pixel sensor array 10 includes a plurality of unit pixels P1-P4 arranged two-dimensionally in a first direction D1 and a second direction D2 intersecting each other. As an example, the active pixel sensor array 10 may include first to fourth unit pixels P1 to P4 sequentially arranged in a clockwise direction. As used herein, a unit pixel may refer to a single sensor element of an image sensor and may refer to the smallest addressable photosensitive element of an image sensor.

[0044] The active pixel sensor array 10 may include a depth pixel array 100 and a polarizer array 200 stacked in a third direction D3 perpendicular to the first direction D1 and the second direction D2 .

[0045] The depth pixel array 100 may include a plurality of depth pixels DP arranged two-dimensionally in a first direction D1 and a second direction D2. The depth pixels DP may sense incident light and may output information about an optical depth relative to an object O. Each of the depth pixels DP may include a photoelectric conversion device and a plurality of transistors for processing a signal.

[0046] The polarizer array 200 may include first to fourth polarization gratings 200a to 200d disposed in the first to fourth unit pixels P1 to P4, respectively. The first to fourth polarization gratings 200a to 200d may have different polarization directions from each other.

[0047] In an embodiment, the first polarization grating 200a may be arranged parallel to the first direction D1, the second polarization grating 200b may be arranged to extend in a direction at an angle of 45° relative to the first direction D1, the third polarization grating 200c may be arranged to extend in a direction at an angle of 90° relative to the first direction D1 (i.e., parallel to the second direction D2), and the fourth polarization grating 200d may be arranged to extend in a direction at an angle of 135° relative to the first direction D1 (which may also be described as being arranged to extend in a direction at an angle of 45° relative to the first direction D1 and in a direction at an angle of 90° relative to the direction in which the second polarization grating 200b extends).

[0048] If the light L (i.e., Figure 1 When the light L is incident on the active pixel sensor array 10, the light L may be polarized by the first to fourth polarization gratings 200a to 200d in the first to fourth unit pixels P1 to P4, thereby forming polarized lights PL1 to PL4 incident on the depth pixel array 100.

[0049] If light L is incident on unit pixels P1-P4, each polarization grating 200a-200d can selectively allow a portion of light L having a specific polarization component to be incident on a corresponding depth pixel DP. Specifically, light L passing through the first polarization grating 200a of the first unit pixel P1 can form first polarized light PL1 having a first polarization component and incident on the depth pixel DP of the first unit pixel P1. Light L passing through the second polarization grating 200b of the second unit pixel P2 can form second polarized light PL2 having a second polarization component and incident on the depth pixel DP of the second unit pixel P2. Light L passing through the third polarization grating 200c of the third unit pixel P3 can form third polarized light PL3 ​​having a third polarization component and incident on the depth pixel DP of the third unit pixel P3. Light L passing through the fourth polarization grating 200d of the fourth unit pixel P4 can form fourth polarized light PL4 having a fourth polarization component and incident on the depth pixel DP of the fourth unit pixel P4.

[0050] In the first to fourth unit pixels P1 to P4, polarized lights PL1 to PL4 passing through the polarizer array 200 may have different intensities. In an embodiment, the flight time of each of the first to fourth polarized lights PL1 to PL4 may be calculated in the depth pixel DP of each of the first to fourth unit pixels P1 to P4.

[0051] In an embodiment, the first to fourth unit pixels P1 to P4 including the first to fourth polarization gratings 200a to 200d may constitute a single optical sensor block. Signals obtained from the optical sensor block composed of the first to fourth unit pixels P1 to P4 may be analyzed to calculate the incident light L (i.e., Figure 1 The polarization degree and direction of the reflected light).

[0052] Figure 4 is a circuit diagram illustrating a depth pixel of a 4-tap structure provided in a depth pixel array according to an embodiment of the inventive concept.

[0053] Reference Figure 4 The depth pixel DP of the 4-tap structure may include a photoelectric conversion device PD, first to fourth read circuits RO1 to RO4, and an overflow transistor OX.

[0054] In the depth pixel DP, the first to fourth read circuits RO1 to RO4 may share one photoelectric conversion device PD and one overflow transistor OX. For example, one photoelectric conversion device PD may be electrically connected to the first to fourth read circuits RO1 to RO4 in common.

[0055] The photoelectric conversion device PD can generate charges from light incident thereto and store the charges. The light incident into the depth pixel DP can be polarized light PL1-PL4 provided by the polarizer array 200, as shown in FIG. Figure 3 The photoelectric conversion device PD may be provided in the form of a photodiode, a phototransistor, a photogate, a pinned photodiode, or any combination thereof. For simplicity, the following description will refer to an example in which a photodiode is used as the photoelectric conversion device PD.

[0056] In an embodiment, each of the first to fourth read circuits RO1 to RO4 may include a floating diffusion node FD1, FD2, FD3, or FD4 and a phototransistor PX1, PX2, PX3, or PX4 connected to the floating diffusion node FD1, FD2, FD3, or FD4 and the photoelectric conversion device PD. Furthermore, each of the first to fourth read circuits RO1 to RO4 may further include a capture transistor TGX1, TGX2, TGX3, or TGX4, a storage transistor CX1, CX2, CX3, or CX4, and a transfer transistor TX1, TX2, TX3, or TX4 disposed between the floating diffusion node FD1, FD2, FD3, or FD4 and the phototransistor PX1, PX2, PX3, or PX4.

[0057] Charges generated in the photoelectric conversion device PD can be transferred to floating diffusion nodes FD1 - FD4 through phototransistors PX1 - PX4 , capture transistors TGX1 - TGX4 , storage transistors CX1 - CX4 , and transfer transistors TX1 - TX4 .

[0058] Specifically, phototransistors PX1-PX4 can be controlled by a photogate signal, and the photogate signals (applied to the photogates of phototransistors PX1-PX4 from photogate electrodes PGA-PGD) for the first to fourth readout circuits RO1 to RO4 can have different phases. Capture transistors TGX1-TGX4 can be controlled by capture signals (applied to the capture gates of capture transistors TGX1-TGX4 from capture gate electrodes TGA-TGD). In response to the capture signals, capture transistors TGX1-TGX4 can store charge therein or transfer charge to storage transistors CX1-CX4, respectively. In response to storage control signals (applied to the storage gates of storage transistors CX1-CX4 from storage gate electrodes SG1-SG4), storage transistors CX1-CX4 can store charge therein or transfer charge to transfer transistors TX1-TX4, respectively. Transfer transistors TX1-TX4 can be connected between the drains of phototransistors PX1-PX4 and the gates of amplifier transistors SF1-SF4. Transfer transistors TX1-TX4 can be controlled by transfer signals (from transfer gate electrodes TG1-TG4 applied to the transfer gates of transfer transistors TX1-TX4), respectively. The above description of connections between transfers refers to electrical connections and may also refer to physical layout connections.

[0059] Although not shown in the figure, in an embodiment, a storage diode connected between the storage transistors CX1-CX4 and the transfer transistors TX1-TX4 may be provided in each of the read circuits RO1-RO4. ​​The storage diode may have a structure similar to that of the photoelectric conversion device PD (i.e., doped with an impurity region having a conductivity type different from that of the semiconductor substrate), or may be provided in the form of a capacitor.

[0060] In each read circuit RO1-RO4, if the phototransistors PX1-PX4 are turned on, photocharges may be generated in the photoelectric conversion device PD, and when the transfer transistors TX1-TX4 are turned on, such photocharges may be transferred to and stored in the floating diffusion nodes FD1-FD4.

[0061] In each of the first to fourth read circuits RO1 to RO4, the stored charge may be periodically discharged from the floating diffusion nodes FD1-FD4 through the reset transistors RX1, RX2, RX3, or RX4, so that the floating diffusion nodes FD1-FD4 are reset. In each of the read circuits RO1-RO4, the reset transistors RX1-RX4 may include a source connected to the floating diffusion nodes FD1-FD4, a resistor connected to a power supply voltage V DD and a drain connected to the reset gate electrodes RG1-RG4.

[0062] Charge can be accumulated in the floating diffusion nodes FD1-FD4 of each readout circuit RO1-RO4, and the amount of charge accumulated in the floating diffusion nodes FD1-FD4 can be controlled by the amplifier transistors SF1-SF4. The amplifier transistors SF1-SF4 can be source-follower-buffer amplifiers whose source-drain current is controlled by the potential of their gate electrodes.

[0063] In each of the first to fourth read circuits RO1 to RO4, a signal proportional to the potential at the floating diffusion nodes FD1-FD4 may be amplified by the amplification transistors SF1-SF4, and the amplified signal may be output to the output line V through the selection transistors SX1-SX4. OUT 1-V OUT 4. The selection transistors SX1-SX4 may be connected to a selection gate electrode SEL.

[0064] The photo transistors PX1-PX4 of the first to fourth reading circuits RO1 to RO4 can be controlled by photo gate signals with different phases. Due to the phase difference between the photo gate signals, the photo transistors PX1-PX4 can be controlled by the first output line V OUT 1 to the fourth output line V OUT 4 output different signals.

[0065] In each depth pixel DP, an overflow transistor OX can be controlled by an overflow control signal OG. When the first to fourth transfer transistors TX1 to TX4 are turned off, the overflow transistor OX can be turned on. When the first to fourth transfer transistors TX1 to TX4 are turned off, photocharges generated in the photoelectric conversion device PD can be discharged through the overflow transistor OX. During the operation of detecting photocharges in the first to fourth floating diffusion nodes FD1 to FD4, the overflow transistor OX prevents the charges generated in the photoelectric conversion device PD from overflowing to the first to fourth floating diffusion nodes FD1 to FD4.

[0066] In an embodiment, Figure 4 Unlike the embodiment shown in , the capture transistors TGX1 - TGX4 , the storage transistors CX1 - CX4 , the transfer transistors TX1 - TX4 , and the overflow transistor OX may be omitted from the first to fourth read circuits RO1 to RO4 .

[0067] Figure 5 is a schematic plan view illustrating a depth pixel array of an image sensor according to an embodiment of the inventive concept. Figure 6 is a plan view illustrating a depth pixel array of an image sensor according to an embodiment of the inventive concept. Figure 7 is a plan view illustrating a polarizer array of an image sensor according to an embodiment of the inventive concept.

[0068] Reference Figure 5 、 Figure 6 and Figure 7 , the depth pixel array 100 may include a plurality of unit pixels P1-P4 arranged in each of two orthogonal directions (e.g., a first direction D1 and a second direction D2). The unit pixels P1-P4 may include a first unit pixel P1 and a second unit pixel P2 adjacent to each other in the first direction D1, a third unit pixel P3 adjacent to the second unit pixel P2 in the second direction D2, and a fourth unit pixel P4 adjacent to the first unit pixel P1 in the second direction D2. The first to fourth unit pixels P1 to P4 may be arranged sequentially in a clockwise direction.

[0069] Reference Figure 5 and Figure 6 In each of the first to fourth unit pixels P1 to P4, the depth pixel may include a reference pixel. Figure 4 The first to fourth reading circuits RO1 to RO4 described above can share a reference circuit in each depth pixel. Figure 4 The photoelectric conversion device PD and the overflow transistor OX described above may include reference Figure 4Description of the transistor.

[0070] According to an embodiment of the present invention, in the depth pixel array 100, the first unit pixel P1 and the second unit pixel P2 (and therefore the layout of the first read circuit RO1 to the fourth read circuit RO4 for the first unit pixel P1 and the second unit pixel P2, and the circuit elements of the first read circuit RO1 to the fourth read circuit RO4 for the first unit pixel P1 and the second unit pixel P2) are arranged in a mirror-symmetrical manner with respect to a line parallel to the second direction D2, and the third unit pixel P3 and the fourth unit pixel P4 (and therefore the layout of the first read circuit RO1 to the fourth read circuit RO4 for the third unit pixel P3 and the fourth unit pixel P4, and the circuit elements of the first read circuit RO1 to the fourth read circuit RO4 for the third unit pixel P3 and the fourth unit pixel P4) are also arranged in a mirror-symmetrical manner with respect to the line parallel to the second direction D2. In addition, the first unit pixel P1 and the fourth unit pixel P4 (and therefore the layout of the first to fourth reading circuits RO1 to RO4 for the first unit pixel P1 and the fourth unit pixel P4, and the circuit elements of the first to fourth reading circuits RO1 to RO4 for the first unit pixel P1 and the fourth unit pixel P4) can be arranged in a mirror-symmetrical manner with respect to a line parallel to the first direction D1, and the second unit pixel P2 and the third unit pixel P3 (and therefore the layout of the first to fourth reading circuits RO1 to RO4 for the second unit pixel P2 and the third unit pixel P3, and the circuit elements of the first to fourth reading circuits RO1 to RO4 for the second unit pixel P2 and the third unit pixel P3) can be arranged in a mirror-symmetrical manner with respect to a line parallel to the first direction D1. For example, the fourth reading circuit RO4 of the first to fourth unit pixels P1 to P4 can be arranged adjacent to each other in the first direction D1 and the second direction D2.

[0071] In an embodiment, Figure 6 As shown in , the first to fourth reading circuits RO1 to RO4 of the first to fourth unit pixels P1 to P4 may include first to fourth photogate electrodes PGA to PGD and first to fourth floating diffusion nodes FD1 to FD4, respectively. Figure 6 In the embodiment, each read circuit RO1-RO4 is shown as including a photo gate electrode PGA-PGD and a floating diffusion node FD1-FD4, but the present invention is not limited to such an example. For example, a plurality of gate electrodes may be provided between the photo gate electrodes PGA-PGD and the floating diffusion nodes FD1-FD4.

[0072] In each of the first to fourth unit pixels P1 to P4 , the first to fourth photo gate electrodes PGA to PGD may be arranged adjacent to each other in the first and second directions D1 and D2 .

[0073] For example, the photogate electrodes PGA and PGB and the floating diffusion nodes FD1 and FD2 of the first read circuit RO1 and the second read circuit RO2 may be arranged in a mirror-symmetrical manner with respect to a line parallel to the second direction D2. The photogate electrodes PGC and PGD and the floating diffusion nodes FD3 and FD4 of the third read circuit RO3 and the fourth read circuit RO4 may be arranged in a mirror-symmetrical manner with respect to a line parallel to the second direction D2. In addition, the photogate electrodes PGA and PGB and the floating diffusion nodes FD1 and FD2 of the first read circuit RO1 and the second read circuit RO2, as well as the photogate electrodes PGC and PGD and the floating diffusion nodes FD3 and FD4 of the third read circuit RO3 and the fourth read circuit RO4 may be arranged in a mirror-symmetrical manner with respect to a line parallel to the first direction D1.

[0074] In addition, due to the symmetrical arrangement of the depth pixels of the first to fourth unit pixels P1 to P4 , the fourth floating diffusion nodes FD4 of the first to fourth unit pixels P1 to P4 may be disposed adjacent to each other in the first and second directions D1 and D2 .

[0075] In an embodiment, Figure 5 and Figure 6 The first to fourth unit pixels P1 to P4 arranged as shown in the figure may constitute a single block, and a plurality of blocks may be regularly arranged in the first direction D1 and the second direction D2. Each block of unit pixels in this embodiment is also referred to as a unit pixel block or a single unit pixel block, which includes Figure 5 and Figure 6 The same number and layout of unit pixels are arranged in the manner shown in FIG.

[0076] Reference Figure 7 The polarizer array 200 may include polarization gratings 200a, 200b, 200c, and 200d having four different polarization directions (e.g., relative to a first direction D1 extending toward the right) of 0°, 45°, 90°, and 135°. In certain embodiments, the polarizer array 200 may include polarization gratings having two different polarization directions of 0° and 90°.

[0077] A first polarization grating 200a may be provided in the first unit pixel P1 and may be a line pattern extending parallel to the first direction D1. A second polarization grating 200b may be provided in the second unit pixel P2 and may be a line pattern extending at a 45° angle relative to the first direction D1. A third polarization grating 200c may be provided in the third unit pixel P3 and may be a line pattern extending parallel to the second direction D2. A fourth polarization grating 200d may be provided in the fourth unit pixel P4 and may be a line pattern extending at a 135° angle relative to the first direction D1. The polarization gratings 200a-200d in the first to fourth unit pixels P1 to P4 may be substantially identical in size and pitch.

[0078] Figure 8A 、 Figure 8B and Figure 8C It is along Figure 5 and Figure 7 1 is a cross-sectional view taken along line II′ of FIG. 1 , illustrating an image sensor according to an embodiment of the inventive concept.

[0079] Reference Figure 5 、 Figure 7 、 Figure 8A 、 Figure 8B and Figure 8C , an image sensor according to an embodiment of the present inventive concept may include a depth pixel array 100, a polarizer array 200, and a microlens array. When viewed in a cross-sectional view, the polarizer array 200 may be disposed between the microlens array including the microlenses ML and the depth pixel array 100.

[0080] The depth pixel array 100 may include a semiconductor substrate 100s, a pixel isolation structure 110 disposed to define unit pixels P1-P4 in the semiconductor substrate 100s, and photoelectric conversion devices PD disposed in the unit pixels P1-P4, respectively.

[0081] Specifically, the semiconductor substrate 100s may have a first surface or front surface 100a and a second surface or back surface 100b opposite to each other. In an embodiment, a substrate in which an epitaxial layer of a first conductivity type (e.g., p-type) is formed on a bulk silicon substrate of the first conductivity type may be provided for the semiconductor substrate 100s. During the process of manufacturing the image sensor, the bulk silicon substrate may be removed, leaving only the p-type epitaxial layer. In a specific embodiment, the semiconductor substrate 100s may be a bulk semiconductor wafer having a well of the first conductivity type formed therein.

[0082] The semiconductor substrate 100s may include first to fourth unit pixels P1 to P4 defined by a pixel isolation structure 110. The first to fourth unit pixels P1 to P4 may be arranged in a matrix shape (eg, in the first and second directions D1 and D2 as described above).

[0083] When viewed in a plan view, the pixel isolation structure 110 may be disposed so as to surround each of the first to fourth unit pixels P1 to P4. Specifically, the pixel isolation structure 110 may include a first portion extending parallel to a first direction D1 and a second portion extending parallel to a second direction D2 to intersect the first portion. When viewed in a plan view, the pixel isolation structure 110 may surround each of the photoelectric conversion devices PD.

[0084] The pixel isolation structure 110 may be formed of an insulating material having a refractive index lower than that of the semiconductor substrate 100s (e.g., silicon), and may include one or more insulating layers. For example, the pixel isolation structure 110 may be formed of a silicon oxide layer, a silicon nitride layer, an undoped polysilicon layer, a gaseous material, or any combination thereof. Forming the pixel isolation structure 110 may include patterning the first surface 100a and / or the second surface 100b of the semiconductor substrate 100s to form deep trenches, and filling the deep trenches with an insulating material.

[0085] The photoelectric conversion devices PD may be provided in the first to fourth unit pixels P1 to P4 of the semiconductor substrate 100s, respectively. The photoelectric conversion devices PD may be arranged two-dimensionally in a first direction D1 and a second direction D2. In an embodiment, the photoelectric conversion devices PD may be formed by implanting impurities into the semiconductor substrate 100s, and the photoelectric conversion devices PD may have a second conductivity type different from the first conductivity type of the semiconductor substrate 100s. In this case, the first conductivity type semiconductor substrate 100s and the second conductivity type photoelectric conversion devices PD may form a pn junction functioning as a photodiode. The photoelectric conversion devices PD may convert light passing through the polarizer array 200 into an electrical signal.

[0086] In each of the first to fourth unit pixels P1 to P4, referring to Figure 4 The described first to fourth read circuits RO1 to RO4 may be disposed on the first surface 100 a of the semiconductor substrate 100 s.

[0087] In detail, when viewed in a plan view, the first to fourth photogate electrodes PGA to PGD may overlap a middle portion of each of the first to fourth unit pixels P1 to P4, and a gate insulating layer may be interposed between the first to fourth photogate electrodes PGA to PGD and the semiconductor substrate 100s.

[0088] As an example, in the unit pixels P1-P4, the storage gate electrodes SG1-SG4 may be disposed adjacent to the first to fourth photogate electrodes PGA to PGD. In addition, the storage diode regions SD1 and SD2 may be disposed between the storage gate electrodes SG1-SG4 and the storage diode regions SD1 and SD2. Figure 4 Storage diode regions SD1 and SD2 are formed between transfer transistors TX1-TX4 and in semiconductor substrate 100s. Impurities may be implanted into semiconductor substrate 100s to form storage diode regions SD1 and SD2, and the storage diode regions SD1 and SD2 may have a different conductivity type from that of semiconductor substrate 100s. In plan view, storage diode regions SD1 and SD2 may partially overlap with storage gate electrodes SG1-SG4. Charge generated in photoelectric conversion device PD may be stored in storage diode regions SD1 and SD2.

[0089] In addition, although Figures 8A to 8C Although not shown, the floating diffusion nodes FD1-FD4 may be formed by implanting impurities into the semiconductor substrate 100s, and the floating diffusion nodes FD1-FD4 may have a conductivity type different from that of the semiconductor substrate 100s. For example, the floating diffusion nodes FD1-FD4 may be n-type impurity regions doped in the semiconductor substrate 100s.

[0090] In addition, a blocking impurity region 105 may be provided in the semiconductor substrate 100s. When viewed in a cross-sectional view, the blocking impurity region 105 may be provided between the photoelectric conversion device PD and the storage diode regions SD1 and SD2, and the floating diffusion nodes FD1-FD4. The blocking impurity region 105 may be formed by implanting impurities into the semiconductor substrate 100s and may have the same conductivity type as the semiconductor substrate 100s.

[0091] In an embodiment, a fixed charge layer 210 may be disposed on the second surface 100 b of the semiconductor substrate 100 s , and the polarization gratings 200 a - 200 d may be disposed on the fixed charge layer 210 .

[0092] The fixed charge layer 210 covers the second surface 100b of the semiconductor substrate 100s. The fixed charge layer 210 may be formed on the second surface 100b of the semiconductor substrate 100s. In some embodiments, the fixed charge layer 210 may be formed to contact the second surface 100b of the semiconductor substrate 100s. As used herein, the term "contact" refers to direct connection (i.e., touching). The fixed charge layer 210 may include negative charges, and the negative charges may couple with holes that may be generated by surface defects on the second surface 100b of the semiconductor substrate 100s. Therefore, black current that may be generated from the second surface 100b of the semiconductor substrate 100s can be suppressed. For example, the fixed charge layer 210 may be formed of or include at least one of Al2O3, CeF3, HfO2, ITO, MgO, Ta2O5, TiO2, ZrO2, Si, Ge, ZnSe, ZnS, and PbF2.

[0093] In each of the unit pixels P1-P4, the polarization gratings 200a-200d may be parallel to each other and may have a linear shape. When viewed in a plan view, the polarization gratings 200a-200d may cross each of the photoelectric conversion devices PD.

[0094] In detail, such as Figure 7 and Figure 8A As shown, the first polarization grating 200a in the first unit pixel P1 may be a linear pattern parallel to the first direction D1. The second polarization grating 200b in the second unit pixel P2 may be a linear pattern at a 45° angle to the first polarization grating 200a. The third polarization grating 200c in the third unit pixel P3 may be a linear pattern at a 90° angle to the first polarization grating 200a. The fourth polarization grating 200d in the fourth unit pixel P4 may be a linear pattern at a 135° angle to the first polarization grating 200a. As discussed herein, and for ease of description, a group of polarization grating lines extending in the same direction (e.g., a grating group in any one of the unit pixels P1-P4) may be referred to as a grating block. Individual lines in a grating block may be referred to as grating lines.

[0095] In each of the first to fourth unit pixels P1 to P4, the first to fourth polarization gratings 200a to 200d may be arranged to have uniform widths and uniform heights and may be spaced apart from each other by a specific distance. For example, each polarization grating block may be arranged to have polarization grating lines, each line having the same width and height as the other lines in the block, wherein the grating lines in the grating block are equally spaced from each other. Furthermore, in plan view, each polarization grating block may have the same size and shape as the other polarization grating blocks, and the polarization grating lines in all polarization grating blocks may have the same height and the same width in a direction perpendicular to the direction in which they extend, and may be spaced apart from each other by the same distance.

[0096] Each of the first to fourth polarization gratings 200a to 200d may include a conductive pattern 212 and a dielectric pattern 214 stacked sequentially. The conductive pattern 212 may be formed of or include a metal material such as tungsten, aluminum, titanium, tantalum, or copper. The dielectric pattern 214 may be formed of or include an insulating material such as SiN, SiON, SiC, SICN, or SiCO.

[0097] The formation of the first to fourth polarization gratings 200 a to 200 d may include sequentially depositing a dielectric layer and a conductive layer on the fixed charge layer 210 , and then patterning the conductive layer and the dielectric layer.

[0098] The insulating planarization layer 260 may be disposed on the fixed charge layer 210 provided with the first to fourth polarization gratings 200a to 200d. The insulating planarization layer 260 may be disposed to fill the gaps between the first to fourth polarization gratings 200a to 200d. For example, the insulating planarization layer 260 may be formed of or include at least one of Al2O3, CeF3, HfO2, ITO, MgO, Ta2O5, TiO2, ZrO2, Si, Ge, ZnSe, ZnS, and PbF2. In an embodiment, the insulating planarization layer 260 may be formed of or include at least one organic material having a high refractive index (e.g., siloxane resin, benzocyclobutene (BCB), polyimide, acrylic acid, polypropylene glycol, polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), etc.). In a specific embodiment, for example, the insulating planarization layer 260 may be formed of or may include at least one of strontium titanate (SrTiO3), polycarbonate, glass, bromine, sapphire, cubic zirconia, potassium niobate (KNbO3), moissanite (SiC), gallium (III) phosphide (GaP), gallium (III) arsenide (GaAs), etc.

[0099] Reference Figure 8B Each of the first to fourth polarization gratings 200a to 200d may include a first dielectric pattern 222 disposed on the fixed charge layer 210 and a second dielectric layer 224 covering the first dielectric pattern 222. Here, the first dielectric pattern 222 may be formed of or include a dielectric material having a refractive index different from that of the second dielectric layer 224. Furthermore, each of the first dielectric patterns 222 may have inclined sidewalls facing each other. For example, the first dielectric pattern 222 may include a wedge-shaped piece or portion. The second dielectric layer 224 may be disposed to conformally cover the exposed surface of the first dielectric pattern 222.

[0100] Reference Figure 8C The first to fourth polarization gratings 200 a to 200 d may be disposed on the second surface 100 b of the semiconductor substrate 100 s and may be formed from the second surface 100 b of the semiconductor substrate 100 s.

[0101] The first to fourth polarization gratings 200a to 200d may be recessed regions formed by forming an etching mask pattern on the second surface 100b of the semiconductor substrate 100s and then anisotropically etching the second surface 100b of the semiconductor substrate 100s using the etching mask pattern. The first to fourth polarization gratings 200a to 200d may be portions of the semiconductor substrate 100s. The recessed regions formed in the semiconductor substrate 100s may be defined by inclined surfaces that oppose each other. In other words, the first to fourth polarization gratings 200a to 200d may have a wedge shape.

[0102] The fixed charge layer 210 may be disposed to conformally cover the first to fourth polarization gratings 200a to 200d disposed on the second surface 100b of the semiconductor substrate 100s. The fixed charge layer 210 contacts the first to fourth polarization gratings 200a to 200d.

[0103] The anti-reflection layer 230 may be provided on the second surface 100b of the semiconductor substrate 100s provided with the first to fourth polarization gratings 200a to 200d. The anti-reflection layer 230 may be provided between the fixed charge layer 210 and the insulating planarization layer 260. For example, the anti-reflection layer 230 may be formed of or include at least one of SiON, SiC, SICN, and SiCO.

[0104] Reference Figures 8A to 8C , microlenses ML may be provided on the insulating planarization layer 260 to correspond to the photoelectric conversion devices PD, respectively. The microlenses ML may be arranged two-dimensionally in two different directions (e.g., a first direction D1 and a second direction D2). The microlenses ML may have an upwardly convex shape and may have a specific radius of curvature. The microlenses ML may change the path of light incident on the image sensor to converge the incident light. The microlenses ML may be formed of or include an optically transparent resin.

[0105] Figure 9 It shows Figure 4 A timing diagram of the operation of a depth pixel in an image sensor.

[0106] Reference Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 and Figure 9, a pulse light signal EL can be emitted from the light source 1 to the object O, such as Figure 1 As shown. Part of the light signal EL may be reflected by the object O to form reflected light incident on the unit pixels P1-P4. Here, the reflected light may be delayed compared to the light signal EL. Although each pulse of the light signal EL is Figure 9 1 is shown as having a rectangular waveform, but the light signal EL may also be provided in the form of a sine wave.

[0107] In each unit pixel P1-P4, the pixel and the object O (eg, see Figure 1 ) of the optical signal EL (see, for example, Figure 1 ) is applied to the first photogate electrode PGA, and a third photocontrol signal PGC_180 having a phase difference of 180° with respect to the first photocontrol signal PGA_0 may be applied to the third photogate electrode PGC. A second photocontrol signal PGB_90 having a phase difference of 90° with respect to the first photocontrol signal PGA_0 may be applied to the second photogate electrode PGB, and a fourth photocontrol signal PGD_270 having a phase difference of 180° with respect to the second photocontrol signal PGB_90 may be applied to the fourth photogate electrode PGD.

[0108] In the case where the depth pixel has a 4-tap structure, the first to fourth photo control signals PGA_0 , PGB_90 , PGC_180 , and PGD_270 may be sequentially applied to the first to fourth photo gate electrodes PGA to PGD at specific time intervals in one sampling period.

[0109] The first to fourth photo control signals PGA_0 to PGD_270 applied to the first to fourth photo gate electrodes PGA to PGD may cause a potential of the photoelectric conversion device PD to change.

[0110] The amount of charge detected from the first to fourth floating diffusion nodes FD1 to FD4 may vary depending on the length of overlap between the reflected light signal RL and the first to fourth photoelectric control signals. Furthermore, the signals output from the first to fourth readout circuits RO1 to RO4 in each of the unit pixels P1 to P4 may include depth information derived from polarized light.

[0111] Specifically, the first group of first to fourth read circuits RO1 to RO4 can output light having a first polarization component and passing through the first polarization grating 200a in the first unit pixel P1 as different electrical signals. The second group of first read circuits RO1 to RO4 can output light having a second polarization component and passing through the second polarization grating 200b in the second unit pixel P2 as different electrical signals. The third group of first read circuits RO1 to RO4 can output light having a third polarization component and passing through the third polarization grating 200c in the third unit pixel P3 as different electrical signals. The fourth group of first read circuits RO1 to RO4 can output light having a fourth polarization component and passing through the fourth polarization grating 200d in the fourth unit pixel P4 as different electrical signals.

[0112] Figure 10A is a diagram schematically illustrating an active pixel sensor array of an image sensor according to an embodiment of the inventive concept. Figure 10B It shows Figure 10A A plan view of the depth pixel array of the image sensor shown in FIG.

[0113] Reference Figure 10A , each group of the first to fourth unit pixels P1 to P4 may constitute a single optical sensor block, and a plurality of optical sensor blocks may be two-dimensionally arranged in the first direction D1 and the second direction D2.

[0114] Each of the first to fourth unit pixels P1 to P4 may include one of the polarization gratings 200a-200d and a depth pixel including the first to fourth read circuits RO1 to RO4, as described above. The polarization gratings 200a-200d of the first to fourth unit pixels P1 to P4 may have different polarization directions from each other, as previously described with reference to FIG. Figure 7 Description.

[0115] The first unit pixel P1 may include a first polarization grating 200a and first to fourth readout circuits RO1 to RO4 corresponding to the first polarization grating 200a. The second unit pixel P2 may include a second polarization grating 200b and first to fourth readout circuits RO1 to RO4 corresponding to the second polarization grating 200b. The third unit pixel P3 may include a third polarization grating 200c and first to fourth readout circuits RO1 to RO4 corresponding to the third polarization grating 200c. The fourth unit pixel P4 may include a fourth polarization grating 200d and first to fourth readout circuits RO1 to RO4 corresponding to the fourth polarization grating 200d.

[0116] In the depth pixel array 100, the first unit pixel P1 and the second unit pixel P2, which are adjacent to each other in the first direction D1, can be arranged in a mirror-symmetrical manner with respect to a line parallel to the second direction D2. Furthermore, the first unit pixel P1 and the second unit pixel P2 can be arranged in a mirror-symmetrical manner with respect to a line parallel to the first direction D1, and the third unit pixel P3 and the fourth unit pixel P4 can be arranged in a mirror-symmetrical manner with respect to the line parallel to the first direction D1. Therefore, the fourth read circuit RO4 of the first unit pixel P1 to the fourth unit pixel P4 can be arranged adjacent to each other in the first direction D1 and the second direction D2. Furthermore, the first read circuit RO1 to the third read circuit RO3 can be arranged in the same manner.

[0117] exist Figure 10A and Figure 10B In the illustrated embodiment, by performing one operation of sensing a single optical sensor block consisting of the first to fourth unit pixels P1 to P4, information on polarization states in four directions and depth information generated by photo gate signals of four different phases can be obtained.

[0118] Furthermore, polarization information or depth information may be selectively obtained depending on how the region S1 , S2 , or S3 is selected to sum signals to be output from the first to fourth reading circuits RO1 to RO4 of the first to fourth unit pixels P1 to P4 .

[0119] As an example, by summing the first to fourth output signals output from the first to fourth reading circuits RO1 to RO4 of the first unit pixel P1, information about the first polarized light PL1 having the first polarization state (for example, see Figure 3 By summing the first to fourth output signals output from the first to fourth reading circuits RO1 to RO4 of the second unit pixel P2, information about the second polarized light PL1 having the second polarization state (for example, see Figure 3 By summing the first to fourth output signals output from the first to fourth reading circuits RO1 to RO4 of the third unit pixel P3, information about the third polarized light PL3 ​​having a third polarization state (for example, see Figure 3 By summing the first to fourth output signals output from the first to fourth reading circuits RO1 to RO4 of the fourth unit pixel P4, information about the fourth polarized light PL4 (for example, see FIG. Figure 3 )’s depth information.

[0120] In an embodiment, depth information can be obtained by summing the fourth output signals outputted from the fourth reading circuit (i.e., region S2) of the first unit pixel P1 to the fourth unit pixel P4 (i.e., four fourth reading circuits). For example, the depth information may include polarized light PL1, PL2, PL3, and PL4 (e.g., see FIG. 1 ) having first to fourth polarization components and passing through the first to fourth polarization gratings. Figure 3 ) is the mean of .

[0121] In an embodiment, depth information may be obtained by obtaining first to fourth output signals respectively output from the first to fourth readout circuits RO1 to RO4 (ie, region S3 ) from photo gate signals having four different phases.

[0122] Figure 11 1 is a circuit diagram showing a depth pixel of a 2-tap structure provided in a depth pixel array of an image sensor according to an embodiment of the present invention. The difference between the 2-tap structure and the 4-tap structure is that the 2-tap structure has only two readout circuits per unit pixel, while the 4-tap structure has four readout circuits per unit pixel. Figure 4 Essentially the same features as described.

[0123] Reference Figure 11 The depth pixel of the 2-tap structure may include a photoelectric conversion device PD, a first readout circuit RO1 and a second readout circuit RO2, and an overflow transistor OX.

[0124] The first read circuit RO1 and the second read circuit RO2 may be configured to have the same Figure 4 The first reading circuit RO1 and the second reading circuit RO2 described above have substantially the same structure. In addition, the first reading circuit RO1 and the second reading circuit RO2 can share one photoelectric conversion device PD and one overflow transistor OX.

[0125] Figure 12A 、 Figure 13A and Figure 14A Each is a diagram schematically illustrating an active pixel sensor array of an image sensor according to an embodiment of the inventive concept. Figure 12B 、 Figure 13B 、 Figure 14B and Figure 14C Each of the Figure 12A 、 Figure 13A and Figure 14A is a plan view of a depth pixel array of a corresponding one of the image sensors shown in .

[0126] Reference 12A to 14AEach of the first to fourth unit pixels P1 to P4 in the depth pixel array 100 may include a photoelectric conversion device PD, a first read circuit RO1 and a second read circuit RO2, and an overflow transistor OX, as shown in FIG. Figure 11 Description.

[0127] The polarizer array 200 may include polarization gratings 200 a - 200 d respectively disposed in the first to fourth unit pixels P1 to P4 and aligned in different directions, as described above.

[0128] The first unit pixel P1 may include a first polarization grating 200a and first and second readout circuits RO1 and RO2 corresponding to the first polarization grating 200a. The second unit pixel P2 may include a second polarization grating 200b and first and second readout circuits RO1 and RO2 corresponding to the second polarization grating 200b. The third unit pixel P3 may include a third polarization grating 200c and first and second readout circuits RO1 and RO2 corresponding to the third polarization grating 200c. The fourth unit pixel P4 may include a fourth polarization grating 200d and first and second readout circuits RO1 and RO2 corresponding to the fourth polarization grating 200d.

[0129] As described above, the first to fourth unit pixels P1 to P4 may constitute a single optical sensor block, and a plurality of optical sensor blocks may be two-dimensionally arranged in the first and second directions D1 and D2.

[0130] Reference Figure 12A and Figure 12B In the depth pixel array 100, the first unit pixel P1 and the second unit pixel P2 (each of which includes a first read circuit RO1 and a second read circuit RO2) may be arranged alternately in the first direction D1. In addition, the third unit pixel P3 and the fourth unit pixel P4 (each of which includes a first read circuit RO1 and a second read circuit RO2) may be arranged alternately in the first direction D1. Here, the first read circuits RO1 of the first unit pixel P1 and the second unit pixel P2 may be adjacent to each other, and the second read circuits RO2 of the first unit pixel P1 and the second unit pixel P2 may be adjacent to each other. Similarly, the first read circuits RO1 of the third unit pixel P3 and the fourth unit pixel P4 may be adjacent to each other, and the second read circuits RO2 of the third unit pixel P3 and the fourth unit pixel P4 may be adjacent to each other.

[0131] Reference Figure 13A and Figure 13B In each of the first to fourth unit pixels P1 to P4 , the first and second read circuits RO1 and RO2 may be arranged in a diagonal direction with respect to the first and second directions D1 and D2 .

[0132] The first unit pixel P1 and the second unit pixel P2 adjacent to each other in the first direction D1 may be arranged in a mirror-symmetrical manner, and the third unit pixel P3 and the fourth unit pixel P4 adjacent to each other in the first direction D1 may be arranged in a mirror-symmetrical manner. In addition, the first unit pixel P1 and the fourth unit pixel P4 adjacent to each other in the second direction D2 may be arranged in a mirror-symmetrical manner, and the second unit pixel P2 and the third unit pixel P3 adjacent to each other in the second direction D2 may be arranged in a mirror-symmetrical manner. The first unit pixels P1 to the fourth unit pixels P4 adjacent to each other may be arranged in a mirror-symmetrical manner in the first direction D1 and the second direction D2.

[0133] Reference Figure 14A 、 Figure 14B and Figure 14C , each of the first to fourth unit pixels P1 to P4 may include a pair of reading circuits, and an adjacent pair of unit pixels may be configured to obtain depth information from photo gate signals having four different phases.

[0134] For example, Figure 14A and Figure 14B As shown in FIG, each of the first unit pixel P1 and the third unit pixel P3 may include a first reading circuit RO1 and a second reading circuit RO2, and each of the second unit pixel P2 and the fourth unit pixel P4 may include a third reading circuit RO3 and a fourth reading circuit RO4. Here, the third reading circuit RO3 and the fourth reading circuit RO4 may be substantially the same as the first reading circuit RO1 and the second reading circuit RO2, respectively. In this embodiment, a pair of unit pixels adjacent to each other in the first direction D1 or the second direction D2 may constitute a reference Figure 4 Describes the 4-tap structure of depth pixels.

[0135] A first photo gate signal and a second photo gate signal having a phase difference of 180° with respect to each other may be applied to the photo gate electrodes of the first read circuit RO1 and the second read circuit RO2, and a third photo gate signal and a fourth photo gate signal having a phase difference of 180° with respect to each other may be applied to the photo gate electrodes of the third read circuit RO3 and the fourth read circuit RO4. Here, the third photo gate signal and the fourth photo gate signal may have different phases from the first photo gate signal and the second photo gate signal.

[0136] In detail, the first unit pixel P1 and the second unit pixel P2 adjacent to each other in the first direction D1 may be arranged in a mirror-symmetrical manner, and the third unit pixel P3 and the fourth unit pixel P4 adjacent to each other in the first direction D1 may be arranged in a mirror-symmetrical manner. The first unit pixel P1 and the fourth unit pixel P4 adjacent to each other in the second direction D2 may be arranged in a mirror-symmetrical manner, and the second unit pixel P2 and the third unit pixel P3 adjacent to each other in the second direction D2 may be arranged in a mirror-symmetrical manner.

[0137] Therefore, the second reading circuits RO2 of the first unit pixel P1 and the third unit pixel P3 may be adjacent to each other in the diagonal direction, and the fourth reading circuits RO4 of the second unit pixel P2 and the fourth unit pixel P4 may be adjacent to each other in the diagonal direction. In addition, the first reading circuits RO1 of the first unit pixel P1 and the third unit pixel P3 may be adjacent to each other in the diagonal direction, and the third reading circuits RO3 of the second unit pixel P2 and the fourth unit pixel P4 may be adjacent to each other in the diagonal direction.

[0138] In an embodiment, Figure 14C As shown in , each of the first unit pixel P1 and the second unit pixel P2 may include a first read circuit RO1 and a second read circuit RO2, and each of the third unit pixel P3 and the fourth unit pixel P4 may include a third read circuit RO3 and a fourth read circuit RO4.

[0139] The first and second unit pixels P1 and P2 adjacent to each other in the first direction D1 may be disposed in a mirror-symmetrical manner, and the third and fourth unit pixels P3 and P4 adjacent to each other in the first direction D1 may be disposed in a mirror-symmetrical manner.

[0140] The second read circuits RO2 of the first unit pixel P1 and the second unit pixel P2 may be adjacent to each other in the first direction D1, and the fourth read circuits RO4 of the third unit pixel P3 and the fourth unit pixel P4 may be adjacent to each other in the first direction D1. Since the optical sensor blocks (each of which is composed of the first unit pixel P1 to the fourth unit pixel P4) are arranged two-dimensionally, the third read circuits RO3 of the third unit pixel P3 and the fourth unit pixel P4 may be adjacent to each other in the first direction D1, and the first read circuits RO1 of the first unit pixel P1 and the second unit pixel P2 may be adjacent to each other in the first direction D1.

[0141] Figure 15 It shows Figure 11 1 is a timing diagram of the operation of a depth pixel in an image sensor shown in FIG.

[0142] Reference Figure 15, a pulse light signal EL can be emitted from the light source 1 to the object O, such as Figure 1 As shown. Although each pulse of the light signal EL Figure 15 , the light signal EL may also be provided in the form of a sine wave. Part of the light signal EL may be reflected by an object to form reflected light incident on the unit pixels P1-P4. The reflected light may be delayed compared to the light signal EL.

[0143] In each of the unit pixels P1-P4, a first photo control signal PGA_0 synchronized with a light signal EL provided to an object may be applied to the first photo gate electrode PGA, and a second photo control signal PGA_180 having a phase difference of 180° with respect to the first photo control signal PGA_0 may be applied to the second photo gate electrode PGB. The first photo control signal PGA_0 and the second photo control signal PGA_180 may be alternately activated.

[0144] Then, a third photo control signal PGB_90 having a 90° phase difference with respect to the first photo control signal PGA_0 may be applied to the first photo gate electrode PGA, and a fourth photo control signal PGB_270 having a 180° phase difference with respect to the third photo control signal PGB_90 may be applied to the second photo gate electrode PGB. After the first photo control signal PGA_0 and the second photo control signal PGA_180 are applied, the third photo control signal PGB_90 and the fourth photo control signal PGB_270 may be sequentially applied at specific time intervals.

[0145] The first and second photo control signals PGA_0 and PGA_180 or the third and fourth photo control signals PGB_90 and PGB_270 applied to the first and second photo gate electrodes PGA and PGB may cause a potential change of the photoelectric conversion device PD.

[0146] Photo charges in the first and second floating diffusion nodes FD1 and FD2 may be detected in response to the first and second photo control signals PGA_0 and PGA_180 and then in response to the third and fourth photo control signals PGB_90 and PGB_270.

[0147] Specifically, when a high voltage is applied to the first photogate electrode PGA via the first photo control signal PGA_0, photocharge generated in the photoelectric conversion device PD can be transferred to the first floating diffusion node FD1. The photocharge accumulated in the first floating diffusion node FD1 can be output as a first pixel signal via the first readout circuit RO1. Furthermore, when a positive voltage is applied to the second photogate electrode PGB via the second photo control signal PGA_180, the photocharge generated in the photoelectric conversion device PD can be transferred to the second floating diffusion node FD2. The photocharge accumulated in the second floating diffusion node FD2 can be output as a second pixel signal via the second readout circuit RO2.

[0148] The amount of charges detected from the first and second floating diffusion nodes FD1 and FD2 may be changed according to the length by which the reflected light signal RL overlaps the first and second photo control signals PGA_0 and PGA_180 .

[0149] Specifically, the delay time of the reflected light can be detected based on the difference between the amount of charge measured from the first floating diffusion node FD1 during the overlap time of the reflected light signal RL and the first photo-control signal PGA_0, and the amount of charge measured from the second floating diffusion node FD2 during the overlap time of the reflected light signal RL and the second photo-control signal PGA_180. The delay time of the reflected light can then be detected based on the difference between the amount of charge measured from the first floating diffusion node FD1 during the overlap time of the reflected light signal RL and the third photo-control signal PGB_90, and the amount of charge measured from the second floating diffusion node FD2 during the overlap time of the reflected light signal RL and the fourth photo-control signal PGB_270. The difference between the signals output from the first floating diffusion node FD1 and the second floating diffusion node FD2 can be detected twice, and the detected signal difference can be used to measure the distance between the light source and the object (i.e., optical depth).

[0150] According to embodiments of the present inventive concept, an image sensor having a stacked polarizer array and a depth pixel array is disclosed, and various arrangements of the polarizer array and the depth pixel array are disclosed for easily extracting polarization information and depth information. Thus, a more accurate three-dimensional image can be estimated.

[0151] Ordinal numbers such as "first," "second," and "third" may simply be used as labels for specific elements, steps, and the like to distinguish them from one another. Terms not described using "first," "second," and the like in the specification may still be referred to as "first," "second," and the like in the claims. In addition, a term referenced by a specific ordinal number (e.g., "first" in a specific claim) may be described elsewhere using a different ordinal number (e.g., "second" in the specification or in another claim).

[0152] While example embodiments of the inventive concepts have been particularly shown and described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An image sensor, comprising: a polarizer array comprising first to fourth unit pixels arranged in first and second directions intersecting each other, the polarizer array comprising polarization gratings respectively provided in the first to fourth unit pixels, wherein the polarization gratings of the first to fourth unit pixels have different polarization directions from each other; and a depth pixel array including first to fourth depth pixels corresponding to the first to fourth unit pixels, respectively, each of the first to fourth depth pixels including a photoelectric conversion device, and a first reading circuit and a second reading circuit commonly connected to the photoelectric conversion device; wherein the first reading circuit and the second reading circuit are controlled by signals having different phases from each other, wherein the first depth pixel and the second depth pixel are arranged adjacent to each other in the first direction, The first reading circuit of the first depth pixel and the first reading circuit of the second depth pixel are arranged adjacent to each other in the first direction. The first reading circuit and the second reading circuit of the first depth pixel are arranged in a mirror-symmetrical manner with the first reading circuit and the second reading circuit of the second depth pixel in the first direction, and Herein, in each of the first to fourth depth pixels, the first reading circuit and the second reading circuit are arranged adjacent to each other in a third direction different from the first direction and the second direction.

2. The image sensor according to claim 1, wherein Each of the first read circuit and the second read circuit includes: floating diffusion nodes; and A photogate electrode is connected between the photoelectric conversion device and the floating diffusion node.

3. The image sensor according to claim 2, wherein: Each of the first read circuit and the second read circuit further includes: a transfer gate electrode located between the photogate electrode and the floating diffusion node; a storage gate electrode located between the transfer gate electrode and the photogate electrode; and A capture gate electrode is located between the photogate electrode and the storage gate electrode.

4. The image sensor according to claim 1, further comprising: a microlens array comprising a plurality of microlenses corresponding to the first to fourth unit pixels, respectively; Wherein, when viewed in a cross-sectional view, the polarizer array is disposed between the microlens array and the depth pixel array.

5. The image sensor according to claim 1, wherein The first to fourth unit pixels include first to fourth polarization gratings, respectively. The first polarization grating extends parallel to the first direction, The second polarization grating extends in a direction forming an angle of 45° with respect to the first direction, The third polarization grating extends parallel to the second direction, The fourth polarization grating extends in a direction forming an angle of 135° relative to the first direction, and The first to fourth unit pixels are sequentially arranged in a clockwise direction.

6. The image sensor according to claim 1, wherein Each of the first to fourth depth pixels of the depth pixel array further includes a third reading circuit and a fourth reading circuit that share the photoelectric conversion device.

7. The image sensor according to claim 6, wherein: Each of the third read circuit and the fourth read circuit includes: floating diffusion nodes; and A photogate electrode is connected between the photoelectric conversion device and the floating diffusion node.

8. The image sensor according to claim 6, wherein: The first to fourth reading circuits of the first depth pixel and the first to fourth reading circuits of the second depth pixel are arranged in a mirror-symmetrical manner with respect to a line parallel to the second direction and between the first depth pixel and the second depth pixel, and The first to fourth reading circuits of the first and second depth pixels and the first to fourth reading circuits of the third and fourth depth pixels are arranged in a mirror-symmetrical manner with respect to a line parallel to the first direction.

9. An image sensor comprising: a semiconductor substrate having a first surface and a second surface opposite to each other and including first to fourth pixel regions arranged along first and second directions intersecting each other; Photoelectric conversion devices, which are respectively located in the first pixel area to the fourth pixel area of ​​the semiconductor substrate; a first reading circuit and a second reading circuit located on the first surface of the semiconductor substrate in each of the first to fourth pixel regions, wherein the first reading circuit and the second reading circuit are controlled by signals having different phases from each other; and a polarizer array located on the second surface of the semiconductor substrate, the polarizer array comprising polarization gratings respectively disposed in the first pixel region to the fourth pixel region, wherein the polarization gratings in the first pixel region to the fourth pixel region have different polarization directions from each other; wherein the first pixel region and the second pixel region are arranged adjacent to each other in the first direction, The first reading circuit and the second reading circuit of the first pixel region and the first reading circuit and the second reading circuit of the second pixel region are arranged in a mirror-symmetrical manner with respect to a line parallel to the second direction. Wherein, each of the first reading circuit and the second reading circuit includes: floating diffusion nodes; and a photogate electrode connected between the photoelectric conversion device and the floating diffusion node, and In each pixel area from the first pixel area to the fourth pixel area, the floating diffusion node and the photogate electrode of the first reading circuit and the floating diffusion node and the photogate electrode of the second reading circuit are arranged in a mirror-symmetrical manner relative to a line parallel to the second direction.

10. The image sensor according to claim 9, wherein: In each of the first to fourth pixel areas, polarization grating lines of the polarization grating are arranged to have a uniform width and a uniform height and are spaced apart from each other by a specific distance.

11. The image sensor according to claim 9, wherein: The polarization grating includes a conductive pattern and a dielectric pattern stacked on the second surface of the semiconductor substrate.

12. The image sensor according to claim 9, wherein: In each of the first to fourth pixel regions, the polarization grating includes a first dielectric pattern provided on the second surface of the semiconductor substrate, and a dielectric layer covering the first dielectric pattern, and The first dielectric pattern includes a dielectric material having a refractive index different from that of the dielectric layer.

13. The image sensor according to claim 12, wherein: The first dielectric patterns have inclined sidewalls facing each other.

14. The image sensor according to claim 9, wherein: In each of the first to fourth pixel regions, the polarization grating includes a recessed region defined in the second surface of the semiconductor substrate, and The recessed area is defined by inclined surfaces that are opposed to each other.

15. The image sensor according to claim 14, further comprising: an anti-reflection layer covering the second surface of the semiconductor substrate, Wherein, the anti-reflection layer fills the recessed area.

16. The image sensor according to claim 9, further comprising: a fixed charge layer covering the second surface of the semiconductor substrate, Wherein, the polarization grating is arranged on the fixed charge layer.

17. The image sensor according to claim 9, further comprising: A third reading circuit and a fourth reading circuit are provided on the first surface of the semiconductor substrate in each of the first to fourth pixel regions.

18. The image sensor according to claim 9, further comprising: a microlens array comprising microlenses two-dimensionally arranged on the second surface of the semiconductor substrate, Wherein, when viewed in a cross-sectional view, the polarizer array is disposed between the microlens array and the semiconductor substrate.

19. An image sensor comprising: a polarizer array including first to fourth unit pixels arranged two-dimensionally, and including polarization gratings respectively provided in the first to fourth unit pixels and having polarization directions different from each other; a depth pixel array comprising first to fourth depth pixels corresponding to the first to fourth unit pixels, respectively, wherein each of the first to fourth depth pixels comprises a photoelectric conversion device and first to fourth reading circuits connected to the photoelectric conversion device; as well as a microlens array comprising microlenses corresponding to the first to fourth unit pixels, respectively; Wherein, the polarizer array is arranged between the microlens array and the depth pixel array, The first depth pixel and the second depth pixel are arranged adjacent to each other in the first direction. The first reading circuit of the first depth pixel and the first reading circuit of the second depth pixel are arranged adjacent to each other in the first direction. The first to fourth unit pixels are sequentially arranged in a clockwise direction to constitute a single optical sensor block. wherein a plurality of optical sensor blocks are two-dimensionally arranged in the first direction and in a second direction intersecting the first direction, The first to fourth reading circuits of the first depth pixel and the first to fourth reading circuits of the second depth pixel are arranged in a mirror-symmetrical manner with respect to a line parallel to the second direction. The first to fourth reading circuits of the first depth pixel and the second depth pixel and the first to fourth reading circuits of the third depth pixel and the fourth depth pixel are arranged in a mirror-symmetrical manner with respect to a line parallel to the first direction.

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