Display Panel

Abstract

A display panel includes: a substrate including a display area and a first area in the display area; a plurality of pixels in the display area, wherein the plurality of pixels include a first group of first pixels adjacent to the first area, and each of the first pixels includes a first semiconductor layer, wherein the first semiconductor layer of each of the first pixels is connected to the first semiconductor layer of another of the first pixels in a first direction to form a plurality of first rows arranged on the substrate, and the plurality of first rows are connected to first connection lines extending in a second direction intersecting the first direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0023294, filed on February 27, 2019, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments are directed to a display panel including a first area in an inner portion of a display area. Background Art

[0004] Recently, display devices have been used for various purposes. In addition, due to the reduced thickness and light weight of the display device, the display device has been more widely used.

[0005] As the display area occupies a larger portion of the display device, additional functions are transplanted or linked to the display device. In order to increase various functions while increasing the size of the display area, display devices including a display area in which various suitable components may be disposed have been studied and learned. Summary of the invention

[0006] Aspects of one or more embodiments relate to a display panel having a display area including a first area in which various components may be disposed, and a display device including the display panel. However, the above aspects are exemplary, and the scope of the present disclosure is not limited by these aspects.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, may be obvious from the description, or may be learned by practice of the embodiments.

[0008] According to one or more embodiments, a display panel includes: a substrate including a display area and a first area in the display area; and a plurality of pixels in the display area, wherein the plurality of pixels include a first group of first pixels adjacent to the first area, and each of the first pixels includes a first semiconductor layer, wherein the first semiconductor layer of each of the first pixels is connected to the first semiconductor layer of another of the first pixels in a first direction to form a plurality of first rows arranged on the substrate, and wherein the plurality of first rows are connected to first connecting lines extending in a second direction intersecting the first direction.

[0009] Each of the plurality of first rows may include a first end adjacent to the first region and a second end opposite to the first end, and the first connection line may be connected to at least one of the first end and the second end.

[0010] The plurality of pixels may include a first adjacent pixel group adjacent to the first group, and each of the pixels in the first adjacent pixel group may include a semiconductor layer, wherein the semiconductor layer of each of the pixels in the first adjacent pixel group may be connected to the semiconductor layer of another pixel in the pixels in the first adjacent pixel group in a first direction to form a plurality of rows arranged on a substrate, and wherein a first connecting line is connected to the plurality of rows in the first adjacent pixel group.

[0011] The total area of ​​the first semiconductor layer in the first group is different from the total area of ​​the semiconductor layer in the first adjacent pixel group.

[0012] The first connection line and the first semiconductor layer include the same material.

[0013] The plurality of pixels may further include a second group of second pixels spaced apart from the first group of first pixels, with the first region being between the first group and the second group, wherein each of the second pixels includes a second semiconductor layer, and wherein the second semiconductor layer of each of the second pixels is connected to the second semiconductor layer of another of the second pixels in a first direction to form a plurality of second rows arranged on the substrate.

[0014] The display panel may further include a second connection line extending in the second direction, and each of the plurality of second rows may be connected to the second connection line.

[0015] Each of the plurality of second rows may include a first end adjacent to the first region and a second end opposite to the first end, and wherein the second connection line may be connected to at least one of the first end and the second end of each of the plurality of second rows.

[0016] The multiple pixels may further include a second neighboring pixel group adjacent to the second group, and each of the pixels in the second neighboring pixel group includes a semiconductor layer, wherein the semiconductor layer of each of the pixels in the second neighboring pixel group can be connected to the semiconductor layer of another pixel in the second neighboring pixel group in a first direction to form a plurality of rows arranged on the substrate, and wherein the second connecting line can be connected to the plurality of rows in the second neighboring pixel group.

[0017] The second connection line and the second semiconductor layer may include the same material.

[0018] According to one or more embodiments, a display panel includes: a substrate including a first area and a second area; a plurality of first rows in the second area, each of the plurality of first rows including a plurality of first semiconductor layers connected to each other in a first direction; a plurality of second rows in the second area, each of the plurality of second rows including a plurality of second semiconductor layers connected to each other in the first direction; and first connecting lines connected to the plurality of first rows and extending in a second direction intersecting the first direction.

[0019] The first connection line and the plurality of first semiconductor layers may include the same material.

[0020] Each of the plurality of first rows may include a first end adjacent to the first region and a second end opposite to the first end, and wherein the first connection line may be connected to at least one of the first end and the second end.

[0021] The display panel may further include a plurality of first adjacent rows adjacent to the plurality of first rows, each of the plurality of first adjacent rows including a plurality of semiconductor layers connected to each other in the first direction, and first connection lines connected to the plurality of first adjacent rows.

[0022] The plurality of first semiconductor layers and the plurality of semiconductor layers may be connected to adjacent first semiconductor layers or semiconductor layers, respectively, in the second direction.

[0023] The plurality of first rows and the plurality of second rows may be separated from each other, with the first region being between the plurality of first rows and the plurality of second rows.

[0024] The plurality of first semiconductor layers and the plurality of second semiconductor layers may be step-wise disposed in a region adjacent to the first region.

[0025] The display panel may further include second connection lines connected to the plurality of second rows and extending in the second direction.

[0026] The second connection line and the plurality of second semiconductor layers may include the same material.

[0027] The display panel may further include a plurality of second adjacent rows adjacent to the plurality of second rows, each of the plurality of second adjacent rows including a plurality of semiconductor layers connected to each other in the first direction, and the second connection line is connected to the plurality of second adjacent rows.

[0028] Aspects and features other than those described will be apparent from the drawings, claims, and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] These and / or other aspects will become apparent and more readily understood from the following description of embodiments taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1 is a schematic perspective view showing a display device according to an embodiment;

[0031] Figure 2A and Figure 2B are simplified cross-sectional views each showing a display device according to an embodiment;

[0032] FIG. 3A to FIG. 3D are schematic cross-sectional views each showing a display panel according to an embodiment;

[0033] FIG. 4A to FIG. 4D are schematic cross-sectional views each showing a display panel according to an embodiment;

[0034] Figure 5 is an equivalent circuit diagram showing any one pixel in the display panel according to the embodiment;

[0035] Fig. 6A is a top plan view of an n-th pixel in a display panel according to an embodiment;

[0036] Figure 6B is a fragment of a top plan view of an nth pixel circuit and an (n+1)th pixel circuit in the pixel circuits in the display panel according to the embodiment;

[0037] Figure 7 is a cross-sectional view of any one pixel according to the embodiment;

[0038] Figure 8 is a schematic top plan view showing a display panel according to an embodiment;

[0039] Fig. 9 is a fragment of a top plan view of a semiconductor layer included in each of pixels disposed near a first region in a display panel according to an embodiment;

[0040] Fig. 10A and Fig. 10B are top plan views each showing a portion of a display panel according to an embodiment;

[0041] Fig.11 is a fragment of a top plan view of a semiconductor layer included in each of pixels disposed near a first region in a display panel according to another embodiment;

[0042] FIG. 12A to FIG. 12D Each is along Fig.11 A cross-sectional view of the display panel taken along line XII-XII' shown;

[0043] Fig.13 is a schematic top plan view showing a display panel according to another embodiment;

[0044] Fig.14 is a fragment of a top plan view showing a semiconductor layer included in each of pixels disposed near a first region in a display panel according to another embodiment;

[0045] Fig.15 is a top plan view showing a display panel according to another embodiment; and

[0046] Fig.16 is a top plan view illustrating a semiconductor layer disposed near a first region in a display panel according to an embodiment. DETAILED DESCRIPTION

[0047] Since the embodiment allows various suitable changes, the specific embodiment will be illustrated in the drawings and described more specifically in the written description. With reference to the embodiments described in detail below and in the drawings, the embodiments and the features of the embodiments can become apparent. However, the embodiments are not limited to the embodiments set forth herein and can be embodied in various forms. It will be further understood that the terms "include" and / or "include" specify the existence of stated features, ensembles, steps, operations, elements and / or parts when used in this specification, but do not exclude the existence or addition of one or more other features, ensembles, steps, operations, elements, parts and / or their combinations. As used herein, the term "and / or" indicates any and all combinations of one or more of the listed items associated. Expressions such as "at least one of...", when after the list of elements, modify the list of the entire element and do not modify the individual elements in the list. In addition, when describing the embodiments of the present invention, the use of "may" refers to one or more embodiments of the present invention.

[0048] Hereinafter, the embodiments will be described in more detail with reference to the accompanying drawings. The same reference numerals in the drawings denote the same elements, and their repeated description will be omitted.

[0049] In the embodiments described herein, terms such as “first,” “second,” “third,” and “fourth” are not used in a limiting sense and are only used to distinguish one component from another.

[0050] An expression used in the singular includes the plural expression unless it has an obviously different meaning in the context.

[0051] In the embodiments set forth herein, terms such as “include,” “comprises,” and “has” are intended to indicate the presence of features or components disclosed in the specification, and are not intended to exclude the possibility that one or more features or components may exist or may be added.

[0052] It will be understood that when a layer, region or component is referred to as being “formed on” another layer, region or component, it may be directly or indirectly formed on the other layer, region or component. That is, for example, intervening layers, regions or components may be present.

[0053] For the convenience of explanation, the sizes of components in the drawings may be exaggerated. In other words, since the sizes and thicknesses of components in the drawings are arbitrarily illustrated for the convenience of explanation, the embodiments are not limited thereto.

[0054] When a certain embodiment can be implemented differently, a specific process sequence can be performed in a different order than described. For example, two processes described in succession can be performed substantially at the same time, or in a reverse order to the described order.

[0055] In the present specification, "A and / or B" means "A", "B", or "A and B". In the present specification, "at least one of A and B" means "A", "B", or "A and B".

[0056] In the embodiments set forth herein, when a layer, region, or component is connected to another layer, region, or component, the layers, regions, or components may be directly connected to each other, and the layers, regions, or components may also be indirectly connected to each other with another layer, region, or component between them. For example, in this specification, when a layer, region, or component is electrically connected to another layer, region, or component, the layers, regions, or components may be directly electrically connected to each other, and the layers, regions, or components may also be indirectly electrically connected to each other with another layer, region, or component between them.

[0057] As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation and not as terms of degree, and are intended to take into account the inherent deviations in measured or calculated values ​​that will be recognized by those of ordinary skill in the art.

[0058] For ease of description, spatially relative terms such as "below," "below," "below," "downward," "above," "above," etc. may be used herein to describe the relationship of one element or feature relative to another element or feature as illustrated in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the accompanying drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, an element described as being "below" or "below" other elements or features will then be oriented "above" the other elements or features. Thus, the exemplary term "below" may encompass both above and below orientations. The device may be otherwise positioned (rotated 90 degrees or positioned in other orientations), and the spatially relative descriptors used herein are interpreted accordingly.

[0059] The term "use" as used herein may be considered synonymous with the term "utilize."

[0060] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and / or this specification, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0061] Figure 1 is a schematic perspective view showing a display device 1 according to the embodiment.

[0062] refer to Figure 1 , the display device 1 includes a first area OA and a display area (or second area) DA. In other words, the second area DA at least partially surrounds the first area OA. The display device 1 can provide an image by using light emitted from a plurality of pixels disposed in the display area DA. Figure 1 In the embodiment, a first area OA is disposed in an inner portion of the display area DA, and the first area OA may be completely surrounded by the display area DA. The first area OA may be disposed with a portion to be referred to later. Figure 2A and Figure 2B Describes the area of ​​the widget.

[0063] The middle area (or third area) MA may be disposed between the first area OA and the display area DA, and the display area DA may be surrounded by the peripheral area (or fourth area) PA. The middle area MA and the peripheral area PA may be non-display areas in which pixels are not disposed. The middle area MA may be completely surrounded by the display area DA, and the display area DA may be completely surrounded by the peripheral area PA.

[0064] In the following, an organic light emitting display is explained as an example of the display device 1 according to the embodiment, but the display device 1 is not limited thereto. In an embodiment, the display device 1 may be an inorganic light emitting display, an inorganic electroluminescent display, or a quantum dot light emitting display. For example, the emission layer of the display element provided in the display device 1 may include an organic material, an inorganic material, or a quantum dot. In one or more embodiments, the emission layer may include an organic material and a quantum dot, or an inorganic material and a quantum dot.

[0065] exist Figure 1, a first area OA that is approximately circular is illustrated, but the embodiment is not limited thereto. There may be one or more first areas OA, and each of the one or more first areas OA may be any suitable shape, for example, circular, elliptical, polygonal, star-shaped, and / or rhombus-shaped.

[0066] Figure 2A and Figure 2B are schematic cross-sectional views each showing a display device 1 according to an embodiment, and can be compared with Figure 1 The cross section of the display device 1 taken along line II-II' corresponds to the cross section of the display device 1 shown.

[0067] refer to Figure 2A and Figure 2B , the display device 1 may include a display panel 10, an input sensing layer 40 disposed on the display panel 10, and an optical function layer 50. The display panel 10, the input sensing layer 40, and the optical function layer 50 may be covered by a window 60. The display device 1 may include various types of electronic devices, such as a mobile phone, a laptop computer, or a smart watch.

[0068] The display panel 10 may display an image. The display panel 10 includes pixels arranged in a display area DA. The pixels may each include a display element and a pixel circuit connected to the display element. The display element may include an organic light emitting diode or a quantum dot organic light emitting diode, etc.

[0069] The input sensing layer 40 may acquire coordinate information according to an external input (e.g., a touch event). The input sensing layer 40 may include a sensing electrode (or a touch electrode) and a trace connected to the sensing electrode. The input sensing layer 40 may be disposed on the display panel 10. The input sensing layer 40 may sense an external input by a mutual capacitance method (e.g., a mutual capacitance method) and / or a self capacitance method (e.g., a self capacitance method).

[0070] The input sensing layer 40 may be directly formed on the display panel 10, or formed separately and then combined to the display panel 10 by using an adhesive layer such as an optically transparent adhesive. For example, the input sensing layer 40 may be formed continuously after the process of forming the display panel 10 (for example, the input sensing layer 40 may be formed continuously with the display panel 10). In this case, the input sensing layer 40 may be understood as a part of the display panel 10, and there may be no adhesive layer between the input sensing layer 40 and the display panel 10. Although Figure 2A An embodiment in which the input sensing layer 40 is between the display panel 10 and the optical functional layer 50 is shown, but in another embodiment, the input sensing layer 40 may be disposed on the optical functional layer 50 .

[0071] The optical functional layer 50 may include an anti-reflection layer. The anti-reflection layer may reduce the reflectivity (e.g., light reflectivity value) of light (external light) incident on the display panel 10 from the outside through the window 60. The anti-reflection layer may include a retarder and a polarizer. The retarder may include a film type or a liquid crystal coating type, and may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may also include a film type or a liquid crystal coating type. The film type polarizer may include a stretched synthetic resin film, and the liquid crystal coating type polarizer may include a liquid crystal arranged in a certain arrangement. The retarder and the polarizer may further include a protective film. The protective film of the retarder and the polarizer may be defined as a base layer of the anti-reflection layer.

[0072] In an embodiment, the anti-reflection layer may include a black matrix and a color filter. The color filter may be set in consideration of the color of the light emitted from each pixel of the display panel 10. Each color filter in the color filter may include a red, green or blue pigment or dye. Alternatively, each color filter in the color filter may further include quantum dots other than the pigment or dye. Alternatively, some of the color filters in the color filter may include dispersed particles such as titanium oxide instead of the above-mentioned pigment or dye.

[0073] In an embodiment, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer respectively disposed on different layers. The first reflected light and the second reflected light respectively reflected from the first reflective layer and the second reflective layer may undergo destructive interference. Therefore, the reflectivity of the external light incident on the display panel 10 may be reduced.

[0074] The optical function layer 50 may include a lens layer. The lens layer may improve the luminous efficiency of light emitted from the display panel 10 or reduce color deviation. The lens layer may include a layer having a concave lens shape or a convex lens shape and / or a plurality of layers having different refractive indices. The optical function layer 50 may include an anti-reflection layer and / or a lens layer.

[0075] In an embodiment, the optical function layer 50 may be continuously formed after the process of forming the display panel 10 and / or the input sensing layer 40 (for example, the optical function layer 50 may be continuously formed with the display panel 10 and the input sensing layer 40). In this case, the adhesive layer may not be located between the optical function layer 50 and the display panel 10 and / or the input sensing layer 40.

[0076] The display panel 10, the input sensing layer 40 and / or the optical functional layer 50 may each include an opening. In this regard, Figure 2AAn embodiment is shown in which the display panel 10, the input sensing layer 40, and the optical function layer 50 respectively include a first opening 10H, a second opening 40H, and a third opening 50H that overlap each other. The first opening 10H, the second opening 40H, and the third opening 50H are arranged to correspond to the first area OA. In an embodiment, one or more of the display panel 10, the input sensing layer 40, and the optical function layer 50 may not include an opening. For example, one or two components selected from the display panel 10, the input sensing layer 40, and the optical function layer 50 may not include an opening. Alternatively, the display panel 10, the input sensing layer 40, and the optical function layer 50 may not include an opening. Figure 2B Opening shown.

[0077] As described in one or more of the above embodiments, the first area OA may be a component area of ​​the type in which a component 20 for adding various suitable functions to the display device 1 is located (e.g., a sensor area, a camera area, and / or a speaker area, etc.). The component 20 may be located in the first opening 10H, the second opening 40H, and the third opening 50H, such as Figure 2A Alternatively, the component 20 may be disposed below the display panel 10, as shown. Figure 2B shown.

[0078] The component 20 may include electronic components. For example, the component 20 may include electronic components that use light or sound. For example, the electronic components may include sensors that output and / or receive light (such as infrared sensors), cameras that receive light and capture images, sensors that measure distance or recognize fingerprints by outputting and sensing light or sound, small lamps that output light, speakers that output sound, and the like. Electronic components that use light may use light with various suitable bands, such as visible light, infrared light, ultraviolet light, and the like. In one or more embodiments, the first area OA may be understood as a transmission area, through which light and / or sound output from the component 20 to the outside or traveling from the outside to the electronic components of the component 20 may be transmitted.

[0079] In an embodiment, when the display device 1 is used as a smart watch or an instrument panel of a vehicle, the component 20 may be a member such as a pointer of a watch or a needle indicating certain information (e.g., the speed of the vehicle). When the display device 1 includes a pointer of a clock or an instrument panel for a vehicle, the component 20 may be exposed to the outside through the window 60, and the window 60 may include an opening corresponding to the first area OA.

[0080] As described above, in one or more embodiments, the component 20 may include an element related to the function of the display panel 10 or an element such as an accessory for improving the aesthetic impression of the display panel 10. Figure 2A and Figure 2BAlthough not shown in the drawings, an optically transparent adhesive or the like may be located between the window 60 and the optical functional layer 50 .

[0081] FIG. 3A to FIG. 3D is a schematic cross-sectional view showing a display panel 10 according to an embodiment.

[0082] refer to Figure 3A The display panel 10 includes a display layer 200 disposed on a substrate 100. The substrate 100 may include glass and / or a polymer resin. The substrate 100 may include a single layer or multiple layers. For example, Figure 3A As shown in the enlarged view of , the substrate 100 may include a first base layer 101 , a first barrier layer 102 , a second base layer 103 and a second barrier layer 104 .

[0083] The first substrate layer 101 and the second substrate layer 103 may each include a polymer resin. For example, the first substrate layer 101 and the second substrate layer 103 may include a high molecular weight resin such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), triacetyl cellulose (TAC), cellulose acetate propionate (CAP), etc. The first substrate layer 101 and the second substrate layer 103 may include a transparent polymer resin.

[0084] The first barrier layer 102 and the second barrier layer 104 , which are barrier layers for preventing penetration of external foreign substances, may each include a single layer or a multilayer including an inorganic material such as silicon nitride or silicon oxide.

[0085] The display layer 200 includes a plurality of pixels. The display layer 200 may include a display element layer 200A and a pixel circuit layer 200B, wherein the display element layer 200A includes a display element disposed in each pixel, and the pixel circuit layer 200B includes a pixel circuit disposed in each pixel and an insulating layer. Each pixel circuit in the pixel circuit may include a transistor and a storage capacitor, and may be electrically connected to each display element in the display element. Each display element in the display element may each include an organic light emitting diode OLED.

[0086] The display element in the display layer 200 may be covered by an encapsulation member including at least one inorganic encapsulation layer and at least one organic encapsulation layer, such as a thin film encapsulation layer 300. When the display panel 10 includes the substrate 100 including a polymer resin and the thin film encapsulation layer 300 including the inorganic encapsulation layer and the organic encapsulation layer, the flexibility of the display panel 10 may be enhanced.

[0087] The display panel 10 may include a first opening 10H that penetrates (or extends through) the display panel 10. The first opening 10H may be located in the first area OA, and in an embodiment, as shown in FIG. Figure 3A As shown, the first area OA may be a type of opening area (or opening). Figure 3A In the embodiment, the substrate 100 and the thin film encapsulation layer 300 respectively include a first through hole 100H and a third through hole 300H corresponding to the first opening 10H of the display panel 10. The display layer 200 may also include a second through hole 200H corresponding to the first area OA.

[0088] In an embodiment, Figure 3B As shown, the substrate 100 may not include the first through hole 100H corresponding to the first area OA. The display layer 200 may include the second through hole 200H corresponding to the first area OA. The thin film encapsulation layer 300 may not include the third through hole 300H corresponding to the first area OA. In an embodiment, as shown in FIG. Figure 3C As shown, the display layer 200 may not include the second through-hole 200H corresponding to the first area OA, and the display element layer 200A is not located in the first area OA.

[0089] exist FIG. 3A to FIG. 3C In the embodiment, the display element layer 200A is not located in the first area OA, but the embodiment is not limited thereto. Figure 3D As shown, the auxiliary display element layer 200C may be located in the first area OA. The auxiliary display element layer 200C may include display elements having a different structure and / or operating in a different manner than the display elements in the display element layer 200A.

[0090] In an embodiment, each pixel in the display element layer 200A may include an active matrix organic light emitting diode, and the auxiliary display element layer 200C may include pixels each including a passive matrix organic light emitting diode. When the auxiliary display element layer 200C includes a display element of a passive matrix organic light emitting diode, the elements included in the pixel circuit may not be located below the passive matrix organic light emitting diode. For example, in the pixel circuit layer 200B, the portion below the auxiliary display element layer 200C does not include a transistor and a storage capacitor.

[0091] In an embodiment, the auxiliary display element layer 200C may include a display element (e.g., an active matrix organic light emitting diode) having a similar type (e.g., the same type) as the display element layer 200A, but the structure of the pixel circuit below the auxiliary display element layer 200C may be different from the structure of the pixel circuit below the display element layer 200A. For example, the pixel circuit below the auxiliary display element layer 200C (e.g., a pixel circuit having a light shielding film between the substrate 100 and the transistor) may include a structure different from the structure of the pixel circuit below the display element layer 200A. Alternatively, the display element in the auxiliary display element layer 200C may operate in response to a control signal different from the signal applied to the display element in the display element layer 200A. Components (e.g., infrared sensors, etc.) that do not require relatively high transmittance may be disposed in the first region OA in which the auxiliary display element layer 200C is disposed. In this case, the first region OA may be understood as a component region and an auxiliary display region.

[0092] FIG. 4A to FIG. 4D are schematic cross-sectional views each showing a display panel 10' according to another embodiment. FIG. 3A to FIG. 3D Unlike the display panel 10 described above, which includes the thin film encapsulation layer 300, FIG. 4A to FIG. 4D The illustrated display panel 10 ′ may include an encapsulation substrate 300A and a sealant 340 .

[0093] like FIG. 4A to FIG. 4C As shown, one or more of the substrate 100, the display layer 200, and the packaging substrate 300A may include a first through-hole 100H, a second through-hole 200H, and a third through-hole 300AH, each corresponding to the first area OA. In an embodiment, the display element layer 200A may not be disposed in the first area OA. In an embodiment, the auxiliary display element layer 200C may be disposed in the first area OA, such as Figure 4D The auxiliary display element layer 200C is similar to the above reference Figure 3D The auxiliary display element layer 200C described is the same or substantially similar.

[0094] Figure 5 is an equivalent circuit diagram showing a pixel P in a display panel according to an embodiment.

[0095] refer to Figure 5 , the pixel P includes a pixel circuit PC and an organic light emitting diode OLED connected to the pixel circuit PC. The pixel circuit PC may include a plurality of transistors and a storage capacitor. The transistor and the storage capacitor may be connected to a signal line (e.g., a first scan line SWL, a second scan line SIL, an emission control line EL, and a data line DL), an initialization voltage line VIL, and a drive voltage line PL.

[0096] Figure 5 An embodiment in which each pixel P is connected to a signal line (a first scan line SWL, a second scan line SIL, an emission control line EL, and a data line DL), an initialization voltage line VIL, and a drive voltage line PL is shown, but the embodiment is not limited thereto. In an embodiment, at least one of the signal line (a first scan line SWL, a second scan line SIL, an emission control line EL, and a data line DL), an initialization voltage line VIL, and a drive voltage line PL, etc., may be shared between adjacent pixels.

[0097] The plurality of transistors may include a driving transistor T1, a switching transistor T2, a compensation transistor T3, a first initialization transistor T4, an operation control transistor T5, an emission control transistor T6, and a second initialization transistor T7. Here, all of the plurality of transistors are thin film transistors.

[0098] The signal lines include a first scan line SWL that delivers a scan signal GW, a second scan line SIL that delivers a previous scan signal GI to a first initialization transistor T4 and a second initialization transistor T7, an emission control line EL that delivers an emission control signal EM to an operation control transistor T5 and an emission control transistor T6, and a data line DL that crosses the first scan line SWL and delivers a data signal Dm to a switching transistor T2. A driving voltage line PL delivers a driving voltage ELVDD to a driving transistor T1, and an initialization voltage line VIL delivers an initialization voltage Vint that initializes the driving transistor T1 and a pixel electrode.

[0099] The driving gate electrode G1 of the driving transistor T1 is connected to the first capacitance plate CE1 of the storage capacitor Cst; the driving source electrode S1 of the driving transistor T1 is connected to the driving voltage line PL through the operation control transistor T5; and the driving drain electrode D1 of the driving transistor T1 is electrically connected to the pixel electrode of the organic light emitting diode OLED through the emission control transistor T6. The driving transistor T1 receives the data signal Dm in response to the switching operation of the switching transistor T2, and drives the driving current I OLED Supplied to the organic light emitting diode OLED.

[0100] The switching gate electrode G2 of the switching transistor T2 is connected to the first scanning line SWL; the switching source electrode S2 of the switching transistor T2 is connected to the data line DL; the switching drain electrode D2 of the switching transistor T2 is connected to the driving source electrode S1 of the driving transistor T1, and is also connected to the driving voltage line PL through the operation control transistor T5. The switching transistor T2 is turned on in response to the scanning signal GW delivered through the first scanning line SWL, and performs a switching operation of delivering the data signal Dm delivered through the data line DL to the driving source electrode S1 of the driving transistor T1.

[0101] The compensation gate electrode G3 of the compensation transistor T3 is connected to the first scan line SWL; the compensation source electrode S3 of the compensation transistor T3 is connected to the driving drain electrode D1 of the driving transistor T1, and is also connected to the pixel electrode of the organic light emitting diode OLED through the emission control transistor T6; the compensation drain electrode D3 of the compensation transistor T3 is connected to the first capacitance plate CE1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization transistor T4, and the driving gate electrode G1 of the driving transistor T1. The compensation transistor T3 is turned on in response to the scan signal GW received through the first scan line SWL to electrically connect the driving gate electrode G1 and the driving drain electrode D1 of the driving transistor T1, so that the driving transistor T1 has a diode connection.

[0102] A first initialization gate electrode G4 of the first initialization transistor T4 is connected to the second scan line SIL; a first initialization source electrode S4 of the first initialization transistor T4 is connected to the second initialization drain electrode D7 of the second initialization transistor T7 and the initialization voltage line VIL; and a first initialization drain electrode D4 of the first initialization transistor T4 is connected to the first capacitance plate CE1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation transistor T3, and the driving gate electrode G1 of the driving transistor T1. The first initialization transistor T4 is turned on in response to the previous scan signal GI received through the second scan line SIL, and transmits the initialization voltage Vint to the driving gate electrode G1 of the driving transistor T1, thereby performing an initialization operation to initialize the voltage of the driving gate electrode G1 of the driving transistor T1.

[0103] The operation control gate electrode G5 of the operation control transistor T5 is connected to the emission control line EL; the operation control source electrode S5 of the operation control transistor T5 is connected to the driving voltage line PL; the operation control drain electrode D5 of the operation control transistor T5 is connected to the driving source electrode S1 of the driving transistor T1 and the switching drain electrode D2 of the switching transistor T2.

[0104] The emission control gate electrode G6 of the emission control transistor T6 is connected to the emission control line EL; the emission control source electrode S6 of the emission control transistor T6 is connected to the driving drain electrode D1 of the driving transistor T1 and the compensation source electrode S3 of the compensation transistor T3, and the emission control drain electrode D6 of the emission control transistor T6 is electrically connected to the second initialization source electrode S7 of the second initialization transistor T7 and the pixel electrode of the organic light emitting diode OLED.

[0105] The operation control transistor T5 and the emission control transistor T6 are concurrently (eg, simultaneously) turned on in response to the emission control signal EM received through the emission control line EL, so that the driving voltage ELVDD is delivered to the organic light emitting diode OLED and the driving current I OLEDFlow through the organic light emitting diode OLED.

[0106] The second initialization gate electrode G7 of the second initialization transistor T7 is connected to the second scan line SIL; the second initialization source electrode S7 of the second initialization transistor T7 is connected to the emission control drain electrode D6 of the emission control transistor T6 and the pixel electrode of the organic light emitting diode OLED; and the second initialization drain electrode D7 of the second initialization transistor T7 is connected to the first initialization source electrode S4 of the first initialization transistor T4 and the initialization voltage line VIL. The second initialization transistor T7 is turned on in response to the previous scan signal GI delivered through the second scan line SIL, and initializes the pixel electrode of the organic light emitting diode OLED.

[0107] Figure 5 An embodiment in which the first initialization transistor T4 and the second initialization transistor T7 are connected to the second scan line SIL is shown, but the embodiment is not limited thereto. As another embodiment, the first initialization transistor T4 may be connected to the second scan line SIL and driven in response to the previous scan signal GI, and the second initialization transistor T7 may be connected to the first scan line or the second scan line of the pixels arranged in the previous row or the next row.

[0108] The second capacitor plate CE2 of the storage capacitor Cst is connected to the driving voltage line PL, and the counter electrode of the organic light emitting diode OLED is connected to the common voltage ELVSS. Therefore, the organic light emitting diode OLED can receive the driving current I from the driving transistor T1. OLED and emits light to display images.

[0109] exist Figure 5 In the embodiment, the compensation transistor T3 and the first initialization transistor T4 each include a double gate electrode, but the compensation transistor T3 and the first initialization transistor T4 may each include one gate electrode.

[0110] refer to Figure 5 A pixel circuit PC including seven transistors T1 to T7 and one storage capacitor Cst is described, but the embodiment is not limited thereto. In one or more embodiments, the number of transistors T1 to T7 may be appropriately modified to, for example, be less than or equal to six, or equal to or greater than eight, depending on the design of the pixel circuit PC. In one or more embodiments, the number of storage capacitors Cst may be appropriately modified to, for example, be equal to or greater than two, depending on the design of the pixel circuit PC.

[0111] Fig. 6A is a top plan view of an n-th pixel in a display panel according to an embodiment, and Figure 6Bis a fragment of a top plan view of an nth pixel circuit and an (n+1)th pixel circuit selected from pixel circuits in a display panel according to an embodiment.

[0112] refer to Fig. 6A , a driving transistor T1 , a switching transistor T2 , a compensation transistor T3 , a first initialization transistor T4 , an operation control transistor T5 , an emission control transistor T6 , and a second initialization transistor T7 are disposed along the semiconductor layer 1130 .

[0113] Portions of the semiconductor layer 1130 each correspond to the semiconductor layer of each of the driving transistor T1, the switching transistor T2, the compensation transistor T3, the first initialization transistor T4, the operation control transistor T5, the emission control transistor T6, and the second initialization transistor T7. In other words, it can be understood that the semiconductor layers of the driving transistor T1, the switching transistor T2, the compensation transistor T3, the first initialization transistor T4, the operation control transistor T5, the emission control transistor T6, and the second initialization transistor T7 are connected to each other and bent into various suitable shapes.

[0114] The semiconductor layer 1130 includes a channel region, a source region, and a drain region. The source region and the drain region are on the respective sides of each channel region in the channel region, wherein the source region and the drain region can be understood as the source electrode and the drain electrode of the relevant transistor. In the following, for convenience, the source region and the drain region are respectively referred to as the source electrode and the drain electrode.

[0115] The driving transistor T1 includes a driving gate electrode G1 overlapping the driving channel region and a driving source electrode S1 and a driving drain electrode D1 on both sides of the driving channel region. The driving channel region overlapping the driving gate electrode G1 can form a large channel length in a narrow area by having a curved shape similar to an omega shape. When the driving channel region is long, the driving range of the gate voltage increases. Therefore, the level of light emitted from the organic light emitting diode OLED can be more delicately controlled, and the quality of display can be improved.

[0116] The switch transistor T2 includes a switch gate electrode G2 overlapping the switch channel region, a switch source electrode S2 and a switch drain electrode D2. The switch source electrode S2 and the switch drain electrode D2 are on both sides of the switch channel region. The switch drain electrode D2 may be connected to the driving source electrode S1.

[0117] The compensation transistor T3, which may be a dual transistor (e.g., a dual-gate transistor), may include a compensation gate electrode G3 overlapping two compensation channel regions, and may also include a compensation source electrode S3 and a compensation drain electrode D3 located on both sides of the compensation channel region. The compensation transistor T3 may be connected to the driving gate electrode G1 of the driving transistor T1 through a node connection line 1174 that may be described later.

[0118] The first initialization transistor T4 , which may be a dual transistor (eg, a dual-gate transistor), may include a first initialization gate electrode G4 overlapping two first initialization channel regions, and may also include a first initialization source electrode S4 and a first initialization drain electrode D4 located at both sides of the first initialization channel region.

[0119] The operation control transistor T5 may include an operation control gate electrode G5 overlapping the operation control channel region, and may include an operation control source electrode S5 and an operation control drain electrode D5 located at both sides of the operation control channel region. The operation control drain electrode D5 may be connected to the driving source electrode S1.

[0120] The emission control transistor T6 may include an emission control gate electrode G6 overlapping the emission control channel region, and may include an emission control source electrode S6 and an emission control drain electrode D6 located at both sides of the emission control channel region. The emission control source electrode S6 may be connected to the driving drain electrode D1.

[0121] The second initialization transistor T7 may include a second initialization gate electrode G7 overlapping the second initialization channel region, and may include a second initialization source electrode S7 and a second initialization drain electrode D7 located at both sides of the second initialization channel region.

[0122] The first scan line SWL, the second scan line SIL, the emission control line EL, and the driving gate electrode G1 may be disposed on the semiconductor layer 1130 with an insulating layer therebetween.

[0123] The first scan line SWL, the second scan line SIL, and the emission control line EL may each extend in the first direction (x direction). Portions of the first scan line SWL may correspond to the switch gate electrode G2 and the compensation gate electrode G3, respectively. Portions of the second scan line SIL may correspond to the first initialization gate electrode G4 and the second initialization gate electrode G7, respectively. Portions of the emission control line EL may correspond to the operation control gate electrode G5 and the emission control gate electrode G6, respectively.

[0124] The driving gate electrode G1 , which may be an island electrode, may be connected to the compensation transistor T3 through a node connection line 1174 .

[0125] The electrode voltage line HL may be disposed above the first scan line SWL, the second scan line SIL, the emission control line EL, and the driving gate electrode G1 with an insulating layer therebetween.

[0126] The electrode voltage line HL may extend in the first direction to cross the data line DL and the driving voltage line PL. A portion of the electrode voltage line HL may cover at least a portion of the driving gate electrode G1. For example, a portion of the electrode voltage line HL may overlap the driving gate electrode G1 and may form a storage capacitor Cst together with the driving gate electrode G1. For example, the driving gate electrode G1 may be a first capacitive plate CE1 of the storage capacitor Cst, and a portion of the electrode voltage line HL may be a second capacitive plate CE2 of the storage capacitor Cst.

[0127] The second capacitive plate CE2 of the storage capacitor Cst is electrically connected to the driving voltage line PL which may be described later. In this regard, the electrode voltage line HL may contact the driving voltage line PL disposed above the electrode voltage line HL through the contact hole CNT. Therefore, the electrode voltage line HL may have a voltage level (e.g., a positive voltage) that is the same as or substantially similar to the voltage level of the driving voltage line PL. The electrode voltage line HL may be understood as a lateral driving voltage line.

[0128] The data line DL, the driving voltage line PL, the initialization connection line 1173 and the node connection line 1174 may be disposed above the electrode voltage line HL with an insulating layer therebetween.

[0129] The data line DL and the driving voltage line PL may extend in the second direction (y direction). The data line DL may contact the switching source electrode S2 of the switching transistor T2 through the contact hole 1154. A portion of the data line DL may be understood as the switching source electrode S2.

[0130] The driving voltage line PL contacts the electrode voltage line HL through the contact hole CNT. The driving voltage line PL may also be connected to the operation control transistor T5 through the contact hole 1155. The driving voltage line PL may contact the operation control source electrode S5 through the contact hole 1155.

[0131] An end of the initialization connection line 1173 may be connected to the first and second initialization transistors T4 and T7 through a contact hole 1152 , and the other end of the initialization connection line 1173 may be connected to an initialization voltage line VIL, which may be described later, through a contact hole 1151 .

[0132] An end portion of the node connection line 1174 may be connected to the compensation drain electrode D3 through the contact hole 1156 , and the other end portion of the node connection line 1174 may contact the driving gate electrode G1 via the contact hole 1157 .

[0133] The initialization voltage line VIL may be disposed on the data line DL, the driving voltage line PL, the initialization connection line 1173 and the node connection line 1174 with an insulating layer therebetween.

[0134] The initialization voltage line VIL may extend in the first direction (x direction) and may be connected to the first initialization transistor T4 and the second initialization transistor T7 through an initialization connection line 1173 .

[0135] The initialization voltage line VIL may be disposed on the same layer as the pixel electrode 210 of the organic light emitting diode OLED and may include the same material as the pixel electrode 210 of the organic light emitting diode OLED. The pixel electrode 210 may be connected to the emission control transistor T6. The pixel electrode 210 may contact the contact metal 1175 through the contact hole 1163, and the contact metal 1175 may contact the emission control drain electrode D6 through the contact hole 1153. Fig. 6A The initialization voltage line VIL is set to be connected to the pixel electrode 210 (see Figure 7 However, in another embodiment, the initialization voltage line VIL may be disposed on the same layer as the electrode voltage line HL.

[0136] exist Fig. 6A In the embodiment, the second initialization transistor T7 is electrically connected to the second scan line SIL, however, as another embodiment, the second initialization transistor T7 can be connected to the first scan line or the second scan line included in the pixel circuit of the n-1th pixel, or can be connected to the first scan line or the second scan line included in the pixel circuit of the n+1th pixel.

[0137] refer to Figure 6B , the semiconductor layer 1130n in the nth pixel can be connected to the semiconductor layer 1130n+1 in the n+1th pixel. In this case, adjacent pixel circuits (e.g., the pixel circuit of the nth pixel and the pixel circuit of the n+1th pixel) can share one or more signal lines, and the pixel circuits can be effectively arranged in a small range of areas (e.g., a relatively small area).

[0138] Figure 7 is a cross-sectional view of a pixel according to an embodiment; Figure 7 is along Fig. 6A Cross-sectional views of a top plan view of the n-th pixel taken along lines II' and II-II' are shown.

[0139] As described above, the substrate 100 may include glass and / or a polymer resin. The buffer layer 111 located on the substrate 100 may reduce or prevent foreign matter, moisture, or external air from penetrating from the lower portion of the substrate 100, and provide a flat surface on the substrate 100. The buffer layer 111 may include an inorganic material such as an oxide or a nitride, an organic material, or an organic-inorganic composite material, and may include a single layer or multiple layers of an inorganic material and / or an organic material.

[0140] The semiconductor layers 1130a and 1130b may include polycrystalline silicon. In an embodiment, the semiconductor layers 1130a and 1130b may include amorphous silicon, an oxide semiconductor, or an organic semiconductor. Figure 7 The semiconductor layers 1130a and 1130b are shown as reference Fig. 6A Portions of semiconductor layer 1130 are depicted.

[0141] The driving gate electrode G1 and the emission control gate electrode G6 are respectively disposed on the semiconductor layers 1130a and 1130b, and the first gate insulating layer 112 is between the driving gate electrode G1 and the emission control gate electrode G6 and the semiconductor layers 1130a and 1130b. Each of the driving gate electrode G1 and the emission control gate electrode G6 may include molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and may include a single layer or multiple layers. For example, each of the driving gate electrode G1 and the emission control gate electrode G6 may include a single layer of Mo. The first scan line SWL, the second scan line SIL, and the emission control line EL (see Fig. 6A ) can be formed in the same layer as the driving gate electrode G1 and the emission control gate electrode G6. That is, the driving gate electrode G1, the emission control gate electrode G6, the first scan line SWL, the second scan line SIL and the emission control line EL (see Fig. 6A ) may be disposed on the first gate insulating layer 112.

[0142] The first gate insulating layer 112 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, or zinc oxide.

[0143] The second gate insulating layer 113 may be provided to cover the driving gate electrode G1 and the emission control gate electrode G6. The second gate insulating layer 113 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, or zinc oxide.

[0144] The first capacitive plate CE1 of the storage capacitor Cst may be integrally formed with the driving gate electrode G1 of the driving transistor T1. That is, the driving gate electrode G1 of the driving transistor T1 may serve as the first capacitive plate CE1 of the storage capacitor Cst.

[0145] The second capacitor plate CE2 of the storage capacitor Cst overlaps the first capacitor plate CE1, and the second gate insulating layer 113 is between the second capacitor plate CE2 and the first capacitor plate CE1. In this case, the second gate insulating layer 113 can be used as a dielectric layer of the storage capacitor Cst. The second capacitor plate CE2 may include a conductive material including Mo, Al, Cu and Ti, and may include a single layer or multiple layers including the above materials. For example, the second capacitor plate CE2 may include a single layer of Mo or a multilayer such as Mo / Al / Mo.

[0146] Although the storage capacitor Cst is shown to overlap with the driving transistor T1, the embodiment is not limited thereto. The arrangement of the storage capacitor Cst may be variously changed, for example, in one or more embodiments, the storage capacitor Cst may be disposed not to overlap with the driving transistor T1.

[0147] The second capacitive plate CE2 may be used as the electrode voltage line HL. For example, a portion of the electrode voltage line HL may be the second capacitive plate CE2 of the storage capacitor Cst.

[0148] An interlayer insulating layer 115 may be provided to cover the second capacitor plate CE2. The interlayer insulating layer 115 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, or zinc oxide.

[0149] The data line DL, the driving voltage line PL, and the contact metal 1175 may be disposed on the interlayer insulating layer 115. The data line DL, the driving voltage line PL, and the contact metal 1175 may each include a conductive material including Mo, Al, Cu, and Ti, and may include a multilayer or a single layer including the above materials. For example, the data line DL, the driving voltage line PL, and the contact metal 1175 may include a multilayer structure such as Ti / Al / Ti.

[0150] The data line DL and the driving voltage line PL can deliver signals and voltages to each pixel, respectively. The specific resistance (e.g., specific resistance) of the data line DL and the driving voltage line PL can be less than the specific resistance of the second capacitor plate CE2 or the specific resistance of the electrode voltage line HL. In one or more embodiments, the specific resistance of the data line DL and the driving voltage line PL can be about one tenth (about one tenth) of the specific resistance of the second capacitor plate CE2 or the specific resistance of the electrode voltage line HL.

[0151] The second capacitance plate CE2 of the storage capacitor Cst may contact the driving voltage line PL through the contact hole CNT defined in the interlayer insulating layer 115. This may indicate that the electrode voltage line HL contacts the driving voltage line PL through the contact hole CNT. Therefore, the electrode voltage line HL may have a voltage level (e.g., a positive voltage) that is the same as or substantially similar to that of the driving voltage line PL.

[0152] The contact metal 1175 contacts the semiconductor layer 1130b of the emission control transistor T6 through the contact hole 1153 penetrating (or extending through) the interlayer insulating layer 115, the second gate insulating layer 113, and the first gate insulating layer 112. The emission control transistor T6 may be electrically connected to the pixel electrode 210 of the organic light emitting diode OLED through the contact metal 1175.

[0153] A planarization layer 117 may be located on the data line DL, the driving voltage line PL, and the contact metal 1175 , and an organic light emitting diode OLED may be located on the planarization layer 117 .

[0154] The planarization layer 117 may have a flat upper surface so that the pixel electrode 210 is formed into a flat shape. The planarization layer 117 may include a single layer or multiple layers including a film formed by an organic material. The planarization layer 117 may include a general commercial polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA) and / or polystyrene (PS), a general commercial polymer with a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorinated polymer, a p-xylene polymer, a vinyl alcohol polymer and / or a blend thereof. In an embodiment, the planarization layer 117 may include an inorganic material such as silicon nitride and / or silicon oxide, and when the planarization layer 117 includes an inorganic material, a chemical polarization polishing operation may be performed as needed. In an embodiment, the planarization layer 117 may include both organic and inorganic materials.

[0155] A contact hole 1163 exposing the contact metal 1175 is in the planarization layer 117 , and the pixel electrode 210 contacts the contact metal 1175 through the contact hole 1163 .

[0156] The pixel electrode 210 may be a (semi) transmissive electrode or a reflective electrode. In one or more embodiments, the pixel electrode 210 may include a reflective film including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) and / or a combination thereof, and may also include a transparent or semi-transparent electrode layer formed on the reflective film. The transparent or semi-transparent electrode layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), at least one of indium gallium oxide (IGO) and aluminum zinc oxide (AZO). In one or more embodiments, the pixel electrode 210 may include a stacked structure (eg, ITO / Ag / ITO).

[0157] The pixel defining layer 119 may be disposed on the planarization layer 117, and the pixel defining layer 119 may define an emission region of a pixel by having an opening 119OP exposing a central portion of the pixel electrode 210. In addition, the pixel defining layer 119 may prevent or substantially prevent arcing at one or more edges of the pixel electrode 210, etc., by increasing a distance between the edge of the pixel electrode 210 and the counter electrode 230 at an upper portion of the pixel electrode 210. The pixel defining layer 119 may include an organic insulating material such as polyimide, polyamide, acrylic resin, BCB, HMDSO, and phenolic resin, and may be formed using a spin coating method, etc.

[0158] The intermediate layer 220 of the organic light emitting diode OLED may include an organic emission layer. The organic emission layer may include an organic material including a fluorescent material or a phosphorescent material that emits red, green, blue or white light. The organic emission layer may include a low molecular weight organic material or a high molecular weight organic material. Functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL) and an electron injection layer (EIL) may be alternatively and additionally disposed below and above the organic emission layer. The intermediate layer 220 may be disposed to correspond to each pixel electrode 210 in a plurality of pixel electrodes 210. However, the intermediate layer 220 is not limited thereto. The intermediate layer 220 may be appropriately modified, for example, in one or more embodiments, the intermediate layer 220 includes a layer integrally formed across a plurality of pixel electrodes 210.

[0159] The counter electrode 230 may be a light-transmitting electrode or a reflective electrode. In one or more embodiments, the counter electrode 230 may include a transparent or semi-transparent electrode and may include a metal film containing lithium (Li), calcium (Ca), lithium fluoride (LiF) / Ca, LiF / Al, aluminum (Al), silver (Ag), magnesium (Mg) and / or a combination thereof and having a small work function. 2 O 3 A transparent conductive oxide (TCO) layer of the like may be further disposed on the metal film. The counter electrode 230 may be disposed to span the display area DA and the peripheral area PA, and may be disposed on the intermediate layer 220 and the pixel defining layer 119. The counter electrode 230 may be formed as a single body with respect to the plurality of organic light emitting diodes OLED to correspond to the plurality of pixel electrodes 210.

[0160] When the pixel electrode 210 is a reflective electrode and the counter electrode 230 is a transmissive electrode, the light emitted from the intermediate layer 220 is emitted toward the counter electrode 230, and thus the display device may be a top emission type. When the pixel electrode 210 includes a transparent or semi-transparent electrode and the counter electrode 230 includes a reflective electrode, the light emitted from the intermediate layer 220 is emitted toward the substrate 100, and thus the display device may be a bottom emission type. However, the embodiment is not limited thereto. The display device in the present embodiment may be a dual emission type that emits light in two directions (e.g., toward the top and toward the bottom).

[0161] Figure 8 is a schematic top plan view of a display panel 10 according to an embodiment, and Fig. 9 is a fragment of a top plan view of a selected semiconductor layer including pixels disposed around a first region in the display panel 10 according to an embodiment.

[0162] refer to Figure 8 , the display panel 10 may include a first area OA, a display area DA surrounding the first area OA, a middle area MA located between the first area OA and the display area DA, and a peripheral area PA surrounding the display area DA. Figure 8 It may be understood as illustrating the substrate 100 in the display panel 10. For example, it may be understood that the substrate 100 of the display panel 10 includes a first area OA, a display area DA, a middle area MA, and a peripheral area PA.

[0163] The display area DA is an area in which a plurality of pixels are arranged. Hereinafter, for convenience of explanation, the display area DA is described as including a plurality of sub-display areas. Figure 8 In the top plan view, the portions of the display area DA located above, below, on the left and on the right relative to the first area OA are respectively referred to as the first sub-display area SDA1, the second sub-display area SDA2, the third sub-display area SDA3 and the fourth sub-display area SDA4.

[0164] The plurality of pixels may include a first pixel P1 disposed in the first sub display area SDA1, a second pixel P2 disposed in the second sub display area SDA2, a third pixel P3 disposed in the third sub display area SDA3, and a fourth pixel P4 disposed in the fourth sub display area SDA4. A first group of the first pixels P1 may be disposed in the first sub display area SDA1; a second group of the second pixels P2 may be disposed in the second sub display area SDA2; a third group of the third pixels P3 may be disposed in the third sub display area SDA3; and a fourth group of the fourth pixels P4 may be disposed in the fourth sub display area SDA4.

[0165] The first pixel P1, the second pixel P2, the third pixel P3, and the fourth pixel P4 may each include the above reference Fig. 6A The pixel circuit described above, and each pixel may include Fig. 9 The semiconductor layer 1130 shown. Around the first area OA, the semiconductor layer 1130 may have a stepped configuration. The semiconductor layers 1130 included in adjacent pixels may be connected to each other in the first direction (ie, the y direction), such as Fig. 9 shown.

[0166] refer to Figure 8 and Fig. 9 , each of the first pixels P1 in the first sub display area SDA1 includes a semiconductor layer 1130, and as Fig. 9 As shown, the semiconductor layers 1130 included in the first pixel P1 may be connected to each other in the y direction and form a plurality of first rows R1. That is, each of the first rows R1 includes a plurality of semiconductor layers 1130 connected to each other in the y direction.

[0167] Similarly, each of the second pixels P2 in the second sub display area SDA2 includes a semiconductor layer 1130, and as shown in FIG. Fig. 9 As shown, the semiconductor layers 1130 in the second pixel P2 may be connected to each other in the y direction and form a plurality of second rows R2. Each of the second rows R2 includes a plurality of semiconductor layers 1130 connected to each other in the y direction.

[0168] The third pixel P3 and the fourth pixel P4 respectively disposed in the third sub-display area SDA3 and the fourth sub-display area SDA4 also each include a semiconductor layer 1130. The semiconductor layers 1130 in the third pixel P3 may be connected to each other in the y direction and form a plurality of third rows R3, and the semiconductor layers 1130 in the fourth pixel P4 may be connected to each other in the y direction and form a plurality of fourth rows R4. The third row R3 and the fourth row R4 respectively include a plurality of semiconductor layers 1130 connected to each other in the y direction.

[0169] That is, the semiconductor layer 1130 located in the display area DA extends in the y direction and forms a plurality of rows (e.g., a first row R1, a second row R2, a third row R3, and a fourth row R4), wherein the first row R1 and the second row R2 are separated (or spaced apart) from each other, and the first area OA may be between the first row R1 and the second row R2. The third row R3 and the fourth row R4 may extend in the y direction across the display area DA (e.g., continuously), respectively, as shown in FIG. Fig. 9As shown. Since the first area OA is provided between the first row R1 and the second row R2, the length (e.g., the length in the y direction) of each of the first row R1 and the second row R2 may be smaller than the length of the third row R3 or the fourth row R4. The total range or area of ​​the first row R1 may be smaller than the total range or area of ​​the third row R3 or the fourth row R4. Similarly, the total range or area of ​​the second row R2 may be smaller than the total range or area of ​​the third row R3 or the fourth row R4.

[0170] According to the above-mentioned structural difference, load deviation is caused in each part of the display area DA, and brightness non-uniformity may be caused in each part of the display area DA due to the load deviation. For example, in a part where a row of a relatively short semiconductor layer is provided (e.g., Figure 8 In the first sub-display area SDA1 shown, the brightness non-uniformity may be significant. However, the display panel 10 according to the embodiment may include a connection line connecting the rows of the semiconductor layer disposed around the first area OA, thereby reducing the load deviation and preventing or reducing the brightness non-uniformity.

[0171] In an embodiment, the first rows R1 extending in a first direction (eg, y direction) may be connected to a first connection line extending in a second direction (eg, x direction) intersecting or crossing the direction in which the first rows R1 extend. Fig. 9 An embodiment is shown in which the first connection lines connecting the first rows R1 to each other include a first-first connection line CAL1-1 and a first-second connection line CAL1-2. In one or more embodiments, the first-first connection line CAL1-1 and the first-second connection line CAL1-2 may include the same material as the semiconductor layer 1130, and may be formed concurrently (e.g., simultaneously) with the semiconductor layer 1130 during a process of forming the semiconductor layer 1130. The first connection line may be formed integrally with the first row R1.

[0172] As another embodiment, the second rows R2 extending in the first direction (eg, the y direction) may be connected to a second connection line extending in a second direction (eg, the x direction) intersecting the direction in which the second rows R2 extend. Fig. 9 The second connection lines connecting the second rows R2 to each other are shown to include a second-first connection line CAL2-1 and a second-second connection line CAL2-2. In one or more embodiments, the second-first connection line CAL2-1 and the second-second connection line CAL2-2 may include the same material as the semiconductor layer 1130, and may be formed concurrently (e.g., simultaneously) with the semiconductor layer 1130 during a process of forming the semiconductor layer 1130. The second connection lines may be formed integrally with the second rows R2.

[0173] When the display panel 10 includes Figure 8 and Fig. 9 When both the first connecting line and the second connecting line are included in the embodiment, in one or more embodiments, the first connecting line or the second connecting line may be omitted.

[0174] The first connection line may be connected to an end of the first row R1. For example, the first row R1 may include a first end and a second end opposite to the first end, respectively. The first-first connection line CAL1-1 may be connected to each of the first ends of the first row R1, and the first-second connection line CAL1-2 may be connected to each of the second ends of the first row R1. The first-first connection line CAL1-1 may be positioned relatively adjacent to the first area OA, and the first-second connection line CAL1-2 may be positioned relatively away from (e.g., not directly adjacent to) the first area OA.

[0175] The first-first connection line CAL1-1 and the first-second connection line CAL1-2 are respectively connected to the first row R1, and the first-second connection line CAL1-2 may be further extended in the second direction (eg, the x direction) to be connected to a row in another semiconductor layer located adjacent to the first row R1. Figure 8 and Fig. 9 As shown, the first-second connection line CAL1-2 may be connected to one end portion of each of the third row R3 and / or the fourth row R4.

[0176] exist Figure 8 and Fig. 9 In the embodiment, the first connection line includes both the first-first connection line CAL1-1 and the first-second connection line CAL1-2, but the embodiment is not limited thereto. In one or more embodiments, the first connection line may include only the first-first connection line CAL1-1 or only the first-second connection line CAL1-2. However, when the first connection line includes both the first-first connection line CAL1-1 and the first-second connection line CAL1-2, the load deviation can be more effectively reduced.

[0177] Similarly, the second rows R2 may include first ends and second ends opposite to the first ends, respectively, the second-first connection wire CAL2-1 may be connected to each of the first ends of the second rows R2, and the second-second connection wire CAL2-2 may be connected to each of the second ends of the second rows R2. The second-first connection wire CAL2-1 may be positioned relatively adjacent to the first area OA, and the second-second connection wire CAL2-2 may be positioned relatively separated from the first area OA (e.g., not directly adjacent to the first area OA).

[0178] The second-first connection line CAL2-1 and the second-second connection line CAL2-2 are respectively connected to the second row R2, and the second-second connection line CAL2-2 may be further extended in the second direction (eg, the x direction) to be connected to a row in another semiconductor layer located adjacent to the second row R2. Figure 8 and Fig. 9 As shown, the second-second connection line CAL2-2 may be connected to the other end portion of each of the third row R3 and / or the fourth row R4.

[0179] exist Figure 8 and Fig. 9 In the embodiment, the second connection line includes both the second-first connection line CAL2-1 and the second-second connection line CAL2-2, but the embodiment is not limited thereto. In one or more embodiments, the second connection line may include only the second-first connection line CAL2-1 or only the second-second connection line CAL2-2. In terms of reducing load deviation, it may be preferred that the second connection line includes the second-first connection line CAL2-1 and the second-second connection line CAL2-2.

[0180] Fig. 10A and Fig. 10B are each showing a portion of the display panel 10 according to the embodiment and Figure 8 The enlarged view of the X portion shown corresponds to a top plan view.

[0181] refer to Figure 8 , Fig. 10A and Fig. 10B , the corners of the display area DA may be rounded (see Figure 8 ), and the semiconductor layer 1130 at the corner portion has a step configuration (see Fig. 10A and Fig. 10B ).

[0182] A plurality of semiconductor layers may be disposed in the display area DA, wherein each semiconductor layer in each row may be an effective semiconductor layer. Here, the effective semiconductor layer indicates a semiconductor layer on which a transistor for operating each pixel is formed, that is, a semiconductor layer in which a pixel circuit is formed. In an embodiment, some of the semiconductor layers disposed in a row may be dummy semiconductor layers 1130D. For example, Fig. 10B As shown, each of the first rows R1 includes a dummy semiconductor layer 1130D located at one side of an end of the first row R1, and each of the third rows R3 may include a dummy semiconductor layer 1130D located at one side of an end of the third row R3.

[0183] Fig.11is a top plan view of a semiconductor layer included in each of pixels disposed around a first region in a display panel 10 according to an embodiment, and FIG. 12A to FIG. 12D Each is along Fig.11 The cross-sectional view of the display panel 10 ′ is taken along line XII-XII′.

[0184] The display panel 10' may include a plurality of first regions. In this regard, Fig.11 Two first areas OA1 and OA2 are shown. Since other features except the number of first areas OA1 and OA2 are the same as those of reference Figure 8 and Fig. 9 Other features of the described display panel 10 are the same, so the differences between the display panel 10 and the display panel 10 ′ may be described below.

[0185] refer to Fig. 12A , the display panel 10' may include a first opening 10H located in each of the first areas OA1 and OA2. Fig. 12B As shown, the display panel 10' may include a first opening 10H located in one of the first areas OA1 and OA2, and may not provide an opening in the other of the first areas OA1 and OA2. Fig. 12C As shown, the display panel 10 ′ may not include openings corresponding to the first areas OA1 and OA2 .

[0186] Each of the first areas OA1 and OA2 may be an area in which a component is located. In this regard, FIG. 12A to FIG. 12C The first component 21 and the second component 22 are shown. The first component 21 and the second component 22 may include different elements, respectively. For example, one of the first component 21 and the second component 22 may include a camera, a speaker, etc., and the other of the first component 21 and the second component 22 may include a sensor. In an embodiment, the first component 21 and the second component 22 may include the same components. In an embodiment, as Fig.12D As shown, one component 20 may be positioned to overlap a plurality of first areas (eg, first areas OA1 and OA2 ).

[0187] Fig.13 is a schematic top plan view of a display panel 10 ″ according to an embodiment, and Fig.14 is a fragment of a top plan view of a selected semiconductor layer included in each of pixels disposed around a first region in a display panel 10 ″ according to an embodiment.

[0188] According to reference Figures 8 to 11 In the described embodiment, the semiconductor layers are connected to each other in the y direction, but the embodiment is not limited thereto. Fig.13 and Fig.14 As shown, the semiconductor layers can be connected to one another in the x-direction.

[0189] refer to Fig.13 , a plurality of pixels are arranged in the display area DA. The plurality of pixels may include a first pixel P1 arranged in the first sub-display area SDA1', a second pixel P2 arranged in the second sub-display area SDA2', a third pixel P3 arranged in the third sub-display area SDA3', and a fourth pixel P4 arranged in the fourth sub-display area SDA4'. The first pixel P1, the second pixel P2, the third pixel P3, and the fourth pixel P4 may each include the above reference pixel P1. Fig. 6A The pixel circuit described above, and the semiconductor layer may be as Fig.14 The diagrams are shown connected to each other in the x-direction.

[0190] refer to Fig.13 and Fig.14 , each of the first pixels P1 corresponding to the first sub display area SDA1' may include a semiconductor layer 1130', and as Fig.14 As shown, the semiconductor layers 1130' in the first pixel P1 may be connected to each other in the x direction and form a plurality of first rows R1'. That is, each of the first rows R1' includes a plurality of semiconductor layers 1130' connected to each other in the x direction. Similarly, the second pixel P2, the third pixel P3, and the fourth pixel P4 each include a semiconductor layer 1130', and as shown in FIG. Fig.14 As shown, the semiconductor layers 1130 ′ may be connected to each other in the x-direction and form a second row R2 ′, a third row R3 ′, and a fourth row R4 ′.

[0191] Each of the third row R3' and the fourth row R4' extends in the x direction across the display area DA (eg, continuously extends), as shown in FIG. Fig.14 As shown. In contrast, the first row R1' and the second row 'R2 are arranged to be separated from each other (e.g., spaced apart), the first area OA is between the first row R1' and the second row 'R2, and therefore, the length of each of the first row R1' and the second row R2' (e.g., in the x direction) may be smaller than the length of the third row R3' or the fourth row R4'. In order to reduce the load deviation according to the structural difference, the display panel 10" may include a connection line connecting the rows in the semiconductor layer. In this regard, Fig.14 A first connection line connecting the first rows R1 ′ to one another and a second connection line connecting the second rows R2 ′ to one another are shown.

[0192] The first connection lines may include a first-first connection line CAL1-1' connected to a first end of each of the first rows R1' and / or a first-second connection line CAL1-2' connected to a second end of each of the first rows R1'. The first-first connection line CAL1-1' may be positioned relatively adjacent to the first area OA, and the first-second connection line CAL1-2' may be positioned relatively separated from the first area OA (e.g., not directly adjacent to the first area OA). Fig. 9 Similar to the first-second connection line CAL1-2 described above, the first-second connection line CAL1-2' may be connected to a row in the semiconductor layer included in other groups (e.g., a group of third pixels P3 and / or a group of fourth pixels P4) disposed adjacent to the first pixel P1. Fig.13 and Fig.14 As shown, the first-second connection line CAL1-2' may extend in the second direction (eg, the y direction) and be connected to one end of each of the third row R3' and the fourth row R4'.

[0193] The second connection lines may include a second-first connection line CAL2-1' connected to a first end of each of the second rows R2' and / or a second-second connection line CAL2-2' connected to a second end of each of the second rows R2'. The second-first connection line CAL2-1' may be positioned relatively adjacent to the first area OA, and the second-second connection line CAL2-2' may be positioned relatively separated from the first area OA (e.g., not directly adjacent to the first area OA). Fig. 9 Like the second-second connection line CAL2-2 described above, the second-second connection line CAL2-2' may be connected to a row in the semiconductor layer included in other groups (e.g., a group of third pixels P3 and / or a group of fourth pixels P4) disposed adjacent to the first pixel P1. Fig.13 and Fig.14 As shown, the second-second connection line CAL2-2' may be connected to the other end of each of the third row R3' and / or the fourth row R4'.

[0194] exist Fig.13 and Fig.14 In the embodiment, the display panel 10 ″ includes the first connection line and the second connection line, but the embodiment is not limited thereto. In the embodiment, only one of the first connection line and the second connection line may be provided in the display panel 10 ″.

[0195] exist Fig.13 and Fig.14In the embodiment, the first connection line includes a first-first connection line CAL1-1' and a first-second connection line CAL1-2'. However, in one or more embodiments, the display panel 10" may include one of the first-first connection line CAL1-1' and the first-second connection line CAL1-2'. Similarly, Fig.13 and Fig.14 It is shown that the second connection line includes the second-first connection line CAL2-1' and the second-second connection line CAL2-2'. However, in one or more embodiments, the display panel 10" may include one of the second-first connection line CAL2-1' and the second-second connection line CAL2-2'.

[0196] Fig.15 is a top plan view showing a display panel 10'' according to an embodiment, and Fig.16 1 is a top plan view showing a semiconductor layer disposed around a first region in a display panel 10 ′″ according to an embodiment.

[0197] refer to Fig.15 The display panel 10'' may include a first-first connection line CAL1-1'', a first-second connection line CAL1-2'', a second-first connection line CAL2-1'' and / or a second-second connection line CAL2-2''. The first-second connection line CAL1-2'' and the second-second connection line CAL2-2'' are respectively connected to the reference Figure 8 and Fig. 9 The described first-second connection line CAL1 - 2 and second-second connection line CAL2 - 2 are the same or substantially similar, and their differences may be described below.

[0198] The first-first connection line CAL1-1" can be connected not only to the first row R1" of the semiconductor layer set in the first sub-display area SDA1, but also to the third row R3" of the semiconductor layer set in the third sub-display area SDA3 adjacent to the first sub-display area SDA1 and / or the fourth row R4" of the semiconductor layer set in the fourth sub-display area SDA4. Similarly, the second-first connection line CAL2-1" can be connected not only to the second row R2" of the semiconductor layer set in the second sub-display area SDA2, but also to the third row R3" of the semiconductor layer set in the third sub-display area SDA3 adjacent to the second sub-display area SDA2 and / or the fourth row R4" of the semiconductor layer set in the fourth sub-display area SDA4.

[0199] Each of the first rows R1″ in the semiconductor layer may extend in the y direction and be connected to an adjacent row in the x direction. Fig.16As shown, any one of the first rows R1” can be connected to an adjacent first row R1”, or to a third row R3” or a fourth row R4” adjacent to the first row R1”. Similarly, the second row R2”, the second row R3”, and the fourth row R4” can each extend in the y direction and be connected to an adjacent row in the x direction. As described above, when each of the first row R1”, the second row R2”, the third row R3”, and the fourth row R4” is connected to an adjacent row, the semiconductor layers can be connected to each other in the x direction or the y direction.

[0200] The display panel 10 ′″ may further include third and / or fourth connection lines CAL3 and CAL4 extending in the y direction, and the third and fourth connection lines CAL3 and CAL4 may be connected to the third and fourth rows R3 ″ and R4 ″, respectively.

[0201] Fig.15 and Fig.16 A structure in which semiconductor layers are connected to each other in the y direction to form rows and adjacent rows are connected to each other in the x direction, that is, a structure in which semiconductor layers are connected in the y direction and the x direction, is shown, but the embodiment is not limited thereto. Fig.15 and Fig.16 The features of the first-first connection line CAL1-1" and the second-first connection line CAL2-1" described above can also be applied to the above reference Figure 8 and Fig. 9 The display panel 10 is described.

[0202] According to the embodiment, brightness non-uniformity occurring in each portion of the display area in the display panel including the first area in the inner portion of the display area may be prevented or reduced.

[0203] It should be understood that the embodiments described herein should be considered in a descriptive rather than a limiting sense. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments.

[0204] Although one or more embodiments have been described with reference to the drawings, it will be understood by those skilled in the art that various appropriate changes in form and details may be made in the embodiments without departing from the spirit and scope as defined by the appended claims and their equivalents.

Claims

1. A display panel, comprising: A substrate including a display area and a first area in the display area; and a plurality of pixels in the display area and surrounding the first area, each of the plurality of pixels being configured to emit light, wherein the plurality of pixels include a first group of first pixels adjacent to the first region, and each of the first pixels includes a first semiconductor layer, wherein the first semiconductor layer of each of the first pixels is connected to the first semiconductor layer of another of the first pixels in a first direction to form a first row disposed on the substrate, and The first row is connected to a first connection line extending in a second direction crossing the first direction.

2. The display panel according to claim 1, wherein: The first row includes a first end adjacent to the first region and a second end opposite to the first end, and The first connection line is connected to at least one of the first end portion and the second end portion.

3. The display panel according to claim 1, wherein: The plurality of pixels include a first adjacent pixel group adjacent to the first group, and each of the pixels in the first adjacent pixel group includes a semiconductor layer, wherein the semiconductor layer of each of the pixels in the first adjacent pixel group is connected to the semiconductor layer of another of the pixels in the first adjacent pixel group in the first direction to form a plurality of rows disposed on the substrate, and The first connection lines are connected to the plurality of rows in the first adjacent pixel group.

4. The display panel according to claim 3, wherein: A total area of ​​the first semiconductor layer in the first group is different from a total area of ​​the semiconductor layer in the first adjacent pixel group.

5. The display panel according to claim 1, wherein: The first connection line and the first semiconductor layer include the same material.

6. The display panel according to claim 1, wherein: The plurality of pixels further includes a second group of second pixels spaced apart from the first group of the first pixels, and the first region is between the first group and the second group, wherein each of the second pixels comprises a second semiconductor layer, and The second semiconductor layer of each of the second pixels is connected to the second semiconductor layer of another of the second pixels in the first direction to form a second row disposed on the substrate.

7. The display panel according to claim 6, further comprising: A second connection line extends in the second direction, and the second row is connected to the second connection line.

8. The display panel according to claim 7, wherein: The second row includes a first end adjacent to the first region and a second end opposite to the first end, and The second connection line is connected to at least one of the first end and the second end of the second row.

9. The display panel according to claim 7, wherein: The plurality of pixels further include a second adjacent pixel group adjacent to the second group, and each of the pixels in the second adjacent pixel group includes a semiconductor layer, wherein the semiconductor layer of each of the pixels in the second adjacent pixel group is connected to the semiconductor layer of another of the pixels in the second adjacent pixel group in the first direction to form a plurality of rows disposed on the substrate, and The second connection lines are connected to the plurality of rows in the second adjacent pixel group.

10. The display panel according to claim 7, wherein: The second connection line and the second semiconductor layer include the same material.

11. A display panel, comprising: A substrate including a first region and a second region; a plurality of rows, in the second area, the first area is surrounded by the second area where the plurality of rows are located, the plurality of rows comprising: a plurality of first rows in the second region and configured to drive the display panel to emit light, each of the plurality of first rows including a plurality of first semiconductor layers connected to each other in a first direction; and a plurality of second rows in the second region, each of the plurality of second rows including a plurality of second semiconductor layers connected to each other in the first direction; and A first connection line is connected to the plurality of first rows and extends in a second direction crossing the first direction.

12. The display panel according to claim 11, wherein: The first connection line and the plurality of first semiconductor layers include a same material.

13. The display panel according to claim 11, wherein: Each of the plurality of first rows includes a first end adjacent to the first region and a second end opposite to the first end, and The first connecting line is connected to at least one of the first end and the second end.

14. The display panel according to claim 11, further comprising: a plurality of first adjacent rows adjacent to the plurality of first rows, each of the plurality of first adjacent rows including a plurality of semiconductor layers connected to each other in the first direction, Wherein, the first connection line is connected to the plurality of first adjacent rows.

15. The display panel according to claim 14, wherein: The plurality of first semiconductor layers and the plurality of semiconductor layers are respectively connected to adjacent first semiconductor layers or semiconductor layers in the second direction.

16. The display panel according to claim 11, wherein: The plurality of first rows and the plurality of second rows are separated from each other, and the first region is between the plurality of first rows and the plurality of second rows.

17. The display panel according to claim 16, wherein: The plurality of first semiconductor layers and the plurality of second semiconductor layers are step-wise disposed in a region adjacent to the first region.

18. The display panel according to claim 11, further comprising: Second connection lines are connected to the plurality of second rows and extend in the second direction.

19. The display panel according to claim 18, wherein: The second connection line and the plurality of second semiconductor layers include a same material.

20. The display panel according to claim 18, further comprising: a plurality of second adjacent rows adjacent to the plurality of second rows, each of the plurality of second adjacent rows including a plurality of semiconductor layers connected to each other in the first direction, Wherein, the second connection line is connected to the plurality of second adjacent rows.

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