Variation-Resistant 3T3R Binary Weight Cell with Low Output Current and High On / Off Ratio

Abstract

This disclosure provides a variation - resistant 3T3R binary weight cell and device with low output current and high on / off ratio. The weight cell includes: a first field - effect transistor (FET) and a first resistive memory element connected to the drain of the first FET; a second FET and a second resistive memory element connected to the drain of the second FET, the drain of the first FET is connected to the gate of the second FET, and the drain of the second FET is connected to the gate of the first FET; a third FET; and a load resistor connected to the drain of the third FET.

Description

[0001] Priority

[0002] This application claims priority to U.S. Provisional Application Serial No. 62 / 812,826, filed on March 1, 2019, and to U.S. Provisional Application Serial No. 62 / 812,529, filed on March 1, 2019. This application claims priority to U.S. Application Serial No. 16 / 448,820, filed on June 21, 2019, the entire content of which is incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to a binary weight cell that effectively increases the on / off ratio of a resistive memory device that can have a relatively small intrinsic on / off ratio and reduces the magnitude and variation of the output current cumulatively generated in parallel during inference. Background Art

[0004] There is a growing need for hardware accelerators for machine learning (ML) applications. The computation that dominates many of these ML applications is matrix-vector multiplication. It is possible to perform matrix-vector multiplication very efficiently in an analog manner through a crossbar network. However, in order to represent the weights, a memory element must be introduced in each weight cell. Static random access memory (SRAM) is large and has low power consumption. Non-volatile memory options such as resistive random access memory (RRAM), FLASH, or spin-transfer torque magnetic random access memory (STT-MRAM) typically suffer from a subset of other challenges, including low on / off ratio, high variation, and incompatible programming voltages. Summary of the Invention

[0005] According to one embodiment, a weight cell is provided. The weight cell includes: a first field effect transistor (FET) and a first resistive memory element connected to the drain of the first FET; a second FET and a second resistive memory element connected to the drain of the second FET, the drain of the first FET being connected to the gate of the second FET, and the drain of the second FET being connected to the gate of the first FET; a third FET; and a load resistor connected to the drain of the third FET.

[0006] According to one embodiment, a device is provided. The device includes an array of weight cells, each weight cell including: a first field-effect transistor (FET) and a first resistive memory element connected to the drain of the first FET; a second FET and a second resistive memory element connected to the drain of the second FET, the drain of the first FET being connected to the gate of the second FET, and the drain of the second FET being connected to the gate of the first FET; a third FET; and a load resistor connected to the drain of the third FET. The device includes a processor configured to perform inference on the array of weight cells by setting inputs to rows of weight cells in the weight array according to the logic values of corresponding neurons and reading outputs of columns of weight cells from the weight array.

[0007] According to one embodiment, a device is provided. The device includes an array of weight cells, each weight cell including: a first field-effect transistor (FET) and a first resistive memory element connected to the drain of the first FET; a second FET and a second resistive memory element connected to the drain of the second FET, the drain of the first FET being connected to the gate of the second FET, and the drain of the second FET being connected to the gate of the first FET; a third FET; and a load resistor connected to the drain of the third FET. The processor is configured to write to the resistive memory element according to the direction of the current supplied to the resistive memory element. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a circuit diagram of a weight cell according to an embodiment;

[0010] Figure 2 is a circuit diagram of an array of weight cells according to an embodiment;

[0011] Figure 3A is a graph of the current output of an array of weight cells with a linear axis according to an embodiment;

[0012] Figure 3B is a graph of the current output of an array of weight cells with a semi-logarithmic axis according to an embodiment; and

[0013] Figure 4 is a block diagram of an electronic device in a network environment according to one embodiment. DETAILED DESCRIPTION

[0014] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that although the same elements are shown in different drawings, they will be denoted by the same reference numerals. In the following description, only specific details such as detailed configurations and components are provided to assist in the overall understanding of the embodiments of the present disclosure. Therefore, it is obvious to those skilled in the art that various changes and modifications can be made to the embodiments described herein without departing from the scope of the present disclosure. In addition, descriptions of well-known functions and configurations are omitted for clarity and conciseness. The terms described below are defined in consideration of the functions in the present disclosure and may vary according to the user, the user's intention, or custom. Therefore, the definitions of the terms should be determined based on the content throughout the specification.

[0015] The present disclosure may have various modifications and various embodiments. In the following, embodiments will be described in detail with reference to the accompanying drawings. However, it should be understood that the present disclosure is not limited to the embodiments, but includes all modifications, equivalent forms, and alternative forms within the scope of the present disclosure.

[0016] Although ordinal terms such as first, second, etc. may be used to describe various elements, the structural elements are not limited by such terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, the first structural element may be referred to as the second structural element. Similarly, the second structural element may also be referred to as the first structural element. As used herein, the term "and / or" includes any and all combinations of one or more related items.

[0017] The terms used herein are only for describing various embodiments of the present disclosure and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form. In the present disclosure, it should be understood that the term "comprising" means the presence of features, numbers, steps, operations, structural elements, components, or combinations thereof, and does not exclude the presence or possibility of one or more other features, numbers, steps, operations, structural elements, components, or combinations thereof.

[0018] Unless otherwise defined, all terms used herein have the same meaning as understood by those skilled in the art to which the present disclosure pertains. Unless clearly defined in the present disclosure, the meanings of terms such as those defined in a general dictionary should be interpreted as having the same meaning as the context meaning in the relevant field and should not be interpreted as having an ideal or overly formal meaning.

[0019] An electronic device according to an embodiment may be one of various types of electronic devices. The electronic device may include, for example, a portable communication device (e.g., a smart phone), a computer, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance. According to an embodiment of the present disclosure, the electronic device is not limited to those described above.

[0020] The terms used in this disclosure are not intended to limit this disclosure, but are intended to include various changes, equivalents, or substitutions of the corresponding embodiments. Regarding the description of the drawings, like reference numerals may be used to refer to like or related elements. The singular form of a noun corresponding to an item may include one or more things, unless the relevant context clearly indicates otherwise. As used herein, each phrase such as "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" may include all possible combinations of the items listed together in one of the corresponding phrases. As used herein, terms such as "first" and "second" may be used to distinguish a corresponding component from another component, but are not intended to limit these components in other respects (e.g., importance or order). It is intended that if an element (e.g., a first element) is referred to as being, having, or not having the terms "operatively" or "communicatively" coupled, connected, or joined to another element (e.g., a second element), it indicates that the element may be coupled to the other element directly (e.g., wired), wirelessly, or via a third element.

[0021] As used herein, the term "module" may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with other terms such as "logic", "logic block", "component", and "circuit". A module may be a single integral component or its smallest unit or part adapted to perform one or more functions. For example, according to an embodiment, a module may be implemented in the form of an application specific integrated circuit (ASIC).

[0022] The present disclosure provides a binary weight unit that effectively increases the on / off ratio of a resistive memory device that may have a relatively small inherent on / off ratio, and reduces the magnitude and variation of the output current cumulatively generated in parallel during inference.

[0023] In an exemplary scenario, a binary weight cell for semi-digital matrix vector multiplication includes two magnetic tunnel junctions (MTJs), three N-type field effect transistors (NFETs), and a polysilicon load resistor. Each MTJ is a resistive memory element that can be in one of two states: a high-resistive state or a low-resistive state. Existing MTJ technologies can only achieve a relatively small high / low conductivity (usually only 2 - 3). Additionally, compared to the ideal option of parallel reading during inference, the conductance values of MTJs are relatively large, resulting in a large output current. The present disclosure provides a binary weight cell configuration with logical values {1, 0}, where even if the MTJ has an on / off ratio of only 2 - 3, the on / off ratio of the output current is close to that of a transistor (10 4 –10 5 ). Moreover, the magnitude and variation of the output current for logic 1 are limited by the load resistor, which can be designed to match the current output required for large-scale parallel reading and has a smaller variation amplitude than the MTJ.

[0024] Figure 1 FIG. is a circuit diagram of a weight cell 100 according to an embodiment. The weight cell 100 includes a first magnetic tunnel junction (MTJ) 102, a second MTJ 104, and a load resistor 106. The weight cell 100 also includes a first field effect transistor (FET) 110, a second FET 120, and a third FET 130. Although p-type FETs can be used, FETs 110, 120, and 130 are described as n-type FETs (NFETs). FET 110 includes a drain 112, a gate 114, and a source 116. Similarly, FET 120 includes a drain 122, a gate 124, and a source 126. The weight cell 100 includes a first cross-coupling such that the drain 112 of FET 110 is connected to the gate 124 of FET 120, and the drain 122 of FET 120 is connected to the gate 114 of FET 110. FET 130 includes a drain 132, a gate 134, and a source 136. The load resistor 106 is connected to the drain 132 of FET 130, and the gate 134 of FET 130 is connected to the gate 114 of FET 110.

[0025] MTJ 102 has a conductance G, while MTJ 104 has a conductance The weight cell 100 includes five independent external connections: an input V to MTJ 102 and the load resistor 106 in , an input to MTJ 104 , an input V to the source 116 of FET 110 prog , an input to the source 126 of FET 120 and an output I to the source 136 of FET 130out MTJ102 has a conductance G, while MTJ 104 has a conductance Each of MTJs 102 and 104 can be in one of two states, namely a high-conductance state G H or a low-conductance state G L Cross-coupling allows for a high on / off ratio of the output. MTJs 102 and 104 have different conductance states, and this configuration determines the logic value. For example, if the logic value of weight cell 100 is 1, then G = G L , Likewise, if the logic value of weight cell 100 is 0, then G = G H , as shown in Table 1.

[0026] Table 1

[0027]

[0028] During inference, weight cell 100 performs a multiplication operation in an analog manner based on the potential on the input line and the state of weight cell 100. The product is the analog current on output line I out For an input with a logic value of 0, both input lines V in and are held grounded, thus turning off FETs 110, 120, and 130, and therefore there is no current on the collective output line I out For an input with a logic value of 1, both input lines V in and are held at the read voltage V r , which should be small enough so that the current through the MTJ is less than the current that would cause a state change (i.e., a read disturbance fault). Cross-coupling ensures that when , the transistor connected to the MTJ in the low-conductance state will conduct, and the transistor connected to the MTJ in the high-conductance state will turn off. Thus, if the gate 134 of FET 130 connected to load resistor 106 is connected to the gate 114 of FET 110, then whenever FET 110 conducts, FET 130 will conduct, and whenever FET 110 turns off, FET 130 will turn off. Then, respectively, in the limits of no leakage current through the transistor and zero series resistance, the output current is approximately equal to 0 or the read current I r , where I r = V r / R load . Due to the conduction of FET 110 or FET 120, there is a parasitic static current G L V r in each weight cell whenever the input is logic 1.

[0029] Figure 2 It is a circuit diagram of the weight cell array 200 according to an embodiment. The weight cell array 200 includes two rows of weight cells. The first row includes weight cells 202 - 206, and the second row includes weight cells 208 - 212. To perform inference on the weight cell array 200, the inputs to each row are set according to the logical values of the corresponding neurons. The output lines are read in parallel along each column. and measure the total current on output I out and divide it by I r to obtain the binary product between N input neurons and N binary weights in a given column. The inputs to each row are set according to the logical values corresponding to the neurons.

[0030] Figure 3A It is a graph 300 of the current output of the weight cell array 200 with a linear axis according to an embodiment. Referring to the weight cell array 200, each weight cell has a logical value. The logical value of weight cell 202 is 0, the logical value of weight cell 204 is 1, the logical value of weight cell 206 is 1, the logical value of weight cell 208 is 0, the logical value of weight cell 210 is 0, and the logical value of weight cell 212 is 1.

[0031] Referring to graph 300, the currents read at the output of each column are different, representing different values for different logical value pairs along each column. The output at I out 1 is shown as line 302, the output at I out 2 is shown as line 304, and the output at I out 3 is shown as line 306.

[0032] Figure 3B It is a graph 310 of the current output of the weight cell array 200 with a semi - logarithmic axis according to an embodiment. Referring to graph 310, the currents read at the output of each column are different, representing different values for different logical value pairs along each column. The output at I out 1 is shown as line 312, the output at I out 2 is shown as line 314, and the output at I out 3 is shown as line 316.

[0033] Writing to a given cell requires a separate step depending on the direction in which the MTJ is written ("down" or "up"), which is defined as the direction of the current relative to Figure 1 the direction of the weight cell 100 shown. Any MTJ can be written in either direction according to one of the three steps outlined in Table 2 and Table 3.

[0034] Table 2

[0035]

[0036] Table 2 summarizes the write operations in the downward direction and the voltages for writing to the MTJs downward for all columns in a given row. V w is defined as the write voltage, which should be large enough to switch the MTJ. I out should be held at V w , in order to eliminate the parasitic current across R load during writing. By setting all the input lines to the voltages shown in Table 2, each cell in a given row can be programmed downward for GMTJ or MTJ.

[0037] Table 3

[0038]

[0039] Table 3 summarizes the write operations in the upward direction and the voltages for writing to the MTJs upward for all rows in a given column. I out should be held at V w , in order to eliminate the parasitic current across R load during writing. By setting all the input lines to the voltages shown in Table 3, each cell in a given row can be programmed for GMTJ or MTJ.

[0040] Other non-volatile storage technologies can be used instead of STT-MRAM resistive memory elements, such as pulse code modulation (PCM), flash memory, ferroelectric random access memory (FeRAM), resistive random access memory (RRAM), etc. The transistor can alternatively be implemented with a p-type field effect transistor. With PFETs, all polarities are reversed for inference and writing.

[0041] Figure 4 is a block diagram of an electronic device 401 in a network environment 400 according to one embodiment. Refer to Figure 4, an electronic device 401 in a network environment 400 may communicate with an electronic device 402 via a first network 498 (e.g., a short-range wireless communication network), or may communicate with an electronic device 404 or a server 408 via a second network 499 (e.g., a long-range wireless communication network). The electronic device 401 may communicate with the electronic device 404 via the server 408. The electronic device 401 may include a processor 420, a memory 430, an input device 450, a sound output device 455, a display device 460, an audio module 470, a sensor module 476, an interface 477, a haptic module 479, a camera module 480, a power management module 488, a battery 489, a communication module 490, a subscriber identification module (SIM) 496, or an antenna module 497. At least one of the components may be omitted from the electronic device 401 (e.g., the display device 460 or the camera module 480), or one or more other components may be added to the electronic device 401. Some components may be implemented as a single integrated circuit (IC). For example, the sensor module 476 (e.g., a fingerprint sensor, an iris sensor, or an illuminance sensor) may be embedded in the display device 460 (e.g., a display).

[0042] The processor 420 may run software (e.g., a program 440), for example, to control at least one other component (e.g., a hardware or software component) of the electronic device 401 coupled to the processor 420, and may perform various data processing or computations. As at least part of the data processing or computation, the processor 420 may load commands or data received from another component (e.g., the sensor module 476 or the communication module 490) into the volatile memory 432, process the commands or data stored in the volatile memory 432, and store the resulting data in the non-volatile memory 434. The processor 420 may include a main processor 421 (e.g., a central processing unit (CPU) or an application processor (AP)), and an auxiliary processor 423 (e.g., a graphics processing unit (GPU), an image signal processor (ISP), a sensor hub processor, or a communication processor (CP) that may operate independently of or together with the main processor 421). Additionally or alternatively, the auxiliary processor 423 may be adapted to consume less power than the main processor 421, or to run a specific function. The auxiliary processor 423 may be implemented as separate from or as part of the main processor 421.

[0043] When the main processor 421 is in an inactive (e.g., sleep) state, the auxiliary processor 423 may replace the main processor 421 or, when the main processor is in an active state (e.g., running an application), the auxiliary processor 423 may, together with the main processor 421, control at least some of the functions or states related to at least one of the components of the electronic device 401 (e.g., the display device 460, the sensor module 476, or the communication module 490). The auxiliary processor 423 (e.g., an image signal processor or a communication processor) may be implemented as part of another component (e.g., the camera module 480 or the communication module 490) that is functionally related to the auxiliary processor 423.

[0044] The memory 430 may store various data used by at least one component of the electronic device 401 (e.g., the processor 420 or the sensor module 476). The various data may include, for example, software (e.g., the program 440) and input data or output data related to commands thereof. The memory 430 may include a volatile memory 432 or a non-volatile memory 434.

[0045] The program 440 may be stored in the memory 430 as software and may include, for example, an operating system (OS) 442, middleware 444, or an application 446.

[0046] The input device 450 may receive commands or data from the outside of the electronic device 401 (e.g., a user) to be used by other components of the electronic device 401 (e.g., the processor 420). The input device 450 may include, for example, a microphone, a mouse, or a keyboard.

[0047] The sound output device 455 may output a sound signal to the outside of the electronic device 401. The sound output device 455 may include, for example, a speaker or a receiver. The speaker may be used for general purposes, such as playing multimedia or recording, and the receiver may be used for receiving an incoming call. The receiver may be implemented separately from the speaker or as part of the speaker.

[0048] The display device 460 may visually provide information to the outside of the electronic device 401 (e.g., a user). The display device 460 may include, for example, a display, a holographic device, or a projector, and a control circuit for controlling the corresponding one of the display, the holographic device, and the projector. The display device 460 may include a touch circuit suitable for detecting a touch, or a sensor circuit (e.g., a pressure sensor) suitable for measuring the intensity of a force caused by the touch.

[0049] The audio module 470 may convert sound into an electrical signal and vice versa. The audio module 470 may obtain sound via the input device 450, or output sound via the sound output device 455 or headphones of an external electronic device 402 directly (e.g., wired) or wirelessly coupled to the electronic device 401.

[0050] The sensor module 476 may detect an operating state of the electronic device 401 (e.g., power or temperature) or an environmental state external to the electronic device 401 (e.g., a state of a user), and then generate an electrical signal or a data value corresponding to the detected state. The sensor module 476 may include, for example, a posture sensor, a gyro sensor, an atmospheric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0051] The interface 477 may support one or more specified protocols to be used for the electronic device 401 to be directly (e.g., wired) or wirelessly coupled to an external electronic device 402. The interface 477 may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, a secure digital (SD) card interface, or an audio interface.

[0052] The connection terminal 478 may include a connector via which the electronic device 401 may be physically connected to an external electronic device 402. The connection terminal 478 may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0053] The haptic module 479 may convert an electrical signal into a mechanical stimulus (e.g., vibration or movement) or an electrical stimulus that may be recognized by a user via tactile sensation or kinesthetic sensation. The haptic module 479 may include, for example, a motor, a piezoelectric element, or an electrical stimulator.

[0054] The camera module 480 may capture a still image or a moving image. The camera module 480 may include one or more lenses, an image sensor, an image signal processor, or a flash.

[0055] The power management module 488 may manage power provided to the electronic device 401. The power management module 488 may be implemented as at least a part of, for example, a power management integrated circuit (PMIC).

[0056] The battery 489 may supply power to at least one component of the electronic device 401. The battery 489 may include, for example, a non-rechargeable primary cell, a rechargeable storage battery, or a fuel cell.

[0057] The communication module 490 may support establishing a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device 401 and an external electronic device (e.g., the electronic device 402, the electronic device 404, or the server 408), and perform communication via the established communication channel. The communication module 490 may include one or more communication processors, which may operate independently of the processor 420 (e.g., the AP) and support direct (e.g., wired) communication or wireless communication. The communication module 490 may include a wireless communication module 492 (e.g., a cellular communication module, a short-range wireless communication module, or a Global Navigation Satellite System (GNSS) communication module) or a wired communication module 494 (e.g., a Local Area Network (LAN) communication module or a Power Line Communication (PLC) module). The corresponding communication module among these communication modules may communicate with the external electronic device via a first network 498 (e.g., a short-range communication network such as Bluetooth TM , Wi-Fi direct communication, or Infrared Data Association (IrDA)) or a second network 499 (e.g., a telecommunication network, such as a cellular network, the Internet, or a computer network (e.g., a LAN or a Wide Area Network (WAN))). These variants of the communication module may be implemented as a single component (e.g., a single IC), or may be implemented as multiple components separated from each other (e.g., multiple ICs). The wireless communication module 492 may identify and authenticate the electronic device 401 in the communication network using the subscriber information (e.g., the International Mobile Subscriber Identity (IMSI)) stored in the subscriber identification module 496, such as the first network 498 or the second network 499.

[0058] The antenna module 497 may transmit a signal or power to the outside of the electronic device 401 (e.g., an external electronic device) or receive a signal or power from the outside of the electronic device 401 (e.g., an external electronic device). The antenna module 497 may include one or more antennas, and from there, for example, at least one antenna suitable for a communication scheme used in a communication network (such as the first network 498 or the second network 499) may be selected by the communication module 490 (e.g., the wireless communication module 492). Then, a signal or power may be transmitted or received between the communication module 490 and the external electronic device via the selected at least one antenna.

[0059] At least some of the above components may be coupled to each other and transmit signals (e.g., commands or data) therebetween via a peripheral communication scheme (e.g., a bus, a General-Purpose Input and Output (GPIO), a Serial Peripheral Interface (SPI), or a Mobile Industry Processor Interface (MIPI)).

[0060] According to one embodiment, commands or data can be sent or received between the electronic device 401 and an external electronic device 404 via a server 408 coupled to a second network 499. Each of the electronic devices 402 and 404 can be a device of the same type or a different type from the electronic device 401. All or some of the operations to be run at the electronic device 401 can be run at one or more of the external electronic devices 402, 404, or 408. For example, if the electronic device 401 is to automatically perform a function or service, or in response to a request from a user or another device, then instead of or in addition to running the function or service, the electronic device 401 can request that one or more external electronic devices perform at least a part of the function or service. One or more of the external electronic devices that receive the request can perform at least a part of the requested function or service, or additional functions or additional services related to the request, and transmit the result of the performance to the electronic device 401. The electronic device 401 can provide the result as at least a part of the reply to the request, whether or not further processing is performed on the result. For this purpose, for example, cloud computing, distributed computing, or client-server computing techniques can be used.

[0061] One embodiment can be implemented as software (e.g., program 440) including one or more instructions stored in a storage medium (e.g., internal memory 436 or external memory 438) readable by a machine (e.g., electronic device 401). For example, a processor of the electronic device 401 can call at least one of the one or more instructions stored in the storage medium, with or without using one or more other components, under the control of the processor, and run the instruction. Thus, the machine can be operated according to the at least one instruction called to perform at least one function. The one or more instructions can include code generated by a compiler or code executable by an interpreter. The machine-readable storage medium can be provided in the form of a non-transitory storage medium. The term "non-transitory" means that the storage medium is a tangible device and does not include signals (e.g., electromagnetic waves), but the term does not distinguish between a location where data is semi-permanently stored in the storage medium and a location where data is temporarily stored in the storage medium.

[0062] According to one embodiment, the method of the present disclosure can be included and provided in a computer program product. The computer program product can be traded between a seller and a buyer as a product. The computer program product can be distributed in the form of a machine-readable storage medium (e.g., compact disc read-only memory (CD-ROM)), or via an app store (e.g., PlayStore TM)Online distribution (e.g., downloading or uploading), or direct distribution between two user devices (e.g., smartphones). If distributed online, at least a portion of the computer program product may be temporarily generated or at least temporarily stored in a machine-readable storage medium, such as the memory of a manufacturer server, the server of an app store, or a relay server.

[0063] According to one embodiment, each of the above components (e.g., modules or programs) may include a single entity or multiple entities. One or more of the above components may be omitted, or one or more of other components may be added. Alternatively or additionally, multiple components (e.g., modules or programs) may be integrated into a single component. In such a case, the integrated component may still perform one or more functions of each of the multiple components in the same or similar manner as the corresponding components among the multiple components performed before integration. The operations performed by a module, program, or another component may be executed sequentially, in parallel, repeatedly, or heuristically, or one or more operations may be run in a different order or omitted, or one or more other operations may be added.

[0064] Although certain embodiments of the present disclosure have been described in the detailed description of the present disclosure, the present disclosure may be modified in various forms without departing from the scope of the present disclosure. Therefore, the scope of the present disclosure should not be determined based only on the described embodiments, but should be determined based on the appended claims and their equivalents.

Claims

1. A weight unit, comprising: a first field-effect transistor (FET) and a first resistive memory element connected to the drain of the first FET; a second FET and a second resistive memory element connected to the drain of the second FET, the drain of the first FET being connected to the gate of the second FET, and the drain of the second FET being connected to the gate of the first FET, a third FET; and a load resistor connected to the drain of the third FET; wherein, an input to the source of the first FET includes a first programming voltage, and an input to the source of the second FET includes a second programming voltage opposite to the first programming voltage, such that a current output from the source of the third FET indicates the logic weight of the weight unit.

2. The weight unit according to claim 1, wherein, the first FET, the second FET, and the third FET comprise n-type FETs.

3. The weight unit according to claim 1, wherein, the first FET, the second FET, and the third FET comprise p-type FETs.

4. The weight unit according to claim 1, wherein, the first resistive memory element and the second resistive memory element comprise magnetic tunnel junctions (MTJs).

5. The weight unit according to claim 1, wherein, the first resistive memory element and the second resistive memory element comprise resistive random access memory (RRAM) elements.

6. The weight unit according to claim 1, wherein, the first resistive memory element and the second resistive memory element comprise ferroelectric random access memory (FeRAM) elements.

7. The weight unit according to claim 1, wherein, the first resistive memory element and the second resistive memory element comprise pulse code modulation (PCM) memory elements.

8. The weight unit according to claim 1, wherein, the gate of the third FET is connected to the gate of the first FET.

9. The weight unit according to claim 1, further comprising a first external connection to a lead of the first resistive memory element and a second external connection to a lead of the second resistive memory element.

10. The weight unit according to claim 9, wherein, the first external connection provides a first input voltage to the first resistive memory element, and the second external connection provides a second input voltage opposite to the first input voltage to the second resistive memory element.

11. The weight unit according to claim 9, further comprising a third external connection to the source of the third FET, the third external connection being configured to provide the current output from the source of the third FET.

12. The weight unit according to claim 1, wherein, the weight unit generates a logic value based on the conductance of the first resistive memory element and the conductance of the second resistive memory element.

13. An electronic device, comprising: an array of weight units, each weight unit comprising: A first field effect transistor (FET) and a first resistive memory element connected to the drain of the first FET; A second FET and a second resistive memory element connected to the drain of the second FET, wherein the drain of the first FET is connected to the gate of the second FET, and the drain of the second FET is connected to the gate of the first FET, A third FET; and A load resistor connected to the drain of the third FET; and A processor configured to perform inference on the weight cell array by: Setting inputs for row weight cells from the weight cell array according to the logic values of corresponding neurons; and Reading the outputs of column weight cells from the weight cell array.

14. The apparatus according to claim 13, wherein, The processor is further configured to perform inference by measuring the total current from the read output and dividing the total current by the output current.

15. The apparatus according to claim 13, wherein, The first resistive memory element and the second resistive memory element include magnetic tunnel junctions (MTJs).

16. The apparatus according to claim 13, wherein, The first FET, the second FET, and the third FET include n-type FETs.

17. An electronic device, comprising: A weight cell array, each weight cell including: A first field effect transistor (FET) and a first resistive memory element connected to the drain of the first FET; A second FET and a second resistive memory element connected to the drain of the second FET, wherein the drain of the first FET is connected to the gate of the second FET, and the drain of the second FET is connected to the gate of the first FET, A third FET; and A load resistor connected to the drain of the third FET; wherein the input of the source of the first FET includes a first programming voltage, and the input of the source of the second FET includes a second programming voltage opposite to the first programming voltage, such that the current output from the source of the third FET indicates the logical weight of the weight cell; and A processor configured to write to the first resistive memory element and the second resistive memory element according to the direction of the current supplied to the first resistive memory element and the second resistive memory element.

18. The apparatus according to claim 17, wherein, The processor is configured to perform row-by-row writing to the first resistive memory element and the second resistive memory element of the weight cell array when the direction of the current is downward.

19. The apparatus according to claim 17, wherein, The processor is configured to perform column-by-column writing to the first resistive memory element and the second resistive memory element of the array when the direction of the current is upward.

20. The apparatus according to claim 17, wherein, The first resistive memory element and the second resistive memory element include magnetic tunnel junctions (MTJs).

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