A low voltage ESD protection device and manufacturing method thereof

Abstract

The invention discloses a low-voltage ESD protection device and a manufacturing method thereof. The device comprises an N-type single crystal material layer, N+ polycrystalline silicon, an N-type base region, and a P-type base region. A first isolation medium layer, a first metal layer, a second isolation medium layer, and a second metal layer are sequentially arranged on the N-type single crystal material layer. The N+ polycrystalline silicon, the N-type base region, and the P-type base region are all arranged on the top of the N-type single crystal material layer. A P+ source region and an N+ source region are arranged in the N+ polycrystalline silicon. A thermal oxidation layer is arranged between the outside of the N+ polycrystalline silicon and the N-type single crystal material layer. A P+ source region is arranged in the N-type base region. A P+ source region, an N+ source region, an N+ source region, and a P+ source region are sequentially arranged in the P-type base region. The invention effectively improves the utilization rate of a chip and reduces the chip cost; does not increase the cell size, reduces the chip area occupied by maintaining the metal spacing, can reduce the cell size by about 20%, and improves the current discharge capacity by at least 50%.

Description

Technical Field

[0001] The present invention relates to the field of electronic science and technology, and in particular to a low-voltage ESD protection device and a manufacturing method thereof. Background Art

[0002] Nowadays, the era of artificial intelligence combined with the Internet of Things has officially arrived, and smart homes are playing an increasingly important role in life. With the continuous development of technology, the chips required for the Internet of Things are further developed towards high integration and lower power consumption, which requires the line width of its manufacturing process to be further reduced. The narrow line width and low power consumption also make the chip more fragile and sensitive when it is subjected to electrostatic discharge effects, resulting in increasingly stringent electrostatic discharge tests. As power consumption is further reduced, its power supply voltage is also further reduced, and there are further requirements for ESD devices with low trigger voltage and strong discharge capacity.

[0003] According to the characteristics of low operating voltage of low-power systems. There are requirements for low-voltage ESD protection devices with voltage levels of 1V, 1.8V, 2V, 2.5V, 2.8V, 3.3V, etc. However, most of the ESD protection devices for low-voltage systems currently have a breakdown voltage between 5V and 10V, and have not achieved true low-voltage ESD protection. Devices commonly used for ESD protection include diodes, GGNMOS (gate-grounded NMOS), BJT (transistor), SCR (silicon controlled rectifier), etc. Low-voltage ESD protection devices often use SCR to obtain strong discharge capabilities. However, due to the increasing requirements for the size of ESD devices, it is becoming increasingly important to improve their ESD discharge capabilities at a certain size. Summary of the invention

[0004] The purpose of the present invention is to provide a low-voltage ESD protection device and a method for manufacturing the same, and to obtain an ESD protection device with a truly low trigger voltage and high ESD discharge current for specific low-voltage applications of 1V~3.3V, so as to solve the problems of high ESD trigger voltage and low 8 / 20 current density used in low-voltage systems at this stage.

[0005] The technical solution adopted by the present invention is:

[0006] A low-voltage ESD protection device, characterized in that it includes an N-type single crystal material layer, N+ polycrystalline silicon, an N-type base region, and a P-type base region, wherein a first layer of isolation dielectric, a first metal layer, a second layer of isolation dielectric, and a second metal layer are arranged on the N-type single crystal material layer, the N+ polycrystalline silicon, the N-type base region, and the P-type base region are all arranged on the top of the N-type single crystal material layer, the N+ polycrystalline silicon is provided with a P+ source region and an N+ source region, a thermal oxidation layer is provided between the outside and the N-type single crystal material layer, the N-type base region is provided with a P+ source region, and the P-type base region is provided with a P+ source region, an N+ source region, an N+ source region, and a P+ source region in sequence.

[0007] The method for manufacturing a low-voltage ESD protection device is characterized by comprising the following steps:

[0008] Step 1: Prepare N-type high-resistance single crystal material, and perform surface cleaning and flattening treatment;

[0009] Step 2: Deposit a mask layer on the surface of the silicon wafer, photolithography and etch grooves to form deep grooves, remove the etching mask layer, the depth of the grooves is 1~5μm, preferably 3μm, too deep a groove depth will cause excessive stress on the original wafer and increase the cost, after the groove etching is completed, wet oxygen grows a 3000~8000Å thermal oxide layer, the thickness is preferably 5000Å, and the thermal oxidation temperature is between 950~1150℃;

[0010] Step 3: Then deposit 3~5μm of in-situ doped N+ polysilicon, preferably 3μm thick. Then perform CMP planarization until the unetched area exposes the N-type material;

[0011] Step 4: After CMP is completed, pre-oxidation growth is performed, and N-type impurities and P-type impurities are implanted by photolithography ions and N-type base regions and P-type base regions are formed by high-temperature push-in.

[0012] Step 5: In the N+ polysilicon, N-type base region and P-type base region, high-concentration P-type impurities are photolithographically implanted to form a P+ source region, and then high-concentration N-type impurities are photolithographically implanted to form an N+ source region;

[0013] Step 6: Then, the first layer of isolation dielectric is deposited, and after dense reflow, the first layer contact hole area is photoetched, the first metal layer is deposited, and the first metal layer is completed, and finally, the photolithography, etching, and alloying of the first metal layer are completed;

[0014] Step 7: Then deposit the second layer of isolation dielectric, after dense reflow, photolithography and etch the second layer contact hole area, deposit the second metal layer, and complete the second metal layer. Finally, complete the photolithography, etching, and alloying of the second metal layer to form the lead area.

[0015] The P+ source region and the N+ source region form a diode string.

[0016] In the step 5, high concentration ion implantation is used in the P+ source region and the N+ source region, and the energy thereof is 30kev~90kev, and a relatively low implantation energy is combined with a rapid thermal annealing process.

[0017] After the first layer of etching lead holes is completed in step 6, a layer of TI / TIN is deposited and then the first metal layer AlSiCu alloy is grown.

[0018] After the second layer of etching lead holes is completed in step 7, the deposited second metal layer is thicker than the first metal layer.

[0019] The advantages of the present invention are as follows: a polysilicon forward-biased diode string triggered by a small current is placed below the lead area, which effectively improves chip utilization and reduces chip cost; the N+ polysilicon is located behind the thermal oxide layer grown after deep pit etching, forming effective electrical isolation, and CMP flattening treatment is performed after the N+ polysilicon 103 is deposited. The structure formed in the polysilicon is compatible with subsequent conventional processes, and the trigger area current is introduced into the P-type base area 105 from the first layer. The trigger current routing direction is perpendicular to the metal running direction of the SCR. The area of ​​the trigger area current access point is obtained by adjusting the graphics of other injection areas, and the cell size will not be increased, reducing the chip area occupied by maintaining the metal spacing. The low-voltage ESD protection device manufactured by the present invention can reduce the cell size by about 20% and improve the current discharge capacity by at least 50%; the forward-biased diode string can reduce the SCR's flyback current to 1.5V, and by adjusting the number of forward-biased diodes, an ultra-low trigger voltage ESD protection device of voltage levels such as 1.2V, 1.8V, 2V, 2.5V, 2.8V, and 3.3V can be realized; by optimizing the device size and ultra-low residual voltage, it is suitable for the protection of ultra-high-speed signals in low-voltage systems. At the same time, bidirectional ESD protection can be achieved through layout optimization, providing a solution for the bidirectional protection of ultra-high-speed signals in low-voltage systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0021] Figure 1 A schematic diagram of the layout of the low-voltage ESD protection device of the present invention;

[0022] Figure 2 is an equivalent circuit diagram of the low voltage ESD protection device of the present invention;

[0023] Figure 3 The first metal layer and the second contact hole layout pattern of the low voltage ESD protection device of the present invention;

[0024] Figure 4 It is the second metal layer layout of the low voltage ESD protection device of the present invention;

[0025] Figure 5 It is a schematic diagram of the positions of the A-A' section and the BB' section of the low-voltage ESD protection device of the present invention;

[0026] Figure 6 is a longitudinal structural schematic diagram of the A-A' section of the low-voltage ESD protection device of the present invention;

[0027] Figure 7 It is a longitudinal structural schematic diagram of the BB' section of the low-voltage ESD protection device of the present invention;

[0028] Figure 8 It is a schematic diagram of process step 1 of the BB' section of the present invention;

[0029] Fig. 9 It is a schematic diagram of process step 2 of the BB' section of the present invention;

[0030] Fig.10 It is a schematic diagram of process step 3 of the BB' section of the present invention;

[0031] Fig.11 It is a schematic diagram of process step 4 of the BB' section of the present invention;

[0032] Fig.12 It is a schematic diagram of process step 5 of the BB' section of the present invention;

[0033] Fig.13 It is a schematic diagram of process step 6 of the BB' section of the present invention;

[0034] Fig.14 It is a schematic diagram of process step 7 of the BB' section of the present invention;

[0035] Fig.15 This is a cross-sectional view of an improved BB' structure of the present invention.

[0036] Among them: 101, N-type single crystal material layer; 102, thermal oxide layer; 103, N+ polysilicon; 104, N-type base region; 105, P-type base region; 106, P+ source region; 107, N+ source region; 108, first isolation dielectric layer; 109, first metal layer; 110, second isolation dielectric layer; 111, second metal layer. DETAILED DESCRIPTION

[0037] like Figure 1-15 As shown, a low-voltage ESD protection device includes an N-type single crystal material layer 101, an N+ polycrystalline silicon 103, an N-type base region 104, and a P-type base region 105. A first layer of isolation dielectric 108, a first metal layer 109, a second layer of isolation dielectric 110, and a second metal layer 111 are arranged on the N-type single crystal material layer 101. The N+ polycrystalline silicon 103, the N-type base region 104, and the P-type base region 104 are all arranged on the top of the N-type single crystal material layer 101. A P+ source region 106 and an N+ source region 107 are arranged in the N+ polycrystalline silicon 103. A thermal oxide layer 102 is arranged between the outside and the N-type single crystal material layer 101. A P+ source region 106 is arranged in the N-type base region 104. A P+ source region 106, an N+ source region 107, an N+ source region 107, and a P+ source region 106 are arranged in the P-type base region 105 in sequence.

[0038] A method for manufacturing a low voltage ESD protection device comprises the following steps:

[0039] Step 1: Prepare N-type high-resistance single crystal material 101, first select a phosphorus-doped N-type single crystal with a resistivity of 1000~10000Ω·cm, preferably 2000Ω·cm, and a crystal orientation of <100> , perform surface cleaning and flattening treatment to ensure that the material surface has high flatness;

[0040] Step 2: Deposit a mask layer on the surface of the silicon wafer, photoetch a groove to form a deep groove, and remove the etching mask layer. The depth of the groove is 1~5μm, preferably 3μm. Too deep a groove will cause excessive stress on the original wafer and increase the cost. After the groove etching is completed, wet oxygen grows a 3000~8000Å thermal oxide layer, preferably 5000Å thick, and the thermal oxidation temperature is between 950~1150℃;

[0041] Step 3: Then, 3-5 μm of in-situ doped N+ polysilicon 103 is deposited, with a thickness of preferably 3 μm, and then CMP planarization is performed until the unetched area exposes the N-type material 101;

[0042] Step 4: After CMP is completed, pre-oxidation growth is performed, and N-type impurities and P-type impurities are implanted by photolithography ion implantation. P-type boron impurities are implanted with an implantation dose of 1E13~1E14cm -2 , preferably 5E13cm -2 The high temperature push junction is formed to form a junction depth of 3~5μm, followed by the implantation of N-type phosphorus impurities with an implantation dose of 1E14~1E15cm -2 , preferably 5E14cm -2 and forming an N-type base region 104 and a P-type base region 105 by high temperature push junction, the junction depth is preferably 2 μm;

[0043] Step 5: In the N+ polysilicon 103, N-type base region 104 and P-type base region 105, high-concentration P-type impurities are photolithographically implanted to form a P+ source region 106, and then high-concentration N-type impurities are photolithographically implanted to form an N+ source region 107. The junction depth dose of the P+ source region 106 and the N+ source region 107 is 2E15~1E16cm -2 , the preferred dose is 5E15cm -2 , the junction depth is about 0.5μm;

[0044] Step 6: Then, a first isolation dielectric layer 108 is deposited, and a 3000Å ​​dielectric layer is deposited using a low-pressure tetraethoxysilane growth process (LPTEOS), and then a 6000Å phosphosilicate glass PSG isolation dielectric is deposited. After dense reflow, the first contact hole area is photoetched. After the first layer of lead hole etching is completed, a layer of TI / TIN is deposited and then the first metal layer AlSiCu alloy is grown, which can effectively reduce the failure rate of metal overheating while reducing the contact resistance, and complete the first metal layer 109. Finally, the photolithography, etching, and alloying of the first metal layer are completed;

[0045] Step 7: Then, a second layer of isolation dielectric 110 is deposited. The second layer is a combination of tetraethoxysilane (TEOS), phosphosilicate glass PSG, and borophosphosilicate glass BPSG, with a thickness of 1.5~2.5μm, preferably 2μm. After dense reflow, the second layer contact hole area is photoetched, a second metal layer is deposited, and the second metal layer 111 is completed. The thickness is preferably 2~5μm, preferably 3μm. Finally, the second metal layer is photolithographically etched, and alloyed to form a lead area.

[0046] In the present invention, N-type doping ions may also be particles of phosphorus, arsenic, antimony, etc.

[0047] The P+ source region 106 and the N+ source region 107 form a diode string. When the pulse voltage exceeds 1.5V, the polysilicon diode string is turned on, and the current flows into the trigger area of ​​the SCR through the first metal layer, thereby triggering the SCR to turn on. Since the trigger current can be adjusted by adjusting the resistance R1 of the P-type base region 105 and the resistance R2 of the N-type base region 104, it is usually controlled within 50mA, so the first metal layer is usually relatively thin and can also meet this part of the current demand; the layout of the P+ source region 106 and the N+ source region 107 in the polysilicon can be adjusted, and increasing the spacing can introduce a series polysilicon resistor, which is beneficial to current limiting the small current path and avoiding overcurrent failure of the small current path due to excessive current.

[0048] The N-type base region 104, P-type base region 105, P+ source region 106, and N+ source region 107 of the SCR cell region form a PNPN type thyristor with integrated R1 and R2 base region resistors, wherein the resistance of the base region sandwich resistors R1 and R2 determines the turn-on current of the SCR, and its trigger current is provided by the forward biased diode string.

[0049] The first insulating dielectric layer 108 is located between the N-type single crystal material 101 and the first metal layer 109 ; the second insulating dielectric layer 110 is located between the first metal layer 109 and the second metal layer 111 ; the N-type single crystal material layer 101 may also be made of P-type single crystal material.

[0050] In the present invention, the N+ polysilicon is located behind the thermal oxide layer grown after the deep pit etching, forming an effective electrical isolation, and the CMP planarization process is performed after the N+ polysilicon 103 is deposited. The structure formation in the polysilicon is compatible with the subsequent conventional process, and the trigger area current is introduced into the P-type base area 105 from the first layer, and the trigger current routing direction is perpendicular to the metal running direction of the SCR. The area of ​​the trigger area current access point is obtained by adjusting the graphics of other injection areas, and the cell size will not be increased, reducing the chip area occupied by maintaining the metal spacing.

[0051] In the above step 2, the trench etching and thermal oxidation need to minimize the wafer stress as much as possible to avoid warping caused by excessive wafer stress, thereby ensuring that the effective thickness consistency of polysilicon in the wafer is high after CMP planarization. The high-temperature annealing temperature is 950℃~1250℃, and the annealing time is one hour; the injection concentration and push-junction temperature of the N-type base region 104 and the P-type base region 105 can affect the base resistance R1 and R2 and the spacing between the high resistance regions. The specific temperature and injection dose need to be determined according to the actual process conditions. The resistances R1 and R2 directly affect the on-current of the SCR.

[0052] The P+ source region 106 and the N+ source region 107 in the above step 5 are implanted with high concentration ions with an energy of 30kev~90kev. By using lower implantation energy combined with a rapid thermal annealing process, a shallower junction depth can be achieved to reduce the cell size and increase the current density per unit area of ​​the chip.

[0053] After the first layer of etching lead holes is completed in the above step 6, a layer of TI / TIN is deposited and then the first metal layer AlSiCu alloy is grown, which can effectively reduce the failure rate of metal overheating while reducing the contact resistance.

[0054] After the second layer of etching lead holes is completed in step 7, the deposited second metal layer is thicker than the first metal layer, which increases the routing current capacity and prevents protection failure due to metal thickness.

[0055] The layout diagram of the present invention is as follows Figure 1 As shown, it is an overall superposition diagram of the first metal layer, the second contact hole, and the second metal layer. The first metal layer is Figure 3 The gray area in the figure shows the second metal layer. Figure 3The dark area in the figure shows that the large second metal layers on both sides are the lead areas of the chip-level package. It can be seen that the area between the lead areas is the SCR effective area. The discharge current needs to directly reach the second metal layer and be led out from the lead end. The thinner first metal layer cannot meet the strong ESD protection requirements. Based on the requirements of strong discharge current and chip-level packaging, the SCR area for the main discharge current cannot be manufactured under the second metal layer of the two lead areas. Therefore, the polysilicon forward-biased diode string, which acts as a small current trigger, is placed under the lead area, which effectively improves the chip utilization.

[0056] like Figure 2 As shown, the present invention is a low trigger voltage ESD protection device, and its ESD discharge current direction is: CH to GND. The channel includes a small current path L1 through forward-biased diodes D1, D2 and resistor R1, and a PNPN SCR large current discharge path L2. When the two current paths are independent, the turn-on voltage of the small current path is the forward bias voltage of the two diodes, 1.4V. The turn-on voltage of the large current path PNPN tube is mainly determined by the base PN junction, and its avalanche withstand voltage BV>6V. When the voltage pulse impacts the CH port, due to the low turn-on voltage of the small current path, the current I1 first passes through the path L1, and the current I1 is injected into the P base region of the NPN tube and flows through the base short-circuit resistor R1. When I1·R1>0.7V, the NPN in the SCR is turned on, and its current I2 is injected into the N-type base region of the PNP tube. When I2·R3>0.7V, the SCR is then turned on, thereby quickly discharging the pulse charge.

[0057] like Figure 5 As shown in FIG. 1 , the AA' direction includes the longitudinal structure of the current triggering region of the SCR.

[0058] like Figure 5 As shown in the B-B' position, its longitudinal structure includes the effective discharge area of ​​the SCR. Furthermore, since the effective SCR area does not have current injected into the contact area, it is beneficial to further reduce the width of the high resistance area of ​​the SCR, reduce the residual pressure of the device for large current discharge, reduce the power consumption of the device, and improve the current discharge capacity of the protection device. In addition, the SCR can be turned on on both sides, not on one side, and the current capacity is greatly improved.

[0059] like Fig.15 The structure of the present invention can also adopt the forward-biased diode string with PN junction isolation as shown in the figure, and this process is compatible with the process of the present invention.

[0060] By utilizing the manufacturing method of the low-voltage ESD protection device of the present invention, it is only necessary to adjust the number of forward-biased diodes in series in the diode area to adjust the retrace voltage of the SCR and apply it to ESD protection of low-voltage systems such as 1.2V, 1.8V, 2V, 2.5V, 2.8V, and 3.3V. The retrace current of the SCR can be adjusted by adjusting the base resistance of the N-base region and the P-type base region. At the same time, by adjusting the junction depth and the spacing between high-resistance regions, low-voltage ESD protection with ultra-low residual voltage can be achieved.

[0061] The lead areas on both sides of the low-voltage ESD protection device of the present invention are mainly for chip-level packaging, and are mainly used for high-speed signal transmission protection of low-voltage power supply systems, requiring the protection device to have characteristics such as low residual voltage and low trigger voltage. Compared with traditional packaging forms, the chip-level greatly reduces the cost and volume.

[0062] The polysilicon forward-biased diode string with small current triggering function of the present invention is placed under the lead area, which effectively improves the utilization rate of the chip and reduces the chip cost; the N+ polysilicon is located behind the thermal oxide layer grown after deep pit etching, forming an effective electrical isolation, and the N+ polysilicon 103 is subjected to CMP flattening treatment after deposition. The structure formation in the polysilicon is compatible with subsequent conventional processes. In addition, the trigger area current is introduced into the P-type base area 105 from the first layer, and the direction of the trigger current routing is perpendicular to the metal direction of the SCR. The area of ​​the trigger area current access point is obtained by adjusting the graphics of other injection areas, and the cell size will not be increased. The chip area occupancy caused by maintaining the metal spacing is reduced. The low-voltage ESD protection device manufactured by the present invention can reduce the cell size by about 20% and improve the current discharge capacity by at least 50%; the forward-biased diode string can reduce the SCR's flyback current to 1.5V, and by adjusting the number of forward-biased diodes, low-voltage ESD protection devices with voltage levels such as 1.2V, 1.8V, 2V, 2.5V, 2.8V, and 3.3V can be realized; by optimizing the device size and achieving ultra-low residual voltage, it is suitable for the protection of ultra-high-speed signals in low-voltage systems, and bidirectional ESD protection can be achieved through layout optimization, providing a solution for bidirectional protection of ultra-high-speed signals in low-voltage systems.

Claims

1. A method for manufacturing a low voltage ESD protection device, characterized in that: The device comprises an N-type single crystal material layer, N+ polycrystalline silicon, an N-type base region, and a P-type base region. A first isolation dielectric layer, a first metal layer, a second isolation dielectric layer, and a second metal layer are sequentially arranged on the N-type single crystal material layer. The N+ polycrystalline silicon, the N-type base region, and the P-type base region are all arranged on the top of the N-type single crystal material layer. A P+ source region and an N+ source region are arranged in the N+ polycrystalline silicon. A thermal oxidation layer is arranged between the outside of the N+ polycrystalline silicon and the N-type single crystal material layer. A P+ source region is arranged in the N-type base region. A P+ source region, an N+ source region, an N+ source region, and a P+ source region are sequentially arranged in the P-type base region. The manufacturing method comprises the following steps: Step 1: Prepare N-type high-resistance single crystal material, and perform surface cleaning and flattening treatment; Step 2: Deposit a mask layer on the surface of the silicon wafer, photoetch a groove to form a deep groove, remove the etching mask layer, the depth of the groove is 1~5μm, after the groove etching is completed, wet oxygen grows a 3000~8000Å thermal oxide layer, and the thermal oxidation temperature is between 950~1150℃; Step 3: Then deposit 3~5μm of in-situ doped N+ polysilicon, and then perform CMP planarization until the unetched area exposes the N-type high-resistance single crystal material; Step 4: After CMP is completed, pre-oxidation growth is performed, and N-type impurities and P-type impurities are implanted by photolithography ion implantation and N-type base regions and P-type base regions are formed by high-temperature push-in junction; Step 5: In the N+ polysilicon, N-type base region and P-type base region, high-concentration P-type impurities are photolithographically implanted to form a P+ source region, and then high-concentration N-type impurities are photolithographically implanted to form an N+ source region; Step 6: Then, the first layer of isolation dielectric is deposited, and after dense reflow, the first layer of contact hole area is photoetched, and after the first layer of lead hole etching is completed, the first metal layer is deposited, and finally the first metal layer is photoetched and alloyed; Step 7: Then, a second layer of isolation dielectric is deposited. After dense reflow, the second layer contact hole area is photoetched. After the second layer lead hole is etched, a second metal layer is deposited. Finally, the second metal layer is photoetched and alloyed to form a lead area.

2. The method for manufacturing a low voltage ESD protection device according to claim 1, characterized in that: The P+ source region and the N+ source region form a diode string.

3. The method for manufacturing a low voltage ESD protection device according to claim 1, characterized in that: In the step 5, high concentration ion implantation is used in the P+ source region and the N+ source region, and the energy thereof is 30kev~90kev, and a relatively low implantation energy is combined with a rapid thermal annealing process.

4. The method for manufacturing a low voltage ESD protection device according to claim 1, characterized in that: After the first layer of lead hole etching is completed in step 6, a layer of TI / TIN is deposited and then the first metal layer is grown.

5. The method for manufacturing a low voltage ESD protection device according to claim 1, characterized in that: After the second layer of etching lead holes is completed in step 7, the deposited second metal layer is thicker than the first metal layer.

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