Switching power supply control device

Abstract

The present invention provides a control device for a switching power supply capable of suppressing the overshoot of the output voltage when starting a current resonance type switching power supply with a high-speed response. The soft start control circuit of the control device initially sets the start opening width signal (Ton_ss) of the switch in a register just after starting, and starts the soft start control if the hysteresis comparator (COMP2) detects the rise of the feedback voltage. A subtraction counter (DOWNC1) counts the number of switches (on trigger signal (on_trg)) and generates an opening width signal (Ton) obtained by increasing the value of the register by a stepping signal (Ton_step) by an adding circuit every time the value of the increase switching number signal (Nsw_step) is reached. If the subtraction counter (DOWNC2) counts the number of switches and the number of switches reaches the value of the generated opening width signal, a soft start closing signal (to_ss) is output.

Description

Technical Field

[0001] The invention relates to a control device for a switching power supply. Background Art

[0002] Current resonance type switching power supplies are widely used in LCD TVs, AC-DC adapters, etc. because they are suitable for high efficiency and thinness. Such current resonance type switching power supplies have a soft start circuit that suppresses overshoot of the output voltage at startup. The soft start circuit usually performs switching control at a high switching frequency at the beginning, and then gradually reduces the switching frequency according to the output voltage, thereby suppressing overshoot caused by a rapid increase in the output voltage.

[0003] Although the switching frequency is controlled according to the output voltage, the output voltage rises from almost 0 volts (V) at startup. Therefore, at startup, the required switching frequency is not known in advance, making it difficult to generate a smooth rising waveform of the output voltage.

[0004] Therefore, as a soft start circuit, a circuit that uses a feedback voltage to control the output voltage is known (for example, refer to Patent Document 1). According to the soft start circuit described in Patent Document 1, during the soft start period, the duty cycle of the drive pulse signal for the switch is gradually increased according to the feedback voltage, and the switching frequency is gradually reduced. Through this gradually changing control, the overshoot of the output voltage generated at the start-up is suppressed.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: International Publication No. 2014 / 074923 Summary of the invention

[0008] Technical issues

[0009] The soft start control of Patent Document 1 has the problem that it cannot be applied to the high-speed response switching power supplies that have been developed in recent years. This is because in the high-speed response switching power supply, if the soft start is started at startup, the feedback voltage will rise immediately, so the feedback voltage cannot be used as a control signal for the soft start circuit.

[0010] The present invention has been made in view of the above-mentioned situation, and an object of the present invention is to provide a control device for a switching power supply including a soft start circuit capable of appropriately performing soft start.

[0011] Technical Solution

[0012] In order to solve the above-mentioned problems, the present invention provides a control device for a current resonance type switching power supply having a soft start control circuit for suppressing overshoot of an output voltage at startup. The soft start control circuit of the control device for the switching power supply increases the opening width of a driving signal for driving a switching element of the switching power supply in a predetermined step every time a predetermined number of switching times is reached.

[0013] In the present invention, in order to solve the above-mentioned problem, in one scheme, in a control device of a current resonance type switching power supply having a soft start control circuit for suppressing overshoot of the output voltage at startup, there is also an input voltage level determination circuit for determining the level according to the input voltage of the switching power supply input at startup, and the input voltage level determination circuit outputs a value corresponding to the level.

[0014] Technical Effects

[0015] According to the control device for a switching power supply having the above-described configuration, it is possible to provide a control device for a switching power supply including a soft start circuit capable of appropriately performing soft start. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 1 is a circuit diagram showing a configuration example of a switching power supply to which the control device according to the first embodiment is applied.

[0017] Figure 2 This is a block diagram showing a configuration example of a control device according to the first embodiment.

[0018] Figure 3 : is a circuit diagram showing a configuration example of a shutdown control circuit.

[0019] Figure 4 : is a circuit diagram showing a configuration example of a soft start control circuit.

[0020] Figure 5 : is a circuit diagram showing a configuration example of a switch on / off control circuit.

[0021] Figure 6 : is a flowchart showing the operation of the on-width setting circuit in the soft start control circuit.

[0022] Figure 7 is a timing chart showing changes in the opening width.

[0023] Figure 8 1 is a diagram showing waveforms of main parts of a switching power supply.

[0024] Fig. 9 : is a circuit diagram showing a configuration example of a switching power supply to which the control device according to the second embodiment is applied.

[0025] Fig.10It is a block diagram showing a configuration example of a control device according to the second embodiment.

[0026] Fig.11 It is a diagram showing examples of parameter values ​​of different levels corresponding to input voltage.

[0027] Fig.12 : is a circuit diagram showing a configuration example of a soft start control circuit.

[0028] Fig.13 : is a flowchart showing the operation of the soft start control circuit.

[0029] Explanation of symbols

[0030] 10p, 10n input terminal

[0031] 11p, 11n output terminals

[0032] 12.12a Control device

[0033] 21 Close the control circuit

[0034] 22. 22a Soft start control circuit

[0035] 23 Switch on / off control circuit

[0036] 24 High-side drive circuit

[0037] 25 Low-side drive circuit

[0038] 26 Input voltage level determination circuit

[0039] 31 Open width setting circuit

[0040] 32 Open width counter circuit

[0041] ADD1 Addition Circuit

[0042] AND1, AND2, AND3, AND4 AND gate circuits

[0043] C1 Input capacitor

[0044] C2, C5, C11, Ca, Cb, Cos, Ctd capacitors

[0045] C6 Resonance capacitor

[0046] C10 Output capacitor

[0047] COMP1 Comparator

[0048] COMP2, COMP4 hysteresis comparator

[0049] COMP3 Digital Comparator

[0050] D3, D4 diodes

[0051] DFF1, DFF2, DFF3 D flip-flops

[0052] DOWNC1, DOWNC2 subtraction counter

[0053] INV1, INV2, INV3, INV4, INV5, INV6 inverter circuit

[0054] Ios, Itd constant current source

[0055] MPX1, MPX2 Multiplexer Circuits

[0056] OR1, OR2 OR gate circuit

[0057] OS1, OS2 one-shot circuit

[0058] P1 Primary coil

[0059] PC1 Photocoupler

[0060] Qa, Qb Switching elements

[0061] R1, R2, R6, R7, R8, R9, R10 resistors

[0062] REG1 Register

[0063] RSFF1, RSFF2 RS flip-flop

[0064] S1, S2 secondary coil

[0065] SR1 Shunt Regulator

[0066] SW1, SW2 switches

[0067] T1 Transformer DETAILED DESCRIPTION

[0068] Hereinafter, the embodiment of the present invention will be described in detail with reference to the accompanying drawings, taking the case of an LLC current resonance type switching power supply applied to a high-speed response as an example. Here, as an LLC current resonance type switching power supply capable of high-speed response, there is a switching power supply that uses current mode control to control the power transmission from the primary side to the secondary side of the transformer in each switching cycle. It should be noted that, in the accompanying drawings, the components represented by the same symbol represent the same component. In addition, in the following description, the same symbol is sometimes used for the terminal name and the voltage, signal, etc. on the terminal. Moreover, each embodiment can implement multiple embodiments in a partially combined manner within the scope that does not cause contradictions.

[0069] <First Embodiment>

[0070] Figure 1 is a circuit diagram showing a configuration example of a switching power supply to which the control device of the first embodiment is applied. Figure 2 This is a block diagram showing a configuration example of a control device according to the first embodiment.

[0071] Figure 1 The switching power supply shown has input terminals 10p and 10n to which a DC input voltage Vi is input, and the input terminal 10p is connected to the positive terminal of the input capacitor C1, and the input terminal 10n is connected to the negative terminal of the input capacitor C1. The positive terminal and the negative terminal of the input capacitor C1 are connected to a half-bridge circuit formed by connecting a high-side switching element Qa and a low-side switching element Qb in series. In this embodiment, N-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) are used for the switching elements Qa and Qb.

[0072] The common connection point of the switching elements Qa and Qb is connected to one end of the primary coil P1 of the transformer T1, and the other end of the primary coil P1 is connected to the ground via the resonant capacitor C6. Here, the resonant circuit is formed by the excitation inductance of the primary coil P1 of the transformer T1, the leakage inductance (leakage inductance) between the primary coil P1 and the secondary coils S1 and S2, and the resonant capacitor C6. It should be noted that the drain terminal and the source terminal of the switching elements Qa and Qb are connected to capacitors Ca and Cb, respectively. These capacitors Ca and Cb are equivalent capacitors including external capacitors, output capacitance of MOSFET, parasitic capacitance on the positive side and negative side of the transformer T1, etc.

[0073] One end of the secondary coil S1 of the transformer T1 is connected to the anode terminal of the diode D3, and one end of the secondary coil S2 is connected to the anode terminal of the diode D4. The cathode terminals of the diodes D3 and D4 are connected to the positive terminal of the output capacitor C10 and the output terminal 11p. The negative terminal of the output capacitor C10 is connected to the common connection point of the secondary coils S1 and S2 and the output terminal 11n. The secondary coils S1, S2, the diodes D3, D4 and the output capacitor C10 constitute a circuit that rectifies and smoothes the AC voltage generated in the secondary coils S1 and S2 and converts it into a DC voltage, and constitutes an output circuit of the switching power supply. The output terminals 11p and 11n are connected to a load not shown.

[0074] The output terminal 11p is connected to the anode terminal of the light-emitting diode of the photocoupler PC1 via the resistor R8, and the cathode terminal of the light-emitting diode is connected to the cathode terminal of the parallel regulator SR1. Resistor R6 is connected in parallel to the anode terminal and the cathode terminal of the light-emitting diode at both ends. The anode terminal of the parallel regulator SR1 is connected to the output terminal 11n. The parallel regulator SR1 has a reference terminal, which is connected to the connection point of the resistors R9 and R10 connected in series between the positive terminal and the negative terminal of the output capacitor C10. The parallel regulator SR1 has a series circuit of a resistor R7 and a capacitor C11 connected between the reference terminal and the cathode terminal. The parallel regulator SR1 is a device that allows a current corresponding to the difference between the built-in reference voltage and the potential obtained by dividing the output voltage Vo (the voltage across the output capacitor C10) to flow through the light-emitting diode. The collector terminal of the phototransistor of the photocoupler PC1 is connected to the FB terminal of the control device 12 composed of an IC (Integrated Circuit), and the emitter terminal of the phototransistor of the photocoupler PC1 is connected to the ground. A capacitor C2 is connected in parallel between the collector terminal and the emitter terminal of the phototransistor of the photocoupler PC1. The photocoupler PC1 and the shunt regulator SR1 constitute a feedback circuit that feeds back the error between the output voltage Vo and the reference voltage to the control circuit 12.

[0075] The control device 12 has an HO terminal connected to the gate terminal of the high-side switching element Qa via a resistor R1, an LO terminal connected to the gate terminal of the low-side switching element Qb via a resistor R2, and a GND terminal connected to the ground. The control device 12 also has a VB terminal and a VS terminal connected to the power supply line and the reference potential line of the high-side drive circuit, respectively. A capacitor C5 is connected between the VB terminal and the VS terminal, and the VS terminal is connected to the common connection point of the switching elements Qa and Qb.

[0076] like Figure 2 As shown, the control device 12 includes a shutdown control circuit 21 , a soft start control circuit 22 , a switch on / off control circuit 23 , a high-side drive circuit 24 , and a low-side drive circuit 25 .

[0077] The FB terminal of the control device 12 is connected to the input terminals of the shutdown control circuit 21 and the soft start control circuit 22, and the feedback voltage Vfb is provided respectively. The shutdown control circuit 21 is connected in a manner of receiving the signal Td from the switch on / off control circuit 23 and providing the shutdown signal to to the switch on / off control circuit 23. The soft start control circuit 22 is connected in a manner of receiving the on trigger signal on_trg from the switch on / off control circuit 23 and providing the soft start shutdown signal to_ss to the switch on / off control circuit 23.

[0078] The switch on / off control circuit 23 is connected so as to supply a high-side drive signal hi_pre to the high-side drive circuit 24 , and is connected so as to supply a low-side drive signal lo_pre to the low-side drive circuit 25 .

[0079] The high-side drive circuit 24 is connected to the VB terminal and the VS terminal constituting the high-side power supply, and is also connected to the HO terminal outputting the high-side drive signal VHO. The low-side drive circuit 25 is connected to the LO terminal outputting the low-side drive signal VLO.

[0080] In the control device 12, the switch on / off control circuit 23 generates a high-side drive signal hi_Pre and a low-side drive signal lo_pre. The high-side drive signal hi_pre and the low-side drive signal lo_pre alternately turn on the high-side switch element Qa and the low-side switch element Qb. The switch on / off control circuit 23 receives the shutdown signal to from the shutdown control circuit 21 and the soft start shutdown signal to_ss from the soft start control circuit 22 to generate a signal Td indicating the time when the high-side drive signal hi_pre and the low-side drive signal lo_pre are turned off, and an on trigger signal on_trg indicating the rising moment of the high-side drive signal hi_pre and the low-side drive signal lo_pre.

[0081] The switch on / off control circuit 23 receives the soft start shutdown signal to_ss from the soft start control circuit 22 at startup and controls the pulses of the high-side drive signal hi_pre and the low-side drive signal lo_pre to be turned off. The switch on / off control circuit 23 also receives the shutdown signal to from the shutdown control circuit 21 during normal operation and controls the pulses of the high-side drive signal hi_pre and the low-side drive signal lo_pre to be turned off.

[0082] The soft start control circuit 22 is controlled in such a way that the generation time of the soft start shutdown signal to_ss that determines the width of the pulse of the high-side drive signal hi_pre and the low-side drive signal lo_pre is gradually delayed. Specifically, each time a predetermined number of switching times is reached, the soft start control circuit 22 delays the generation time of the soft start shutdown signal to_ss by a predetermined increase in the opening width and increases the opening width of the pulse. Thus, soft start can be achieved without relying on the response speed of the switching power supply. Therefore, the overshoot of the output voltage generated at startup can be suppressed. It should be noted that the soft start control circuit 22 can set the duty cycle (time ratio) at this time to be constant so that it does not change with the increase in the number of switching times each time. Thus, the possibility of resonance deviation (i.e., the phenomenon that the switching frequency deviates from its control range, resonance) of the switching power supply can be reduced.

[0083] Next, a specific configuration example of the shutdown control circuit 21 , the soft start control circuit 22 , and the switch on / off control circuit 23 will be described.

[0084] Figure 3 is a circuit diagram showing a configuration example of a shutdown control circuit, Figure 4 FIG. 1 is a diagram showing a configuration example of a soft start control circuit. Figure 5 : is a circuit diagram showing a configuration example of a switch on / off control circuit.

[0085] like Figure 3 As shown, the shutdown control circuit 21 has an FB terminal, a Td terminal and a to terminal. The FB terminal is connected to the inverting input terminal of the comparator COMP1. The non-inverting input terminal of the comparator COMP1 is connected to the connection point between one terminal of the constant current source Ios and one terminal of the capacitor Cos, and receives the charging voltage Vos of the capacitor Cos. The other terminal of the constant current source Ios receives the voltage VDD, and the other terminal of the capacitor Cos is connected to the ground. A switch SW1 is connected in parallel to the capacitor Cos, and the control terminal of the switch SW1 is connected to the Td terminal. In addition, the output terminal of the comparator COMP1 is connected to the to terminal.

[0086] The shutdown control circuit 21 is a circuit for determining the opening width of the high-side drive signal hi_pre and the low-side drive signal lo_pre, that is, the closing time. However, the shutdown signal to output to the to terminal is ignored in the switch on / off control circuit 23 during the soft start period, and becomes effective during the normal operation after the soft start ends.

[0087] Here, when a high (H) level signal Td indicating the moment (dead time) of closing the high-side drive signal hi_pre and the low-side drive signal lo_pre is received from the switch on / off control circuit 23, the switch SW1 is turned on (connected). At this time, the charge of the capacitor Cos is released. It should be noted that the moment when the signal Td becomes L level is determined by the circuit for determining the dead time described later.

[0088] When the signal Td becomes L level, the switch SW1 is closed (opened), the capacitor Cos starts to be charged, and its charging voltage Vos increases. When the charging voltage Vos increases and becomes higher than the feedback voltage Vfb, the comparator COMP1 outputs an H level shutdown signal to to the to terminal.

[0089] Thus, the shutdown control circuit 21 outputs the shutdown signal to of the H level at a time delayed by the time corresponding to the feedback voltage Vfb after receiving the signal Td of the L level. However, the time when the shutdown signal to becomes the H level becomes very late during the soft start period because the feedback voltage Vfb is very high, and becomes a short delay corresponding to the feedback voltage Vfb after the soft start period has passed.

[0090] like Figure 4 As shown, the soft start control circuit 22 has an FB terminal, an on_trg terminal, and a to_ss terminal, and includes a hysteresis comparator COMP2, an on-width setting circuit 31, and an on-width counter circuit 32.

[0091] The FB terminal is connected to the non-inverting input terminal of the hysteresis comparator COMP2 to receive the feedback voltage Vfb. Two reference voltages Vfb_ref1 and Vfb_ref2 (Vfb_ref1>Vfb_ref2) are applied to the inverting input terminal of the hysteresis comparator COMP2.

[0092] The on-width setting circuit 31 has a subtraction counter DOWNC1 for counting a predetermined number of switching times. The subtraction counter DOWNC1 receives a preset increase switching number signal Nsw_step and sets the increase switching number as an initial value, and subtracts the initial value each time the on trigger signal on_trg is received. The subtraction counter DOWNC1 outputs an L-level zero flag signal zero_flag during the subtraction process. If the initial value becomes 0, the H-level zero flag signal zero_flag is output, and the initial value is set again.

[0093] The output terminal of the subtraction counter DOWNC1 is connected to one input terminal of the AND circuit AND1, and the other input terminal of the AND circuit AND1 is connected to the output terminal of the digital comparator COMP3. The output terminal of the AND circuit AND1 is connected to the control terminal of the multiplexer circuit MPX1.

[0094] The maximum open width signal Ton_max is input to the non-inverting input terminal of the digital comparator COMP3, and the inverting input terminal of the digital comparator COMP3 is connected to one input terminal of the adding circuit ADD1, the first input terminal of the multiplexer circuit MPX1, and the output terminal of the register REG1. The step signal Ton_step is input to the other input terminal of the adding circuit ADD1, and the output terminal of the adding circuit ADD1 is connected to the second input terminal of the multiplexer circuit MPX1.

[0095] The start-on width signal Ton_ss is input to a first input terminal of the multiplexer circuit MPX2, and a second input terminal of the multiplexer circuit MPX2 is connected to an output terminal of the multiplexer circuit MPX1. The output terminal of the multiplexer circuit MPX2 is connected to an input terminal of the register REG1.

[0096] It should be noted that the multiplexer circuits MPX1 and MPX2 are circuits that select one of the signals input to the first input terminal represented by "0" and the second input terminal represented by "1". That is, when a signal of an L level is input to the control terminal, the signal input to the first input terminal is selected, and when a signal of an H level is input to the control terminal, the signal input to the second input terminal is selected and output.

[0097] The open width setting circuit 31 also has an OR gate circuit OR1, one input terminal of the OR gate circuit OR1 is connected to the output terminal of the hysteresis comparator COMP2, and receives the feedback state signal fb_state. The output terminal of the OR gate circuit OR1 is connected to the input terminal of the D flip-flop DFF1, and the output terminal of the D flip-flop DFF1 is connected to the other input terminal of the OR gate circuit OR1 and the control terminal of the multiplexer circuit MPX2.

[0098] Here, the OR gate circuit OR1 and the D flip-flop DFF1 constitute a self-holding circuit. That is, if the feedback state signal fb_state of the H level is input to one input terminal of the OR gate circuit OR1, and the clock signal is input to the D flip-flop DFF1, the D flip-flop DFF1 is set and outputs an H level signal. The H level signal is fed back to the other input terminal of the OR gate circuit OR1 so that the H level signal is always input to the D flip-flop DFF1. Therefore, even if the feedback state signal fb_state of the H level drops to the L level once, the multiplexer circuit MPX2 will not select the start opening width signal Ton_ss of the initial value.

[0099] If the feedback state signal fb_state of the L level is input to the OR gate circuit OR1 immediately after the switching power supply is started, the signal of the L level is input to the control input terminal of the multiplexer circuit MPX2, and thus the start opening width signal Ton_ss input to the first input terminal is selected. As a result, the start opening width signal Ton_ss is stored in the register REG1 as an initial value. The storage of the start opening width signal Ton_ss is performed only once when the switching power supply is started.

[0100] Thereafter, when the D flip-flop DFF1 is set upon receiving the H-level feedback state signal fb_state, the multiplexer circuit MPX2 to which the H-level signal is input to its control input terminal selects the output signal of the multiplexer circuit MPX1 .

[0101] During the soft start period, since the value stored in the register REG1 is sufficiently smaller than the value of the maximum opening width signal Ton_max, the digital comparator COMP3 outputs an H-level signal to enable the AND gate circuit AND1. It should be noted that if the value stored in the register REG1 exceeds the value of the maximum opening width signal Ton_max, the digital comparator COMP3 outputs an L-level signal to disable the AND gate circuit AND1. In this case, since the AND gate circuit AND1 outputs an L-level signal, the multiplexer circuit MPX2 fixedly selects the first input terminal.

[0102] When the zero flag signal zero_flag output by the subtraction counter DOWNC1 is at an L level, the AND gate circuit AND1 outputs an L level signal, so the multiplexer circuit MPX1 selects the value stored in the register REG1 and outputs it to the multiplexer circuit MPX2. The open width signal Ton stored in the register REG1 via the multiplexer circuit MPX2 is output to the open width counter circuit 32.

[0103] On the other hand, if the subtraction counter DOWNC1 ends the subtraction operation and outputs the zero flag signal zero_flag of the H level, the multiplexer circuit MPX1 selects the value obtained by the addition circuit ADD1 and outputs it to the multiplexer circuit MPX2. At this time, because the multiplexer circuit MPX2 selects the output signal of the multiplexer circuit MPX1, the signal output by the addition circuit ADD1 is input to the register REG1 for storage. It should be noted that the addition circuit ADD1 outputs the value obtained by adding the value stored in the register REG1 when the zero flag signal zero_flag is at the L level to the value of the step signal Ton_step. It should be noted that the "step" of the step signal Ton_step here refers to the increase in the opening width in the soft start.

[0104] When the next on trigger signal on_trg is input, the subtraction counter DOWNC1 starts subtraction from the initial value. Therefore, since the subtraction counter DOWNC1 is in the subtraction process, it outputs the zero flag signal zero_flag of the L level. Thus, since the multiplexer circuit MPX1 selects the first input terminal and the multiplexer circuit MPX2 selects the second input terminal, the register REG1 maintains the storage of the newly stored signal.

[0105] Next, the on-width signal Ton in the register REG1 set by the on-width setting circuit 31 is output to the on-width counter circuit 32. The on-width counter circuit 32 has a down counter DOWNC2, a D flip-flop DFF2, and an AND circuit AND2.

[0106] The subtraction counter DOWNC2 receives the on-width signal Ton and the on-trigger signal on_trg, and performs a subtraction operation on the value of the on-width signal Ton each time the on-trigger signal on_trg is received. The signal zero output by the subtraction counter DOWNC2 is at an L level during the subtraction operation of the on-width signal Ton, and becomes an H level if the value of the on-width signal Ton becomes 0.

[0107] The output terminal of the subtraction counter DOWNC2 is connected to the input terminal of the D flip-flop DFF2 and the positive logic input terminal of the AND circuit AND2. The output terminal of the D flip-flop DFF2 is connected to the negative logic input terminal of the AND circuit AND2, and the output terminal of the AND circuit AND2 is connected to the to_ss terminal.

[0108] The D flip-flop DFF2 and the AND gate circuit AND2 constitute a one-shot circuit. Since the output of the D flip-flop DFF2 is at an L level when the signal zero output by the subtraction counter DOWNC2 is at an L level, the AND gate circuit AND2 is effective. Therefore, the soft start shutdown signal to_ss becomes a pulse that rises when the value of the subtraction counter DOWNC2 is subtracted to 0 (zero=H), and then falls when the first clock signal is input to the D flip-flop DFF2. The soft start shutdown signal to_ss is output to the switch on / off control circuit 23.

[0109] like Figure 5 As shown, the switch on / off control circuit 23 has a Td terminal, a to terminal, a to_ss terminal, an on_trg terminal, a hi_pre terminal, and a lo_pre terminal. The switch on / off control circuit 23 has an OR gate circuit OR2, one input terminal of the OR gate circuit OR2 is connected to the to terminal, and the other input terminal of the OR gate circuit OR2 is connected to the to_ss terminal. The output terminal of the OR gate circuit OR2 is connected to the set input terminal of the reset priority RS flip-flop RSFF1.

[0110] The output terminal of the RS flip-flop RSFF1 is connected to the Td terminal, the input terminal of the inverter circuit INV3 , and the input terminal of the one-shot circuit OS2 . The output terminal of the inverter circuit INV3 is connected to the input terminal of the one-shot circuit OS1 .

[0111] The output terminal of the inverter circuit INV3 is also connected to the control terminal of the switch SW2. One terminal of the switch SW2 is connected to one terminal of the constant current source Itd, one terminal of the capacitor Ctd, and the input terminal of the inverter circuit INV1, and the inverter circuit INV1 receives the charging voltage Vtd of the capacitor Ctd. The other terminal of the constant current source Itd is connected to the line of the voltage VDD, and the other terminal of the capacitor Ctd and the other terminal of the switch SW2 are connected to the ground. The output terminal of the inverter circuit INV1 is connected to the input terminal of the inverter circuit INV2, and the output terminal of the inverter circuit INV2 is connected to the second reset input terminal of the RS flip-flop RSFF1.

[0112] Here, the constant current source Itd, the switch SW2, the capacitor Ctd, and the inverter circuits INV1 and INV2 constitute a circuit for determining the above-mentioned dead time.

[0113] The first reset input terminal of the RS flip-flop RSFF1 is connected to the output terminal of the hysteresis comparator COMP4. The inverting input terminal of the hysteresis comparator COMP4 receives the voltage VCC of the power supply of the control device 12, and the non-inverting input terminal of the hysteresis comparator COMP4 receives the threshold voltages Vthvcch and Vthvccl. The hysteresis comparator COMP4 constitutes an under voltage malfunction prevention (UVLO: Under Voltage Lock Out) circuit to prevent abnormal operation when the voltage VCC drops to a voltage lower than the voltage at which the internal circuit of the control device 12 can operate.

[0114] The output terminal of the one-shot circuit OS1 is connected to the set input terminal and the on_trg terminal of the RS flip-flop RSFF2. The one-shot circuit OS1 generates an on trigger signal on_trg that rises synchronously with the falling edge (trailing edge) of the signal Td. The output terminal of the one-shot circuit OS2 is connected to the reset input terminal of the RS flip-flop RSFF2. The output terminal of the RS flip-flop RSFF2 is connected to one input terminal of the AND gate circuits AND3 and AND4.

[0115] The output terminal of the one-shot circuit OS2 is also connected to the input terminal of the inverter circuit INV4, and the output terminal of the inverter circuit INV4 is connected to the clock input terminal of the D flip-flop DFF3. The one-shot circuit OS2 generates a shutdown trigger signal off_trg that rises synchronously with the rising edge (front edge) of the signal Td. The input terminal of the D flip-flop DFF3 is connected to the output terminal of the inverter circuit INV5, and the input terminal of the inverter circuit INV5 is connected to the output terminal of the D flip-flop DFF3. The output terminal of the D flip-flop DFF3 is also connected to the other input terminal of the AND gate circuit AND3 and the input terminal of the inverter circuit INV6, and outputs the drive selection signal dri_sel. The output terminal of the inverter circuit INV6 is connected to the other input terminal of the AND gate circuit AND4. The output terminal of the AND gate circuit AND3 is connected to the hi_pre terminal and outputs the high-side drive signal hi_pre. The output terminal of the AND gate circuit AND4 is connected to the lo_pre terminal and outputs the low-side drive signal lo-pre. The reset input terminal of the D flip-flop DFF3 is connected to the output terminal of the hysteresis comparator COMP4.

[0116] The switch on / off control circuit 23 receives the soft start off signal to_ss from the soft start control circuit 22 at startup and controls the pulses of the high-side drive signal hi_pre and the low-side drive signal lo_pre to be turned off. The switch on / off control circuit 23 also receives the off signal to from the off control circuit 21 during normal operation and controls the pulses of the high-side drive signal hi_Pre and the low-side drive signal lo_pre to be turned off. This means that among the soft start off signal to_ss and the off signal to input to the OR gate circuit OR2, the soft start off signal to_ss is output during startup, i.e., during the soft start period, and the off signal to is preferentially output during normal operation, i.e., during the non-soft start period. Because the feedback voltage Vfb drops during normal operation, i.e., during the non-soft start period, the input of the inverting input terminal of the comparator COMP1 drops.

[0117] If the shutdown signal to or the soft start shutdown signal to_ss is input to the OR gate circuit OR2, the output signal of the OR gate circuit OR2 becomes H level, and the RS flip-flop RSFF1 is set. As a result, the RS flip-flop RSFF1 outputs the H level signal Td. The signal Td is input to the one-shot circuit OS2, and the one-shot circuit OS2 outputs the shutdown trigger signal off_trg that rises synchronously with the rising edge of the signal Td, and resets the RS flip-flop RSFF2. As a result, since one input terminal of the AND gate circuits AND3 and AND4 is provided with an L level signal, the high side drive signal hi_pre and the low side drive signal lo_pre output by the AND gate circuits AND3 and AND4 become L level.

[0118] At this time, since the output of the inverter circuit INV3 becomes L level, the switch SW2 is closed (disconnected), the capacitor Ctd starts to be charged, and its charging voltage Vtd rises. If the charging voltage Vtd rises and becomes higher than the threshold voltage of the inverter circuit INV1 (after the dead time), the output of the inverter circuit INV1 becomes L level, and the output of the inverter circuit INV2 becomes H level. The H level signal resets the RS flip-flop RSFF1 and makes its output signal Td L level.

[0119] The L-level signal Td is logically inverted by the inverter circuit INV3 and input to the one-shot circuit OS1. As a result, the one-shot circuit OS1 outputs an on-trigger signal on_trg of a predetermined on-width that rises in synchronization with the rising edge of the output signal of the inverter circuit INV3, that is, the falling edge of the signal Td. The on-trigger signal on_trg sets the RS flip-flop RSFF2, and the RS flip-flop RSFF2 provides an H-level signal to one input terminal of the AND gate circuits AND3 and AND4.

[0120] At this time, the D flip-flop DFF3 is outputting the drive selection signal dri_sel. If the drive selection signal dri_sel is at the H level, the AND gate circuit AND3 outputs the high-side drive signal hi_pre, and if the drive selection signal dri_sel is at the L level, the AND gate circuit AND4 outputs the low-side drive signal lo_pre. It should be noted that the D flip-flop DFF3 switches the logic state of the drive selection signal dri_sel whenever the RS flip-flop RSFF2 is reset.

[0121] Furthermore, when the RS flip-flop RSFF1 is reset by the circuit that determines the dead time, the signal Td becomes L level, and the shutdown control circuit 21 starts to generate the shutdown signal to. At this time, since the output signal of the inverter circuit INV3 becomes H level, the switch SW2 is turned on (turned on) to discharge the charge of the capacitor Ctd, and the value that determines the dead time is cleared to zero.

[0122] Next, if the shutdown signal to or the soft start shutdown signal to_ss is input to the OR gate circuit OR2, the RS flip-flop RSFF1 is set, and the single-shot circuit OS2 outputs a shutdown trigger signal off_trg with a small opening width. The shutdown trigger signal off_trg is logically inverted by the inverter circuit INV4 and input to the clock input terminal of the D flip-flop DFF3. As a result, the D flip-flop DFF3 latches the output state of the inverter circuit INV5 synchronously with the falling edge of the shutdown trigger signal off_trg. That is, the D flip-flop DFF3 latches the H-level signal when its output state is L-level, and outputs the H-level drive selection signal dri_sel. On the contrary, the D flip-flop DFF3 latches the L-level signal obtained by the logic inversion of the inverter circuit INV5 when its output state is H-level, and outputs the L-level drive selection signal dri_sel.

[0123] It should be noted that when the hysteresis comparator COMP4 detects an abnormal drop in the voltage VCC, the hysteresis comparator COMP4 outputs an H-level signal to forcibly reset the RS flip-flop RSFF1 and the D flip-flop DFF3.

[0124] Next, the operation of the soft start control circuit 22 will be described in more detail.

[0125] Figure 6 is a flow chart showing the operation of the on-width setting circuit in the soft start control circuit, Figure 7 is a timing diagram showing the change of the opening width, Figure 8 is a diagram showing the waveforms of the main parts of the switching power supply. Figure 8 , changes in the output voltage Vo with respect to time, changes in the feedback voltage Vfb with respect to time, changes in the feedback state signal fb_state with respect to time, and changes in the on-width signal Ton with respect to time are respectively shown from the upper side.

[0126] If the switching power supply is turned on and soft start begins, Figure 6 As shown in FIG. 1 , in the opening width setting circuit 31, the initial setting is first performed (step S1). That is, the preset values ​​are substituted into the increase switching number signal Nsw_step, the maximum opening width signal Ton_max, the step signal Ton_step and the start opening width signal Ton_ss, and the start opening width signal Ton_ss of the initial value is set for Ton_1. Here, as an example, it is assumed that the increase switching number signal Nsw_step is set to "6". At this time, Ton_1 is as follows: Figure 7 As shown in FIG. 1 , the opening width of the high-side drive signal VHO and the low-side drive signal VLO at startup becomes. In addition, just after startup, as Figure 8As shown, the output voltage Vo is 0V, the feedback voltage Vfb increases rapidly, and the feedback state signal fb_state is L level “0”. Therefore, the multiplexer circuit MPX2 selects the input of the start opening width signal Ton_ss and stores the start opening width signal Ton_ss as the opening width signal Ton in the register REG1.

[0127] Next, the ON width setting circuit 31 waits until the feedback state signal fb_state becomes "1" at the H level (step S2). Figure 8 As shown, when the feedback voltage Vfb exceeds the reference voltage Vfb_ref1 , the feedback state signal fb_state becomes “1”.

[0128] If the feedback state signal fb_state becomes "1", in the open width setting circuit 31, the multiplexer circuit MPX2 selects the output of the multiplexer circuit MPX1, and the subtraction counter DOWNC1 counts the number of switching times Nsw (step S3). Since the zero flag signal zero_flag output by the subtraction counter DOWNC1 is initially at an L level, the output of the AND gate circuit AND1 is at an L level, and the multiplexer circuit MPX1 selects the output of the register REG1.

[0129] Next, the open width setting circuit 31 determines whether the number of switching times Nsw is counted to the value set by the increasing switching times signal Nsw_step based on the counting of the subtraction counter DOWNC1 (step S4). In the above example, since the increasing switching times signal Nsw_step is set to "6", when the number of switching times Nsw does not reach 6 when the subtraction counter DOWNC1 starts the subtraction operation from "6", it returns to step S3.

[0130] If the number of switching times Nsw counted by the subtraction counter DOWNC1 reaches "6" and zero_flag = 1 is output, the open width setting circuit 31 substitutes Ton_i+Ton_step into Ton_i+1 (i is a positive integer) (step S5). That is, at this time, since the multiplexer circuit MPX1 selects the output of the addition circuit ADD1, the open width signal Ton is updated to a value obtained by adding the value of the step signal Ton_step to the value of the open width stored in the register REG1.

[0131] Thereafter, the opening width setting circuit 31 determines whether the increased Ton_i+1 exceeds the value of the maximum opening width signal Ton_max (step S6). When Ton_i+1 exceeds the value of the maximum opening width signal Ton_max, the opening width setting circuit 31 updates the opening width value stored in the register REG1 to the value obtained by adding the value of the step signal Ton_step.

[0132] In step S6 , when Ton_i+1 does not exceed the value of the maximum on-width signal Ton_max, the process returns to step S3 , and the on-width setting circuit 31 counts the number of switching times Nsw by the subtraction counter DOWNC1 .

[0133] Thus, initially, after the opening width setting circuit 31 sets the start opening width signal Ton_ss, Figure 7 As shown, the opening width of the start opening width signal Ton_ss is used to control the opening of the switching elements Qa and Qb. At this time, the number of switching times Nsw is being counted. If it is counted to "6" of the increasing number of switching times signal Nsw_step, the opening width of the opening width signal Ton is increased by the value of the step signal Ton_step and changes from Ton_1 to Ton_2. Thereafter, each time the number of switching times Nsw is counted to 6 times, the step signal Ton_step is repeatedly increased.

[0134] It should be noted that the reason why the on width is increased every time the predetermined number of switching times Nsw is reached is that even for a high-speed response switching power supply, the clock frequency must be set to a considerable high level in order to accurately generate the step signal Ton_step most suitable for soft start.

[0135] It should be explained, such as Figure 8 As shown, regardless of the operation of updating the value obtained by adding the value of the step signal Ton_step to the value of the open width stored in the register REG1, the feedback state signal fb_state becomes "0" according to the feedback voltage Vfb, and the soft start is terminated. That is, if the feedback voltage Vfb drops, the shutdown signal to output by the shutdown control circuit 21 is output at an earlier time than the soft start shutdown signal to_ss according to the feedback voltage Vfb. Therefore, since the shutdown signal to of the shutdown control circuit 21 is preferentially input to the switch on / off control circuit 23, the soft start is terminated.

[0136] According to the above switching power supply control device, since the increase of the opening width in soft start is controlled by the switching number Nsw, an output voltage detection circuit for soft start is not required, and overshoot can be suppressed even in a high-speed response switching power supply.

[0137] <Second Embodiment>

[0138] Fig. 9 is a circuit diagram showing a configuration example of a switching power supply to which a control device according to the second embodiment is applied. Fig.10 2 is a frame showing a configuration example of a control device according to a second embodiment. Fig.11 is a diagram showing examples of parameter values ​​of different levels corresponding to input voltage, Fig.12 is a circuit diagram showing a configuration example of a soft start control circuit. Fig.13 is a flow chart showing the operation of the soft start control circuit. Fig. 9 , Fig.10 and Fig.12 In, with Figure 1 , Figure 2 and Figure 4 The same or equivalent components are denoted by the same reference numerals, and detailed description thereof is omitted.

[0139] Fig. 9 The switching power supply shown in the figure has a resistor R9 having one terminal connected to the input terminal 10p, the other terminal of the resistor R9 being connected to one terminal of a resistor R10, the other terminal of the resistor R10 being connected to the input terminal 10n. The connection point between the resistor R9 and the resistor R10 is connected to the BO terminal of the control device 12a. Figure 1 The switching power supply is the same.

[0140] Resistors R9 and R10 form a voltage divider circuit, and input a voltage obtained by dividing the input voltage Vi by the resistance ratio of resistor R9 to resistor R10. Thus, the control device 12a can know the value of the input voltage Vi input to the input terminals 10p and 10n, and can control the soft start at an optimal value corresponding to the value of the input voltage Vi.

[0141] like Fig.10 As shown, the control device 12a is the control device 12 ( Figure 2 ), it also has an input voltage level determination circuit 26. The input voltage level determination circuit 26 generates the following parameters: the parameters that are predetermined fixed values ​​in the control device 12 of the first embodiment depend on the parameters obtained by the change of the input voltage Vi. Therefore, the input voltage level determination circuit 26 has an input terminal connected to the BO terminal, an output terminal of the minimum opening width signal Ton_min, an output terminal of the maximum opening width signal Ton_max, an output terminal of the step signal Ton_step, and an output terminal of the increase switching number signal Nsw_step. These output terminals of the input voltage level determination circuit 26 are connected to the parameter input terminal of the soft start control circuit 22a.

[0142] exist Fig.11 In the example shown, the input voltage level determination circuit 26 divides the input voltage Vi of 380V to 100V into 0 to 15 levels. For each level, the value of the minimum opening width signal Ton_min, the maximum opening width signal Ton_max, the step signal Ton_step and the increase switching number signal Nsw_step is set. To this end, the input voltage level determination circuit 26 can be composed of, for example, 16 comparators, a logic circuit for determining the level division according to the output signal of the comparator, and a memory for storing the signal value of each level. If the input voltage Vi and the level are determined by the comparator and the logic circuit, the corresponding parameters are read from the memory and provided to the soft start control circuit 22a.

[0143] like Fig.12 As shown, the soft start control circuit 22a has parameter input terminals for a minimum opening width signal Ton_min, a maximum opening width signal Ton_max, a step signal Ton_step, and an increase switching number signal Nsw_step in addition to the FB terminal, the on_trg terminal, and the to_ss terminal. The minimum opening width signal Ton_min is input to the multiplexer circuit MPX2 of the opening width setting circuit 31, the maximum opening width signal Ton_max is input to the digital comparator COMP3, the step signal Ton_step is input to the adding circuit ADD1, and the increase switching number signal Nsw_step is input to the subtraction counter DOWNC1.

[0144] It should be noted that the opening width setting circuit 31 and the opening width counter circuit 32 of the soft start control circuit 22a have the same functions as the soft start control circuit 22 ( Figure 4 ) has the same structure and the same action.

[0145] According to the control device 12a of the second embodiment, the soft start control circuit 22a Fig.13 First, if the switching power supply is started and the soft start begins, the input voltage Vi and the level are determined in the input voltage level determination circuit 26, and the parameters corresponding to the level are output. At this time, in the soft start control circuit 22a, as shown in FIG. Fig.13As shown, a parameter corresponding to a level depending on the input voltage Vi is obtained from the input voltage level determination circuit 26 (step S11). As a result, the value of the increase switching number signal Nsw_step is set to the subtraction counter DOWNC1. In addition, the maximum opening width signal Ton_max is applied to the digital comparator COMP3, and the step signal Ton_step is input to the addition circuit ADD1, and the minimum opening width signal Ton_min is input to the multiplexer circuit MPX2. At this time, since the feedback state signal fb_state is "0" of the L level, the multiplexer circuit MPX2 selects the minimum opening width signal Ton_min and stores it in the register REG1.

[0146] Thereafter, if the feedback state signal fb_state becomes "1" of the H level (step S12), the multiplexer circuit MPX2 selects the output of the multiplexer circuit MPX1, and the subtraction counter DOWNC1 starts counting the number of switching times Nsw (step S13). Initially, the register REG1 outputs the minimum open width signal Ton_min as the open width signal Ton. It should be noted that step S11 may also be performed after the feedback state signal fb_state becomes "1" of the H level (after step S12).

[0147] Next, the open width setting circuit 31 determines whether the subtraction counter DOWNC1 counts the number of switching times Nsw to the value set by the increase switching times signal Nsw_step (step S14). If the subtraction counter DOWNC1 does not count to the value set by the increase switching times signal Nsw_step, the circuit returns to step S13 and continues to count the number of switching times Nsw based on the subtraction counter DOWNC1.

[0148] If the subtraction counter DOWNC1 counts to the value set by increasing the switching number signal Nsw_step, the on-width setting circuit 31 substitutes Ton_i+Ton_step into Ton_i+1 (i is a positive integer) (step S15 ).

[0149] Then, it is determined whether the incremented Ton_i+1 exceeds the value of the maximum opening width signal Ton_max (step S16). If Ton_i+1 does not exceed the value of the maximum opening width signal Ton_max, the process returns to step S13 to continue counting the number of switching times Nsw by the subtraction counter DOWNC1.

[0150] In step S16 , when Ton_i+1 exceeds the value of the maximum open width signal Ton_max, the open width setting circuit 31 fixes the open width signal Ton at the value of the maximum open width signal Ton_max, and the increase operation ends.

[0151] According to the control device 12a of the second embodiment, it is possible to suppress overshoot at the time of startup by suitably applying the control device to a high-speed response current resonance type switching power supply in the world where the input voltage Vi varies.

[0152] In addition, in the control device 12a of the second embodiment, the predetermined index is set as the number of switching times Nsw, but the present invention is not limited to this example.

Claims

1. A control device for a switching power supply, characterized in that: The switching power supply control device is a current resonance type switching power supply control device having a soft start control circuit for suppressing an overshoot of an output voltage at startup. The soft start control circuit alternately performs the following steps until the opening width of the driving signal obtained by increasing the predetermined step exceeds the maximum opening width signal: If the number of switching times does not reach a predetermined value, the process of making the opening width of the driving signal of the switching element driving the switching power supply constant; as well as If the switching times reaches a predetermined value, the opening width of the driving signal for driving the switching element of the switching power supply is increased in a predetermined step. The soft start control circuit has: A comparator, detecting a rise in a feedback voltage of the output voltage; an opening width setting circuit, which generates an opening width signal obtained by increasing the opening width by a predetermined step whenever a predetermined number of switching times is reached; and an on-width counter circuit, generating a soft start off signal indicating a time when the generated on-width signal ends, The opening width setting circuit has: A first counter, for counting the number of on-triggering of the driving signal, and outputting a zero mark signal whenever the counted number of on-triggering reaches a predetermined number of switching times; A register for storing the value of the opening width; an adder for adding the predetermined step to the value stored in the register; a first multiplexer, selecting the value stored in the register when the zero flag signal is not output, and selecting the output of the adder when the zero flag signal is output; as well as The second multiplexer selects the initial value of the on-width before the comparator detects the rise of the feedback voltage, and selects the output of the first multiplexer and outputs it to the register after the comparator detects the rise of the feedback voltage.

2. The control device for the switching power supply according to claim 1, characterized in that: The soft start control circuit sets the duty cycle of the driving signal to be constant.

3. The control device for the switching power supply according to claim 1, characterized in that: The opening width setting circuit has: a digital comparator that compares the value stored in the register with a maximum on-width signal; and The AND gate circuit sets the zero flag signal to be invalid only when the value stored in the register exceeds the maximum open width signal.

4. The control device for the switching power supply according to claim 3, characterized in that: The opening width setting circuit has a self-holding circuit, If the comparator detects a rise in the feedback voltage of the output voltage, the self-holding circuit holds the state.

5. The control device for the switching power supply according to claim 1, characterized in that: The open width counter circuit has: A second counter counts the number of times the drive signal is triggered to start, and outputs a zero signal when the value of the start width signal is reached; as well as The one-shot circuit outputs the soft-start shutdown signal with a predetermined opening width based on the zero signal.

6. The control device for the switching power supply according to claim 3, characterized in that: The switching power supply control device further comprises an input voltage level determination circuit which determines a level according to an input voltage of the switching power supply input at startup and outputs a value corresponding to the level to the opening width setting circuit.

7. The control device for the switching power supply according to claim 6, characterized in that: The value corresponding to the level is at least any one of the number of switches counted by the first counter, the step added by the adder, the minimum open width signal selected by the second multiplexer as the initial value of the open width, and the maximum open width signal as the reference input signal of the digital comparator.

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