A driving circuit

Abstract

The embodiment of the present invention discloses a driving circuit, which includes: a power control circuit, a switching circuit, at least one first load control circuit, at least one second load control circuit, a self-locking protection circuit and a controller; wherein the self-locking protection circuit is used to form a self-locking protection circuit to protect the driving circuit when a fault occurs in the driving circuit; the controller is used to input a control signal to a first enable input terminal, a second enable input terminal, a third enable input terminal, a fourth enable input terminal and a fifth enable input terminal to control the connection or disconnection of the first load control circuit and / or the second load control circuit. The driving circuit realizes that the first load control circuit and the second load control circuit can be controlled by the driving circuit, without the need to use a separate driving control circuit to drive each load separately, thereby reducing the number of chips and components required for driving, and reducing power consumption and cost.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of LED driving, and in particular to a driving circuit. Background Art

[0002] As a new type of light source, LED has many excellent properties, such as small size, easy combination, and can be used to form different lines and shapes, so it is widely used. For example, LED is often used in the lighting of vehicles such as cars, electric cars and trains.

[0003] Generally, due to the changeable shape of LED light sources, the response speed is required to be relatively fast, and the current requirement is relatively high, which puts high demands on the LED driver. In the prior art, due to the limitations of the power supply voltage range and the difficulty in selecting the power supply topology, each load is usually controlled by a separate control strategy. However, this method will result in a large number of control chips and related components, resulting in high power consumption and high costs. Summary of the invention

[0004] The present invention provides a driving circuit, by which at least two loads are controlled and driven, the number of chips and components required for driving can be reduced, and power consumption and cost can be reduced.

[0005] An embodiment of the present invention provides a driving circuit, which includes: a power control circuit, a switching circuit, at least one first load control circuit, at least one second load control circuit, a self-locking protection circuit and a controller;

[0006] The power input terminal of the switching circuit is connected to the first power signal, the switching circuit is electrically connected to the power control circuit, the power input terminal of the power control circuit is connected to the first power signal, the power control circuit is electrically connected to the first load control circuit, the first load control circuit is electrically connected to the second load control circuit, and the second load control circuit is electrically connected to the switching circuit;

[0007] The self-locking protection circuit is electrically connected to the power control circuit and the controller respectively, and is used to form a self-locking protection circuit to protect the drive circuit when a fault occurs in the drive circuit;

[0008] The first load control circuit includes a first enable input terminal, the second load control circuit includes a second enable input terminal, the switching circuit includes a third enable input terminal, a fourth enable input terminal and a fifth enable input terminal, and the controller is electrically connected to the first enable input terminal, the second enable input terminal, the third enable input terminal, the fourth enable input terminal and the fifth enable input terminal respectively;

[0009] The controller is used to input control signals to the first enable input terminal, the second enable input terminal, the third enable input terminal, the fourth enable input terminal and the fifth enable input terminal to control the connection or disconnection of the first load control circuit and / or the second load control circuit.

[0010] The present invention provides a driving circuit, which includes: a power control circuit, a switching circuit, at least one first load control circuit, at least one second load control circuit, a self-locking protection circuit and a controller; wherein the self-locking protection circuit is used to form a self-locking protection circuit to protect the driving circuit when a fault occurs in the driving circuit; the first load control circuit includes a first enable input terminal, the second load control circuit includes a second enable input terminal, the switching circuit includes a third enable input terminal, a fourth enable input terminal and a fifth enable input terminal, and the controller is used to input a control signal to the first enable input terminal, the second enable input terminal, the third enable input terminal, the fourth enable input terminal and the fifth enable input terminal to control the connection or disconnection of the first load control circuit and / or the second load control circuit. It can be seen that the controller controls the output state of each end of the first enable input terminal, the second enable input terminal, the third enable input terminal, the fourth enable input terminal and the fifth enable input terminal, and cooperates with the output of the power control circuit and the switching circuit to control the working state of the first load control circuit and the second load control circuit, thereby realizing the control of the first load and the second load, and realizing the protection of each load circuit fault through the self-locking protection circuit. The drive circuit can be used to control the first load control circuit and the second load control circuit without using a separate drive control circuit to drive each load separately, thereby reducing the number of chips and components required for driving, reducing power consumption and cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a schematic structural diagram of a driving circuit in Embodiment 1 of the present invention;

[0012] Figure 2 It is a schematic diagram of the structure of a driving circuit in the second embodiment of the present invention. DETAILED DESCRIPTION

[0013] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0014] Embodiment 1

[0015] Figure 1A schematic diagram of a driving circuit according to the first embodiment of the present invention is shown in FIG. Figure 1 , comprising: a power supply control circuit 100, a switching circuit 200, at least one first load control circuit 300, at least one second load control circuit 400, a self-locking protection circuit 500 and a controller 600;

[0016] The power input terminal B0 of the switching circuit 200 is connected to the first power signal VIN, the switching circuit 200 is electrically connected to the power control circuit 100, the power input terminal A0 of the power control circuit 100 is connected to the first power signal VIN, the power control circuit 100 is electrically connected to the first load control circuit 300, the first load control circuit 300 is electrically connected to the second load control circuit 400, and the second load control circuit 400 is electrically connected to the switching circuit 200;

[0017] The self-locking protection circuit 500 is electrically connected to the power control circuit 100 and the controller 600 respectively, and the self-locking protection circuit 500 is used to form a self-locking protection circuit to protect the driving circuit when a fault occurs in the driving circuit;

[0018] The first load control circuit 300 includes a first enable input terminal C0, the second load control circuit 400 includes a second enable input terminal D0, the switching circuit 200 includes a third enable input terminal B1, a fourth enable input terminal B2 and a fifth enable input terminal B3, and the controller 600 is electrically connected to the first enable input terminal C0, the second enable input terminal D0, the third enable input terminal B1, the fourth enable input terminal B2 and the fifth enable input terminal B3 respectively;

[0019] The controller 600 is used to input control signals to the first enable input terminal C0 , the second enable input terminal D0 , the third enable input terminal B1 , the fourth enable input terminal B2 and the fifth enable input terminal B3 to control the first load control circuit 300 and / or the second load control circuit 400 to be turned on or off.

[0020] The controller 600 inputs the same control signal to the first enable input terminal C0 , the third enable input terminal B1 , and the fourth enable input terminal B2 , and inputs the same control signal to the second enable input terminal D0 and the fifth enable input terminal B3 .

[0021] The first load control circuit 300 includes a first load, and the second load control circuit 400 includes a second load, and the first load and the second load may be, for example, an LED, etc. The controller 600 inputs control signals to the first enable input terminal C0, the second enable input terminal D0, the third enable input terminal B1, the fourth enable input terminal B2, and the fifth enable input terminal B3 to control the first load control circuit 300 and / or the second load control circuit 400 to be turned on or off, including four situations: turning off both the first load control circuit 300 and the second load control circuit 400, even if both the first load and the second load are not working; turning on both the first load control circuit 300 and the second load control circuit 400, that is, both the first load and the second load are working; turning on the first load control circuit 300 and turning off the second load control circuit 400, that is, the first load is working and the second load is not working; turning off the first load control circuit 300 and turning on the second load control circuit 400, that is, the second load is working and the first load is not working.

[0022] In the technical solution of this embodiment, the implementation process of the driving circuit is: Figure 1 When the user wants to make the first load work and the second load not work, the user can send a corresponding signal to the controller 600 through a switch, a button or a voice function. After the controller 600 receives the user's demand signal, the controller 600 controls the power input terminal A0 of the power control circuit 100 and the power input terminal B0 of the switching circuit 200 to access the first power signal VIN, so that the switching circuit 200 and the power control circuit 100 work. At the same time, the controller 600 inputs a high-level signal to the first enable input terminal C0, the third enable input terminal B1 and the fourth enable input terminal B2, and inputs a low-level signal to the second enable input terminal D0 and the fifth enable input terminal B3, so that the first load control circuit 300 is turned on, while the second load control circuit 400 cannot be turned on, that is, the first load works and the second load does not work.

[0023] When the user wants to make the first load not work and the second load work, the user can send a corresponding signal to the controller 600 through a switch, a button or a voice function. After the controller 600 receives the user's demand signal, the controller 600 controls the power input terminal A0 of the power control circuit 100 and the power input terminal B0 of the switching circuit 200 to access the first power signal VIN, so that the switching circuit 200 and the power control circuit 100 work. At the same time, the controller 600 inputs a low-level signal to the first enable input terminal C0, the third enable input terminal B1 and the fourth enable input terminal B2, and inputs a high-level signal to the second enable input terminal D0 and the fifth enable input terminal B3, so that the first load control circuit 300 cannot be turned on, and the second load control circuit 400 is turned on, that is, the first load does not work and the second load works.

[0024] When the user wants to make both the first load and the second load work, the user can send a corresponding signal to the controller 600 through a switch, a button or a voice function. After the controller 600 receives the user's demand signal, the controller 600 controls the power input terminal A0 of the power control circuit 100 and the power input terminal B0 of the switching circuit 200 to access the first power signal VIN, so that the switching circuit 200 and the power control circuit 100 work. At the same time, the controller 600 inputs a high-level signal to the first enable input terminal C0, the third enable input terminal B1, the fourth enable input terminal B2, the second enable input terminal D0 and the fifth enable input terminal B3, so that the first load control circuit 300 and the second load control circuit 400 are both turned on, so that the first load and the second load are both working.

[0025] When the controller 600 inputs low-level signals to the first enable input terminal C0, the second enable input terminal D0, the third enable input terminal B1, the fourth enable input terminal B2 and the fifth enable input terminal B3, the first load control circuit 300 and the second load control circuit 400 cannot be turned on, and at this time, the first load and the second load cannot work.

[0026] During the process of the controller 600 controlling the first load control circuit and the second load control circuit, if a circuit failure occurs, the self-locking protection circuit 500 will continue to send a high-level signal to the power control circuit 100 to form a self-locking protection circuit, thereby protecting the safety of the circuit and preventing damage to the device.

[0027] The technical solution of this embodiment provides a driving circuit, which includes: a power control circuit, a switching circuit, at least one first load control circuit, at least one second load control circuit, a self-locking protection circuit and a controller; wherein the self-locking protection circuit is used to form a self-locking protection circuit to protect the driving circuit when a fault occurs in the driving circuit; the first load control circuit includes a first enable input terminal, the second load control circuit includes a second enable input terminal, the switching circuit includes a third enable input terminal, a fourth enable input terminal and a fifth enable input terminal, and the controller is used to input a control signal to the first enable input terminal, the second enable input terminal, the third enable input terminal, the fourth enable input terminal and the fifth enable input terminal to control the connection or disconnection of the first load control circuit and / or the second load control circuit. It can be seen that the controller controls the output state of each end of the first enable input terminal, the second enable input terminal, the third enable input terminal, the fourth enable input terminal and the fifth enable input terminal, and cooperates with the output of the power control circuit and the switching circuit to control the working state of the first load control circuit and the second load control circuit, thereby realizing the control of the first load and the second load, and realizing the protection of each load circuit fault through the self-locking protection circuit. The drive circuit can be used to control the first load control circuit and the second load control circuit without using a separate drive control circuit to drive each load separately, thereby reducing the number of chips and components required for driving, reducing power consumption and cost.

[0028] Embodiment 2

[0029] Figure 2 is a schematic diagram of a driving circuit provided in Embodiment 2 of the present invention. Figure 2 The switching circuit 200 includes a first inductor L1 and a second inductor L2. The power input terminal B0 of the switching circuit 200 is electrically connected to the first end of the first inductor L1, the second end of the first inductor L1 is electrically connected to the first end of the second inductor L2, and the second end of the second inductor L2 is electrically connected to the power control circuit 100.

[0030] The power input terminal B0 of the switching circuit 200 inputs the first power signal VIN for supplying power to the first inductor L1. The first inductor L1 has a filtering function.

[0031] Optionally, refer to Figure 2 , the switching circuit 200 further includes a first diode D1, a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a second capacitor C2, a first transistor Q1, a second transistor Q2 and a third transistor Q3;

[0032] The cathode of the first diode D1 is electrically connected to the second end of the first inductor L1, the anode of the first diode D1 is electrically connected to the first end of the first resistor R1 and the first end of the first capacitor C1 respectively, the second end of the first resistor R1 is electrically connected to the second load control circuit 400, and the second end of the first capacitor C1 is electrically connected to the power supply control circuit 100; wherein the first resistor R1 can be used as a voltage dividing resistor.

[0033] The first end of the first transistor Q1 is electrically connected to the controller through the second resistor R2. For example, the first end of the first transistor Q1 is electrically connected to the first end of the second resistor R2, and the second end of the second resistor R2 is used as the third enable input terminal B1. The third enable input terminal B1 inputs the control signal of VIN-LOAD1 through the controller. The second end of the first transistor Q1 is electrically connected to the anode of the first diode D1, and the third end of the first transistor Q1 is grounded; the first end of the second transistor Q2 is electrically connected to the controller through the third resistor R3. For example, the first end of the second transistor Q2 is electrically connected to the first end of the third resistor R3, and the second end of the third resistor R3 is used as the fourth enable input terminal B2. The fourth enable input terminal B2 inputs the control signal of VIN-LOAD1 through the controller. The second end of the second transistor Q2 is electrically connected to the first end of the first transistor Q1, and the third end of the second transistor Q2 is grounded; the first end of the third transistor Q3 is electrically connected to the controller, and the first end of the third transistor Q3 can be used as the fifth enable input terminal B3. The fifth enable input terminal B3 inputs the control signal of VIN-LOAD2 through the controller. The second end of the third transistor Q3 is electrically connected to the first end of the second transistor Q2, and the third end of the third transistor Q3 is grounded. In addition, the switching circuit also includes capacitors C9 and C10, the first end of the capacitor C9 is electrically connected to the first end of the first inductor L1, the second end of the capacitor C9 is grounded, the first end of the capacitor C10 is electrically connected to the second end of the first inductor L1, and the second end of the capacitor C10 is grounded. The capacitor C9, the capacitor C10 and the first inductor L1 constitute a filter circuit.

[0034] The first transistor Q1, the second transistor Q2 and the third transistor Q3 may be NPN-type MOS transistors. The control process of the first transistor Q1, the second transistor Q2 and the third transistor Q3 is as follows: when the controller controls VIN-LOAD1 to be a high-level signal and VIN-LOAD2 to be a low-level signal: since IN-LOAD2 is a low-level signal, the first end input of the NPN-type MOS transistor Q3 is a low-level signal, and the NPN-type MOS transistor Q3 cannot be turned on, and since VIN-LOAD1 is a high-level signal, the first end input of the NPN-type MOS transistor Q2 is a high-level signal, the first end of the NPN-type MOS transistor Q2 is pulled high (that is, the base potential is pulled high), and the NPN-type MOS transistor Q2 is turned on. After the NPN-type MOS transistor Q2 is turned on, the first end of the NPN-type MOS transistor Q1 is pulled low (that is, the base potential is pulled low), so the NPN-type MOS transistor Q1 cannot be turned on.

[0035] When the controller controls VIN-LOAD1 to be a low-level signal and VIN-LOAD2 to be a high-level signal: since IN-LOAD2 is a high-level signal, the first end input of the NPN MOS tube Q3 is a high-level signal, and the NPN MOS tube Q3 is turned on. After the NPN MOS tube Q3 is turned on, the first end of the NPN MOS tube Q2 is turned on and pulled low. Since VIN-LOAD1 is a low-level signal, the first end of the NPN MOS tube Q2 is still pulled low, and the NPN MOS tube Q2 is not turned on. Since VIN-LOAD1 is a low-level signal, the NPN MOS tube Q1 cannot be turned on.

[0036] When the controller controls VIN-LOAD1 and VIN-LOAD2 to be high level signals: since IN-LOAD2 is a high level signal, the first end input of the NPN MOS tube Q3 is a high level signal, then the NPN MOS tube Q3 is turned on, and after the NPN MOS tube Q3 is turned on, the first end of the NPN MOS tube Q2 is turned on and pulled low, then the NPN MOS tube Q2 is not turned on, so that the first end of the NPN MOS tube Q1 is pulled high, and since VIN-LOAD1 is a high level signal, the NPN MOS tube Q1 is turned on.

[0037] Optionally, refer to Figure 2 The power control circuit 100 includes a power conversion module U1, a second diode D2, a fourth transistor Q4 and a fourth resistor R4, and the switching circuit 200 includes a first output end and a second output end; wherein, the second end of the second inductor L2 can be used as the first output end of the switching circuit 200, and the second end of the first capacitor C1 can be used as the second output end of the switching circuit 200.

[0038] A first end of the fourth transistor Q4 is electrically connected to the first output end SWO of the power conversion module U1, a second end of the fourth transistor Q4 is electrically connected to the first output end of the switching circuit 200, that is, the second end of the fourth transistor Q4 is electrically connected to the second end of the second inductor L2, and a third end of the fourth transistor Q4 is grounded;

[0039] The anode of the second diode D2 is electrically connected to the first output end of the switching circuit 200, that is, the anode of the second diode D2 is electrically connected to the second end of the second inductor L2, the cathode of the second diode D2 is electrically connected to the second output end of the switching circuit 200, that is, the cathode of the second diode D2 is electrically connected to the second end of the first capacitor C1, the first end of the fourth resistor R4 is electrically connected to the cathode of the second diode D2 and the first input end FBH of the power conversion module U1, respectively, and the second end of the fourth resistor R4 is electrically connected to the first load control circuit 300 and the second input end FBL of the power conversion module U1, respectively.

[0040] The second inductor L2, the fourth transistor Q4 and the second diode D2 form a boost topology structure. The fourth transistor Q4 may be an NPN MOS tube.

[0041] Optionally, refer to Figure 2 , the power control circuit 100 further includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8 and a third diode D3;

[0042] Wherein, a first end of the fifth resistor R5 is electrically connected to the first output end SWO of the power conversion module U1, a second end of the fifth resistor R5 is electrically connected to the first end of the fourth transistor Q4, an anode of the third diode D3 is electrically connected to the first end of the fourth transistor Q4, and a cathode of the third diode D3 is electrically connected to the first output end SWO of the power conversion module U1;

[0043] A first end of the sixth resistor R6 is electrically connected to a third end of the fourth transistor Q4, a second end of the sixth resistor R6 is grounded, a third end of the fourth transistor Q4 is also electrically connected to a third input end SWCS of the power conversion module U1, and a second end of the sixth resistor R6 is also electrically connected to a ground end of the power conversion module U1;

[0044] The first end of the seventh resistor R7 is electrically connected to the cathode of the second diode D2, the second end of the seventh resistor R7 is electrically connected to the first end of the eighth resistor R8, the second end of the eighth resistor R8 is grounded, and the second end of the seventh resistor R7 is also electrically connected to the fourth input end OVFB of the power conversion module U1.

[0045] The fifth resistor R5, the sixth resistor R6, the seventh resistor R7 and the eighth resistor R8 are used for current limiting. The third diode D3 can be a common diode for reverse protection. Figure 2The power control circuit 100 further includes a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C14, a resistor R22, a resistor R23, a resistor R24 ​​and a resistor R25, wherein the first end of the capacitor C11 is electrically connected to the power terminal IVCC of the power conversion module U1, the second end of the capacitor C11 is grounded, the first end of the capacitor C12 is electrically connected to the cathode of the second diode, and the second end of the capacitor C12 is grounded. Among them, the resistors R22, R23, R24 and R25 are used for current limiting.

[0046] Optionally, the power conversion module is a DC-DC converter.

[0047] Optionally, refer to Figure 2 The driving circuit further includes a filter circuit 700, the filter circuit 700 includes a third inductor L3, a third capacitor C3 and a fourth capacitor C4, the first end of the third inductor L3 is electrically connected to the power control circuit 100, for example, the first end of the third inductor L3 is electrically connected to the second end of the fourth resistor R4 of the power control circuit 100. The second end of the third inductor L3 is electrically connected to the first load control circuit 300, the first end of the third capacitor C3 is electrically connected to the first end of the third inductor L3, the second end of the third capacitor C3 is grounded, the first end of the fourth capacitor C4 is electrically connected to the second end of the third inductor L3, and the second end of the fourth capacitor C4 is grounded.

[0048] The filter circuit 700 is used to filter the voltage signal or current signal output by the power control circuit 100 and then output it to the first load control circuit 300 .

[0049] Optionally, refer to Figure 2 , the first load control circuit 300 includes a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, a first load LOAD1, a fifth capacitor C5, a sixth capacitor C6, a fourth diode D4 and a fifth diode D5;

[0050] The first end of the ninth resistor R9 is electrically connected to the controller, and the first end of the ninth resistor R9 can be used as a first enable input terminal C0, and the first enable input terminal C0 inputs the control signal of VIN-LOAD1 through the controller. The second end of the ninth resistor R9 is electrically connected to the first end of the fifth transistor Q5, and the second end of the fifth transistor Q5 is electrically connected to the power supply terminal IVCC through the eleventh resistor R11, and the third end of the fifth transistor Q5 is grounded;

[0051] A first end of the sixth transistor Q6 is electrically connected to a second end of the fifth transistor Q5, a second end of the sixth transistor Q6 is electrically connected to a first end of the seventh transistor Q7 through a twelfth resistor R12, a third end of the sixth transistor Q6 is grounded, a second end of the seventh transistor Q7 is electrically connected to a first end of the first load LOAD1, and a third end of the seventh transistor Q7 is electrically connected to a second end of the first load LOAD1;

[0052] The first end of the tenth resistor R10 is electrically connected to the second end of the ninth resistor R9, the second end of the tenth resistor R10 is grounded, the fourth diode D4 is connected between the first end and the third end of the fifth transistor Q5, the anode of the fourth diode D4 is electrically connected to the third end of the fifth transistor Q5, the fifth capacitor C5 is connected between the first end and the second end of the seventh transistor Q7, the fifth diode Q5 is connected between the first end and the second end of the seventh transistor Q7, the anode of the fifth diode D5 is electrically connected to the first end of the seventh transistor Q7, the thirteenth resistor R13 is connected between the first end and the second end of the seventh transistor Q7, and the sixth capacitor C6 is connected between the first end and the third end of the seventh transistor Q7.

[0053] The fourth diode D4 and the fifth diode D5 may be voltage stabilizing diodes. The first load LOAD1 may be an LED lamp, such as a light emitting diode. The fifth transistor Q5 may be an NPN transistor, the sixth transistor Q6 may be an NPN MOS transistor, and the seventh transistor Q7 may be a PNP MOS transistor.

[0054] In the technical solution of this embodiment, taking the fifth transistor Q5 as an NPN-type triode, the sixth transistor Q6 as an NPN-type MOS tube, and the seventh transistor Q7 as a PNP-type MOS tube as an example, the working principle of the first load control circuit is described, and its working principle is: when the controller controls the first enable input terminal C0 to input a high-level signal, the NPN-type triode Q5 works in the saturation region, the base of the NPN-type MOS tube Q6 is pulled down, and thus the NPN-type MOS tube Q6 cannot be turned on. Since the NPN-type MOS tube Q6 cannot be turned on, the voltage of its base and source remain consistent, so that the PNP-type MOS tube Q7 cannot be turned on. Therefore, the current input from the power supply control circuit 100 to the first load control circuit will flow out through the first load LOAD1, and will not flow out through the PNP-type MOS tube Q7. When the controller controls the first enable input terminal C0 to input a low-level signal, the NPN transistor Q5 works in the cut-off region, the base of the NPN MOS transistor Q6 is pulled high, and the NPN MOS transistor Q6 is turned on. After the NPN MOS transistor Q6 is turned on, a voltage difference is generated between its base and source, which satisfies the conduction condition of the base and source of the PNP MOS transistor Q7, so that the PNP MOS transistor Q7 is turned on. As a result, the current input from the power supply control circuit 100 to the first load control circuit will flow out through the PNP MOS transistor Q7, and will not flow out from the first load LOAD1.

[0055] Optionally, refer to Figure 2 , the second load control circuit 400 includes a second load LOAD2, an eighth transistor Q8, a ninth transistor Q9, a tenth transistor Q10, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a sixth diode D6, a seventh diode D7 and a seventh capacitor C7;

[0056] Wherein, the first end of the fourteenth resistor R14 is electrically connected to the controller, the first end of the fourteenth resistor R14 can be used as the second enable input terminal D0, and the second enable input terminal D0 inputs the control signal of VIN-LOAD2 through the controller. The second end of the fourteenth resistor R14 is electrically connected to the first end of the eighth transistor Q8, the second end of the eighth transistor Q8 is electrically connected to the power supply terminal IVCC through the sixteenth resistor R16, and the third end of the eighth transistor Q8 is grounded;

[0057] A first end of the ninth transistor Q9 is electrically connected to the second end of the eighth transistor Q8, a second end of the ninth transistor Q9 is electrically connected to the first end of the tenth transistor Q10 through the seventeenth resistor R17, a third end of the ninth transistor Q9 is grounded, a second end of the tenth transistor Q10 is electrically connected to the first end of the second load LOAD2, and a third end of the tenth transistor Q10 is electrically connected to the second end of the second load LOAD2;

[0058] The first end of the fifteenth resistor R15 is electrically connected to the second end of the fourteenth resistor R14, the second end of the fifteenth resistor R15 is grounded, the sixth diode D6 is connected between the first end and the third end of the eighth transistor Q8, the cathode of the sixth diode D6 is electrically connected to the first end of the eighth transistor Q8, the seventh capacitor C7 is connected between the first end and the second end of the tenth transistor Q10, the seventh diode D7 is connected between the first end and the second end of the tenth transistor Q10, and the eighteenth resistor R18 is connected between the first end and the second end of the tenth transistor Q10.

[0059] The sixth diode D6 and the seventh diode D7 may be voltage stabilizing diodes. The second load LOAD2 may be an LED lamp, such as a light emitting diode. The eighth transistor Q8 may be an NPN transistor, the ninth transistor Q9 may be an NPN MOS transistor, and the tenth transistor Q10 may be a PNP MOS transistor.

[0060] In the technical solution of this embodiment, taking the eighth transistor Q8 as an NPN-type triode, the ninth transistor Q9 as an NPN-type MOS tube, and the tenth transistor Q10 as a PNP-type MOS tube as an example, the working principle of the second load control circuit is described, and the working principle is as follows: when the controller controls the second enable input terminal D0 to input a high-level signal, the NPN-type triode Q8 works in a saturation region, the base of the NPN-type MOS tube Q9 is pulled low, and thus the NPN-type MOS tube Q9 cannot be turned on. Since the NPN-type MOS tube Q9 cannot be turned on, the voltages of its base and source remain consistent, and thus the PNP-type MOS tube Q10 cannot be turned on. Therefore, the current output by the first load control circuit will flow out through the second load LOAD1, but will not flow out through the PNP-type MOS tube Q10. When the controller controls the second enable input terminal D0 to input a low-level signal, the NPN transistor Q8 works in the cut-off region, the base of the NPN MOS transistor Q9 is pulled high, and the NPN MOS transistor Q9 is turned on. After the NPN MOS transistor Q9 is turned on, a voltage difference is generated between its base and source, which satisfies the conduction condition of the base and source of the PNP MOS transistor Q10, so that the PNP MOS transistor Q10 is turned on. As a result, the current output by the first load control circuit will flow out through the PNP MOS transistor Q10, and will not flow out from the second load LOAD2.

[0061] It should be noted that the drive circuit may also include multiple first load control circuits and second load control end circuits. Specifically, the supply voltage of the power control end circuit may be adjusted according to actual needs to achieve control of multiple loads. The specific number of the first load control circuit and the second load control end circuit may be set according to actual needs and is not specifically limited here.

[0062] In the technical solution of this embodiment, the implementation process of the driving circuit is: Figure 2When the user wants to make the first load work and the second load not work, the user can send a corresponding signal to the controller 600 through a switch, a button or a voice function. After the controller 600 receives the user's demand signal, the controller 600 controls the power input terminal A0 of the power conversion module U1 and the power input terminal B0 of the switching circuit 200 to access the first power signal VIN, so that the switching circuit 200 and the power control circuit 100 work. At the same time, the controller 600 inputs a high voltage to the first enable input terminal C0, the third enable input terminal B1 and the fourth enable input terminal B2. A flat signal is input to the second enable input terminal D0 and the fifth enable input terminal B3, and a low level signal is input to the second enable input terminal D0 and the fifth enable input terminal B3. At this time, the working process of the drive circuit is: the first power signal VIN supplies power to the power conversion module U1 and the first inductor L1, and the power signal is output to the boost topology structure composed of the second inductor L2, the fourth transistor Q4 and the second diode D2 after filtering by the first inductor L1, and then output through the boost topology structure, and then output to the filter circuit 700 through the current sampling resistor fourth resistor R4, and then output to the first load control circuit 300 after filtering by the filter circuit 700. Since a high-level signal is input to the first enable input terminal C0 of the first load control circuit 300, the NPN transistor Q5 operates in the saturation region, and the base of the NPN MOS transistor Q6 is pulled down, so that the NPN MOS transistor Q6 cannot be turned on. Since the NPN MOS transistor Q6 cannot be turned on, the voltages of its base and source remain consistent, so that the PNP MOS transistor Q7 cannot be turned on. Therefore, the current output to the first load control circuit 300 after filtering by the filter circuit 700 will flow out through the first load LOAD1, but will not flow out through the PNP MOS transistor Q7. Since the second enable input terminal D0 of the second load control circuit 400 inputs a low-level signal, the NPN transistor Q8 works in the cut-off region, the base of the NPN MOS transistor Q9 is pulled high, and the NPN MOS transistor Q9 is turned on. After the NPN MOS transistor Q9 is turned on, a voltage difference is generated between its base and source, which satisfies the conduction condition of the base and source of the PNP MOS transistor Q10, so that the PNP MOS transistor Q10 is turned on. Therefore, the current output by the first load LOAD1 of the first load control circuit 300 will directly flow out through the PNP MOS transistor Q10, and will not flow out from the second load LOAD2.Since the third enable input terminal B1 and the fourth enable input terminal B2 input high-level signals, and the fifth enable input terminal B3 inputs a low-level signal, the first terminal of the NPN MOS transistor Q3 inputs a low-level signal, and the NPN MOS transistor Q3 cannot be turned on. Since VIN-LOAD1 is a high-level signal, the first terminal of the NPN MOS transistor Q2 inputs a high-level signal, the first terminal of the NPN MOS transistor Q2 is pulled high (that is, the base potential is pulled high), and the NPN MOS transistor Q2 is turned on. After the NPN MOS transistor Q2 is turned on, the first terminal of the NPN MOS transistor Q1 is pulled low (that is, the base potential is pulled low), so the NPN MOS transistor Q1 cannot be turned on. Therefore, the current output by the PNP MOS tube Q10 of the second load control circuit 400 returns to the power input terminal VIN through the first diode D1 after the voltage division effect of the first resistor R1. The current loop thus formed is: the negative terminal of the first load LOAD1 (taking the first load LOAD1 as a light emitting diode as an example) becomes the positive terminal of the power input, and the output voltage is the sum of the load voltage of the first load LOAD1, the voltage division of the first resistor R1, and the power voltage input by the power supply VIN. In this way, the first load LOAD1 can work while the second load LOAD does not work.

[0063] When the user wants to make the first load not work and the second load work, the user can send a corresponding signal to the controller 600 through a switch, a button or a voice function. After the controller 600 receives the user's demand signal, the controller 600 controls the power input terminal A0 of the power control circuit 100 and the power input terminal B0 of the switching circuit 200 to access the first power signal VIN, so that the switching circuit 200 and the power control circuit 100 work. At the same time, the controller 600 inputs a low voltage to the first enable input terminal C0, the third enable input terminal B1 and the fourth enable input terminal B2. A high-level signal is input to the second enable input terminal D0 and the fifth enable input terminal B3. At this time, the working process of the drive circuit is: the first power signal VIN supplies power to the power conversion module U1 and the first inductor L1, and the power signal is filtered by the first inductor L1 and output to the boost topology structure composed of the second inductor L2, the fourth transistor Q4 and the second diode D2, and then output through the boost topology structure, and then output to the filter circuit 700 through the current sampling resistor fourth resistor R4, and then output to the first load control circuit 300 after filtering by the filter circuit 700. Since a low-level signal is input to the first enable input terminal C0 of the first load control circuit 300, the NPN transistor Q5 works in the cut-off region, the base of the NPN MOS transistor Q6 is pulled high, and the NPN MOS transistor Q6 is turned on. After the NPN MOS transistor Q6 is turned on, a voltage difference is generated between its base and source, which satisfies the conduction condition of the base and source of the PNP MOS transistor Q7, so that the PNP MOS transistor Q7 is turned on. Therefore, the current output to the first load control circuit 300 after being filtered by the filter circuit 700 will flow out through the PNP MOS transistor Q7, and will not flow out of the first load LOAD1. Since a high-level signal is input to the second enable input terminal D0, the NPN transistor Q8 operates in the saturation region, and the base of the NPN MOS transistor Q9 is pulled low, so that the NPN MOS transistor Q9 cannot be turned on. Since the NPN MOS transistor Q9 cannot be turned on, the voltages of its base and source remain consistent, so that the PNP MOS transistor Q10 cannot be turned on. Therefore, the current output by the PNP MOS transistor Q7 of the first load control circuit 300 will flow out through the second load LOAD1, but will not flow out through the PNP MOS transistor Q10. Since the third enable input terminal B1 and the fourth enable input terminal B2 input low-level signals, and the fifth enable input terminal B3 inputs a high-level signal, the first terminal of the NPN MOS transistor Q3 is input with a high-level signal, and the NPN MOS transistor Q3 is turned on. After the NPN MOS transistor Q3 is turned on, the first terminal of the NPN MOS transistor Q2 is turned on and pulled low. Since VIN-LOAD1 is a low-level signal, the first terminal of the NPN MOS transistor Q2 is still pulled low, and the NPN MOS transistor Q2 is not turned on. Moreover, since VIN-LOAD1 is a low-level signal, the NPN MOS transistor Q1 cannot be turned on.Therefore, the current output by the second load LOAD2 of the second load control circuit 400 returns to the power input terminal VIN through the first diode D1 after the voltage division effect of the first resistor R1. The current loop thus formed is: the negative terminal of the second load LOAD2 (taking the second load LOAD2 as a light emitting diode as an example) becomes the positive terminal of the power input, and the output voltage thereof is the sum of the load voltage of the second load LOAD2, the voltage division of the first resistor R1, and the power voltage input by the power supply VIN. In this way, the first load LOAD1 can be made inoperative while the second load LOAD is inoperative.

[0064] When the user wants to make both the first load and the second load work, the user can send a corresponding signal to the controller 600 through a switch, a button or a voice function. After the controller 600 receives the user's demand signal, the controller 600 controls the power input terminal A0 of the power control circuit 100 and the power input terminal B0 of the switching circuit 200 to access the first power signal VIN, so that the switching circuit 200 and the power control circuit 100 work. At the same time, the controller 600 inputs a high-level signal to the first enable input terminal C0, the third enable input terminal B1, the fourth enable input terminal B2, the second enable input terminal D0 and the fifth enable input terminal B3. At this time, the working process of the drive circuit is as follows: the first power signal VIN supplies power to the power conversion module U1 and the first inductor L1, and the power signal is output to the boost topology structure composed of the second inductor L2, the fourth transistor Q4 and the second diode D2 after filtering by the first inductor L1, and then output through the boost topology structure, and then output to the filter circuit 700 through the current sampling resistor fourth resistor R4, and then output to the first load control circuit 300 after filtering by the filter circuit 700. Since a high-level signal is input to the first enable input terminal C0 of the first load control circuit 300, the NPN transistor Q5 operates in the saturation region, and the base of the NPN MOS transistor Q6 is pulled down, so that the NPN MOS transistor Q6 cannot be turned on. Since the NPN MOS transistor Q6 cannot be turned on, the voltages of its base and source remain consistent, so that the PNP MOS transistor Q7 cannot be turned on. Therefore, the current output to the first load control circuit 300 after filtering by the filter circuit 700 will flow out through the first load LOAD1, but will not flow out through the PNP MOS transistor Q7. Since a high-level signal is input to the second enable input terminal D0, the NPN transistor Q8 operates in the saturation region, and the base of the NPN MOS transistor Q9 is pulled low, so that the NPN MOS transistor Q9 cannot be turned on. Since the NPN MOS transistor Q9 cannot be turned on, the voltages of its base and source remain consistent, so that the PNP MOS transistor Q10 cannot be turned on. Therefore, the current output by the PNP MOS transistor Q7 of the first load control circuit 300 will flow out through the second load LOAD1, but will not flow out through the PNP MOS transistor Q10. Since the third enable input terminal B1, the fourth enable input terminal B2 and the fifth enable input terminal B3 input high-level signals, the first terminal of the NPN MOS transistor Q3 is input with a high-level signal, and the NPN MOS transistor Q3 is turned on. After the NPN MOS transistor Q3 is turned on, the first terminal of the NPN MOS transistor Q2 is turned on and pulled low, and the NPN MOS transistor Q2 is not turned on. The non-conduction of the NPN MOS transistor Q2 causes the first terminal of the NPN MOS transistor Q1 to be pulled high, and the NPN MOS transistor Q1 is turned on.Therefore, the current output by the second load LOAD2 of the second load control circuit 400 returns to the ground terminal through the NPN MOS tube Q1 after the voltage division effect of the first resistor R1. The current loop thus formed is: the negative terminal of the second load LOAD2 (taking the second load LOAD2 as a light emitting diode as an example) becomes the power input ground, and the output voltage is the sum of the load voltage of the first load LOAD1, the load voltage of the second load LOAD2, and the voltage division of the first resistor R1. In this way, the first load LOAD1 and the second load LOAD can work simultaneously.

[0065] When the controller 600 inputs low level signals to the first enable input terminal C0 , the second enable input terminal D0 , the third enable input terminal B1 , the fourth enable input terminal B2 and the fifth enable input terminal B3 , the first load and the second load cannot work.

[0066] The technical solution of this embodiment provides a driving circuit, which includes: a power control circuit, a switching circuit, at least one first load control circuit, at least one second load control circuit, a self-locking protection circuit and a controller; wherein the self-locking protection circuit is used to form a self-locking protection circuit to protect the driving circuit when a fault occurs in the driving circuit; the first load control circuit includes a first enable input terminal, the second load control circuit includes a second enable input terminal, the switching circuit includes a third enable input terminal, a fourth enable input terminal and a fifth enable input terminal, and the controller is used to input a control signal to the first enable input terminal, the second enable input terminal, the third enable input terminal, the fourth enable input terminal and the fifth enable input terminal to control the connection or disconnection of the first load control circuit and / or the second load control circuit. It can be seen that the controller controls the output state of each end of the first enable input terminal, the second enable input terminal, the third enable input terminal, the fourth enable input terminal and the fifth enable input terminal, and cooperates with the output of the power control circuit and the switching circuit to control the working state of the first load control circuit and the second load control circuit, thereby realizing the control of the first load and the second load, and realizing the protection of each load circuit fault through the self-locking protection circuit. The drive circuit can be used to control the first load control circuit and the second load control circuit without using a separate drive control circuit to drive each load separately, thereby reducing the number of chips and components required for driving, reducing power consumption and cost.

[0067] Optionally, refer to Figure 2, the self-locking protection circuit 500 includes an eighth diode D8, a ninth diode D9, a tenth diode D10, an eighth capacitor C8, an eleventh transistor Q11, a twelfth transistor Q12, a thirteenth transistor Q13, a fourteenth transistor Q14, a nineteenth resistor R19, a twentieth resistor R20 and a twenty-first resistor R21; the power control circuit 100 includes a power conversion module U1;

[0068] Among them, the anode of the eighth diode D8 is electrically connected to the enable input terminal EN / PWM of the controller and the power conversion module U1 respectively, for example, the controller inputs a VIN-PWM control signal to the enable input terminal EN / PWM, the cathode of the eighth diode D8 is electrically connected to the first end of the nineteenth resistor R19, the second end of the nineteenth resistor R19 is electrically connected to the first end of the eleventh transistor Q11, the second end of the eleventh transistor Q11 is electrically connected to the cathode of the eighth diode D8 through the twentieth resistor R20, the third end of the eleventh transistor Q11 is grounded, the cathode of the ninth diode D9 is electrically connected to the third end of the eleventh transistor Q11, the anode of the ninth diode D9 is electrically connected to the second end of the twelfth transistor Q12, the first end of the twelfth transistor Q12 is electrically connected to the second output end of the power conversion module U1, and the second end of the twelfth transistor Q12 is electrically connected to the controller, for example, the controller inputs the VIN-PWM control signal to the second end of the twelfth transistor Q12, and the third end of the twelfth transistor Q12 is grounded;

[0069] The first end of the twenty-first resistor R21 is electrically connected to the first end of the eleventh transistor Q11, the second end of the twenty-first resistor R21 is electrically connected to the second end of the thirteenth transistor Q13, the first end of the thirteenth transistor Q13 is electrically connected to the third end of the eleventh transistor Q11, the third end of the thirteenth transistor Q13 is grounded, the first end of the thirteenth transistor Q13 is electrically connected to the anode of the tenth diode D10, the cathode of the tenth diode D10 is electrically connected to the first end of the fourteenth transistor Q14, the second end of the fourteenth transistor Q14 is electrically connected to the fifth input terminal SET of the power conversion module U1, and the third end of the fourteenth transistor Q14 is grounded.

[0070] The ninth diode D9 and the tenth diode D10 are used for reverse protection. The eleventh transistor Q11 can be a PNP MOS tube, the twelfth transistor Q12 can be an NPN triode, the thirteenth transistor Q13 can be an NPN MOS tube, and the fourteenth transistor Q14 can be an NPN MOS tube. The self-locking protection circuit 500 also includes a resistor R26, a resistor R27, a resistor R28, a resistor R29 and a capacitor C15.

[0071] In the technical solution of the present embodiment, the eleventh transistor Q11 is a PNP MOS tube, the twelfth transistor Q12 is an NPN triode, the thirteenth transistor Q13 is an NPN MOS tube, and the fourteenth transistor Q14 is an NPN MOS tube. The implementation process of the self-locking protection circuit of the driving circuit is as follows: when the driving circuit works normally, the control signal VIN-PWM input by the controller is a high-level signal. When the first load, the second load or the circuit fails, the second output terminal ST of the power conversion module U1 outputs a signal from a high-level signal to a low-level signal. At this time, the second end of the twelfth transistor Q12 is pulled high, and the high-level signal is output to the fourteenth transistor Q14 after passing through the ninth diode D9 and the tenth diode D10, so that the fourteenth transistor Q14 is turned on. After the fourteenth transistor Q14 is turned on, the fifth input terminal SET of the power conversion module U1 is pulled low, so that the output of the chip is turned off to protect the circuit. Further, the process of the self-locking protection circuit forming self-locking protection is as follows: since the second end of the twelfth transistor Q12 is pulled high, the high-level signal is outputted through the ninth diode D9 and then outputted to the first end of the thirteenth transistor Q13, so that the thirteenth transistor Q13 is turned on, and the thirteenth transistor Q13 is outputted through the twenty-first resistor R21 after being turned on, and the voltage of the first end of the eleventh transistor Q11 is the voltage divided by the nineteenth resistor R19 and the twenty-first resistor R21, and at this time, the voltage satisfies the turn-on condition of the eleventh transistor Q11, and the eleventh transistor Q11 is turned on. After the eleventh transistor Q11, the first end of the thirteenth transistor Q13 is always pulled high, thereby forming self-locking. When the control signal VIN-PWM is still a high-level signal, even if the power conversion module U1 automatically restarts due to its own protection function, causing the second output terminal ST to become a high-level signal, the entire circuit is still in a self-locking protection state, and the system can only restart when the control signal VIN-PWM loses power.

[0072] In addition, when the system is in the over-temperature protection state, the control signal VIN-PWM is in the PWM dimming mode, so that the average current of the first load and the second load can be reduced to reduce heat. For example, when the circuit fails, when the control signal VIN-PWM is in the PWM dimming mode, when PWM is high, the power conversion module U1 will report an error, that is, the second output terminal ST of the power conversion module U1 outputs a low-level signal, and according to the working principle of the above-mentioned self-locking protection circuit, it will form a self-locking; when PWM is low, the power conversion module U1 will not report an error, but at this time, the PWM signal passes through the eighth diode D8 and the eighth capacitor C8, and the high-level signal formed by the control circuit to form a self-locking still exists, that is, it can still form a self-locking protection, so an error can still be reported at this time.

[0073] When the system does not fail, when PWM is at a high level, the power conversion module U1 will not report an error, the second output terminal ST of the power conversion module U1 outputs a high level signal, and the self-locking protection circuit does not work. When PWM is at a low level, the power conversion module U1 will not report an error, and the second output terminal ST of the power conversion module U1 outputs a low level signal, and the self-locking protection circuit does not work, but the drive circuit can work normally.

[0074] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A driving circuit, characterized in that: include: A power supply control circuit, a switching circuit, at least one first load control circuit, at least one second load control circuit, a self-locking protection circuit and a controller; The power input terminal of the switching circuit is connected to the first power signal, the switching circuit is electrically connected to the power control circuit, the power input terminal of the power control circuit is connected to the first power signal, the power control circuit is electrically connected to the first load control circuit, the first load control circuit is electrically connected to the second load control circuit, and the second load control circuit is electrically connected to the switching circuit; The self-locking protection circuit is electrically connected to the power control circuit and the controller respectively, and is used to form a self-locking protection circuit to protect the drive circuit when a fault occurs in the drive circuit; The first load control circuit includes a first enable input terminal, the second load control circuit includes a second enable input terminal, the switching circuit includes a third enable input terminal, a fourth enable input terminal and a fifth enable input terminal, and the controller is electrically connected to the first enable input terminal, the second enable input terminal, the third enable input terminal, the fourth enable input terminal and the fifth enable input terminal respectively; The controller is used to input a control signal to the first enable input terminal, the second enable input terminal, the third enable input terminal, the fourth enable input terminal and the fifth enable input terminal to control the connection or disconnection of the first load control circuit and / or the second load control circuit; The switching circuit comprises a first inductor and a second inductor, a power input terminal of the switching circuit is electrically connected to a first terminal of the first inductor, a second terminal of the first inductor is electrically connected to a first terminal of the second inductor, and a second terminal of the second inductor is electrically connected to the power control circuit; The power control circuit includes a power conversion module, a second diode, a fourth transistor and a fourth resistor, and the switching circuit includes a first output terminal and a second output terminal; A first end of the fourth transistor is electrically connected to the first output end of the power conversion module, a second end of the fourth transistor is electrically connected to the first output end of the switching circuit, and a third end of the fourth transistor is grounded; The anode of the second diode is electrically connected to the first output end of the switching circuit, the cathode of the second diode is electrically connected to the second output end of the switching circuit, the first end of the fourth resistor is electrically connected to the cathode of the second diode and the first input end of the power conversion module, respectively, and the second end of the fourth resistor is electrically connected to the first load control circuit and the second input end of the power conversion module, respectively.

2. The driving circuit according to claim 1, characterized in that: The switching circuit further includes a first diode, a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor, a first transistor, a second transistor and a third transistor; The cathode of the first diode is electrically connected to the second end of the first inductor, the anode of the first diode is electrically connected to the first end of the first resistor and the first end of the first capacitor respectively, the second end of the first resistor is electrically connected to the second load control circuit, and the second end of the first capacitor is electrically connected to the power supply control circuit; The first end of the first transistor is electrically connected to the controller through the second resistor, the second end of the first transistor is electrically connected to the anode of the first diode, and the third end of the first transistor is grounded; The first end of the second transistor is electrically connected to the controller through the third resistor, the second end of the second transistor is electrically connected to the first end of the first transistor, and the third end of the second transistor is grounded; A first terminal of the third transistor is electrically connected to the controller, a second terminal of the third transistor is electrically connected to the first terminal of the second transistor, and a third terminal of the third transistor is grounded.

3. The driving circuit according to claim 1, characterized in that: The power control circuit further includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor and a third diode; Wherein, the first end of the fifth resistor is electrically connected to the first output end of the power conversion module, the second end of the fifth resistor is electrically connected to the first end of the fourth transistor, the anode of the third diode is electrically connected to the first end of the fourth transistor, and the cathode of the third diode is electrically connected to the first output end of the power conversion module; The first end of the sixth resistor is electrically connected to the third end of the fourth transistor, the second end of the sixth resistor is grounded, the third end of the fourth transistor is also electrically connected to the third input end of the power conversion module, and the second end of the sixth resistor is also electrically connected to the ground end of the power conversion module; The first end of the seventh resistor is electrically connected to the cathode of the second diode, the second end of the seventh resistor is electrically connected to the first end of the eighth resistor, the second end of the eighth resistor is grounded, and the second end of the seventh resistor is also electrically connected to the fourth input end of the power conversion module.

4. The driving circuit according to claim 1, characterized in that: The power conversion module is a DC-DC converter.

5. The driving circuit according to claim 1, characterized in that: It also includes a filtering circuit, which includes a third inductor, a third capacitor and a fourth capacitor. The first end of the third inductor is electrically connected to the power control circuit, the second end of the third inductor is electrically connected to the first load control circuit, the first end of the third capacitor is electrically connected to the first end of the third inductor, the second end of the third capacitor is grounded, the first end of the fourth capacitor is electrically connected to the second end of the third inductor, and the second end of the fourth capacitor is grounded.

6. The driving circuit according to claim 1, characterized in that: The first load control circuit includes a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fifth transistor, a sixth transistor, a seventh transistor, a first load, a fifth capacitor, a sixth capacitor, a fourth diode and a fifth diode; Wherein, a first end of the ninth resistor is electrically connected to the controller, a second end of the ninth resistor is electrically connected to a first end of the fifth transistor, a second end of the fifth transistor is electrically connected to a power supply end of the power conversion module through the eleventh resistor, and a third end of the fifth transistor is grounded; The first end of the sixth transistor is electrically connected to the second end of the fifth transistor, the second end of the sixth transistor is electrically connected to the first end of the seventh transistor through the twelfth resistor, the third end of the sixth transistor is grounded, the second end of the seventh transistor is electrically connected to the first end of the first load, and the third end of the seventh transistor is electrically connected to the second end of the first load; The first end of the tenth resistor is electrically connected to the second end of the ninth resistor, the second end of the tenth resistor is grounded, the fourth diode is connected between the first end and the third end of the fifth transistor, the anode of the fourth diode is electrically connected to the third end of the fifth transistor, the fifth capacitor is connected between the first end and the second end of the seventh transistor, the fifth diode is connected between the first end and the second end of the seventh transistor, the anode of the fifth diode is electrically connected to the first end of the seventh transistor, the thirteenth resistor is connected between the first end and the second end of the seventh transistor, and the sixth capacitor is connected between the first end and the third end of the seventh transistor.

7. The driving circuit according to claim 1, characterized in that: The second load control circuit includes a second load, an eighth transistor, a ninth transistor, a tenth transistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a sixth diode, a seventh diode and a seventh capacitor; Wherein, a first end of the fourteenth resistor is electrically connected to the controller, a second end of the fourteenth resistor is electrically connected to a first end of the eighth transistor, a second end of the eighth transistor is electrically connected to a power supply end of the power conversion module through the sixteenth resistor, and a third end of the eighth transistor is grounded; The first end of the ninth transistor is electrically connected to the second end of the eighth transistor, the second end of the ninth transistor is electrically connected to the first end of the tenth transistor through the seventeenth resistor, the third end of the ninth transistor is grounded, the second end of the tenth transistor is electrically connected to the first end of the second load, and the third end of the tenth transistor is electrically connected to the second end of the second load; The first end of the fifteenth resistor is electrically connected to the second end of the fourteenth resistor, the second end of the fifteenth resistor is grounded, the sixth diode is connected between the first end and the third end of the eighth transistor, the cathode of the sixth diode is electrically connected to the first end of the eighth transistor, the seventh capacitor is connected between the first end and the second end of the tenth transistor, the seventh diode is connected between the first end and the second end of the tenth transistor, and the eighteenth resistor is connected between the first end and the second end of the tenth transistor.

8. The driving circuit according to claim 1, characterized in that: The self-locking protection circuit includes an eighth diode, a ninth diode, a tenth diode, an eighth capacitor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a nineteenth resistor, a twentieth resistor and a twenty-first resistor; the power control circuit includes a power conversion module; wherein, an anode of the eighth diode is electrically connected to the enable input terminals of the controller and the power conversion module respectively, a cathode of the eighth diode is electrically connected to a first terminal of the nineteenth resistor, a second terminal of the nineteenth resistor is electrically connected to a first terminal of the eleventh transistor, a second terminal of the eleventh transistor is electrically connected to a cathode of the eighth diode through a twentieth resistor, a third terminal of the eleventh transistor is grounded, a cathode of the ninth diode is electrically connected to a third terminal of the eleventh transistor, an anode of the ninth diode is electrically connected to a second terminal of the twelfth transistor, a first terminal of the twelfth transistor is electrically connected to a second output terminal of the power conversion module, a second terminal of the twelfth transistor is electrically connected to the controller, and a third terminal of the twelfth transistor is grounded; The first end of the twenty-first resistor is electrically connected to the first end of the eleventh transistor, the second end of the twenty-first resistor is electrically connected to the second end of the thirteenth transistor, the first end of the thirteenth transistor is electrically connected to the third end of the eleventh transistor, the third end of the thirteenth transistor is grounded, the first end of the thirteenth transistor is electrically connected to the anode of the tenth diode, the cathode of the tenth diode is electrically connected to the first end of the fourteenth transistor, the second end of the fourteenth transistor is electrically connected to the fifth input end of the power conversion module, and the third end of the fourteenth transistor is grounded.

Images