A superjunction SOI-LDMOS device with low resistance N-type electron channel

Abstract

The present invention relates to a super junction SOI-LDMOS device with a low resistance N-type electron channel, and belongs to the field of semiconductor technology. The device includes a source contact region, a gate-source isolation oxide layer, a gate oxide layer, a gate contact region, a field oxide layer, a drain contact region, a source P+ region, a source, a drain, a P-body, an N-type drift region, a buried oxide layer, a substrate, a low resistance N-type electron channel and a super junction region; the left side of the low resistance N-type electron channel is adjacent to the upper right side of the P-body, the right side is close to the left side of the drain, and the top is adjacent to the right side below the gate oxide layer and the bottom of the field oxide layer from left to right, and the bottom is adjacent to the super junction region; the left side of the super junction region is adjacent to the lower right side of the P-body, the right side is adjacent to the N-type drift region, and the bottom is adjacent to the buried oxide layer. The present invention improves the concentration of the drift region and reduces R on,sp At the same time, it can also increase the breakdown voltage.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to a super junction SOI-LDMOS device with a low-resistance N-type electron channel. Background Art

[0002] With the continuous increase in demand for power semiconductor devices, the development of power semiconductor devices has been promoted. Among them, the lateral double diffused field effect transistor (LDMOS) used to process medium and low power plays a very important role in this process, and the manufacturing process of LDMOS is compatible with the traditional CMOS process, and the manufacturing process is simple and stable. Since LDMOS is a voltage-controlled device, compared with current-controlled devices (such as power bipolar transistors, traditional thyristors), its input impedance is very high and the driving circuit is easier. Moreover, it only conducts with majority carriers and has no minority carrier storage effect, so it can obtain a higher switching speed, so its operating frequency will have a higher operating frequency than other devices with multiple carriers conducting. These advantages of LDMOS also make it extremely competitive in the power semiconductor industry, and at the same time promote the healthy development of power semiconductor devices. Using LDMOS for medium and low power processing can make the use of electric energy more efficient, save energy, and improve the effect.

[0003] In addition, due to the unique structural characteristics of the SOI (Silicon-On-Insulator) substrate, which overcomes many of the shortcomings of bulk silicon materials, its use in integrated circuits can fully tap the potential of silicon integrated circuit technology. High Voltage Integrated Circuit (HVIC) based on SOI substrate integrates SOI technology, microelectronics technology and power electronics technology, and has been rapidly developed. It has extremely broad application prospects in weapon equipment, aerospace, industrial automation, power electronics and other high-tech industries. One of the cornerstones and core parts of SOI HVIC is the SOI-LDMOS (Lateral Double-diffused Metal-Oxide-Semiconductor) device. The main problem of this device at present is that the specific on-resistance R on,sp ∝BV 2.5 That is, to obtain a high breakdown voltage (BV), a long and low-concentration lateral drift region is required, so the device specific on-resistance (R on,sp ) is higher, BV and R on,sp In order to better measure the comprehensive performance of the device, the Baliga figure of merit (FOM) is used as an important indicator for evaluating the device, where FOM = BV 2 / Ron,sp .

[0004] In order to resolve this contradictory relationship and break the electrical performance limit of the silicon device, the present invention designs a super junction (SJ) structure to improve BV by expanding the electric field region. Summary of the invention

[0005] In view of this, the object of the present invention is to provide a super junction SOI-LDMOS device with a low resistance N-type electron channel, which improves the concentration of the drift region and reduces the specific on-resistance R on,sp At the same time, it can also increase the breakdown voltage.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] A super junction SOI-LDMOS device with a low resistance N-type electron channel, comprising a source contact region 1, a gate-source isolation oxide layer 2, a gate oxide layer 3, a gate contact region 4, a field oxide layer 6, a drain contact region 9, a source P+ region 10, a source 11, a drain 12, a P-body 13, an N-type drift region 14, a buried oxide layer 15, a substrate 16, a low resistance N-type electron channel 7 and a super junction region;

[0008] The low-resistance N-type electron channel 7 is adjacent to the upper right side of the P-body 13 on the left, adjacent to the left side of the drain 12 on the right, adjacent to the right side of the gate oxide layer 4 and the bottom of the field oxide layer 6 from left to right on the top, and borders the super junction region on the bottom; the super junction region is adjacent to the lower right side of the P-body 13 on the left, adjacent to the N-type drift region 14 on the right, and adjacent to the buried oxide layer 15 on the bottom.

[0009] Further, the super junction region includes m N-type columns 5 and m P-type columns 8 arranged alternately, one N-type column 5 and one P-type column 8 constitute a super junction column, where m≥2; the N-type column 5 is on the leftmost side, adjacent to the lower right side of the P-body 13; the P-type column 8 is on the rightmost side, adjacent to the N-type drift region 14 on the right side.

[0010] Furthermore, the super junction region includes n A-type super junction columns 18 and n-1 or n+1 B-type super junction columns 19 arranged alternately, where n≥2; the A-type super junction columns are arranged on the leftmost and rightmost sides; the front of the A-type super junction column is N-type doped, and the back is P-type doped; the front of the B-type super junction column is P-type doped, and the back is N-type doped.

[0011] Furthermore, the width, thickness and doping concentration of the N-type column 5 and the P-type column 8 can be increased or decreased, and the thickness of the low-resistance N-type electron channel 7 also changes in the opposite direction with its thickness, that is, the sum of the thickness of the N-type column 5 or the P-type column 8 and the low-resistance N-type electron channel 7 is equal to the sum of the thickness of the drain 12 and the N-type drift region 14.

[0012] Furthermore, in the middle part of the device: the right side of the source P+ region 10 is adjacent to the left side of the source 11, and the bottom is adjacent to the lower upper part of the P-body 13; the right side and bottom of the source 11 are close to the recessed part of the P-body 13, and the top is adjacent to the right side part below the source contact region 1, the bottom of the gate-source isolation oxide layer 2, and a part below the gate oxide layer 3 from left to right; the right side of the P-body 13 is adjacent to the left side of the low-resistance N-type electron channel 7 and the left side of the super junction region from top to bottom, and the top is adjacent to the lower surface of the gate oxide layer 3, and the bottom of the P-body 13 is adjacent to the upper surface of the buried oxide layer 15; the bottom of the N-type drift region 14 is adjacent to the right side part above the buried oxide layer 15.

[0013] Further, the device surface portion: the device surface from left to right is the source contact area 1 in the upper left corner, its right side is adjacent to the left side of the gate-source isolation oxide layer 2, and its bottom side is adjacent to the part above the source P+ region 10 and the part above the source 11 from left to right; the right side of the gate-source isolation oxide layer 2 is adjacent to the left side of the gate oxide layer 3 and the left side of the gate contact area 4, and the bottom side is close to the part above the source 11; the left side of the gate contact area 4 is adjacent to the part on the right side of the gate-source isolation oxide layer 2, the right side is close to the part on the left side of the field oxide layer 6, and the bottom side is adjacent to the top of the gate oxide layer 3 ; The left side of the gate oxide layer 3 is adjacent to a part of the right side of the gate-source isolation oxide layer 2, and the right side is close to a part of the left side of the field oxide layer 6, and from left to right below, it borders a part above the source 11, the top of the P-body 13, and the left section above the low-resistance N-type electron channel 7; the field oxide layer 6 is on the upper surface of the device, and from top to bottom on the left side, it is adjacent to the right side of the gate contact area 4 and the right side of the gate oxide layer 3, and on the right side, it is adjacent to the left side of the drain contact area 9, and directly below it borders most of the top of the low-resistance N-type electron channel 7; directly below the drain contact area 9 is the drain 12.

[0014] Furthermore, at the bottom of the device: the upper portion of the buried oxide layer 15 borders the lower surface of the P-body 13 , the lower portion of the super junction region and the lower surface of the N-type drift region 14 from left to right, and the lower portion borders the upper portion of the substrate 16 .

[0015] Furthermore, the width and doping concentration of the A-type super junction 18 and the B-type super junction 19 can be increased or decreased.

[0016] Furthermore, the material of the gate contact region 4 includes doped polysilicon.

[0017] The beneficial effects of the present invention are as follows: the device of the present invention adds longitudinally arranged superjunction N-type columns and superjunction P-type columns in the drift region, and the N-type columns and P-type columns deplete each other during reverse breakdown withstand voltage, expanding the electric field region and thus improving BV. In addition, the device of the present invention designs a low-resistance N-type electron channel. When forward-conducting, the doping concentration of the superjunction N-type column is higher than that of the drift region, providing a low-resistance electron channel for electrons, thereby reducing the specific on-resistance R on,sp The present invention uses an integrated composite superjunction structure to effectively increase the depletion width of the drift region, and can also increase the average electric field on the device surface, effectively increasing the device breakdown voltage. It solves the irreconcilable contradictory relationship between the on-resistance and withstand voltage of the traditional MOSFET, so that the relationship between the on-resistance and withstand voltage is changed from R on,sp ∝BV 2.5 Rewrite as R on,sp ∝BV 1.33 , thus breaking the silicon limit and becoming a milestone in the development of power devices.

[0018] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0020] Figure 1 It is a schematic structural diagram of a SOI-LDMOS device according to Embodiment 1 of the present invention;

[0021] Figure 2 It is a schematic structural diagram of a SOI-LDMOS device according to Embodiment 2 of the present invention;

[0022] Figure 3 It is a schematic structural diagram of a SOI-LDMOS device according to Embodiment 3 of the present invention;

[0023] Figure 4 The new structure SOI-LDMOS device provided by the present invention and the traditional SOI-LDMOS device and the traditional super junction SJ-LDMOS device are 14 cm -3 ,7×10 14 cm -3 ,9×10 14 cm -3 and 11×10 14 cm-3 Comparison chart of breakdown voltage and specific on-resistance;

[0024] Figure 5 The new structure SOI-LDMOS device provided by the present invention and the traditional SOI-LDMOS device and the traditional super junction SJ-LDMOS device are 14 cm -3 ,7×10 14 cm -3 ,9×10 14 cm -3 and 11×10 14 cm -3 Comparison chart of Baliga figure of merit FOM;

[0025] Figure 6 The new structure SOI-LDMOS device provided by the present invention and the traditional SOI-LDMOS device and the traditional super junction SJ-LDMOS device are in the breakdown state at Nd=7×10 14 cm -3 Comparison of two-dimensional electric field intensity at Y = 0.3 μm;

[0026] Figure 7 The new structure SOI-LDMOS device provided by the present invention and the traditional SOI-LDMOS device and the traditional super junction SJ-LDMOS device are in the breakdown state at Nd=7×10 14 cm -3 Comparison of two-dimensional electric field intensity at Y = 1.2 μm;

[0027] Figure 8 The new structure SOI-LDMOS device provided by the present invention and the traditional SOI-LDMOS device and the traditional super junction SJ-LDMOS device are in the breakdown state at Nd=7×10 14 cm -3 Comparison of two-dimensional electric field intensity at Y = 3.2 μm;

[0028] Fig. 9 The new structure SOI-LDMOS device provided by the present invention and the traditional SOI-LDMOS device and the traditional super junction SJ-LDMOS device are in the breakdown state at Nd=7×10 14 cm -3 Comparison of two-dimensional electric field intensity at Y = 5.2 μm;

[0029] Fig.10 The new structure SOI-LDMOS device provided by the present invention has a low resistance N-type electron channel doping concentration of 5×10 15 cm -3 , 8×10 15 cm -3, 1×10 16 cm -3 , 1.2×10 16 cm -3 and 1.5×10 16 cm -3 When the breakdown voltage BV and the on-resistance R on,sp The change curve of

[0030] Fig.11 The new structure SOI-LDMOS device provided by the present invention has a breakdown voltage BV and a specific on-resistance R when the thickness of the low-resistance N-type electron channel is 0.6μm, 0.8μm, 1μm, 1.2μm and 1.4μm. on,sp The change curve of

[0031] Fig.12 The new structure SOI-LDMOS device provided by the present invention has a breakdown voltage BV and a specific on-resistance R when the number of divisions is 1-8. on,sp The change curve of

[0032] Fig.13 A schematic diagram of the main process flow of the SOI-LDMOS device provided by the present invention;

[0033] Figure numerals: 1-source contact region, 2-gate-source isolation oxide layer, 3-gate oxide layer, 4-gate contact region, 5-N-type column, 6-field oxide layer, 7-low-resistance N-type electron channel, 8-P-type column, 9-drain contact region, 10-source P+ region, 11-source, 12-drain, 13-P-body, 14-N-type drift region, 15-buried oxide layer, 16-substrate, 18-A-type super junction column, 19-B-type super junction column. DETAILED DESCRIPTION

[0034] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0035] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0036] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0037] Embodiment 1:

[0038] like Figure 1 As shown, a preferred super junction SOI-LDMOS device with a low resistance N-type electron channel of the present invention includes: a source contact region 1, a gate-source isolation oxide layer 2, a gate oxide layer 3, a gate contact region 4, an N-type column 5, a field oxide layer 6, a low resistance N-type electron channel 7, a P-type column 8, a drain contact region 9, a source P+ region 10, a source 11, a drain 12, a P-body 13, an N-type drift region 14, a buried oxide layer 15, and a substrate 16.

[0039] 1) Device surface: From left to right on the device surface are the source contact area 1 in the upper left corner, its right side is adjacent to the left side of the gate-source isolation oxide layer 2, and its bottom side is adjacent to the source P+ region 10 and a part of the source 11 from left to right; the left side of the gate-source isolation oxide layer 2 is adjacent to the right side of the source contact area 1, and the right side borders the left side of the gate oxide layer 3 and the left side of the gate contact area 4, and the bottom side is close to a part of the source 11; the left side of the gate contact area 4 is adjacent to a part of the right side of the gate-source isolation oxide layer 2, and the right side is close to a part of the left side of the field oxide layer 6, and the top of the gate oxide layer 3 is directly below; the left side of the gate oxide layer 3 is adjacent to a part of the right side of the gate-source isolation oxide layer 2, and the right side is close to a part of the left side of the field oxide layer 6, and the bottom side is adjacent to a part of the source 11 and the P-body from left to right. The top of 13 borders a section above the low-resistance N-type electron channel 7; the field oxide layer is on the device surface, and the left side is adjacent to the right side of the gate contact area 4 and the right side of the gate oxide layer 3 from top to bottom, and the right side is close to the left side of the drain contact area 9, and the bottom side borders most of the top of the low-resistance N-type electron channel 7; the left side of the drain contact area 9 is close to the right side of the field oxide layer 6, and the bottom side is the drain 12;

[0040] 2) Middle part of the device: above the source P+ region 10 is the lower part of the source contact region 1, the right side is close to the left side of the source 11, and the lower part is adjacent to the lower upper part of the P-body 13; the left side of the source 11 is adjacent to the right side of the source P+ region 10, the right side is close to the small part of the P-body 13, and the upper part is adjacent to a part of the lower part of the source contact region 1, a part of the lower part of the gate-source isolation oxide layer 2 and a part of the lower part of the gate oxide layer 3 from left to right, and the lower part of the P-body 13 is below; a part of the left side of the P-body 13 is adjacent to the right side of the source 11, and the right side is adjacent to the left side of the low-resistance N-type electron channel 7 and the left side of the N-type column 5 from top to bottom, and the upper part is close to the lower surface of the gate oxide layer 3, and the slightly lower upper surface of the P-body 13 is adjacent to the lower surfaces of the source P+ region 10 and the source 11 from left to right, and the lower part is adjacent to the upper surface of the buried oxide layer 15; the left side of the low-resistance N-type electron channel 7 is adjacent to the P-body The small part on the right side of 13 is close to the left side of the drain 12 on the right side, and from left to right on the top, it is close to a small part below the gate oxide layer 4 and the bottom of the field oxide layer 6, and from left to right on the bottom, it is adjacent to the top of the seven alternating N-type columns 5 and the top of the P-type column 8; the left side of the drain 12 is close to the right side of the low-resistance N-type electron channel 7, the top is the bottom of the drain contact area 9, and the bottom is close to the top of the N-type drift region 14; the left side of the leftmost N-type column 5 is close to the P-body Most of the right side of 13, the right side is the left side of the P-type column 8, the upper part is a small part below the low-resistance N-type electron channel 7, and the lower part is adjacent to the upper part of the buried oxide layer 15; the distance between the remaining six drift super junction N-type regions 5 and the leftmost N-type column 5 increases from left to right by the width of a P-type column 8, and their left sides are adjacent to the right side of a P-type column 8, and the right side is close to the left side of another P-type column 8, and the upper part is adjacent to a small part below the low-resistance N-type electron channel 7, and the lower part is adjacent to a small part of the buried oxide layer 15; the left side of the rightmost P-type column 8 is adjacent to the right side of a drift super junction N-type region 5, and the right side is close to the N-type drift region 1 4, bordering on a small part of the low-resistance N-type electron channel 7 on the top, and bordering on a small part of the buried oxide layer 15 on the bottom; the distances between the remaining six drift super junction P-type regions 8 and the rightmost P-type column 8 increase from right to left by the width of an N-type column 5, and their left sides are adjacent to the right side of an N-type column 5, and their right sides are close to the left side of another N-type column 5, and bordering on a small part of the low-resistance N-type electron channel 7 on the top, and bordering on a small part of the buried oxide layer 15 on the bottom; the left side of the N-type drift region 14 is adjacent to the right side of the drift super junction P-type region 8, and bordering on the bottom of the drain 12 on the top, and bordering on a part of the top of the buried oxide layer 15 on the bottom;

[0041] 3) Bottom of the device: The upper part of the buried oxide layer 15 borders the lower surface of the P-body 13, the lower part of the seven alternately arranged N-type columns 5, the lower part of the P-type columns 8, and the lower surface of the N-type drift region 14 from left to right, and the lower part is completely covered by the upper surface of the substrate 16; the substrate 16 is at the bottom layer of the device.

[0042] The substrate 16 is doped silicon with a thickness of 2 μm, a width of 20 μm, and a doping concentration of 8×10 14 cm -3 The buried oxide layer 15 is silicon dioxide with a thickness of 2 μm and a width of 20 μm.

[0043] The upper surface of the buried oxide layer 15 has a thickness of 5 μm, a width of 3 μm, and a doping concentration of 1×10 17 cm -3 P-body 13, followed by seven layers with a thickness of 4 μm, a width of 0.5 μm, and a doping concentration of 2.1×10 15 cm -3 The N-type pillars are 5, and seven pillars with a thickness of 4 μm, a width of 1.5 μm, and a doping concentration of 7×10 14 cm -3 The P-type columns 8 are alternately arranged on the upper surface of the buried oxide layer 15, followed by a layer with a thickness of 4 μm, a width of 3 μm and a doping concentration of 7×10 14 cm -3 N-type drift region 14.

[0044] The source P+ region 10 is located at the upper left corner of the P-body 13, and the source is adjacent to its right and is also located in the P-body 13. Their upper surfaces are parallel to the upper surface of the P-body 13. The source P+ region 10 has a thickness and width of 1 μm and a doping concentration of 1×10 19 cm -3 The source electrode has a thickness and width of 1 μm and a doping concentration of 1×10 19 cm -3 .

[0045] The low-resistance N-type electron channel 7 completely covers the upper surface of the seven N-type columns 5 and the seven P-type columns 8. It has a thickness of 1 μm, a width of 14 μm, and a doping concentration of 1×10 16 cm -3 .

[0046] The drain 12 completely covers the N-type drift region 14 and is adjacent to the low-resistance N-type electron channel 7 on the left. It has a thickness of 1 μm, a width of 3 μm, and is doped with phosphorus at a doping concentration of 1×10 19 cm -3 .

[0047] The source contact region 1 covers the entire source P+ region 10 and a portion of the source 11. It is aluminum with a thickness of 0.2 μm and a length of 1.2 μm.

[0048] The gate-source isolation oxide layer 2 is on the right side of the source contact region 1 and above the source 11. It is silicon dioxide with a thickness of 0.2 μm and a length of 0.3 μm.

[0049] The gate oxide layer 3 covers the upper surface of the source, the P-body 13 and a portion of the low-resistance N-type electron channel 7, and the left side is adjacent to the gate-source isolation oxide 2. It is silicon dioxide with a thickness of 0.1 μm and a width of 1.8 μm.

[0050] The gate contact region 4 is located directly above the gate oxide layer 3 and completely covers the gate oxide layer 3. It is polysilicon with a thickness of 0.1 μm and a width of 1.8 μm.

[0051] The left side of the field oxide layer 6 is adjacent to the gate contact region 4 and the gate oxide layer 3, and is located directly above the low-resistance N-type electron channel 7. It is silicon dioxide with a thickness of 0.2 μm and a width of 13.7 μm.

[0052] The drain contact region 9 is located directly above the drain 12 and completely covers the drain 12. It is aluminum with a thickness of 0.2 μm and a width of 3 μm.

[0053] Embodiment 2:

[0054] like Figure 2 As shown, a preferred super junction SOI-LDMOS device with a low resistance N-type electron channel in an embodiment of the present invention includes: a source contact region 1, a gate-source isolation oxide layer 2, a gate oxide layer 3, a gate contact region 4, a field oxide layer 6, a low resistance N-type electron channel 7, a P-type column 8, a drain contact region 9, a source P+ region 10, a source 11, a drain 12, a P-body 13, an N-type drift region 14, a buried oxide layer 15, a substrate 16, an A-type super junction 18, and a B-type super junction 19.

[0055] Based on the structure of Example 1, the part of the drift region consisting of seven N-type columns 5 and seven P-type columns 8 is replaced by four A-type super junctions 18 and three B-type super junctions 19 from left to right. The front of the A-type super junction 18 is N-type doped with a doping concentration of 2.1×10 15 cm -3 , the thickness in the Z direction is 0.25μm; the back is P-type doped, and the doping concentration is 7×10 14 cm -3 , the thickness in the Z direction is 0.75μm. The front of the B-type super junction 19 is P-type doped with a doping concentration of 7×10 14 cm -3, the thickness in the Z direction is 0.75 μm; the latter is N-type doping, where the N-type doping concentration is 2.1×10 15 cm -3 , the P-type doping concentration is 7×10 14 cm -3 The default thickness of the device in the Z direction is 1μm.

[0056] Embodiment 3:

[0057] like Figure 3 As shown, a preferred super junction SOI-LDMOS device with a low resistance N-type electron channel in an embodiment of the present invention includes a source contact region 1, a gate-source isolation oxide layer 2, a gate oxide layer 3, a gate contact region 4, an N-type column 5, a field oxide layer 6, a low resistance N-type electron channel 7, a P-type column 8, a drain contact region 9, a source P+ region 10, a source 11, a drain 12, a P-body 13, an N-type drift region 14, a buried oxide layer 15, and a substrate 16.

[0058] On the basis of the structure of Example 1, the thickness of the part composed of seven N-type columns 5 and seven P-type columns 8 in the drift region is changed from left to right to increase in a diagonal manner, and the thickness of the low-resistance N-type electron channel 7 also changes with it, showing a diagonal decrease. The thickness of the left side of the low-resistance N-type electron channel 7 is 4 μm, and the thickness of the right side is 1 μm.

[0059] Simulation experiment:

[0060] By using the Sentaurus simulation software, the conventional SOI-LDMOS, the conventional superjunction SOI-LDMOS and the novel SOI-LDMOS of Example 1 of the present invention are simulated and compared. During the simulation process, the simulation parameters of the four structures are consistent, wherein N - The total thickness of the drift region is 5 μm, the ambient temperature is 300 K, the length is 20 μm, and the drift region doping concentration is N d The doping concentration of the low-resistance N-type electron channel, the width, thickness and doping concentration of the N-type column and the width, thickness and doping concentration of the P-type column are all adjustable.

[0061] Figure 4 At room temperature T = 300K, the concentration in the drift region is 5×10 14 cm -3 ,7×10 14 cm -3 ,9×10 14 cm -3 and 11×10 14 cm -3 When the traditional LDMOS (its structure is as follows Figure 1 As shown), conventional super junction LDMOS (its structure is as shown Figure 2The comparison diagram of the specific on-resistance and withstand voltage of the new structure SOI-LDMOS device in the on-state and the avalanche breakdown state is shown in the figure. The data results obtained by Sentaurus simulation are then compared with the comparison diagram drawn by the Origin tool. Figure 4 As shown, it can be seen that: under the four drift region doping concentrations: the breakdown voltage of the new structure SOI-LDMOS is higher than that of the traditional SOI-LDMOS structure and the traditional super junction SOI-LDMOS, and the specific on-resistance of the new structure SOI-LDMOS is also lower than that of the traditional SOI-LDMOS structure and the traditional super junction SOI-LDMOS. Figure 5 The FOM comparison of the three structures under the above different doping concentrations is shown. Table 1 records the FOM merits of the traditional SOI-LDMOS device, the traditional superjunction SOI-LDMOS device and the new structure SOI-LDMOS device under four different drift region doping concentrations. It can be seen that under the above different doping concentrations, compared with the traditional SOI-LDMOS and the traditional superjunction SOI-LDMOS, the specific on-resistance of the new structure SOI-LDMOS is reduced, and the breakdown voltage of the device is also significantly improved. Overall, the Baliga merit FOM of the new structure SOI-LDMOS is finally improved.

[0062] Table 1 FOM figures of merit of three devices at different drift region doping concentrations;

[0063]

[0064] Figure 6 The concentration in the drift region is 7×10 14 cm -3 The two-dimensional electric field comparison diagram of the traditional SOI-LDMOS, traditional super junction SOI-LDMOS and new structure SOI-LDMOS devices at Y = 0.3μm in the avalanche breakdown state. Fig. 9 It can be seen that the electric field peak of the new structure SOI-LDMOS is transferred from the drain end to the source end, the average electric field at the drift region Y=0.3μm is improved, the area enclosed by the X-axis is increased, and the breakdown voltage is improved.

[0065] Figure 7 The concentration in the drift region is 7×10 14 cm -3 The two-dimensional electric field comparison diagram of the traditional SOI-LDMOS, traditional super junction SOI-LDMOS and new structure SOI-LDMOS devices at Y = 1.2μm in the avalanche breakdown state. Fig.10 It can be seen that the average electric field of the new structure SOI-LDMOS at the drift region Y=1.2μm is improved, the area enclosed by the X-axis is increased, and the breakdown voltage is improved.

[0066] Figure 8 The concentration in the drift region is 7×10 14 cm -3 The two-dimensional electric field comparison diagram of the traditional SOI-LDMOS, traditional super junction SOI-LDMOS and new structure SOI-LDMOS devices at Y = 3.2μm in the avalanche breakdown state. Fig.11 It can be seen that the average electric field of the new structure SOI-LDMOS at the drift region Y=3.2μm is improved.

[0067] Fig. 9 The concentration in the drift region is 7×10 14 cm -3 The two-dimensional electric field comparison diagram of the traditional SOI-LDMOS, traditional super junction SOI-LDMOS and new structure SOI-LDMOS devices at Y = 5.2μm in the avalanche breakdown state. Fig.12 It can be seen that the average electric field in the drift region of the new structure SOI-LDMOS at the drift region Y=5.2μm is improved.

[0068] Fig.10 The simulation shows that the concentration in the drift region is 7×10 14 cm -3 , the concentration of N-type column is 2.1×10 15 cm -3 , the concentration of P-type column is 7×10 14 cm -3 , when the number of divisions is 7 (i.e., the drift region below the low-resistance N-type electron channel is divided into seven regions, each region consists of an N-type column and a P-type column) and the thickness of the low-resistance N-type electron channel is 1 μm, and the doping concentrations in the low-resistance N-type electron channel are 5×10 15 cm -3 , 8×10 15 cm -3 , 1×10 16 cm -3 , 1.2×10 16 cm -3 , 1.5×10 16 cm -3 When the new structure SOI-LDMOS breakdown voltage and specific on-resistance R on,sp At a concentration of 1×10 16 cm -3 At , the device breakdown voltage reaches a maximum value of 212V, and the minimum breakdown voltage here is 81V; while R on,sp It shows a decreasing trend with the increase of concentration, about 33mΩ·cm 2 Down to 13mΩ·cm2 about.

[0069] Fig.11 The simulation shows that the concentration in the drift region is 7×10 14 cm -3 , the concentration of N-type column is 2.1×10 15 cm -3 , the concentration of P-type column is 7×10 14 cm -3 , the number of divisions is 7 (i.e. the drift region below the low-resistance N-type electron channel is divided into seven regions, each of which consists of an N-type column and a P-type column) and the concentration of the low-resistance N-type electron channel is 1×10 16 cm -3 When the thickness of the low-resistance N-type electron channel is 0.6μm, 0.8μm, 1μm, 1.2μm, and 1.4μm, respectively, the breakdown voltage and specific on-resistance R of the new structure SOI-LDMOS on,sp At a concentration of 1×10 16 cm -3 At , the device breakdown voltage reaches a maximum value of 210V, and the minimum breakdown voltage here is 99V; while R on,sp It shows a decreasing trend with the increase of concentration, about 28mΩ·cm 2 Down to 13mΩ·cm 2 about.

[0070] Fig.12 The simulation shows that the concentration in the drift region is 7×10 14 cm -3 , the concentration of N-type column is 2.1×10 15 cm -3 , the concentration of P-type column is 7×10 14 cm -3 , the thickness of the low-resistance N-type electron channel is 1 μm and the concentration of the low-resistance N-type electron channel is 1×10 16 cm -3 When the number of divisions is 1, 2, 3, 4, 5, 6, 7 and 8 respectively, the breakdown voltage and specific on-resistance R of the new structure SOI-LDMOS on,sp It can be seen that as the number of divisions increases, the breakdown voltage also increases, and finally tends to be stable, ranging from about 184-212V, and reaching a maximum value of 212V when the number of divisions is 7; on,sp As the number of divisions increases, it first rises and then decreases, and the range is about 17mΩ·cm 2 Up to 18.5mΩ·cm 2 .

[0071] The present invention proposes a super junction SOI-LDMOS device with a low resistance N-type electron channel, as shown in FIG. Figure 1 For example, its main process flow is as follows Fig.13 As shown. The specific implementation method includes: selecting an SOI substrate and epitaxially growing an N-drift region. Secondly, ion implantation, diffusion and other processes are used to complete the P-body of the new SOI-LDMOS. Then, ion implantation, diffusion and other processes are used to complete the production of N-type columns and P-type columns in the drift region. The next step is to use ion implantation, high-temperature junction pushing, diffusion and other processes to form the source P+ region, source, low-resistance N-type electron channel and drain. Next, silicon is deposited on the surface and a dense gate oxide layer is grown by dry oxygen oxidation. Thereafter, a gate electrode metal is formed on the oxide layer, and then silicon is deposited and oxidized. Finally, holes are drilled to deposit the source metal contact and the drain metal contact.

[0072] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A superjunction SOI-LDMOS device with a low-resistance N-type electron channel, comprising a source contact region (1), a gate-source isolation oxide layer (2), a gate oxide layer (3), a gate contact region (4), a field oxide layer (6), a drain contact region (9), a source P+ region (10), a source (11), a drain (12), a P-body (13), an N-type drift region (14), a buried oxide layer (15), and a substrate (16), characterized in that: The device also includes a low-resistance N-type electron channel (7) and a super junction region; The left side of the low-resistance N-type electron channel (7) is adjacent to the upper right side of the P-body (13), the right side is adjacent to the left side of the drain (12), the upper side is adjacent to the right side portion below the gate oxide layer (3) and the lower side of the field oxide layer (6) from left to right, and the lower side is adjacent to the super junction region; the left side of the super junction region is adjacent to the lower right side of the P-body (13), the right side is adjacent to the N-type drift region (14), and the lower side is adjacent to the buried oxide layer (15); The super junction region comprises m N-type columns (5) and m P-type columns (8) arranged alternately, wherein one N-type column (5) and one P-type column (8) form a super junction column, wherein m≥2; the N-type column (5) is arranged on the far left, adjacent to the lower right side of the P-body (13); the P-type column (8) is arranged on the far right, adjacent to the N-type drift region (14) on the right side; The width, thickness and doping concentration of the N-type column (5) and the P-type column (8) are increased or decreased according to demand, and the thickness of the low-resistance N-type electron channel (7) also changes inversely with the thickness thereof, that is, the sum of the thicknesses of the N-type column (5) or the P-type column (8) and the low-resistance N-type electron channel (7) is equal to the sum of the thicknesses of the drain (12) and the N-type drift region (14).

2. The superjunction SOI-LDMOS device according to claim 1, characterized in that: In the middle part of the device: the right side of the source P+ region (10) is adjacent to the left side of the source (11), and the lower side is adjacent to the lower upper part of the P-body (13); the right side and the lower side of the source (11) are close to the recessed part of the P-body (13), and the upper side is adjacent to the right side part below the source contact region (1), the lower side of the gate-source isolation oxide layer (2), and a part below the gate oxide layer (3) from left to right; the right side of the P-body (13) is adjacent to the left side of the low-resistance N-type electron channel (7) and the left side of the super junction region from top to bottom, and the upper side is adjacent to the lower surface of the gate oxide layer (3), and the lower side of the P-body (13) is adjacent to the upper surface of the buried oxide layer (15); the lower side of the N-type drift region (14) is adjacent to the right side part above the buried oxide layer (15).

3. The super junction SOI-LDMOS device according to claim 1, characterized in that: The device surface portion: from left to right on the device surface, the source contact area (1) at the upper left corner, its right side is adjacent to the left side of the gate-source isolation oxide layer (2), and its lower side is adjacent to the part above the source P+ area (10) and the part above the source (11) from left to right; the right side of the gate-source isolation oxide layer (2) borders the left side of the gate oxide layer (3) and the left side of the gate contact area (4), and its lower side is adjacent to the part above the source (11); The gate contact region (4) is adjacent to a portion of the right side of the gate-source isolation oxide layer (2) on the left, adjacent to a portion of the left side of the field oxide layer (6) on the right, and adjacent to the top of the gate oxide layer (3) directly below; the gate oxide layer (3) is adjacent to a portion of the right side of the gate-source isolation oxide layer (2) on the left, adjacent to a portion of the left side of the field oxide layer (6) on the right, and adjacent to a portion of the top of the source (11), the top of the P-body (13), and the left section of the top of the low-resistance N-type electron channel (7) from left to right below; the field oxide layer (6) is located on the upper surface of the device, adjacent to the right side of the gate contact region (4) and the right side of the gate oxide layer (3) on the left, adjacent to the left side of the drain contact region (9) on the right, and adjacent to most of the top of the low-resistance N-type electron channel (7) directly below; and the drain (12) is directly below the drain contact region (9).

4. The super junction SOI-LDMOS device according to claim 1, characterized in that: The bottom part of the device: the upper part of the buried oxide layer (15) borders the lower surface of the P-body (13), the lower part of the super junction region and the lower surface of the N-type drift region (14) from left to right, and the lower part borders the upper part of the substrate (16).

5. The super junction SOI-LDMOS device according to claim 3, characterized in that: The material of the gate contact region (4) includes doped polysilicon.

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