System and method for generating a model of a transistor

Abstract

Disclosed are systems and methods for generating a model of a transistor. The method includes initializing hyperparameters; training a neural network based on the hyperparameters and training data that correlates transistor input state values with transistor output state values; determining whether the transistor output state values of the training data match outputs of the neural network; porting the neural network to circuit simulation code to generate a ported neural network; simulating a test circuit using the ported neural network to simulate the behavior of transistors in the test circuit to generate simulation outputs; determining whether a turnaround time for generating the simulation outputs is satisfactory; in response to determining that the turnaround time is unsatisfactory, retraining the neural network based on updated hyperparameters; and in response to determining that the turnaround time is satisfactory, outputting the ported neural network as a model of the transistor.

Description

[0001] This application claims priority to and the benefit of U.S. Provisional Patent Application No. 62 / 831,038, filed in the U.S. Patent and Trademark Office on April 8, 2019, the entire disclosure of which is incorporated herein by reference.

[0002] This application is related to U.S. Patent No. 10,204,188, published on February 12, 2019, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Aspects of embodiments of the present invention relate to the field of semiconductor devices, including systems, methods, and computer programs for designing semiconductor devices and circuits, including modeling transistors of the circuits. Background Art

[0004] Simulating the operation of an electrical circuit typically involves using models of the behavior of the circuit's elements or components (such as the current-voltage (IV) characteristics of various terminals of a transistor). Circuit simulation is a computationally intensive task; for example, a fraction of a second of simulated circuit time can involve hours of real time, where models of various circuit elements are frequently called upon within the circuit simulator's internal loops. Consequently, the execution speed of the circuit element models has a significant impact on the turnaround time for running a circuit simulation. Summary of the Invention

[0005] Aspects of embodiments of the present invention relate to compact, neural network-based models of transistors suitable for incorporation into simulations of electrical circuits.Some aspects of embodiments of the present invention relate to models of transistors that model performance differences due to process variations.

[0006] According to one embodiment of the present invention, a method for generating a model of a transistor includes: initializing, by a computing system, a plurality of hyperparameters that configure the structure of a neural network; training, by the computing system, the neural network based on the plurality of hyperparameters and a plurality of training data that correlates transistor input state values with transistor output state values to calculate a plurality of neural network parameters; determining, by the computing system, whether the transistor output state value of the training data matches the output of the neural network; in response to determining that the transistor output state value does not match the output of the neural network, updating, by the computing system, the plurality of hyperparameters and retraining the neural network based on the updated plurality of hyperparameters; in response to determining that the transistor output state value of the training data matches the output of the neural network, transplanting, by the computing system, the neural network to circuit simulation code to generate a transplanted neural network; simulating a test circuit using the transplanted neural network to simulate the behavior of the transistors of the test circuit to generate a simulation output; determining, by the computing system, whether a turnaround time for generating the simulation output is satisfactory; in response to determining that the turnaround time is unsatisfactory, updating, by the computing system, the plurality of hyperparameters and retraining the neural network based on the updated plurality of hyperparameters; and in response to determining that the turnaround time is satisfactory, outputting the transplanted neural network as a model of the transistor.

[0007] The method may further include simulating a circuit including the transistor, wherein the step of simulating the circuit includes simulating an output of the transistor using the transplanted neural network.

[0008] The neural network may include: an input layer configured to receive transistor input state values; a plurality of hidden layers, the plurality of hidden layers may include: a first hidden layer configured to receive activations from the input layer, and a last hidden layer; an output layer configured to calculate output features from the plurality of activations received from the last hidden layer; and a plurality of conversion functions configured to convert the output features into outputs of the neural network, and the plurality of neural network parameters may include weights and biases that map between adjacent layers of the neural network according to an affine transformation.

[0009] The plurality of hyperparameters may include: the number of the plurality of hidden layers; for each hidden layer, the number of neurons in the hidden layer; and an activation function.

[0010] The step of determining whether the transistor output state value of the training data matches the output of the neural network may include: determining whether the output of the neural network is within a first threshold of the corresponding value of the transistor output state value; and determining whether a first-order derivative of the output of the neural network is within a second threshold of the corresponding value of the first-order derivative of the transistor output state value.

[0011] In response to determining that the output of the neural network is not within a first threshold of the corresponding value of the transistor output state value, the plurality of hyperparameters may be updated to increase the number of the plurality of hidden layers or to increase the number of neurons.

[0012] In response to determining that the first-order derivative of the output of the neural network is not within a second threshold of the corresponding value of the first-order derivative of the transistor output state value, the multiple hyperparameters can be updated to reduce the number of the multiple hidden layers or reduce the number of neurons.

[0013] In response to determining that the turnaround time is unsatisfactory, the plurality of hyperparameters may be updated to reduce the number of the plurality of hidden layers or to reduce the number of neurons.

[0014] The method may further include retargeting the neural network according to a plurality of electrical targets, the retargeting step including updating a plurality of output weights and a plurality of output biases of neural network parameters mapped from a last hidden layer to an output layer to fit the output of the neural network to the plurality of electrical targets, wherein the last hidden layer has fewer neurons than the number of electrical targets.

[0015] The model may capture process variations, and the plurality of training data may include data relating transistor input state values to transistor output state values according to a plurality of process variation corners corresponding to a plurality of process variation sources.

[0016] The method may further include training a plurality of process variation neural networks, each process variation neural network being trained based on training data of a corresponding process variation corner, wherein the transplanted neural network may include the plurality of process variation neural networks.

[0017] The transistor input state value may further include the plurality of process variation sources, and the step of training the neural network may include: performing training based on training data correlating the transistor input state value with the transistor output state value according to the plurality of process variation corners.

[0018] According to one embodiment of the present invention, a system for generating a model of a transistor includes: a processor; and a memory storing instructions that, when executed by the processor, cause the processor to: initialize multiple hyperparameters that configure a structure of a neural network; train the neural network based on the multiple hyperparameters and multiple training data that correlate transistor input state values with transistor output state values to calculate multiple neural network parameters; determine whether the transistor output state values of the training data match the output of the neural network; in response to determining that the transistor output state values do not match the output of the neural network, update the multiple hyperparameters and retrain the neural network based on the updated multiple hyperparameters; in response to determining that the transistor output state values of the training data match the output of the neural network, transplant the neural network to circuit simulation code to generate a transplanted neural network; simulate a test circuit using the transplanted neural network to simulate the behavior of the transistor of the test circuit to generate a simulation output; determine whether the turnaround time for generating the simulation output is satisfactory; in response to determining that the turnaround time is unsatisfactory, update the multiple hyperparameters and retrain the neural network based on the updated multiple hyperparameters; and in response to determining that the turnaround time is satisfactory, output the transplanted neural network as a model of the transistor.

[0019] The memory may also store instructions that, when executed by the processor, cause the processor to simulate a circuit including the transistor by simulating the output of the transistor using the transplanted neural network.

[0020] A neural network may include: an input layer configured to receive transistor input state values; a plurality of hidden layers, the plurality of hidden layers may include: a first hidden layer configured to receive activations from the input layer, and a last hidden layer; an output layer configured to calculate output features from the plurality of activations received from the last hidden layer; and a plurality of transformation functions configured to transform the output features into outputs of the neural network, wherein the plurality of neural network parameters may include weights and biases that map between adjacent layers of the neural network according to an affine transformation.

[0021] The plurality of hyperparameters may include: the number of the plurality of hidden layers; for each hidden layer, the number of neurons in the hidden layer; and an activation function.

[0022] The instructions for determining whether the transistor output state value of the training data matches the output of the neural network may include instructions for determining whether the output of the neural network is within a first threshold of the corresponding value of the transistor output state value; and determining whether a first-order derivative of the output of the neural network is within a second threshold of the corresponding value of the first-order derivative of the transistor output state value.

[0023] The memory may also store instructions that, when executed by the processor, cause the processor to: in response to determining that the output of the neural network is not within a first threshold of the corresponding value of the transistor output state value, update the multiple hyperparameters to increase the number of the multiple hidden layers or increase the number of neurons.

[0024] The memory may also store instructions that, when executed by the processor, cause the processor to: in response to determining that the first-order derivative of the output of the neural network is not within a second threshold of the corresponding value of the first-order derivative of the transistor output state value, update the multiple hyperparameters to reduce the number of the multiple hidden layers or reduce the number of neurons.

[0025] The memory may further store instructions that, when executed by the processor, cause the processor to: in response to determining that the turnaround time is unsatisfactory, update the plurality of hyperparameters to reduce the number of the plurality of hidden layers or reduce the number of neurons.

[0026] The memory may also store instructions that, when executed by the processor, cause the processor to: retarget the neural network according to a plurality of electrical targets, the retargeting step comprising: updating a plurality of output weights and a plurality of output biases of neural network parameters mapped from a last hidden layer to an output layer to fit the output of the neural network to the plurality of electrical targets, wherein the last hidden layer may have fewer neurons than the number of electrical targets.

[0027] The model may capture process variations, and the plurality of training data may include data relating transistor input state values to transistor output state values according to a plurality of process variation corners corresponding to a plurality of process variation sources.

[0028] The memory may further store instructions that, when executed by the processor, cause the processor to: train a plurality of process variation neural networks, each process variation neural network being trained based on training data of a corresponding process variation corner, wherein the transplanted neural network may include the plurality of process variation neural networks.

[0029] The transistor input state value may further include the multiple process variation sources, wherein the memory may further store instructions that, when executed by the processor, cause the processor to: train a neural network based on training data that correlates the transistor input state value with the transistor output state value according to the multiple process variation corners. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The drawings, together with the specification, illustrate exemplary embodiments of the present invention, and, together with the description, serve to explain the principles of the present invention.

[0031] Figure 1 is a schematic block diagram of a neural network for modeling the behavior of a transistor according to one embodiment of the present invention.

[0032] Figure 2 is a flow chart of a method for training a neural network to model a transistor according to one embodiment of the present invention, the method including automatically selecting hyperparameters of the neural network to achieve satisfactory model accuracy and simulation turnaround time.

[0033] Figure 3A is a graph depicting drain current-gate voltage (IV) data from target data (e.g., output from a transistor computer-aided design tool or output from experimental measurements) at different multiple drain voltage biases and corresponding curves calculated by a trained neural network according to one embodiment of the present invention.

[0034] Figure 3B is a graph depicting drain current versus drain voltage (IV) data from target data at different multiple gate voltage biases (from a maximum of 2V to 0.8V with a step size of 0.2V between adjacent curves) and corresponding curves calculated by a trained neural network according to an embodiment of the present invention.

[0035] Figure 4A is a characterization of the transconductance of the target transistor with respect to the gate voltage and is given by Figure 3A and Figure 3B Graph of the corresponding curves calculated by the trained neural network.

[0036] Figure 4B is the output conductance of the target transistor with respect to the drain bias voltage and Figure 3A and Figure 3B Graph of the corresponding curves calculated by the trained neural network.

[0037] Figure 5A 、 Figure 5B 、 Figure 5C and Figure 5D Values predicted by the LUT model and the five neural network models according to the embodiment of the present invention with respect to various output parameters for different driving voltages VDD are shown respectively.

[0038] Figure 6 is a graph depicting turnaround times measured for HSPICE simulations running a 129-stage ring oscillator (RO) using a LUT model and each neural network model according to an embodiment of the present invention.

[0039] Figure 7A is a graph on a logarithmic scale depicting data points corresponding to electrical targets and the output of a neural network model before and after retargeting in accordance with one embodiment of the present invention. Figure 7Bis a graph on a linear scale depicting data points corresponding to electrical targets and the output of the neural network model before and after retargeting in accordance with one embodiment of the present invention.

[0040] Figure 8 FIG. 1 is a schematic diagram of a set of simulation data generated to consider process variations according to an embodiment of the present invention.

[0041] Figure 9 is a schematic block diagram of a neural network according to an embodiment of the present invention, the neural network being used to model the behavior of a transistor and further arranged to receive process variations as input to an input layer.

[0042] Figure 10 is a graph showing ion values in μA / μm for a transistor with a gate length of 40 nm predicted by TCAD simulation and by a neural network trained based on two techniques for modeling process variations according to an embodiment of the present invention. DETAILED DESCRIPTION

[0043] In the following detailed description, only certain exemplary embodiments of the present invention are shown and described by way of illustration. As those skilled in the art will recognize, the invention can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein.

[0044] As mentioned above, circuit simulation is a computationally intensive task, often involving hours or days of simulation time, wherein the execution speed of the models of the individual circuit elements has a significant impact on the turnaround time (TAT) of running the circuit simulation. Because reduced TAT shortens the feedback loop for simulating the performance of any given design, faster circuit simulations also lead to a better experience for both human circuit designers and computer-driven exploration of design choices. Therefore, there is a need for accurate, compact transistor models with fast runtimes for technology benchmarking and circuit design.

[0045] Comparative techniques for modeling circuit components typically use physically derived equations. Such physically based models (e.g., closed-form equations) are typically compact (e.g., have relatively low memory requirements and short execution times) and therefore exhibit good run-time performance in simulations. However, developing physically based model equations requires high expertise (e.g., a deep understanding of semiconductor physics) and associated long turnaround times in developing these physically based models, which limits the use of these techniques for emerging devices (e.g., new transistor designs). Furthermore, the use of human expertise in the process of model parameter extraction makes the process difficult to fully automate.

[0046] Some comparable techniques use lookup tables (LUTs) rather than explicit physics-based equations. However, LUT techniques often exhibit high simulation TAT and convergence issues for large-scale circuits. For example, the simulation TAT can be large because the lookup table may be too large to fit in the computer processor's cache memory (not to mention its registers), and loading the lookup table from main memory for each circuit element at each step of the simulation results in significant delays.

[0047] Some aspects of embodiments of the present invention relate to using a compact modeling method based on an artificial neural network (ANN). Some aspects of embodiments of the present invention relate to methods for automating the development of compact neural network models, methods for re-targeting the developed models, and methods for capturing process variations in the models.

[0048] Thus, using the ability to perform retargeting, aspects of embodiments of the present invention enable faster model development and more efficient model parameter extraction than comparable techniques (compared to physical equation-based methods), as well as better convergence and shorter turnaround times (compared to lookup table-based methods).

[0049] Model development

[0050] One aspect of embodiments of the present invention relates to an automated method for generating compact neural network (NN) based models with high accuracy, robustness and fast simulation turnaround time (TAT). In some embodiments of the present invention, the method includes: initial data preparation and neural network setup, neural network training, model quality checking, model porting (e.g., porting to a language used to implement circuit simulation (such as The Common Model Interface (CMI) or Verilog-A Hardware Description Language (HDL) used with circuit simulators), Specialized Simulation Program for Integrated Circuits (SPICE) simulation verification, and TAT verification.

[0051] Figure 1 FIG. 1 is a schematic block diagram of a neural network for modeling the behavior of a transistor according to an embodiment of the present invention. Figure 1 As shown in FIG, a neural network 100 includes an input layer 110 configured to receive one or more input parameters 112, one or more hidden layers 130, an output layer 150, and one or more transformation functions 170 configured to compute an output 190 from output features 152 of the output layer 150. In general, the neural network 100 takes input parameters corresponding to the state of a transistor (e.g., a voltage bias applied to the terminals of the transistor) and generates an output (e.g., an output current and charge) that represents the behavior of the transistor in the current state.

[0052] In some embodiments, the input parameters 112 include two types: voltage bias (for example, for a 4-terminal field effect transistor (FET), the voltage bias includes the gate-source voltage V GS , drain-source voltage V DS and the body-source voltage V BS ) and device instance parameters (for a typical FET, device instance parameters include gate length L G , FET width W, temperature T, and the number of fins in the case of FinFETs, etc.).

[0053] exist Figure 1 In the particular example neural network shown in FIG, the network's input parameters 112 include transistor input state values, which include gate-source voltage V GS , drain-source voltage V DS , gate length L G , gate width W and temperature T, the output includes the transistor output state value, the transistor output state value includes the drain current I D , gate charge Q G and drain charge Q D .also, Figure 1 The hidden layer 130 of the neural network 100 shown in FIG. 1 includes two layers: a first hidden layer 132 and a second hidden layer 134 .

[0054] According to one embodiment of the present invention, the value x from one layer is mapped to the value of the next layer in a fully connected manner based on an affine transformation of the form Wx+b. For example, the input parameters of the input layer 110 are mapped to the first hidden layer 132 via a first weight W1 and a first bias b1. Similarly, the output of the first hidden layer 132 is mapped to the input of the second hidden layer 134 via a second weight W2 and a second bias b2, and the output of the second hidden layer 134 is mapped to the output layer 150 via a third weight W3 and a third bias b3. In some embodiments of the present invention, an activation function is arranged between the output of the affine function Wx+b and the input of the next layer. Examples of activation functions include rectified linear (ReLU) functions, sigmoid functions, etc. As discussed in more detail below, the specific choice of activation function used between layers can be set as a hyperparameter of the neural network 100.

[0055] Neural networks are generally easier to train when the values propagating between layers are normally distributed with a mean close to zero. Therefore, the output features 152 (y1, y2, y3, ...) of the neural network corresponding to the specific predicted characteristics of the modeled circuit elements generally do not match the units of the physical parameters they model. Moreover, some of the specific output values may be calculated based in part on the specific input parameters 112. Thus, the output features or feature vectors 152 (y1, y2, y3, ...) of the neural network 100 are converted by the conversion function 170 into physically meaningful values representing the behavior of the transistor (e.g., the drain current I D , gate current I G , source current Is, drain charge Q D , gate charge Q G , source charge Q s and body charge Q B ). For example, for the drain current I D The corresponding conversion function 172 mapping the output feature y1 to the predicted drain current in amperes may be:

[0056] I D =exp(y1)·V Ds 1pA

[0057] The specific structure of neural network 100 can be specified by a number of hyperparameters, including the number of hidden layers 130, the number of neurons in each of these hidden layers (each hidden layer can have a different number of neurons), and the choice of activation function between the output of the affine calculation and the input of the next layer. The specific choice of hyperparameters suitable for the network can vary based on, for example, the complexity of the physical properties of the transistor being modeled. However, it is often difficult to predict what set of hyperparameters will produce the best results for the neural network.

[0058] Thus, some aspects of embodiments of the present invention relate to systems and methods for automatically selecting a set of hyperparameters for a neural network used to simulate circuit elements, such as transistors.

[0059] Figure 2 is a flow chart of a method 200 for training a neural network that models a transistor including automatically selecting hyperparameters of the neural network according to one embodiment of the present invention. Figure 2The various operations of the method shown in can be performed by a computing system that includes at least one processor and a memory storing instructions that, when executed by the processor, cause the processor to perform the described operations. Embodiments of the present invention can be implemented in a variety of different computing systems, such as single computers and computer clusters. The computing system may include one or more processors, such as central processing units (CPUs), graphics processing units (GPUs), and other vector processing units. The computing system may also include various types of memory, including multi-level cache memory located on the same die as the processing cores of the processors, dynamic random access memory (DRAM), and persistent mass storage devices (e.g., solid-state flash drives and hard drives).

[0060] In operation 210, the computing system prepares received current-voltage (IV) and charge-voltage (QV) training data for the transistor to be modeled. This training data may be obtained from a transistor simulation tool such as The data may be generated using a technical computer-aided design (TCAD) tool, or may be experimentally measured from one or more manufactured physical devices (e.g., initial data from an early prototype of a device). Data preparation may include cleaning the data and arranging the data into a neural network training platform (such as, or PyTorch). Data preparation may also include separating the data into a training set, a validation set, and a test set. Furthermore, in operation 210, initial hyperparameters of the neural network may be automatically set, for example, based on a set of default values, or may be set to random values within a specified range. (Prior experience with neural network models of similar devices may help select the initial hyperparameters.)

[0061] In operation 220, the computing system trains a neural network model of the transistor based on the supplied training data (e.g., a training set of supplied data), wherein the neural network model has a structure configured based on supplied hyperparameters (e.g., the number of hidden layers, the number of neurons in each hidden layer, etc.). The training is performed by a neural network training platform (e.g., or PyTorch), where techniques such as backpropagation are used to calculate the weights W and biases b of the neural network (e.g., Figure 1 W1, W2, and W3 and b1, b2, and b3 depicted in ), so that the model maps input parameters 112 to outputs 190 in a manner consistent with the training set of data.

[0062] In operation 230, the computing system determines whether the fit between the model and the supplied data is accurate. Typically, this evaluation is performed using a training set / validation set of the supplied data. In the event that the fit between the model and the training set / validation set is inaccurate (e.g., below a threshold accuracy level), then the computing system adjusts the hyperparameters in operation 240. In particular, under this condition ( Figure 2 ), assuming that the previously trained model cannot fit the data because it does not have sufficient dimensions to model the complexity of the underlying physical dynamics of the transistor, the computing system increases the number of hidden layers and / or increases the number of neurons in each hidden layer. The computing system then returns to operation 220 to train a new neural network based on the updated hyperparameters.

[0063] If the fit is found to be sufficiently accurate (e.g., exceeds a threshold level), then in operation 250, the computing system performs a model derivative check to determine whether there is overfitting of the data. For example, in some embodiments, the derivatives (e.g., first-order derivatives) of the IV curve and QV curve generated by the model are compared with the derivatives (e.g., first-order derivatives) of the corresponding curves in the experimental data. If the computing system finds that there is no good match, then the computing system adjusts the hyperparameters in operation 240. In particular, under this condition ( Figure 2 In the example embodiment, labeled “(2)” in the figure), the computing system reduces the number of hidden layers and / or the number of neurons in each hidden layer under the assumption that the previously trained model overfits the data and the model complexity should be reduced (e.g., regularized) to improve performance.

[0064] In some embodiments, the fit accuracy of operation 230 and the model derivative check of operation 250 are automatically performed based on functions integrated into the model training platform. In some embodiments, the fit error is calculated as the square root of the relative error of the model value relative to the target value for each training example. The fit criterion is determined by the requirements of the application of the transistor model (for example, in some embodiments, a criterion of <1% error is used for both IV and QV fits of the transistor).

[0065] If the model derivative check passes in operation 250, then in operation 260, the computing system ports the trained neural network model to circuit simulation code (such as for use with The common model interface (CMI) or Verilog-A hardware description language (HDL) used with a circuit simulator. In one embodiment of the present invention, the parameters of the trained neural network (weights W and biases b of each layer) are copied into a source code file (e.g., a Verilog-A file) as internal variables in a representation of a programming language suitable for the simulator. The corresponding set of equations that implement the neural network is written in the source code file (e.g., a Verilog-A file) to perform neural network calculations (e.g., matrix multiplication and activation functions such as sigmoid functions) according to the stored parameters. (The parameters can be stored in the same file as the equations or in a different file from the equations). The resulting model implemented in the programming language of the simulator takes inputs from the circuit simulator (such as voltage biases and device instance parameters), performs internal calculations based on the neural network parameters, and outputs the terminal current and charge of the device to the circuit simulator.

[0066] In terms of the number of neural network parameters, the size of the model is significantly smaller than the size of a lookup table (LUT). Therefore, the ported neural network model is more compact than corresponding LUT-based techniques for modeling transistors. Furthermore, the more compact size of the neural network-based model according to embodiments of the present invention allows the neural network-based model to fit into, for example, a processor-level cache of a processor and / or one or more vector registers of a processor, thereby allowing faster computation of predicted transistor outputs based on the model without traversing multiple levels of the memory hierarchy of the computing system.

[0067] In operation 270, the computing system runs a simulation of the circuit (e.g., a SPICE simulation), wherein the simulation uses the transplanted neural network model to simulate the behavior of at least one element of the circuit. For example, in the presence of multiple circuit elements of the same type (e.g., multiple transistors of the same type), the simulator can simulate the behavior of each of the circuit elements (e.g., transistors) using the same neural network model. In addition, the simulation can include other neural network models that simulate the behavior of other circuit elements (e.g., different types of transistors). Running the simulation of the electrical circuit can include supplying simulated input voltage and / or current waveforms to a portion of the circuit and calculating simulation results, the simulation results including voltages and / or currents in other portions of the circuit.

[0068] In operation 280, the computing system determines whether the results are satisfactory (e.g., whether the simulated TAT of the benchmark circuit is below the standard provided by the model user). If the results are not satisfactory, the computing system returns to operation 240 to adjust the hyperparameters. In particular, under this condition ( Figure 2(3) in FIG, ), the computing system reduces the number of hidden layers and / or the number of neurons in each hidden layer, assuming that the complexity of the previously trained model should be reduced (e.g., regularized) to improve the simulated TAT. If the results are satisfactory, then in operation 290, the trained model can then be released (e.g., output) for deployment or for further processing according to other aspects of embodiments of the present invention.

[0069] Figure 3A is a graph depicting drain current-gate voltage (IV) data from target data (e.g., output from a transistor computer-aided design tool or output from experimental measurements) at different multiple drain voltage biases and corresponding curves calculated by a trained neural network according to one embodiment of the present invention. Figure 3B is a graph depicting drain current versus drain voltage (IV) data from target data at different multiple gate voltage biases (from a maximum of 2V to 0.8V with a step size of 0.2V between adjacent curves) and corresponding curves calculated by a trained neural network according to one embodiment of the present invention. The target data are shown by circles and the curves calculated by the trained neural network are shown as corresponding shaded lines. Figure 3A In the graph, both the target data and the curve are depicted in both a logarithmic scale (in the target data and the curve on the upper and left-hand side of the graph) and a linear scale (in the target data and the curve on the lower and right-hand side of the graph), while in Figure 3B In the data, the data are shown only on a linear scale. Figure 3A and Figure 3B As seen in , the trained neural network closely and smoothly tracks the target data with a root mean square (RSS) error of less than 0.2%. As described above, this comparison of the output of the neural network with the target data may correspond to the check performed in operation 230.

[0070] A neural network with two hidden layers (15 neurons in the first hidden layer and 10 neurons in the second hidden layer) and a sigmoid activation function between layers was used to generate Figure 3A and Figure 3B The neural network output shown in .

[0071] Figure 4A is a characterization of the transconductance of the target transistor with respect to the gate voltage and is given by Figure 3A and Figure 3B Graph of the corresponding curves calculated by the trained neural network. Figure 4B is the output conductance of the target transistor with respect to the drain bias voltage and Figure 3A and Figure 3BGraph of corresponding curves calculated by the trained neural network at different multiple gate voltage biases (from a maximum of 2V to 0.8V with a step size of 0.2V between adjacent curves). The IV and QV derivatives (transconductance Gm and output conductance Gds) of the neural network model are helpful in detecting potential problems with the model (such as overfitting). To calculate Gm or Gds according to some embodiments of the present invention, the Vg or Vd step size used is smaller than the step size in the target IV data. Figure 4A and Figure 4B As shown in , the derivative of the curve output by this particular trained neural network is smooth and continuous and has a good fit to the target data, so, as described above, this trained neural network will pass the check performed in operation 250.

[0072] In order to measure the performance of the neural network-based method for transistor modeling, several different neural networks were trained using different hyperparameters and a lookup table (LUT) was used to compare the baseline implementation. Specifically, five different neural networks were generated, each with two hidden layers, but with different numbers of neurons in the hidden layers, as shown in Table 1 below.

[0073] Figure 5A 、 Figure 5B 、 Figure 5C and Figure 5D Values predicted by the LUT model and the five neural network models according to the embodiment of the present invention with respect to various output parameters for different driving voltages VDD are shown respectively. Figure 5A plots the predicted switching delays in nanoseconds, Figure 5B plots the predicted leakage power (in arbitrary units), Figure 5C Plot the predicted effective resistance Reff (in arbitrary units), Figure 5D Plot the predicted effective capacitance Ceff (in arbitrary units). Figure 5A 、 Figure 5B 、 Figure 5C and Figure 5D As can be seen in , the values calculated by each of the five models are relatively close, indicating that each model is generally able to calculate reasonably accurate values.

[0074] Figure 6 is a graph depicting the turnaround time (in seconds) measured for HSPICE simulations running a 129-stage ring oscillator (RO) using the LUT model and each neural network model according to an embodiment of the present invention. The turnaround time (TAT) of each simulation run was measured and the error of the results was compared to the baseline LUT model. Figure 6As shown in , simulation runs using the LUT model had turnaround times exceeding 120 seconds, while all simulation runs using the neural network model had turnaround times less than 45 seconds, with smaller networks associated with shorter turnaround times, and the smallest network (number 5, with 3 neurons in each of the two hidden layers) having a turnaround time below 20 seconds. In addition, Figure 6 As shown in Table 1 below, although the error increases with smaller neural networks, the error level remains relatively low until there are 5 neurons in both the first hidden layer and the second hidden layer.

[0075] Table 1:

[0076]

[0077] Thus, using neural networks in transistor models significantly reduces the turnaround time (TAT) for running circuit simulations while maintaining high accuracy relative to models based on comparison techniques, such as lookup tables (LUTs).

[0078] Model Retargeting

[0079] When developing a compact model library for modeling new technologies (e.g., new transistor designs) as described above, a large amount of data for training the models is provided by IV and QV data measured from early hardware or from computer-aided design software. However, this training data may not match the electrical target (ET) of the final design of the circuit elements. Therefore, in some embodiments of the present invention, a selected subset of model parameters is adjusted so that the output of the trained model matches the electrical target (ET). The process of adjusting the parameters of a previously trained model to match the electrical target can be referred to as model retargeting.

[0080] In the case of neural network-based models, simply retraining the neural network to adapt to ET may lead to overfitting due to the limited number of ETs (e.g., due to the small size of the ET dataset). Therefore, some aspects of embodiments of the present invention relate to techniques for retargeting a neural network trained based on ET without causing overfitting.

[0081] One aspect of an embodiment of the present invention relates to constraining Figure 2The hyperparameters of the trained neural network are such that the number of neurons in the final hidden layer is less than the number of ETs (e.g., no more than the number of ETs minus one). (Having more fitting parameters than the number of ETs may lead to under-definition problems.) For example, the initial selection of the hyperparameters in operation 210 may select a number of neurons in the final hidden layer that is less than the number of ETs, and the adjustment of the hyperparameters in operation 240 may ensure that the number of neurons in the final hidden layer is no greater than one less than the number of ETs.

[0082] According to another aspect of an embodiment of the present invention, retargeting of a neural network model 100 trained based on IV and QV data (e.g., from a TCAD model and / or experimental measurements) is performed by adjusting only the learning parameters W and b associated with the output layer of the neural network to match the ET (e.g., from the last hidden layer to the output layer 150, such as from Figure 1 The weights W3 and bias b3 from the second hidden layer 134 to the output layer 150 of the neural network 100 are shown in FIG. 1 . These parameters that map values from the last hidden layer to the output layer may also be referred to as W. output and b output .

[0083] In some embodiments of the present invention, the electrical target includes multiple device instances (e.g., different gate lengths L). Therefore, separate W output and b output The neural network model includes a method for retargeting the same neural network for each device instance to best fit the ET of each device instance. output and b output Parameters are applied as an analytical or table-based model of a function of the device instance.

[0084] Figure 7A is a graph on a logarithmic scale depicting data points corresponding to electrical targets and the output of a neural network model before and after retargeting in accordance with one embodiment of the present invention. Figure 7B is a graph on a linear scale depicting data points corresponding to electrical targets and the output of the neural network model before and after retargeting according to one embodiment of the present invention. The dashed line shows the IV curve calculated by the neural network when fitted to the initial training data. The circles represent the electrical targets for the final design of the transistor. The solid line represents the electrical targets after adjusting W output and b output Parameters to fit the output of the retargeted neural network after ET. Figure 7A and Figure 7BA specific neural network was trained based on TCAD data to model a 3-terminal field effect transistor (FET). The neural network includes two hidden layers, wherein the first hidden layer has a size of 15 neurons, the second hidden layer has a size of 5 neurons, and the total number of parameters is 131. Figure 7A and Figure 7B As shown in , the curve from the retargeted model shows a reasonable shape and does not appear to overfit the data.

[0085] Table 2 below summarizes the various metrics of the modeled transistor, the electrical targets for each of these metrics, the values predicted by the “As fit” model (and the deviation from the electrical targets—in percentages for Ioff, Ilow, Ion, and Idlin, and in millivolts for Vtsat and Vtlin), and the values predicted by the “retargeted” model (and the deviation from the electrical targets—in percentages for Ioff, Ilow, Ion, and Idlin, and in millivolts for Vtsat and Vtlin).

[0086] Table 2

[0087]

[0088]

[0089] Therefore, retargeting according to some embodiments of the present invention may improve the fit between a model trained based on initial TCAD and experimental data and the electrical target of the final design.

[0090] Process variation capture

[0091] Some aspects of embodiments of the present invention relate to capturing process variations (eg, variations in transistor properties that naturally occur when manufacturing integrated circuits).

[0092] According to one aspect of an embodiment of the present invention, in order to evaluate the impact of process variations on transistor characteristics, the first step is to obtain a well-calibrated transistor-level model of a nominal device (e.g., a TCAD simulation platform), wherein the well-calibrated transistor-level model can be controlled to account for one or more sources of process variation (PV). Figure 8 FIG. 1 is a schematic diagram of a set of simulation data generated to take into account process variations according to an embodiment of the present invention. Figure 8 As shown in , a set of N main PV sources (e.g., P1, P2, ..., P N) is identified. Current-voltage (IV) and charge-voltage (QV) data can then be automatically generated by running simulations (e.g., TCAD simulations) of the transistor-level model, where each simulation has the transistors set to the extreme values (e.g., ΔP i =+3σ i Or ΔP = -3σ i ) and all other PV sources are set to 0 (e.g., for j≠i, ΔP j = 0). These situations where one of the PV sources is set to an extreme value will be referred to herein as a PV corner 820. In addition, when all PV sources are set to nominal conditions (for all i, ΔP i =0) 840. This results in a total of 2×N+1 cases. The IV and QV data from the simulation for each of the 2×N+1 cases can then be applied to capture process variations in a compact neural network-based model, as described in more detail below.

[0093] According to one embodiment of the present invention, referred to herein as "Method 1", for each PV corner (e.g., for a given one of the 2×N cases), for example, based on the above Figure 2 In some embodiments of the present invention, all ΔP i = 0 is used according to the nominal Figure 2 The hyperparameters of the neural network are determined, and the same hyperparameters are used to train each of the 2×N cases where one of the PV sources varies.

[0094] When simulating a FET instance with a PV, the values of each PV source in the simulated FET instance are used as model instance parameters. The current and charge at each PV corner are calculated using the corresponding neural network model. The final values of the current and charge for the FET instance are then calculated using methods such as those described in U.S. Patent No. 10,204,188, issued on February 12, 2019, and Wang, Jing et al., “A generic approach for capturing process variations in lookup-table-based FET models.” (2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), IEEE, 2015), the entire disclosures of which are incorporated herein by reference.

[0095] Briefly, in some embodiments, a linear correlation and an exponential correlation are calculated for each PV source.

[0096] The linear dependence can be expressed as follows:

[0097]

[0098] The exponential correlation can be expressed as follows:

[0099]

[0100] Among them, I d0 is the nominal current value, ΔP i is the PV of source i (of number σ) for each model corner instance, and

[0101]

[0102] In general, for a given bias point (Vgs0, Vds0), the voltage with respect to V is measured by extracting the following terms from the lookup table: t Changing I d Dependencies:

[0103] I d (p) = I d (Vgs=Vgs0-ΔVt, Vds=Vds0)

[0104] as well as

[0105] I d (m)=I d (Vgs=Vgs0+ΔVt, Vds=Vds0)

[0106] Additionally, the average value can be calculated:

[0107] I d (ave1)=[I d (p)+I d (m)] / 2

[0108]

[0109] therefore:

[0110]

[0111] Where η = 0 for exponential dependence (e.g., sub-Vt I d ), where η = 1 for linear dependence (e.g., capacitance of metal oxide semiconductors, super-Vt I d ), I d (p) is the drain current of p-type carriers, I d (m) is the drain current of majority carriers.

[0112] Thus, the resulting current I dcan be computed as a linear combination:

[0113] I d =η·I d (lin)+(1-η)·I d (exp)

[0114] or

[0115] I d =β·η·I d (lin)+(1-β·η)·I d (exp)

[0116] Here, β is a parameter that can be set to adjust the smoothness of the IV curve and the QV curve (for example, β=0.6).

[0117] According to another embodiment of the present invention, referred to herein as "Method 2," each process variation (PV) source is added as a neuron to the input layer of the neural network. Figure 9 1 is a schematic block diagram of a neural network according to an embodiment of the present invention, which is used to model the behavior of a transistor and is also arranged to receive process variation as input to the input layer. In the case where one or more process variation inputs (PV1, PV2, PV3, ...) are added to the input layer 110, the neural network model 900 can be used in the same manner as described above with respect to Figure 2 The training is performed in a manner similar to that described for operation 220. For any given set of process variation inputs, the corresponding IV and QV curves generated by transistor-level simulation are used as the corresponding output data (e.g., Figure 9 As shown in I D , Q G and Q D ) to train a single model for all PV corners 820 and the nominal case 840. Thus, when a simulation is run using the modified neural network model 900, the value of each PV is employed as a model instance parameter, and the output of the neural network model is for the current and charge of the transistor with the corresponding PV.

[0118] Figure 10 is a graph showing ion values in μA / μm for a transistor having a length of 40 nm predicted by TCAD simulation and by a neural network trained based on two techniques for modeling process variations according to an embodiment of the present invention. Figure 10 As shown in FIG, both Method 1 and Method 2 are compared with the process variation conditions indicated along the horizontal axis (Tox variation in the range of 1.6 ± 0.1 nm, Lg variation in the range of 40 ± 3 nm, and Nch variation in the range of 5.6 × 10 18The results show that the predictions of the TCAD data for the transistors with the same process variation as those ...

[0119] Thus, aspects of embodiments of the present invention provide systems and methods for compact modeling of transistor behavior, thereby reducing the turnaround time (TAT) for performing simulations of circuits while maintaining high accuracy of the predicted behavior of the modeled transistors.

[0120] While the invention has been described with reference to the specific exemplary embodiments, it will be understood that the invention is not limited to the disclosed embodiments, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims and their equivalents.

Claims

1. A method for generating a model of a transistor, the method comprising: Initialize multiple hyperparameters that configure the structure of the neural network; Training a neural network based on the plurality of hyperparameters and a plurality of training data relating transistor input state values to transistor output state values to calculate a plurality of neural network parameters; determining whether the transistor output state values of the training data match the outputs of the neural network; In response to determining that the transistor output state value does not match the output of the neural network, updating the plurality of hyperparameters and retraining the neural network based on the updated plurality of hyperparameters; In response to determining that the transistor output state values of the training data match the output of the neural network, transplanting the neural network to the circuit simulation code to generate a transplanted neural network; simulating the test circuit using the transplanted neural network to simulate behavior of transistors of the test circuit to generate simulation output; determining whether a turnaround time for generating simulation output is less than a predetermined threshold; In response to determining that the turnaround time is not less than a predetermined threshold, updating the plurality of hyperparameters and retraining the neural network based on the updated plurality of hyperparameters; as well as In response to determining that the turnaround time is less than a predetermined threshold, outputting the transplanted neural network as a model of a transistor, The step of determining whether the transistor output state value of the training data matches the output of the neural network includes: determining whether an output of the neural network is within a first threshold range of a corresponding value of a transistor output state value; and A determination is made as to whether a first-order derivative of the output of the neural network is within a second threshold range of a corresponding value of the first-order derivative of the transistor output state value.

2. The method according to claim 1, further comprising: A circuit including a transistor is simulated, wherein the step of simulating the circuit including the transistor includes simulating an output of the transistor using the transplanted neural network.

3. The method according to claim 1, wherein Neural networks include: An input layer configured to receive transistor input state values; Multiple hidden layers, including: a first hidden layer configured to receive activations from the input layer; and The last hidden layer; an output layer configured to compute output features from a plurality of activations received from the last hidden layer; and Multiple transformation functions are configured to transform the output features into the output of the neural network, The plurality of neural network parameters include weights and biases for mapping between adjacent layers of the neural network according to an affine transformation.

4. The method according to claim 3, wherein: The multiple hyperparameters include: The number of hidden layers; The number of neurons in each hidden layer; and Activation function.

5. The method according to claim 1, wherein In response to determining that the output of the neural network is not within a first threshold range of corresponding values of the transistor output state values, the plurality of hyperparameters are updated to increase the number of hidden layers or increase the number of neurons.

6. The method according to claim 1, wherein In response to determining that the first-order derivative of the output of the neural network is not within a second threshold range of the corresponding value of the first-order derivative of the transistor output state value, the plurality of hyperparameters are updated to reduce the number of hidden layers or reduce the number of neurons.

7. The method according to claim 1, wherein In response to determining that the turnaround time is not less than a predetermined threshold, the plurality of hyperparameters are updated to reduce the number of hidden layers or to reduce the number of neurons.

8. The method according to claim 3, further comprising: Retargeting the neural network according to multiple electrical targets. The retargeting steps include: updating a plurality of output weights and a plurality of output biases of the neural network parameters mapped from the last hidden layer to the output layer to fit the output of the neural network to the plurality of electrical targets, Among them, the last hidden layer has neurons that are smaller than the number of electrical targets.

9. The method according to claim 1, wherein The model captures process variations, and The plurality of training data include data for correlating transistor input state values with transistor output state values according to a plurality of process variation corners corresponding to a plurality of process variation sources.

10. The method according to claim 9, wherein: The method further comprises: training a plurality of process variation neural networks, each process variation neural network being trained based on training data of a corresponding process variation corner, The transplanted neural network includes the multiple process-varied neural networks.

11. The method according to claim 9, wherein The transistor input state value includes the plurality of process variation sources, and The step of training the neural network includes: performing training based on training data that correlates transistor input state values with transistor output state values according to the plurality of process variation corners.

12. A system for generating a model of a transistor, the system comprising: processor; as well as A memory storing instructions that, when executed by a processor, cause the processor to: Initialize multiple hyperparameters that configure the structure of the neural network; Training a neural network based on the plurality of hyperparameters and a plurality of training data relating transistor input state values to transistor output state values to calculate a plurality of neural network parameters; determining whether the transistor output state values of the training data match the outputs of the neural network; In response to determining that the transistor output state value does not match the output of the neural network, updating the plurality of hyperparameters and retraining the neural network based on the updated plurality of hyperparameters; In response to determining that the transistor output state values of the training data match the output of the neural network, transplanting the neural network to the circuit simulation code to generate a transplanted neural network; simulating the test circuit using the transplanted neural network to simulate behavior of transistors of the test circuit to generate simulation output; determining whether a turnaround time for generating simulation output is less than a predetermined threshold; In response to determining that the turnaround time is not less than a predetermined threshold, updating the plurality of hyperparameters, and retraining the neural network based on the updated plurality of hyperparameters; as well as In response to determining that the turnaround time is less than a predetermined threshold, outputting the transplanted neural network as a model of a transistor, The instructions for determining whether the transistor output state value of the training data matches the output of the neural network include instructions for the following operations: determining whether an output of the neural network is within a first threshold range of a corresponding value of a transistor output state value; and A determination is made as to whether a first-order derivative of the output of the neural network is within a second threshold range of a corresponding value of the first-order derivative of the transistor output state value.

13. The system according to claim 12, wherein: The memory also stores instructions that, when executed by the processor, cause the processor to simulate a circuit including the transistor by simulating an output of the transistor using the transplanted neural network.

14. The system according to claim 12, wherein: Neural networks include: An input layer configured to receive transistor input state values; Multiple hidden layers, including: a first hidden layer configured to receive activations from the input layer; and The last hidden layer; an output layer configured to compute output features from a plurality of activations received from the last hidden layer; and Multiple transformation functions are configured to transform the output features into the output of the neural network, Among them, neural network parameters include weights and biases that map between adjacent layers of the neural network according to affine transformations.

15. The system according to claim 14, wherein: The multiple hyperparameters include: The number of hidden layers; The number of neurons in each hidden layer; and Activation function.

16. The system of claim 12, wherein: The memory also stores instructions that, when executed by the processor, cause the processor to: in response to determining that the output of the neural network is not within a first threshold range of the corresponding value of the transistor output state value, update the multiple hyperparameters to increase the number of hidden layers or increase the number of neurons.

17. The system of claim 12, wherein: The memory also stores instructions that, when executed by the processor, cause the processor to: in response to determining that the first-order derivative of the output of the neural network is not within a second threshold range of the corresponding value of the first-order derivative of the transistor output state value, update the plurality of hyperparameters to reduce the number of hidden layers or reduce the number of neurons.

18. The system of claim 12, wherein: The memory further stores instructions that, when executed by the processor, cause the processor to: in response to determining that the turnaround time is not less than a predetermined threshold, update the plurality of hyperparameters to reduce the number of hidden layers or reduce the number of neurons.

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