Method for driving an electronic switch in a power converter and power converter

Abstract

A method for driving an electronic switch in a power converter and a power converter are disclosed. The method comprises: driving an electronic switch (1) coupled to an inductor (2) in the power converter, wherein driving the electronic switch (1) comprises driving a drive signal (S DRV ) drives the electronic switch (1) in a plurality of drive cycles. Driving the electronic switch (1) in at least one drive cycle in the plurality of drive cycles comprises: determining a current (I 1 )’s expected duration (T ON_DES ); and according to the expected duration (T ON_DES ) and the delay time (T DEL ) to adjust the drive signal (S DRV ) of the conduction level (T DRV ). Delay time (T DEL ) is the driving signal (S DRV ) is the duration between a first moment (t1) when the on-level changes to the off-level and a second moment (t2) when the current through the electronic switch (1) drops below a predefined threshold.

Description

Technical Field

[0001] The present disclosure relates generally to driving electronic switches in power converter circuits and to power converter circuits. Background Art

[0002] Switching mode power converter circuits are widely used to convert power in various electronic applications such as automotive applications, industrial applications, telecommunication applications, home or consumer electronic applications. A switching mode power converter may include an electronic switch, an inductor coupled to the electronic switch, and a rectifier circuit coupled to the inductor. Converting power by this type of switching mode power converter typically includes driving the electronic switch in a plurality of consecutive drive cycles, each of the plurality of consecutive drive cycles including an on-time and an off-time, wherein the inductor receives energy from an input terminal during the on-time and transfers energy to the rectifier circuit during the off-time. An output parameter of the power converter, such as an output voltage or an output current, may be adjusted by appropriately adjusting the duration of the on-time and the off-time.

[0003] Driving the electronic switch may include driving the electronic switch by a drive signal received at a drive input of the electronic switch, wherein the drive signal has an on-level for turning on the electronic switch or an off-level for turning off the electronic switch. However, for various reasons, the duration of the on-level of the drive signal is not necessarily equal to the duration of the current flowing through the inductor and magnetizing the inductor. The parasitic output capacitance of the electronic switch may, for example, cause a deviation of the magnetization period from the desired magnetization period defined by the drive signal. When the electronic switch is turned off, for example, when the transistor device is in a transition phase from an on state to an off state, the parasitic output capacitance is charged. Such charging of the output capacitance causes the current through the inductor to continue until the parasitic output capacitor has been charged. In some cases, the energy additionally stored in the inductor in the transition phase from the on state to the off state is largely independent of the duration of the on time and may cause problems when adjusting the output parameters. Especially in a power converter with PFC (power factor correction), such a delay time caused by the parasitic output capacitance of the electronic switch may cause problems such as significant THD (total harmonic distortion). Summary of the invention

[0004] One example relates to a method. The method includes driving an electronic switch coupled to an inductor in a power converter, wherein driving the electronic switch includes driving the electronic switch in a plurality of drive cycles by a drive signal, wherein driving the electronic switch in at least one of the plurality of drive cycles includes determining a desired duration of a current through the switch, and adjusting a duration of an on-level of the drive signal according to the desired duration and a delay time obtained in a previous drive cycle. The delay time is a duration between a first moment when the drive signal changes from an on-level to an off-level in the previous drive cycle and a second moment when the current through the electronic switch drops below a predefined threshold.

[0005] Another example relates to a power converter. The power converter includes an electronic switch coupled to an inductor and a control circuit configured to drive the electronic switch in a plurality of drive cycles by a drive signal. The control circuit is configured to, in at least one drive cycle of the plurality of drive cycles: determine an expected duration of a current through the switch, and adjust the duration of an on-level of the drive signal according to the expected duration and a delay time obtained in a previous drive cycle. The delay time is a duration between a first moment when the drive signal changes from an on-level to an off-level and a second moment when the current through the electronic switch drops below a predefined threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The following examples are described with reference to the accompanying drawings. The accompanying drawings are used to illustrate certain principles so that only aspects necessary for understanding these principles are shown. The accompanying drawings are not drawn to scale. In the accompanying drawings, the same reference numerals represent similar features.

[0007] Figure 1 schematically illustrates an example of a power converter circuit including an inductor and an electronic switch coupled to the inductor;

[0008] FIG. 2A to FIG. 2C An example of an electronic switch implemented as a superjunction transistor device is shown;

[0009] Figure 3 An example of waveforms showing a drive signal of an electronic switch and a current passing through the electronic switch;

[0010] Figure 4 shows the magnitude of the input voltage of the power converter circuit vs. Figure 3 The relationship between the duration of the delay times shown;

[0011] Figure 5 An example of a method for driving an electronic switch is shown, wherein the method includes time delay compensation;

[0012] Figure 6Shows that when Figure 5 The waveforms of the driving signal of the electronic switch and the current passing through the switch when the method shown operates the electronic switch;

[0013] Figure 7 shows (after the power converter circuit is started) in the first drive cycle and the second drive cycle according to Figure 5 and Figure 6 The waveform of the method;

[0014] Figure 8 shows signal waveforms of a drive signal, a current through a switch, and a ramp signal, which shows an example for implementing time delay compensation;

[0015] Fig. 9 shows a signal waveform, which shows Figure 8 A modification of the method shown in ;

[0016] Fig.10 An example of a power converter circuit implemented as a boost converter is shown;

[0017] Fig.11 One example of a power converter circuit implemented as a flyback converter is shown;

[0018] Fig.12 shows that during operation Fig.10 and Fig.11 a signal waveform of a signal appearing in one of the power converters shown;

[0019] Fig.13 According to an example Fig.10 and Fig.11 A block diagram of the control circuit shown; and

[0020] Figures 14 to 17 shows a signal waveform, which shows the signal waveform according to Figure 5 Another example of the method. DETAILED DESCRIPTION

[0021] In the following detailed description, reference is made to the accompanying drawings. The accompanying drawings form a part of the specification and, for illustrative purposes, show examples of how the invention may be used and implemented. It should be understood that the features of the various embodiments described herein may be combined with each other unless otherwise specifically noted.

[0022] Figure 1 An example of a power converter circuit is schematically shown. The power converter circuit is configured to receive an input voltage V at input terminals 31, 32. IN and input current I IN , and provides an output voltage V at outputs 33, 34OUT and output current I OUT The power converter can be configured to regulate an output parameter, such as the output voltage V OUT , output current I OUT or output power (output power is determined by output voltage V OUT Multiply the output current I OUT Given), so that the output parameter has a predefined value. In addition, the power converter can be configured to regulate the input current I IN This is explained in further detail below.

[0023] Reference Figure 1 The power converter includes a switching stage I connected to input terminals 31, 32 and a rectifier stage II connected between the switching stage I and output terminals 33, 34. The switching stage I includes an electronic switch 1 and an inductor 2 coupled to the electronic switch 1. The electronic switch 1 is driven by a drive signal S received at a drive input terminal of the electronic switch 1. DRV Control, so that the electronic switch 1 according to the driving signal S DRV According to one example, the inductor 2 is connected in series with the load path of the electronic switch 1, so that the same current I1 flows through the electronic switch 1 and the inductor 2. The electronic switch 1 is configured to DRV When the electronic switch 1 is turned on (ie, when the drive signal S DRV The driving electronic switch 1 is in the on state) and is configured to conduct current when the driving signal S DRV When the electronic switch 1 is turned off (ie, when the drive signal S DRV The driving electronic switch 1 is blocked when it is in the off state.

[0024] Any kind of electronic switch can be used to implement Figure 1 An electronic switch 1 in a power converter circuit is shown. According to one example, the electronic switch 1 is implemented as a transistor device. Figure 2A shows the circuit symbol, Figure 2B A vertical cross-sectional view of an example of a transistor device is shown, and Figure 2C Shows Figure 2B A detail of a transistor device is shown. Figure 2B , the transistor device includes a semiconductor body 100 and a plurality of transistor units 10 integrated in the semiconductor body 100. Figure 2C , which shows one transistor cell 10 in more detail, each transistor cell 10 includes a drift region 11, a body region 13, a source region 14 and a drain region 15. The body region 13 is arranged between the drift region 11 and the source region 14, and the drift region 11 is arranged between the body region 13 and the drain region 15. Figure 2B and Figure 2CThe transistor device shown is a superjunction transistor device. In this case, each transistor cell 10 further comprises a compensation region 12 adjoining the drift region 11 and the body region 13 and extending from the body region 13 along the drift region 11 towards the drain region 15 .

[0025] like Figure 2B and Figure 2C As shown, the transistor device can be implemented as a vertical transistor device, so that the source region 14 of each transistor cell 10 is spaced apart from the drain region 15 in the vertical direction of the semiconductor 100. The "vertical direction" is a direction perpendicular to the first surface 101 and the opposite second surface 102 of the semiconductor body 100. However, implementing the transistor device as a vertical transistor device is only an example transistor device. The transistor device can also be implemented as a lateral transistor device, in which the source region 14 of each transistor cell 10 is spaced apart from the drain region 15 in the lateral direction of the semiconductor 100. The "lateral direction" is a direction parallel to the first surface 101 and the second surface 102.

[0026] Reference Figure 2B and Figure 2C Each transistor cell 10 further includes a gate electrode 16, which is arranged adjacent to the body region 13 and is dielectrically insulated from the body region 13 by a gate dielectric 17. The gate electrode 16 is used to control a conductive channel in the body region 13 between the source region 14 and the drift region 11. For illustration purposes only, Figure 2B and Figure 2C In the example shown, the gate electrode 16 is a planar electrode arranged above the first surface 101 of the semiconductor body 100 . However, this is only an example. The gate electrode may also be implemented as a trench electrode arranged in a trench extending from the first surface 101 into the semiconductor body 100 .

[0027] Reference Figure 2B , the gate electrode 16 of each transistor cell is connected to the gate node G, and the body region 13 and the source region 14 of each transistor cell 10 are connected to the source metallization layer 18, wherein the source metallization layer 18 forms a source node or is connected to the source node S. In addition, the drain region 15 of each transistor cell 10 is connected to the drain node D of the transistor device. Figure 2B , the drain regions 15 of the plurality of transistor cells 10 may be formed by one common doped semiconductor region, and the drift regions 11 of the plurality of transistor cells 10 may be formed by one common doped semiconductor region. In addition, the compensation region 12, the body region 13 and the source region 14 of two or more adjacent transistor cells 10 may be formed by one corresponding semiconductor region.

[0028] The transistor device can be implemented as an n-type transistor device ( Figure 2A The circuit symbol shown represents an n-type transistor device) or a p-type transistor device. In the n-type transistor device, the source region 14, the drift region 11 and the drain region 15 are n-type semiconductor regions, and the body region 13 and the compensation region 12 are p-type semiconductor regions. In the p-type transistor device, the doping type of each semiconductor region is complementary to the doping type of the corresponding semiconductor region in the n-type transistor device.

[0029] exist FIG. 2A to FIG. 2C In a transistor device of the type shown, the driving input is formed by a gate node G and a source node S, wherein the transistor device is turned on or off according to the voltage level of the driving voltage received between the gate node G and the source node S. That is, when Figure 1 When the electronic switch 1 shown is implemented as a transistor device, the drive signal S DRV is the voltage between the gate node G and the source node S (where this voltage is usually referred to as the gate-source voltage). The load path of the transistor device is the internal path between the drain node D and the source node S. When the driving voltage S DRV When the driving voltage S is higher than the threshold voltage of the transistor device, the transistor device is in the on state, and when the driving voltage S DRV Below the threshold voltage, the transistor device is in the off state. For example, in an n-type transistor device, the threshold voltage is a positive voltage.

[0030] When the transistor device is in the on state, a conductive channel exists in the body region 13 between the source region 14 and the drift region 11 of each transistor cell 10, so that current can flow between the drain node D and the drain node S through the transistor device. In the off state, the conductive channel in the body region 13 is interrupted, so that current flow between the drain node D and the source node S is prevented (when the drain-source voltage V applied between the drain node D and the source node S is DS The polarity of the drift region 11 makes the pn junction between the drift region 11 and the body region 13 reverse biased). The drift region 11 and the body region 13 of each transistor unit 10 and mainly the drift region 11 and the compensation region 12 form a junction capacitance. The junction capacitance is composed of Figure 1 The load path of the electronic switch 1 is shown as a capacitor C1 connected in parallel. When the electronic switch 1 is turned off and the drain-source voltage V DS When the junction capacitance increases, the junction capacitance is charged, and when the electronic switch 1 is turned on again, the junction capacitance is discharged.

[0031] operate Figure 1A power converter of the type shown may comprise driving the electronic switch 1 in a plurality of consecutive drive cycles, wherein each drive cycle comprises switching on the electronic switch 1 for a predefined duration. In order to be able to accurately regulate a desired output parameter of the power converter, such as the output current I OUT , output voltage V OUT or output power, it is important to be able to accurately control the duration of the current flowing through the electronic switch 1. By controlling the current I1 through the electronic switch 1, the instantaneous input power of the power converter can be controlled, wherein by controlling the instantaneous input power, one of the output parameters can be controlled. The large output capacitance of the electronic switch 1, such as the large output capacitance that is inevitably present in a superjunction transistor device, may hinder the accurate control of the duration of the current flow. Figure 3 Explain it.

[0032] Figure 3 The driving signal S is schematically shown DRV And the signal waveform of the current I1 passing through the electronic switch 1. The drive signal S DRV has an on-level for turning on the electronic switch 1 or an off-level for turning off the electronic switch 1. For illustration purposes only, Figure 3 In the example shown, the on-level is a high signal level, and the off-level is a low signal level. Figure 3 Two consecutive drive cycles are shown, wherein in each of these drive cycles, the drive signal S DRV Has a conduction level for a predefined duration T DRV . The driving signal S DRV The duration T of the conduction level DRV During this period, and in addition, the drive signal S DRV The delay time T after the signal level has changed from the on level to the off level DEL During this time, a current different from zero flows through the electronic switch 1. It should be noted that Figure 3 The driving signal S is schematically shown DRV The relationship between the current I1 passing through the electronic switch 1. In fact, when the drive signal S DRV There is a (short) delay time between the moment when the signal level of changes from the off level to the on level and the moment when the current I1 through the electronic switch 1 starts to flow. However, this delay time is Figure 3 Not shown in FIG.

[0033] The current I1 is driven by the signal S DRV The delay time T after the current has changed to the off level DEL It is generated by charging the output capacitor C1. That is, when the driving signal S DRVWhen the signal level of changes from the on level to the off level, the electronic switch 1 is turned off, but the current I1 through the electronic switch 1 continues to flow and charges the output capacitor C1. For example, in a super junction transistor device, the capacitance value of the output capacitor C1 depends on the drain-source voltage V DS , and as the drain-source voltage V DS For example, in modern superjunction transistor devices, as the drain-source voltage V increases from 0 V to about 30 V, the capacitance value of the output capacitor decreases by more than two orders of magnitude, where the voltage blocking capability can be hundreds of volts, such as 600 V or 800 V. Therefore, when the electronic switch 1 is implemented with a superjunction transistor device, the current through the electronic switch 1 (and the inductor 2) essentially continues to flow until the drain-source voltage V DS A voltage level has been reached at which the capacitance value of the output capacitor drops significantly.

[0034] Because the current through the electronic switch 1 continues to flow for a delay time T DEL It is caused by charging the output capacitor C1, so the delay time T DEL The duration depends on the drive signal S DRV The magnitude of the current I1 after it has changed to the off level. Basically, the drive signal S DRV The smaller the amplitude of the current I1 when changing to the off level, the longer the delay time T DEL The longer. Figure 3 is shown in Figure 3 The dotted line area represents the delay time T DEL The charge stored in the output capacitor C1 during the current I1 flows. This charge is substantially the same in each driving cycle and substantially depends on the capacitance value of the output capacitor C1.

[0035] exist Figure 3 In the example shown, the drive signal S DRV After turning on the electronic switch 1, the switch current I1 increases substantially linearly. This can be achieved by connecting the inductor 2 in series with the electronic switch 1 and by connecting the series circuit including the inductor 2 and the electronic switch 1 between the first input node 31 and the second input node 32 of the input terminals 31, 32. In this case, the slope (dI1 / dt) of the switch current I1 is substantially proportional to the input voltage V IN Proportional (dI1 / dt≈V IN / L, where L is the inductance of the inductor 2). In this case, when the drive signal S DRV The conduction level for a given duration T DRV Under the driving signal S DRVThe current level of the switch current I1 at the moment when it changes from the on level to the off level depends on the input voltage V IN , and therefore, the current level after this moment depends on the input voltage V IN Therefore, in this case, the duration of the delay time T DEL Depends on the input voltage V IN .

[0036] This is Figure 4 As schematically shown in Figure 4 shows the variation of input voltage V IN and the delay time duration T DEL The corresponding changes. Figure 4 It can be seen that the delay time duration T DEL With the input voltage V IN For illustration purposes only, Figure 4 The input voltage V IN is one half cycle of the sinusoidal voltage. The frequency of the sinusoidal voltage is, for example, 50 Hz or 60 Hz. In addition, the switching frequency, i.e. the frequency of the generated drive cycle, is higher than 10 kHz, so that Figure 4 Hundreds of drive cycles can be generated in the time period shown.

[0037] The delay time during which the switch current I1 continues to flow may cause serious problems, especially in a power converter receiving an AC input voltage such as a sinusoidal input voltage or a rectified sinusoidal input voltage. Therefore, it is necessary to adjust the duration T of the current I1 flowing through the electronic switch 1 accurately. ON (=T DRV +T DEL ) method to drive the electronic switch 1. Figure 5 An example of a method suitable for driving an electronic switch in this manner is shown in .

[0038] Figure 5 FIG. 1 is a flow chart showing an example of a method for driving an electronic switch 1. Figure 5 The method includes (see 201) determining a desired duration T of the current flow through switch 1 ON_DES (See Figure 5 201 in the following). In the following, the duration T ON_DES The method further includes (see 202) determining the desired current flow duration T according to the desired current flow duration T. ON_DES and the duration T of the delay time obtained in the previous drive cycle DEL To adjust the drive signal S DRV The duration of the conduction level T DRV, where the delay time is the driving signal S DRV The time between a first moment when the on-level changes to an off-level and a second moment when the current I1 through the switch 1 drops below a predefined threshold. DRV The duration of the conduction level T DRV It is called the conduction level duration T DRV , and in the following the duration of the delay time T DEL It is called the delay time duration.

[0039] Refer to the following Figure 6 Description Figure 5 method. Figure 6 It shows that in two consecutive driving cycles i-1, i based on the driving signal S DRV To drive the electronic switch 1. In each of these drive cycles, the drive signal S DRV At the predefined conduction level duration T DRV The drive signal changes from the on level to the off level at the first moment t1; and the delay time duration T after the first moment DEL The internal switch current I1 continues to flow. The delay time duration T DEL The process ends at a second instant t2 when the switch current I1 drops below a predefined threshold. Figure 6 In the figure, t0 represents when each driving cycle starts, that is, when the driving signal S DRV The moment when the off level changes to the on level, and T ON represents the duration of current flow. In addition, i-1 represents Figure 6 The first drive cycle of the two drive cycles shown, and i represents Figure 6 The second drive cycle in the drive cycle shown, wherein the second drive cycle follows the first drive cycle. Equivalently, (i-1) represents the duration and time associated with the first drive cycle i-1, and (i) represents the duration and time associated with the second drive cycle i.

[0040] Reference Figure 5 and Figure 6 The method comprises: determining a desired current flow duration T in the second drive cycle i ON_DES (i) Determine the delay time duration T in the first driving cycle i-1 DEL (i-1), and according to the desired on-time duration T ON_DES (i) and the determined delay time duration T in the first drive cycle i DEL (i-1) to adjust the conduction level duration T in the second driving cycle i DRV(i). According to one example, the conduction level duration T in a driving cycle i DRV (i) The expected current flow duration T in the driving cycle ON_DES (i) Subtract the delay time duration T in the previous drive cycle i-1 DEL (i-1) is given.

[0041] T DRV (i) = T ON_DES (i)-T DEL (i-1) (1a)

[0042] The “previous driving cycle” may be the period immediately preceding the period in which the conduction level duration T is to be adjusted. DRV (i) is a drive cycle before the drive cycle i, or may be a drive cycle before the drive cycle immediately before the drive cycle, so that

[0043] T DRV (i) = T ON_DES (i)-T DEL (in) (1b)

[0044] Wherein n is an integer greater than 0 (n>0).

[0045] The delay time duration T can be determined in each drive cycle DEL , and in the subsequent drive cycle a delay time duration T can be used DEL To adjust the conduction level flow duration T DRV However, it is also possible to determine the delay time duration T in less than every drive cycle. DEL and use the delay time duration T determined in one drive cycle DEL Based on the same delay time duration T DEL and respective current flow durations adjust the conduction level durations in two or more driving cycles.

[0046] Reference Figure 6 , the current flow duration T in the second driving cycle i ON (i) is basically determined by the conduction level duration T in the second driving cycle i DRV (i) Add the delay time duration T DEL (i) is given by the current flow duration T ON (i) Substantially equal to the expected current flow duration T ON_DES (i) because, for the reasons outlined below, it can be assumed that the delay time duration T in the second drive cycle i DEL (i) Substantially equal to the delay time duration T in the previous drive cycleDEL (i-1)(or T DEL (in)), that is, T DEL (i)≈T DEL (i-1)(T DEL (i)≈T DEL (in)).

[0047] The delay time duration can depend on the input voltage V IN , but may also depend on other parameters. It can be assumed that these parameters influencing the duration of the delay time vary slowly relative to the duration of one drive cycle and that the desired current flow duration T ON_DES (at least in the steady state of the power converter) varies at most slightly from drive cycle to drive cycle. Based on this, it can be assumed that the delay time duration T DEL It varies at most slightly from drive cycle to drive cycle. Therefore, by ON_DES (i) and the delay time duration T in the previous driving cycle i-1 (in) DEL (i-1)(T DEL (in)) adjusts the conduction level duration T in a driving cycle i DRV (i) Allow current to flow for a duration of T ON (i) basically reach the desired current flow duration T ON_DES (i) Significant errors may occur only during the initial drive cycle.

[0048] Reference Figure 7 , in the initial drive cycle 1, the conduction level duration T can be adjusted DRV (1), so that it is equal to the desired current flow duration T ON_DES (1). In this case, the switching current is kept constant for the desired current flow duration T ON_DES (1) Add the delay time duration T DEL (1) - which is longer than expected - flows during. However, in the second drive cycle 2, the delay time duration T determined in the first drive cycle 1 is taken into account. DEL (1) To adjust the conduction level duration T DRV (2) so that the conduction level duration T DRV (2) The desired current flow duration T ON_DES (2) Subtract the delay time duration T obtained in the first drive cycle 1 DEL (1) is given. Assuming that the delay time duration T in the second driving cycle DEL (2) substantially equal to the delay time duration T in the first drive cycle 1 DEL(1), then the current flow duration T in the second driving cycle is ON (2) Substantially equal to the expected current flow duration T ON_DES (2).

[0049] Figure 8 An example of a method for determining the delay time duration T in a driving cycle is shown. DEL , and adjust the conduction level duration T based on the desired current flow duration and the delay time duration determined in the continuous driving cycle DRV . Figure 8 The driving signal S is schematically shown DRV , a timing diagram of the switch current I1 and the ramp signal RS, wherein the ramp signal RS is used to determine the delay time duration T DEL And adjust the conduction level duration T DRV . Figure 8 It is shown that the electronic switch 1 is driven in three consecutive driving periods i-1, i, i+1.

[0050] Reference Figure 8 , at the first moment t1 in each drive cycle starting with the starting value (initial value) RS0, the ramp signal RS starts to increase. The initial value RS0 is, for example, zero (0). According to one example, the slope of the ramp signal RS is predefined and fixed. In addition, the ramp signal RS stops increasing at the second moment t2, remains at the level reached by increasing between the first moment t1 and the second moment t2, and at the beginning t0 of the new drive cycle, that is, when the drive signal S DRV When changing from the off level to the on level, it further increases until the ramp signal RS reaches the ramp signal threshold RS TH When the ramp signal RS reaches the threshold RS at the first moment t1 TH When the ramp signal RS reaches the threshold RS0, it is quickly reset to the starting value RS0 and starts to increase again until the switch current I1 drops below the predefined threshold at the second time t2. TH The moment at time defines the first moment t1 in each cycle i.

[0051] exist Figure 8 In the method shown, the slope of the ramp signal RS and the threshold signal RS TH The expected current flow duration is defined as follows: ON Basically it is given by:

[0052]

[0053] Among them, m RS=dRS(t) / dt represents the slope of the ramp signal RS. In this method, the ramp signal RS in each driving cycle starts to increase at the first time t1 with the starting value RS0. In each driving cycle, during the delay time duration T DEL At the end, the signal level of the ramp signal RS is higher than the initial value RS0 by ΔRS1, where ΔRS1 is proportional to the delay time duration T DEL In the next driving cycle, the ramp signal RS increases from the signal level RS0+ΔRS1 to the threshold RS TH The duration taken is proportional to the value ΔRS2, which passes the threshold RS TH Subtract the ramp signal RS during the delay time duration T DEL The signal level at the end is given by RS0+ΔRS1, ΔRS2=RS TH -(RS0+ΔRS1). Therefore, the delay time duration T DEL The longer the ramp signal RS is, the longer the delay time T DEL The higher the signal level RS0+ΔRS1 reached at the end, the longer the conduction level duration T in the next drive cycle. DRV The shorter.

[0054] Reference Figure 8 , when the ramp signal RS reaches the threshold RS TH Afterwards, the ramp signal RS is reset to the starting value RS0. Referring to the above, the ramp signal RS reaches the threshold RS TH The moment defines the first moment t1 in each cycle i. At the first moment t1, the driving signal S DRV From the on level to the off level, the delay time duration T DEL To be able to accurately determine the delay time duration T by using the ramp signal RS DEL , it is important that when the ramp signal RS reaches the threshold RS TH The ramp signal RS is then quickly reset to the initial value RS0. The ramp signal RS may be generated in various ways.

[0055] According to one example, the ramp signal RS is generated using a digital counter that counts according to a clock signal, wherein the ramp signal is a counter reading of the digital counter. Such a counter can be quickly reset, so that the digital counter can be used to easily generate Figure 8 A ramp signal RS of the type shown.

[0056] According to another example, a capacitor charged by a current source may be used to generate the ramp signal RS, where the ramp signal RS is the voltage across the capacitor. In this example, "resetting the ramp signal RS" may include discharging the capacitor. However, it may take some time to discharge the capacitor, so that in this case, the ramp signal RS does not necessarily rise from the threshold RS. TH Rapidly decreases to the initial starting value RS0. According to one example, two ramp signals RS11, RS12 can therefore be used in the method for controlling the electronic switch 1. Fig. 9 is shown in .

[0057] Fig. 9 shows the driving signal S DRV , the switching current I1, the first ramp signal RS11 and the second ramp signal RS12. The functions of these ramp signals RS11 and RS12 are similar to Figure 8 The function of the ramp signal RS shown is the same. However, Fig. 9 In the example shown, it is not necessary to wait until the ramp signals RS11 and RS12 reach the threshold RS TH Afterwards, the ramp signals RS11 and RS12 are quickly reset to the starting value RS0, because the two ramp signals RS11 and RS12 are used alternately to determine the delay time duration T in a drive cycle. DEL And adjust the conduction level duration T in the next driving cycle DRV That is, whenever one of the two ramp signals RS11 and RS12 reaches the threshold RS TH When the other of the two ramp signals RS11, RS12 starts to increase with the starting value RS0. In this way, the threshold value RS TH The ramp signal can be slowly reduced to the starting value RS0, wherein the ramp signal reaches the threshold value RS in the next driving cycle. TH The starting value RS0 should have been reached before. More specifically, Fig. 9 In the example shown, the first ramp signal RS11 determines the delay time duration T in the first driving cycle i-1. DEL (i-1), and adjust the conduction level duration T in the second driving cycle i DRV (i), and the second ramp signal RS12 is used to determine the delay time duration T in the second driving cycle i DEL (i), and adjusting the conduction level duration T in the third driving cycle (i+1) DRV (i+1), wherein the first ramp signal RS11 is used again in the third driving cycle i+1 to determine the delay time duration T DEL (i+1).

[0058] Fig.10 An example of a power converter is shown in more detail. In this example, the power converter is implemented as a boost converter with a non-isolated topology. In this power converter, a series circuit including an electronic switch 1 and an inductor 2 is connected between a first input node 31 and a second node 32. A rectifier stage II is connected between a circuit node common to the electronic switch 1 and the inductor 2 and output terminals 33, 34. The rectifier stage II may include a series circuit including a rectifier element 51, such as a diode and a capacitor 52, wherein the series circuit is connected in parallel with the electronic switch 1. In this example, the output voltage V OUT is available across capacitor 52. However, implementing rectifier stage II in this way is only an example. Rectifier stage II may be implemented in various other ways and may, for example, include an additional inductor. Rectifier stages in boost converters are well known and therefore require no further explanation in this regard.

[0059] Reference Fig.10 The power converter further comprises a control circuit 7. The control circuit is configured to generate a drive signal S received by the electronic switch 1. DRV According to an example, the control circuit 7 is configured to drive the electronic switch 1 so that an output parameter of the power converter, such as the output voltage V OUT Or output current I OUT To this end, the control circuit 7 receives a feedback signal S which depends on the regulated output parameter FB . Feedback signal S FB is generated by a feedback circuit 6 depending on the regulated output parameter, wherein the feedback circuit 6 receives a signal representing the respective output parameter. Fig.10 In the example shown, the regulated output parameter is the output voltage V OUT , so that in this example the feedback circuit 6 receives the output voltage V OUT Alternatively, the feedback circuit 6 may receive a signal representing the output voltage V OUT signal.

[0060] According to one example, the feedback circuit 6 calculates an error signal based on the received output parameter and a reference signal (set point signal), wherein the reference signal defines a desired signal level of the output parameter. In addition, the feedback circuit 6 can generate the feedback signal S by filtering the error signal using a filter, such as a filter having one of a proportional (P) characteristic, an integral (I) characteristic, a proportional integral (PI) characteristic, or a proportional integral derivative (PID) characteristic. FB .

[0061] Input voltage V INIt can be a DC voltage or a rectified AC voltage, such as a rectified sinusoidal voltage. The rectified AC voltage can be obtained by receiving the AC voltage V G The bridge rectifier BR ( Fig.10 The AC voltage V G For example, it is a sinusoidal grid voltage. G The frequency of is, for example, 50 Hz or 60 Hz, so that the frequency of the rectified grid voltage is 100 Hz or 120 Hz. The switching frequency, ie the frequency of the generated drive cycle, is, for example, higher than 10 kHz. In this case, it can be assumed that the delay time duration T DEL The input voltage V IN Changing slowly from one drive cycle to the next.

[0062] exist Fig.10 In the power converter shown, the current flows for a duration of T ON During, ie during the time period when the switch current I1 is different from 0, energy is stored in the inductor 2. After the electronic switch 1 has been turned off and the switch current I1 has decreased to zero, the energy stored in the inductor 2 is transferred to the output terminals 33, 34 via the rectifier stage II.

[0063] Fig.11 A power converter according to another example is shown. In this example, the power converter is a flyback converter, wherein the inductor 2 is the primary winding of a transformer 20. The secondary winding 21 of the transformer 20 is inductively coupled to the primary winding 2 and connected to the rectifier stage II. The transformer 20 provides galvanic isolation between the input terminals 31, 32 and the output terminals 33, 34 of the power converter. Similar to Fig.10 In the power converter shown in FIG. 1 , an inductor 2 is connected in series with an electronic switch 1. In addition to the feedback circuit 6, Fig.11 The power converter shown in FIG. 1 further includes a coupler 8. The coupler 8 is configured to: transmit the feedback signal S provided by the feedback circuit 6 to the feedback circuit 6 via a potential barrier formed by the transformer 20. FB is transmitted to the control circuit 7. The coupler 8 may comprise an optical coupler, a capacitive coupler, an inductive coupler, etc. Couplers of this type are well known and therefore require no further explanation in this regard.

[0064] exist Fig.11 In the power converter shown, the current flows for a duration of T ON During the period, i.e. during the time period when the switching current I1 is different from 0 and the current flows through the primary winding, energy is stored in the transformer 20. After the electronic switch 1 has been turned off and the switching current I1 has decreased to zero, the energy stored in the transformer 20 is transferred to the output terminals 33, 34 via the secondary winding 21 and the rectifier stage II.

[0065] exist Fig.12 The operation for Fig.10 and Fig.11 An example of a method of one of the power converters shown. Fig.12 shows the driving signal S DRV , switch current I1, ramp signal RS and auxiliary voltage V AUX Signal waveform. Auxiliary voltage V AUX is an auxiliary winding 4 inductively coupled to the inductor 2 (see Fig.10 and Fig.11 ) voltage across the terminals. Fig.12 In the example shown, the power converter operates in a quasi-resonant mode (also called critical conduction mode). In this operating mode, the instants t0 at which a new drive cycle begins are defined by those instants at which the inductor 2 is demagnetized. "Demagnetization" means that the current flows for a duration of T ON During this period, the energy stored in the inductor 2 has been completely transferred to the output terminals 33 and 34. When the inductor 2 has been demagnetized, the voltage across the inductor 2 is zero. AUX Proportional to the voltage across inductor 2 (and Fig.10 and Fig.11 In the example shown, they have opposite signs. Fig.12 In the method shown, the auxiliary voltage V AUX The times t used to detect the demagnetization of the inductor 2 ZC These moments ZC It can also be called the zero-crossing moment.

[0066] The control circuit 7 is configured to detect the auxiliary voltage V after the electronic switch 1 has been turned off. AUX When the auxiliary voltage V AUX When the value reaches zero, the electronic switch 1 is turned on immediately. Fig.12 As shown), the control circuit 7 is configured to AUX At the first zero crossing time t ZC Afterwards, the electronic switch 1 is turned on when the first minimum value is reached. This can help reduce switching losses. After the voltage across the inductor 2 has passed zero, parasitic oscillations of the voltage V2 across the inductor 2 and thus the auxiliary voltage V AUX The parasitic oscillations of the inductor 2 are generated until the electronic switch 1 is turned on next time. The period of these oscillations depends on the inductance of the inductor 2 and the capacitance of the parasitic capacitance, such as the output capacitance C1 of the electronic switch 1. The period of these parasitic oscillations can be measured or obtained by simulation. According to one example, a value representing the duration of a period of these parasitic oscillations is stored in the control circuit 7, and the control circuit 7 is configured to AUXThe electronic switch 1 is turned on for a quarter (1 / 4) period after the first zero crossing. In this case, when the inductor voltage V2 reaches the first minimum value after the zero crossing, the electronic switch 1 is turned on.

[0067] In addition, Fig.12 In the example shown, the desired current flow duration T ON_DES With the feedback signal S FB proportional to, or by the feedback signal S FB Therefore, the ramp signal threshold RS TH With the feedback signal S FB Proportional or equal to the feedback signal S FB Therefore, the feedback signal S FB Defines the desired current flow duration T ON_DES . Feedback signal S FB It can be generated by the feedback circuit 6 so that the feedback signal S FB With the adjusted output parameter (V OUT or I OUT ) decreases, so as to suppress the further decrease of the output parameter, and vice versa.

[0068] Referring to the above, the input voltage V IN It may be a rectified sinusoidal voltage. In this case, it may be desirable to operate the power converter so that the input current I IN The average value is basically the same as the input voltage V IN This can be achieved by operating the power converter in critical conduction mode and by FB The desired current flow duration T is adjusted ON_DES To achieve this, no additional control loop is required to achieve the input current I IN and input voltage V IN This is well known. The method described herein before (in which the delay time T is determined in one drive cycle) DEL and use the desired current flow duration T ON_DES and the delay time duration determined in the previous driving cycle to adjust the conduction level duration T in the next driving cycle DRV ) helps ensure that the actual current flow duration T ON Essentially equal to the desired flow duration T ON_DES This is the instantaneous input voltage V IN low and the delay time T introduced by the electronic switch 1 DEL Especially useful for relatively long periods of time.

[0069] exist Fig.12 In the example shown, the auxiliary voltage VAUX It is used not only to detect the zero crossings of the inductor voltage V2, which indicates the demagnetization of the inductor 2, but also to detect those moments when the switching current I1 drops below a predefined threshold, such as zero. When the switching current I1 turns to zero at the end of the magnetization period of the inductor 2, the inductor voltage V2 changes its polarity in the direction opposite to the direction at the first zero crossing after demagnetization. Therefore, the auxiliary voltage V AUX According to one example, the control circuit 7 is configured to detect the driving signal S DRV After the signal level has changed from the on level to the off level, the auxiliary voltage V AUX When to change its polarity. Auxiliary voltage V AUX The moment of changing its polarity is the delay time duration T DEL The second time t2 at the end.

[0070] Fig.13 An example of the control circuit 7 is shown in more detail. In this example, the control circuit 7 comprises a circuit that receives the auxiliary voltage V AUX The zero-crossing detector 71, the ramp signal generator 72, the comparator 74 and the latch 75 are configured to generate a ramp signal RS. The ramp signal RS is generated by the zero-crossing detection signal S generated by the zero-crossing detector 71. ZCD and the driving signal S DRV The latch 75 is controlled according to the zero-crossing detection signal S ZCD and a comparator signal S74 generated by the comparator 74 to provide a drive signal S DRV The comparator 74 receives the feedback signal S FB and the ramp signal RS provided by the ramp signal generator 72. In this example, whenever the ramp signal RS reaches the feedback signal S FB When the latch 75 is reset, the driving signal S DRV The off level of is generated to be zero. The latch 75 is set to ZCD Generate drive signal S DRV More specifically, whenever the zero-crossing detection signal S provided by the zero-crossing detector 71 is ZCD Indicates auxiliary voltage V AUX Already in a predefined direction (e.g. Fig.12 In the example shown, when the zero crossing detection signal S is from positive to negative, the latch 75 is set. ZCD Indicates auxiliary voltage V AUX The time when the zero crossing has occurred in the predefined direction and the latch 75 are set to generate the drive signal S DRVThe delay time introduced by the delay element 73 may correspond to a quarter of the parasitic oscillation of the inductor voltage V2.

[0071] The ramp signal generator 72 is configured to Fig.12 The method shown is based on the zero-crossing detection signal S ZCD and the driving signal S DRV To generate the ramp signal RS. That is, whenever the drive signal S DRV When the zero-crossing detection signal S is changed to the off level, the ramp signal RS is reset to the initial value RS0 and starts to increase from the starting level RS0. ZCD Indicates auxiliary voltage V AUX The driving signal S DRV The second direction is changed to the opposite direction of the zero crossing direction of the conduction level (in Fig.12 The ramp signal generator 72 interrupts the increase of the ramp signal RS when the drive signal S passes through zero (from negative to positive in the example shown). The ramp signal generator 72 is also configured to DRV When changing from the off level to the on level, the ramp signal RS starts to increase again.

[0072] The zero-crossing detector 71 may be configured to generate a zero-crossing detection signal S ZCD , (a) so that when the auxiliary voltage V AUX When crossing zero along the first direction, the zero-crossing detection signal S ZCD changes from the first signal level to the second signal level to indicate that the inductor 2 has been demagnetized, and (b) when the auxiliary voltage V AUX When crossing zero along the second direction, the zero-crossing detection signal S ZCD The signal level changes from the second signal level back to the first signal level to indicate that the switch current I1 has decreased to zero.

[0073] By monitoring the auxiliary voltage V AUX The second time t2 when the switch current I1 decreases to zero is detected by the inductor voltage V2, the voltage V1 across the load path of the switch 1, or the switch current I1 may be monitored instead of the auxiliary voltage. Monitoring the switch current I1 may include measuring the switch current I1 using a current sensor (not shown) and comparing a current measurement signal representing the switch current I1 with a suitable threshold signal, such as zero. Monitoring the switch voltage V1 may include measuring the switch voltage V1 and comparing a voltage measurement signal representing the switch voltage V1 with a voltage measurement signal representing the input voltage V IN The threshold signal is compared.

[0074] Fig.13 The ramp signal generator 72 shown may be configured to generate a signal as follows: Fig.12 a ramp signal as shown, or can be configured to generate Fig. 9 Two ramp signals RS11, RS12 of the type shown, wherein these ramp signals are generated alternately by the ramp signal generator 72 so that in each drive cycle, one of the ramp signals is reset at a first instant t1 and the other of the ramp signals starts increasing at the first instant t1 with a starting value RS0.

[0075] In the above example, the on-state duration T of the electronic switch 1 is DRV Defined by the ramp signal RS, the conduction level duration T DRV The desired current flow duration T ON_DES Subtract the delay time duration T determined in the previous drive cycle DEL In addition, the desired on-time duration T ON_DES The ramp signal threshold RS TH Definition, where the ramp signal threshold RS TH Depending on the output parameter to be adjusted (e.g., V OUT or I OUT ).

[0076] In the method described above, the following may occur: during the delay time duration T DEL During this period, the ramp signal RS reaches the threshold RS TH In this case, the electronic switch 1 remains off, and when the threshold signal RS TH increase (e.g., due to the output voltage V OUT When the ramp signal RS decreases) and is no longer equal to the ramp signal RS, the electronic switch 1 is turned on again.

[0077] According to another example, whenever the inductor 2 has been demagnetized, the electronic switch 1 is turned on for at least a minimum time period T MIN .use Fig.13 In a control circuit 7 of the type shown, this can be achieved by providing a pulse generator 76 which receives the zero-crossing detection signal S from the zero-crossing detector 71 or the delay element 73. ZCD The pulse generator 76 is configured to output a pulse with a minimum time period T whenever a zero crossing is detected. MIN The logic gate 77, such as an OR gate, receives a signal pulse from the pulse generator 76 and an output signal from the latch 75, wherein the logic gate 77 provides a drive signal S DRV (a) When the ramp signal RS has not reached the threshold RS in the previous driving cycle TH When the driving signal S DRV The output signal of latch 75 controls the output signal of latch 75, so that when the ramp signal RS reaches the threshold RS in the current driving cycle, THWhen the latch 75 is reset; and (b) when the ramp signal RS and the threshold RS TH The conduction level duration T adjusted by comparison ON Longer than the minimum duration T MIN When the driving signal S DRV is controlled by the output signal of latch 75. In any other case, namely (c) when the ramp signal RS has reached the threshold RS in the previous driving cycle TH or (d) when the ramp signal RS is connected to the threshold RS in the current driving cycle. TH The conduction level duration T adjusted by comparison ON Less than the minimum duration T MIN When the driving signal S DRV And therefore the conduction level duration T ON Controlled by the output signal of the pulse generator 76.

[0078] Fig.14 A method according to another example is shown. AUX In addition, Fig.14 The switch voltage V1 is also shown in FIG. In this example, the on-level duration T DRV The first conduction level duration T obtained in the manner described above is included DRV1 That is, the first conduction level duration T DRV1 By the ramp signal threshold RS TH The duration represented by minus the delay time duration T obtained in the previous drive cycle DEL In addition, the conduction level duration T DRV Including the second conduction level duration T DRV2 The second conduction level duration T DRV2 Depends on the input voltage V IN , and as the input voltage V IN As described, for example, in DE 10 2007 035 606 A1 or US Pat. No. 7,683,595 (both belong to Infineon Technologies Austria GmbH), the second on-level duration T DRV2 Can help reduce total harmonic distortion (THD).

[0079] Reference Fig.14 , another ramp signal RS2 can be used to generate a second conduction level duration T DRV2 , where whenever the ramp signal RS has reached its threshold RS TH When the other ramp signal RS2 starts to increase with the starting value RS20. In the following, the ramp signal RS is referred to as the first ramp signal, and the threshold RSTH is called the first ramp signal threshold RS TH , the other ramp signal RS2 is called the second ramp signal, and the corresponding threshold RS2 TH is called the second threshold. When the second ramp signal RS2 reaches the second threshold RS2 TH The second conduction level duration T DRV2 In this example, the second ramp signal RS2 reaches the second ramp signal threshold RS2 TH The moment when the driving signal S DRV The moment when the on level changes to the off level.

[0080] Fig.15 shows the second ramp signal threshold RS2 TH For input voltage V IN An example of a dependency. Fig.15 It can be seen that the second ramp signal threshold RS2 TH With the input voltage V IN As described in DE 10 2007 035 606 A1 or US 7,683,595 mentioned above, the input voltage V IN To generate the threshold RS2 TH .

[0081] Fig.16 and Fig.17 shows that at the first threshold RS TH and the second threshold RS2 TH At different levels Fig.14 As shown in the method. Fig.16 It can be seen that due to the input voltage V IN Relatively low so that the delay time duration T DEL Relatively long and the second ramp signal threshold RS2 TH In relatively high cases, such as Fig.16 As shown, the first conduction level duration T DRV1 May become zero after the initial drive cycle.

[0082] Fig.17 The following situation is shown: both the first ramp signal RS and the second ramp signal RS2 reach their respective threshold values ​​RS twice in the initial driving cycle TH 、RS2 TH In this example, the conduction level duration will be zero in the second drive cycle and the consecutive drive cycles. Fig.17 In the example shown, the electronic switch 1 is turned on for at least a minimum time period T in each drive cycle.MIN And it has nothing to do with the ramp signals RS and RS2.

Claims

1. A method for driving an electronic switch (1) in a power converter, comprising: driving the electronic switch (1) coupled to the inductor (2) in the power converter, Wherein, driving the electronic switch (1) comprises: DRV ) drives the electronic switch (1) in a plurality of driving cycles, Wherein, driving the electronic switch (1) in at least one driving cycle among the plurality of driving cycles comprises: Determine the desired duration (T) of the current (I1) through the electronic switch (1) ON_DES );as well as According to the expected duration (T ON_DES ) and the delay time (T DEL ) to adjust the drive signal (S DRV ) of the conduction level (T DRV ), Wherein, the delay time (T DEL ) is the driving signal (S DRV ) is a duration between a first moment (t1) when the on-level changes to the off-level and a second moment (t2) when the current through the electronic switch (1) drops below a predefined threshold, The desired duration (T) of the current (I1) passing through the electronic switch (1) is determined. ON_DES ) includes adjusting a first ramp signal threshold (RS ) of at least one ramp signal (RS ; RS11 , RS12 ) TH ),as well as According to the expected duration (T ON_DES ) and the delay time (T DEL ) to adjust the drive signal (S DRV ) of the conduction level (T DRV )include: starting a ramp of the at least one ramp signal (RS; RS11, RS12) at the first instant (t1) in the previous drive cycle and interrupting the ramp at the second instant (t2) in the previous drive cycle; When the driving signal (S DRV ) changes from the off level to the on level and the drive signal (S DRV ) of the conduction level (T DRV ), continuing the ramp of the at least one ramp signal (RS; RS11, RS12) at another time (t0) in the at least one driving cycle, When the slope of the at least one ramp signal (RS; RS11, RS12) reaches the first ramp signal threshold (RS TH ), the duration of the conduction level (T DRV )Finish.

2. The method according to claim 1, in, The power converter further includes an auxiliary inductor (4) inductively coupled to the inductor (2), and Wherein, the delay time (T DEL ) includes an auxiliary voltage (V AUX ) detects the second moment (t2).

3. The method according to claim 1, in, The delay time (T DEL ) comprises detecting the second time (t2) based on one of: a voltage (V1) across the electronic switch (1); a voltage (V2) across the inductor (2); and A current (I1) passes through the electronic switch (1).

4. The method according to any one of claims 1 to 3, wherein: Adjust the drive signal (S DRV ) of the conduction level (T DRV ) also includes: When the slope of the at least one ramp signal (RS; RS11, RS12) reaches the first ramp signal threshold (RS TH ), the driving signal (S DRV ) changes the signal level from the on-level to the off-level.

5. The method according to any one of claims 1 to 3, in, The at least one ramp signal includes a first ramp signal (RS11) and a second ramp signal (RS12), and Wherein, starting the ramp of the at least one ramp signal at the first time (t1) includes alternately starting the ramps of the first ramp signal (RS11) and the second ramp signal (RS12) in consecutive driving cycles.

6. The method according to any one of claims 1 to 3, wherein: Adjust the drive signal (S DRV ) of the conduction level (T DRV ) also includes: The magnetization state of the inductor (2) is detected, and when a predefined magnetization state is detected, the drive signal (S DRV ) changes the signal level from the off-level to the on-level.

7. The method according to claim 6, in, Detecting the magnetization state of the inductor (2) includes monitoring a voltage across an auxiliary inductor (4) inductively coupled to the inductor (2).

8. The method according to any one of claims 1 to 3, wherein: Adjust the drive signal (S DRV ) of the conduction level (T DRV ) also includes: When the slope of the at least one ramp signal reaches the first ramp signal threshold (RS TH ), start the ramp of another ramp signal (RS2); and When the slope of the other ramp signal (RS2) reaches the second ramp signal threshold (RS2 TH ), the driving signal (S DRV ) changes the signal level from the on-level to the off-level.

9. The method according to any one of claims 1 to 3, wherein: According to the expected duration (T ON_DES ) and the delay time (T DEL ) to adjust the drive signal (S DRV ) of the conduction level (T DRV ) also includes: When the expected duration (T ON_DES ) is equal to or less than the delay time (T DEL ), the driving signal (S DRV )’s conduction level duration is adjusted to zero.

10. The method according to any one of claims 1 to 3, wherein: According to the expected duration (T ON_DES ) and the delay time (T DEL ) to adjust the drive signal (S DRV ) of the conduction level (T DRV ) also includes: When the expected duration (T ON_DES ) and the delay time (T DEL ) is less than the predefined minimum duration (T MIN ), the driving signal (S DRV ) is adjusted to the predefined minimum duration (T MIN ).

11. The method according to any one of claims 1 to 3, wherein: The electronic switch (1) is a super junction transistor device.

12. The method according to any one of claims 1 to 3, wherein: The predefined threshold is zero.

13. A power converter comprising: An electronic switch (1) coupled to an inductor (2); as well as The control circuit (7) is configured to drive the DRV ) drives the electronic switch (1) in a plurality of driving cycles, The control circuit (7) is configured to, in at least one driving cycle among the plurality of driving cycles: Determine the desired duration (T) of the current (I1) through the electronic switch (1) ON_DES );as well as According to the expected duration (T ON_DES ) and the delay time (T DEL ) to adjust the drive signal (S DRV ) of the conduction level (T DRV ), Wherein, the delay time (T DEL ) is the driving signal (S DRV ) is a duration between a first moment (t1) when the on-level changes to the off-level and a second moment (t2) when the current through the electronic switch (1) drops below a predefined threshold, The desired duration (T) of the current (I1) passing through the electronic switch (1) is determined. ON_DES ) includes adjusting a first ramp signal threshold (RS ) of at least one ramp signal (RS ; RS11 , RS12 ) TH ),as well as According to the expected duration (T ON_DES ) and the delay time (T DEL ) to adjust the drive signal (S DRV ) of the conduction level (T DRV )include: starting a ramp of the at least one ramp signal (RS; RS11, RS12) at the first instant (t1) in the previous drive cycle and interrupting the ramp at the second instant (t2) in the previous drive cycle; When the driving signal (S DRV ) changes from the off level to the on level and the drive signal (S DRV ) of the conduction level (T DRV ), continuing the ramp of the at least one ramp signal (RS; RS11, RS12) at another time (t0) in the at least one driving cycle, When the slope of the at least one ramp signal (RS; RS11, RS12) reaches the first ramp signal threshold (RS TH ), the duration of the conduction level (T DRV )Finish.

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