Semiconductor package and manufacturing method thereof

Abstract

The present invention discloses a semiconductor package and a method for manufacturing the same. The semiconductor package comprises: a semiconductor chip having a plurality of external terminals provided on its surface; a lead frame having a plurality of pins for connecting to an external circuit; a connecting portion comprising a plurality of leads serving as connecting circuits and an insulating substrate layer for supporting the plurality of leads, wherein one end of the leads is connected to the external terminals and the other end is connected to the pins; and an encapsulating body covering the semiconductor chip, the lead frame, and the connecting portion, with the pins exposed outside the encapsulating body. The present invention connects the external terminals of the semiconductor chip to the pins on the periphery of the lead frame via the leads on the connecting portion, i.e., the electrical connection of the connecting portion replaces the electrical connection of metal wires, thereby omitting the wire bonding process and resolving the problem of low product yield caused by poor metal wire bonding.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor package and a manufacturing method thereof. Background Art

[0002] Traditional semiconductor packages that use a lead frame as a chip carrier, such as the Quad Flat Package (QFP) and Quad Flat Non-leaded (QFN) semiconductor packages, are manufactured by bonding a semiconductor chip to a lead frame with a chip holder and multiple pins. Multiple metal bonding wires are used to electrically connect the external terminals on the chip surface to the pins on the lead frame. Finally, the chip and metal bonding wires are coated with an encapsulating compound to form a semiconductor package.

[0003] As market demands for consumer electronics continue to rise, so too are the performance requirements for semiconductor chips and semiconductor packages. For example, in mid- to high-end consumer electronics, the QFN products used typically have at least 60 pins around the lead frame and more than 100 metal bond wires. However, in the actual packaging process, wire bending and poor soldering are common, contributing to the low yield of QFN products. Furthermore, as the number of metal bond wires increases, the yield decreases. Summary of the Invention

[0004] An object of the present invention is to provide a semiconductor package and a manufacturing method thereof, wherein the semiconductor package can avoid bending of bonding wires, reduce the frequency of abnormal bonding points, and improve the reliability of the semiconductor package in long-term use.

[0005] According to one aspect of the present invention, a semiconductor package is provided, comprising: a semiconductor chip having a plurality of external terminals provided on its surface; a lead frame having a plurality of pins for connecting to an external circuit; a connecting portion comprising a plurality of leads serving as connecting circuits and an insulating substrate layer for supporting the plurality of leads, wherein one end of the lead is connected to the external terminals and the other end is connected to the pins; and an encapsulating body covering the semiconductor chip, the lead frame, and the connecting portion, with the pins exposed outside the encapsulating body.

[0006] Furthermore, the insulating substrate layer has a first surface and a second surface relative to each other, wherein the first surface is close to the semiconductor chip and the second surface is close to the lead frame; the leads include a first lead located on the first surface, a second lead located on the second surface, and a connecting wire located inside the insulating substrate layer; one end of the first lead is connected to the external terminal of the semiconductor chip, and the other end is connected to the connecting wire; one end of the second lead is connected to the pin of the lead frame, and the other end is connected to the connecting wire.

[0007] Furthermore, the insulating substrate layer has a first surface and a second surface relative to each other, wherein the first surface is close to the semiconductor chip and the second surface is close to the lead frame; one end of the lead is exposed to the first surface and connected to the external terminal of the semiconductor chip, the other end of the lead is exposed to the second surface and connected to the pin of the lead frame, and the other part of the lead is located inside the insulating substrate layer.

[0008] Furthermore, the connecting portion is provided with a positioning point for positioning with the semiconductor chip.

[0009] Furthermore, an insulating layer covering the lead is provided on the surface of the insulating base material layer.

[0010] Furthermore, an adhesive layer is provided on the second surface of the insulating base material layer, and the insulating base material layer is attached to the surface of the lead frame through the adhesive layer.

[0011] Furthermore, both ends of the lead are provided with pads for connecting to the external terminals of the semiconductor chip and the pins of the lead frame.

[0012] Furthermore, the surface of the pad protrudes from the surface of the insulating base material layer.

[0013] Furthermore, the surface of the pad is plated with nickel or tin metal.

[0014] As mentioned above, the semiconductor package further comprises a connecting portion which is a flexible circuit board.

[0015] According to another aspect of the present invention, a method for manufacturing a semiconductor package is provided, comprising the following steps: fixing a connecting portion to a surface of a lead frame, the connecting portion comprising a plurality of leads serving as connecting lines and an insulating substrate layer for supporting the plurality of leads; connecting one end of the lead to an external terminal of a semiconductor chip, and connecting the other end of the lead to a pin of the lead frame; and coating the semiconductor chip, lead frame, and connecting portion with an encapsulating colloid, while at least exposing the pin of the lead frame.

[0016] Furthermore, the method further includes the step of making a connection portion: forming a plurality of leads in the insulating base material layer; forming a pad for connecting to an external terminal at one end of the lead, and forming a pad for connecting to a pin at the other end of the lead.

[0017] Furthermore, the aforementioned connecting portion is a flexible circuit board.

[0018] The beneficial effects of the present invention are as follows:

[0019] The semiconductor package provided by the present invention utilizes leads within the connecting portion to connect the external terminals of the semiconductor chip to the pins of the lead frame. This electrical connection within the connecting portion replaces conventional metal wire connections, thus eliminating the wire bonding process and resolving the issue of low product yields caused by wire bending and poor metal wire bonding. Furthermore, since the connecting portion replaces metal wire connections, the electrical connection within the connecting portion can be completed during processing through processes such as mounting and reflow soldering. This has proven effective in shortening the product manufacturing process and improving manufacturing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0021] Figure 1 FIG. 1 is a schematic structural diagram of a semiconductor package according to an embodiment of the present invention.

[0022] Figure 2 A schematic diagram of the connection structure between the lead frame and the connection portion in an embodiment of the present invention is shown.

[0023] Figure 3 A cross-sectional view of a connection structure among a semiconductor chip, a connection portion, and a lead frame in an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0024] To more clearly illustrate the present invention, the present invention will be further described below in conjunction with preferred embodiments and accompanying drawings. Similar components in the accompanying drawings are represented by the same reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. Those skilled in the art should understand that the detailed description below is illustrative and not restrictive, and should not be used to limit the scope of protection of the present invention.

[0025] like Figure 1-Figure 3 As shown, an embodiment of the present invention provides a semiconductor package, which is similar to a QFN package structure and includes: a semiconductor chip 10, a lead frame 20, a connecting portion 30 and an encapsulation resin (not shown).

[0026] The surface of the semiconductor chip 10 is provided with a plurality of external terminals 11 (also known as PADs or solder joints). Preferably, all external terminals 11 of the semiconductor chip 10 are located on the same side of the semiconductor chip 10 to facilitate connection to the lead frame 20 via the connection portion 30, and further connection to the external circuit.

[0027] The leadframe 20 serves as the chip carrier for the integrated circuit, connecting the semiconductor chip 10 to external circuitry. Specifically, the leadframe 20 includes a die holder (not shown) for securing the semiconductor chip 10. The die holder is surrounded by a number of pins 21 for connecting to external circuitry. According to common definitions in the microelectronics industry, the side of the leadframe 20 (or die holder) used for connection to the semiconductor chip 10 is called the "front side," and the other side is called the "back side."

[0028] The connection portion 30 includes an insulating base material layer 31 and a plurality of leads 32 . Both ends of the leads 32 are connected to the external connection terminals 11 and the pins 21 , respectively.

[0029] The encapsulant is used to encapsulate the semiconductor chip 10, lead frame 20, and connector 30, protecting the semiconductor chip 10 from corrosion and oxidation. To facilitate connection to external circuits, the pins 21 of the lead frame 20 are partially exposed from the encapsulant. For example, this can be done in a manner similar to a QFN package, with the pins 21 exposed from the side and / or back of the encapsulant. In actual products, the back of the lead frame 20 is also exposed outside the encapsulant to facilitate heat dissipation from the semiconductor package. In some products, the pins 21 and the back of the lead frame 20 can also be soldered to a printed circuit board (PCB).

[0030] In conventional processes, the lead frame 20 utilizes bonding materials, such as metal wires (gold, aluminum, or copper), as well as metal bumps, to electrically connect the semiconductor chip 10 to an external circuit, thereby forming an electrical circuit. Specifically, the lead frame 20 utilizes the pins 21 surrounding it, primarily through metal wires, to electrically connect the external terminals 11 of the semiconductor chip 10 to the external circuit. However, during the packaging process, as the melted molding material is filled into the product at a certain mold flow rate, it inevitably exerts pressure on the metal wires within. This is commonly known in the industry as wire sweep. As market requirements for chip and semiconductor package performance continue to increase, the number of metal wires has significantly increased. Simultaneously, as chips and semiconductor packages continue to miniaturize, the density of metal wires has increased significantly, significantly increasing the difficulty of the wire bonding process and significantly reducing production efficiency. Furthermore, problems such as poor metal wire bonding and wire sweeping can significantly reduce product yield.

[0031] The semiconductor package provided by the present invention connects the external terminals 11 of the semiconductor chip 10 to the pins 21 on the periphery of the lead frame 20 via the leads 32 on the connecting portion 30. This means that the electrical connection using the connecting portion 30 replaces the electrical connection using metal wires, thus eliminating the wire bonding process and resolving the issues of poor metal wire bonding and wire bending that can reduce product yield. Furthermore, during the manufacturing process, the electrical connection between the connecting portion 30 and the lead frame 20 can be completed through mounting and reflow soldering. This has been proven to effectively shorten the manufacturing cycle and improve manufacturing efficiency.

[0032] Traditionally, electrical connections (bonding) of metal wires are primarily accomplished using wire bonding equipment and soldering pins (a tooling fixture for the wire bonding process) under specific conditions (power, pressure, time, and temperature). During the welding process, problems such as weak solder joints and cold joints often occur. These problems are difficult to detect during the operation and electrical performance testing. However, over the long term use of a product, these weak and cold joints can become detached, resulting in poor contact and ultimately, product malfunction or even failure.

[0033] In the present invention, the use of connector 30 for electrical connection replaces metal wire bonding, thus avoiding a series of problems such as loose metal wire bonding and cold solder joints, thereby improving the long-term reliability of the semiconductor package and extending its service life. In addition, since connector 30 replaces metal wire bonding for electrical connection, the insulating substrate layer 31 of connector 30 can support, fix, and even protect the lead 32, significantly improving the impact resistance of the circuit and connection points. This is particularly evident in harsh environments such as high temperature, high humidity, and high pressure.

[0034] Specifically, the insulating base material layer 31 of the connection portion 30 has a first surface and a second surface opposite to each other, wherein the first surface is close to (or faces) the semiconductor chip 10 , and the second surface is close to the lead frame 20 .

[0035] In one embodiment, leads 32 include a first lead attached to the first surface of insulating substrate layer 31, a second lead attached to the second surface, and a connecting wire located within insulating substrate layer 31 and connecting the first lead and the second lead at both ends. The first lead is connected to external terminal 11 of semiconductor chip 10, and the second lead is connected to pin 21 of lead frame 20.

[0036] This embodiment does not specifically limit the specific formation methods of the first lead, second lead, and connecting wire. In one implementation, the first lead and second lead are attached to the surface of the insulating substrate layer 31. For example, grooves can be provided on both surfaces of the insulating substrate layer 31, and metal wires can be formed within the grooves to serve as the first and second leads. The connecting wires can specifically be vias extending through both surfaces of the insulating substrate layer 31.

[0037] In another embodiment, the lead 32 is located within the insulating substrate layer 31, with its ends located on the first and second surfaces, respectively. Specifically, one end of the lead 32 is exposed on the first surface and connected to the external terminal 11 of the semiconductor chip 10, while the other end of the lead 32 is exposed on the second surface and connected to the pin 21 of the lead frame 20. The remainder of the lead 32 is located within the insulating substrate layer 31. Specifically, one end of the lead 32 is exposed from the first surface of the insulating substrate layer 31 and connected to the external terminal 11 of the semiconductor chip 10, while the other end of the lead 32 is exposed from the second surface and connected to the pin 21 of the lead frame 20. Placing the lead 32 within the insulating substrate layer 31 allows the insulating substrate layer 31 to better support, secure, and protect the lead 32, thereby improving the reliability of the semiconductor package.

[0038] like Figure 2 As shown, the connection portion 30 is provided with positioning points 33. Specifically, the positioning points 33 can be identification points formed on the first surface of the insulating substrate layer 31, or can be positioning holes located in the insulating substrate layer 31. When the semiconductor chip 10 is placed on the connection portion 30, the grasping mechanism can accurately place the semiconductor chip 10 on the first surface of the insulating substrate layer 31 through the positioning points 33, so that the external terminals 11 of the semiconductor chip 10 contact the ends of the leads 32 of the connection portion 30, facilitating soldering. Specifically, four positioning points 33 are provided, respectively, at the four corners of the central rectangular area of the insulating substrate layer 31. The shapes of the positioning points 33 can be circular, square, cross, etc.

[0039] In one embodiment, the surface of the connecting portion 30 is further provided with an insulating layer, which is coated on the first and second surfaces of the insulating substrate layer 31, thereby effectively covering and protecting the lead wires 32, isolating the lead wires 32 from external dust and moisture. Furthermore, in some products with specific requirements, an electromagnetic shielding film (EMI) may be further provided on the surface of the insulating layer to protect the lead wires 32 from strong external electromagnetic interference.

[0040] In one embodiment, an adhesive layer is provided between the second surface of the insulating substrate layer 31 and the front surface of the lead frame 20, and the insulating substrate layer 31 is attached to the surface of the lead frame 20 via the adhesive layer. The surface of the lead frame 20 is formed with a plurality of protrusions forming positioning posts, and the insulating substrate layer 31 is provided with positioning holes corresponding to the positioning posts. The positioning holes and the positioning posts cooperate to achieve accurate positioning between the connecting portion 30 and the lead frame 20, ensuring that the ends of the leads 32 are in full contact with the pins 21 of the lead frame 20, thereby facilitating an effective connection between the two.

[0041] This embodiment does not specifically limit how to achieve electrical connection between the lead 32 and the pin 21, or between the lead 32 and the external terminal 11, and conventional electrical connection methods in the semiconductor field may be used. Figure 2 and Figure 3 As shown, the leads 32 are provided with pads 34 at both ends for soldering to the external terminals 11 of the semiconductor chip 10 and the pins 21 of the lead frame 20. Metal bumps 12 are formed on the external terminals 11 of the semiconductor chip 10 using a bumping process. These serve as connection points for the semiconductor chip 10 to the outside world. The tops of the metal bumps 12 have dome-shaped or hemispherical metal tin to facilitate soldering to the pads 34.

[0042] In one embodiment, the surfaces of the pads 34 protrude above the surface of the insulating substrate layer 31. That is, the pads 34 at both ends of the lead 32 are higher than the surface of the insulating substrate layer 31, so as to facilitate soldering of the pads 34 to the external terminal 11 and the pin 21, respectively. Preferably, the surfaces of the pads 34 are plated with nickel or tin to facilitate soldering.

[0043] In a preferred embodiment, the connection portion 30 is a circuit board, particularly a flexible circuit board (FPC). The basic structure of a flexible circuit board is a copper foil substrate. The substrate film of the flexible circuit board is an insulating base material layer 31, primarily made of polyimide or polyester. The copper foil in the flexible circuit board forms the leads 32.

[0044] Because flexible printed circuit boards have excellent elasticity, using them as the connecting portion 30 ensures that circuit conduction remains intact despite external stress. Furthermore, the thickness of the flexible printed circuit board can be controlled to below 100 microns, significantly reducing space requirements, facilitating miniaturization of semiconductor packages, and providing greater design freedom for product structure design.

[0045] The present invention also discloses a method for manufacturing a semiconductor package. Figures 1 to 3 , the manufacturing method comprises the following steps:

[0046] The connecting portion 30 is fixed to the surface of the lead frame 20. The connecting portion 30 includes a plurality of leads 32 as connecting lines and an insulating base layer 31 for supporting the leads 32.

[0047] Connect one end of the lead 32 to the external terminal 11 of the semiconductor chip, and connect the other end of the lead 32 to the pin 21 of the lead frame;

[0048] The semiconductor chip 10 , the lead frame 20 and the connecting portion 30 are encapsulated with an encapsulant, and at least the pins 21 of the lead frame 20 are exposed.

[0049] In one embodiment, the following steps are also included:

[0050] Chip grinding: According to product requirements, the processed wafer is thinned to the required thickness by grinding, and then the thinned wafer is cut into single chips (die), namely semiconductor chips 10.

[0051] Back film application: First, apply a protective film to the back of the lead frame 20 to prevent glue overflow during the subsequent plastic packaging process (depending on the process design, this step can also be placed before the plastic packaging process).

[0052] Mounting the connection portion 30: Fix the lead frame 20 on the carrier to prevent the lead frame 20 from warping during subsequent operations. Apply adhesive to the surface of the insulating base layer 31 and attach the connection portion 30 to the surface of the lead frame 20 through the adhesive.

[0053] Chip mounting: The semiconductor chip 10 is mounted on the other surface of the connecting portion 30, electrically connecting the external terminals 11 of the semiconductor chip 10 to the pads 34 at the ends of the leads 32. Preferably, the connecting portion 30 is provided with positioning points 33, which allow the semiconductor chip 10 to be accurately positioned relative to the connecting portion 30, thereby achieving an effective connection between the external terminals 11 and the leads 32.

[0054] This step, also known as flip-chip bonding, is a type of flip-chip bonding. In practice, metal bumps, flux, and flip-chip bonding equipment can be used to achieve electrical connection between the semiconductor chip 10 and the connection portion 30. Of course, other methods are not excluded, as long as they can achieve electrical connection between the external terminals 11 of the semiconductor chip 10 and the leads 32 of the connection portion 30.

[0055] Reflow soldering: Connecting the pads 34 on the second surface of the connection portion 30 to the pins 21 of the lead frame 20 to achieve electrical connection between the external terminals 11 of the semiconductor chip 10 and the pins 21 of the lead frame 20 .

[0056] When this step is specifically implemented, a reflow soldering device may be used to melt and then solidify the metal between the pad 34 on the second surface of the connecting portion 30 and the pin 21 of the lead frame 20 to form a soldering point.

[0057] Water washing: Use a water washing machine to clean the residue left during welding to ensure the reliability of the plastic seal.

[0058] Plastic packaging: The melted packaging gel is wrapped around the semiconductor chip 10, the connecting portion 30 and the front surface of the lead frame 20 by an encapsulation machine and solidified into a shape.

[0059] The appearance of the semiconductor product after plastic encapsulation is similar to that of a traditional QFN packaged product, with the back of the lead frame 20 exposed to facilitate heat dissipation; the pins 21 on the lead frame 20 are also partially exposed to facilitate electrical connection with an external circuit.

[0060] In one embodiment, a ball planting process is further included, in which tin balls are fixed on the back of the lead frame 20 using ball planting equipment, and then high-temperature curing is performed through reflow soldering.

[0061] Furthermore, the process may also include preparing the connection portion 30. For example, using a flexible printed circuit board (FPC), circuit design can begin: based on the positions of the external terminals 11 of the semiconductor chip 10 and the lead frame pins 21, matching connection patterns and circuits are designed using CAD / CAM software. Next, metal bump connection endpoint design is performed: the FPC pads 34 are designed based on the material composition of the metal bumps 12 on the semiconductor chip 10. For example, if the metal bumps 12 on the chip are copper pillars with a semicircular surface composed of nickel and tin, the FPC pads 34 are typically made of a tin alloy, although other metal materials can be used depending on the product's characteristics. Finally, the connection endpoints to the pins 21 are designed based on the material composition of the coating on the lead frame 20 surrounding the pins 21. The FPC pads 34 are typically made of a tin alloy, but other metal materials can be used depending on the product's characteristics.

[0062] The flexible circuit board manufacturing in this embodiment generally only requires single-panel manufacturing, and existing mature manufacturing processes can be used. Obviously, the above embodiments of the present invention are merely examples for the purpose of clearly illustrating the present invention, and are not intended to limit the implementation methods of the present invention. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to list all implementation methods here. All obvious variations or modifications derived from the technical solution of the present invention are still within the scope of protection of the present invention.

Claims

1. A semiconductor package, characterized in that: include: A semiconductor chip having a plurality of external terminals provided on its surface; A lead frame having a plurality of pins for connecting to an external circuit, the lead frame including a chip seat for fixing a semiconductor chip and the pins arranged around the chip seat; a connecting portion comprising a plurality of leads serving as connecting lines and an insulating base layer for carrying the plurality of leads, wherein one end of the leads is connected to the external terminal and the other end is connected to the pin; the insulating base layer having a first surface and a second surface opposite to each other, wherein the first surface is adjacent to the semiconductor chip and the second surface is adjacent to the lead frame; the leads comprising a first lead, a connecting wire, and a second lead connected in sequence, the first lead being located on the first surface, the second lead being located on the second surface, and the connecting wire being located within the insulating base layer; as well as A packaging colloid covers the semiconductor chip, the lead frame and the connection part, and the pins are exposed outside the packaging colloid. In which, the multiple external terminals of the semiconductor chip face the lead frame, and the first lead and the second lead of the connecting part are respectively provided with a first soldering pad and a second soldering pad at one end away from the connecting wire, the first soldering pad protrudes from the first surface and is used for welding with the multiple external terminals of the semiconductor chip, and the second soldering pad protrudes from the second surface and is used for welding with the pins of the lead frame.

2. The semiconductor package according to claim 1, wherein One end of the lead is exposed on the first surface and connected to the external terminal of the semiconductor chip, the other end of the lead is exposed on the second surface and connected to the pin of the lead frame, and the rest of the lead is located inside the insulating substrate layer.

3. The semiconductor package according to claim 2, wherein: An adhesive layer is provided on the second surface of the insulating base layer, and the insulating base layer is attached to the surface of the lead frame through the adhesive layer.

4. The semiconductor package according to any one of claims 1 to 3, wherein: The connecting portion is a flexible circuit board.

5. A method for manufacturing a semiconductor package, characterized in that: The steps include: Providing a lead frame, the lead frame comprising a chip base for fixing a semiconductor chip, and pins arranged around the chip base; Fixing a connecting portion to a surface of a lead frame, the connecting portion comprising a plurality of leads serving as connecting lines and an insulating base layer for supporting the plurality of leads, the insulating base layer having a first surface and a second surface opposite to each other, wherein the second surface is adjacent to the lead frame, the leads comprising a first lead, a connecting wire, and a second lead connected in sequence, the first lead being located on the first surface, the second lead being located on the second surface, and the connecting wire being located within the insulating base layer; Mounting a semiconductor chip on the first surface of the connecting portion, connecting one end of the lead to an external terminal of the semiconductor chip, and connecting the other end of the lead to a pin of the lead frame; The semiconductor chip, the lead frame and the connecting portion are covered with an encapsulating colloid, and at least the pins of the lead frame are exposed. In which, the external terminal of the semiconductor chip faces the lead frame, and the first lead and the second lead of the connecting part are respectively provided with a first soldering pad and a second soldering pad at one end away from the connecting wire, the first soldering pad protrudes from the first surface and is used for welding with the external terminal of the semiconductor chip, and the second soldering pad protrudes from the second surface and is used for welding with the pin of the lead frame.

6. The manufacturing method according to claim 5, characterized in that The step of making the connecting portion is also included: forming a plurality of leads in the insulating base material layer; A first pad for connecting to an external terminal is formed at one end of the lead, and a second pad for connecting to a pin is formed at the other end of the lead.

7. The manufacturing method according to claim 5 or 6, characterized in that: The connecting portion is a flexible circuit board.

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