A power-on timing detection device and method
By designing a power-on timing detection device including buffers, analog switches, comparators, DACs, ADCs and MCUs, high-time resolution detection is achieved using hardware triggering methods, which solves the large size, high cost and The problem of high hardware cost achieves accurate and low-cost power-on timing measurement.
Patent Information
- Application Number
- CN202010654712.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-07-09
- Publication Date
- 2024-12-13
- Estimated Expiration
- 2040-07-09
AI Technical Summary
The existing power-on timing detection methods have the problem of large size, high cost and difficult to achieve batch detection, or the hardware cost will increase significantly when high time resolution is required.
A power-on timing detection device including 2n-channel buffers, n-channel analog switches, n-channel comparators, n-channel DACs, 1-channel ADCs and MCUs is designed to realize high-time resolution detection through hardware triggering, and use buffering The DAC sets the trigger voltage, the comparator record time difference and the ADC performs analog-to-digital conversion, combined with the MCU parsing data for accurate measurement.
The power-on timing detection with simple structure, low cost and high time resolution is realized, which reduces hardware cost and design difficulty, and can achieve accurate measurement without increasing the ADC sampling rate.
Smart Images
Figure CN111835325B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of testing, and in particular to a power-on timing detection device and method. Background Art
[0002] With the advancement of technology and the application of large-scale integrated circuits, the power-on timing of the chip has become an important test indicator for the product. When performing functional testing on the product, it is often necessary to measure the power-on timing of the product under test to detect whether the power supply of the product under test is working normally. If the power-on timing of the chip is abnormal, it will cause the product to work abnormally or even be damaged, so it is necessary to test the power-on timing of the product.
[0003] The existing power-on timing detection methods are mainly the following two methods:
[0004] (1) How to capture data using an oscilloscope
[0005] The advantages of using an oscilloscope are high voltage acquisition time resolution and easy-to-identify graphical display. The disadvantages are that the oscilloscope is large in size, high in cost, requires human experience to judge, and is not easy to achieve batch testing.
[0006] (2) Using ADC to collect and then analyze
[0007] The advantages of using ADC for data acquisition are small size and no reliance on manual judgment. The disadvantage is that a higher sampling rate is required in situations where high time resolution is required, and increasing the sampling rate of the entire sampling circuit will lead to a significant increase in hardware costs. Summary of the invention
[0008] The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art and provide a power-on timing detection device with simple structure, low cost and high time resolution.
[0009] The present invention also provides a method for performing electrical timing detection using the power-on timing detection device. The method has a simple process, high test accuracy, and low cost.
[0010] The technical solution adopted by the power-on timing detection device of the present invention is that, in the present invention, the power-on timing detection device is set to detect n-way power-on timing test signals, and it includes 2n-way buffers, n-way analog switches, n-way comparators, n-way DACs, 1-way ADC and MCU, every two of the buffers are respectively connected to one of the input signals to be tested, wherein the output ends of the n-way buffers are connected to the input ends of the n-way analog switches, and the output ends of the n-way buffers are connected to the positive phase input ends of the n-way comparators, the output ends of the n-way analog switches are connected to the input ends of the ADC, the ADC is connected to the SPI port of the MCU, the channel selection bit of the analog switch is connected to the GPIO port of the MCU, the input ends of the n-way DACs are connected to the MCU, the output ends of the n-way DACs are respectively connected to the negative phase input ends of the n-way comparators, the output ends of the n-way comparators are connected to the trigger points of the MCU, and the MCU is connected to a peripheral host computer, wherein n is the number of power-on timing test signals.
[0011] Further, the power-on timing test signal is a power-on voltage signal.
[0012] The method for detecting the power-on timing sequence of a device using the above-mentioned power-on timing detection device comprises the following steps:
[0013] a. The n power-on timing test signals to be detected are input to n input channels respectively, and then reach the non-inverting input terminal of the comparator after being buffered by the buffer;
[0014] b. The MCU sets the trigger voltage of each input channel through the n-channel DAC and starts the timer when the first channel is triggered;
[0015] c. When the second channel is triggered, the current time is recorded as T1. When the third channel is triggered, the current time is recorded as T2. This continues until the nth channel is triggered. The current time is recorded as Tn-1. The times T2, T3, ..., Tn-1 are obtained respectively, where n is the number of signals to be tested in the power-on timing sequence.
[0016] The power-on timing test signal of the dn-channel after being buffered by the buffer enters the n-channel analog switch, the MCU selects the input channel of the signal through the channel selection bit, and then starts the ADC through the SPI port to perform analog-to-digital conversion and reads the analog-to-digital conversion value, and then stores the analog-to-digital conversion value in the host computer. After data acquisition is completed, the host computer restores the waveform of the power-on timing test signal of the n-channel by analyzing the data;
[0017] e. At this time, any two time differences and waveform amplitudes are used as the basis for determining the power-on timing, and the power-on timing of the device is measured.
[0018] The beneficial effects of the present invention are as follows: in the present invention, a buffer is used to perform buffering, filtering and denoising on the power-on timing test signal, the MCU sets the trigger voltage of each input channel through the n-channel DAC, and starts the timer at the moment when the first channel is triggered, when the second channel is triggered, the current time T1 is recorded, when the third channel is triggered, the current time is recorded as T2, and so on, until the nth channel is triggered, and n-1 times are obtained; after the signal is input to the analog switch, the MCU selects the input channel of the signal through the channel selection bit, and then starts the ADC through the SPI port to perform analog-to-digital conversion and reads the value of the analog-to-digital conversion, and then stores the value of the analog-to-digital conversion in the host computer, after the data acquisition is completed, the host computer restores the waveform of the power-on timing test signal by analyzing the data, at this time, any two time differences and waveform amplitudes are used as the judgment basis for the power-on timing, and the power-on timing of the device is measured; the present invention adopts a hardware triggering method to solve the time measurement problem under high time resolution, and can realize accurate measurement of the power-on timing without increasing the sampling rate of the ADC. The use of hardware triggering can achieve higher time resolution, and at the same time, it is not necessary to increase the sampling rate of the ADC, which reduces the hardware cost and design difficulty. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 It is a principle structure diagram of the present invention. DETAILED DESCRIPTION
[0020] like Figure 1 As shown, the present invention sets the power-on timing detection device to detect n power-on timing detection signals. The power-on timing detection signal is a power-on voltage signal. In this embodiment, n is 8, that is, the power-on timing detection is performed on 8 signals to be detected. The device includes 16 buffers 1, 8 analog switches 2, 8 comparators 3, 8 DACs 4, 1 ADC 5 and MCU 6, wherein every two of the buffers 1 are respectively connected to one of the input signals to be measured, wherein the output ends of the 8 buffers 1 are connected to the input ends of the 8 analog switches 2, and the output ends of the other 8 buffers 1 are connected to the positive input ends of the 8 comparators 3, the output ends of the 8 analog switches 2 are connected to the input end of the ADC 5, the ADC 5 is connected to the SPI port of the MCU 6, the channel selection bits A0, A1, A2 of the analog switch 2 are connected to the GPIO ports GPIO_0, GPIO_1, GPIO_2 of the MCU 6, the input ends of the 8 DACs 4 are connected to the MCU 6, the output ends of the 8 DACs 4 are respectively connected to the negative input ends of the 8 comparators 3, the output ends of the 8 comparators 3 are connected to the trigger points of the MCU 6, and the MCU 6 is connected to the peripheral host computer.
[0021] In the present invention, the function of the buffer 1 is impedance transformation, and its chip model is OPA4354; the function of the analog switch 2 is input channel selection, and its chip model is SN74LV4051; the function of the comparator 3 is input signal amplitude detection, and its chip model is TLV3502; the function of the DAC 4 is to set the trigger threshold, and its chip model is AD5629; the function of the ADC 5 is analog-to-digital conversion, and its chip model is AD7175; the function of the MCU 6 is to select the input channel, set the trigger threshold, read the ADC value and communicate with the host computer, and its chip model is STM32F407.
[0022] The method for detecting the power-on timing sequence of a device by the power-on timing detection device comprises the following steps:
[0023] a. The 8 power-on timing test signals to be detected are input to the 8 input channels respectively, and after being buffered by the buffer 1, they reach the non-inverting input terminal of the comparator 3;
[0024] b. The MCU 6 sets the trigger voltage of each input channel through the 8-channel DAC 4, and starts the timer when the first channel is triggered;
[0025] c. When the second channel is triggered, the current time is recorded as T1. When the third channel is triggered, the current time is recorded as T2. This process continues until the eighth channel is triggered and the current time is recorded as T7. The time is T2, T3, ..., T7 respectively.
[0026] d. The 8-way power-on timing test signals buffered by the buffer 1 enter the 8-way analog switch 2, and the MCU 6 selects the input channel of the signal through the channel selection bits A0, A1, and A2, and then starts the ADC 5 through the SPI port to perform analog-to-digital conversion and reads the analog-to-digital conversion value, and then stores the analog-to-digital conversion value in the host computer. After data acquisition is completed, the host computer restores the waveform of the 8-way power-on timing test signals by analyzing the data;
[0027] e. At this time, any two time differences and waveform amplitudes are used as the basis for determining the power-on timing, and the power-on timing of the device is measured.
[0028] The present invention adopts a hardware triggering method to solve the time measurement problem under high time resolution, and can realize accurate measurement of power-on timing without increasing the ADC sampling rate. The hardware triggering method can achieve higher time resolution, and at the same time does not need to increase the ADC sampling rate, which reduces hardware cost and design difficulty.
Claims
1. A method for detecting the power-on sequence of a device using a power-on sequence detection device, characterized in that: The power-on timing detection device detects n power-on timing detection signals to be detected. The power-on timing detection device comprises 2n buffers (1), n analog switches (2), n comparators (3), n DACs (4), 1 ADC (5) and an MCU (6). Every two buffers (1) are respectively connected to one of the input signals to be detected, wherein the output ends of the n buffers (1) are connected to the input ends of the n analog switches (2), and the output ends of the n buffers (1) are connected to the non-inverting input ends of the n comparators (3), and the output ends of the n analog switches (2) are connected to the input ends of the ADC (5). The ADC (5) is connected to the SPI port of the MCU (6), the channel selection bits (A0, A1, A2) of the analog switch (2) are connected to the GPIO ports (GPIO_0, GPIO_1, GPIO_2) of the MCU (6), the input ends of the n-channel DAC (4) are connected to the MCU (6), the output ends of the n-channel DAC (4) are respectively connected to the negative input ends of the n-channel comparators (3), the output ends of the n-channel comparators (3) are connected to the trigger point of the MCU (6), and the MCU (6) is connected to a peripheral host computer, wherein n is the number of signals to be tested in the power-on timing sequence. The method comprises the following steps: a. The n power-on timing test signals to be detected are input into n input channels respectively, and after being buffered by the buffer (1), they reach the positive input terminal of the comparator (3); b. The MCU (6) sets the trigger voltage of each input channel through the n-channel DAC (4) and starts the timer when the first channel is triggered; c. When the second channel is triggered, the current time is recorded as T1. When the third channel is triggered, the current time is recorded as T2. This continues until the nth channel is triggered. The current time is recorded as Tn-1. The times T2, T3, ..., Tn-1 are obtained respectively, where n is the number of signals to be tested in the power-on timing sequence. The power-on timing test signals of the n-channels are buffered by the buffer (1) and enter the n-channels of the analog switch (2). The MCU (6) selects the input channel of the signal through the channel selection bits (A0, A1, A2), and then starts the ADC (5) through the SPI port to perform analog-to-digital conversion and reads the analog-to-digital conversion value, and then stores the analog-to-digital conversion value in the host computer. After data acquisition is completed, the host computer restores the waveform of the power-on timing test signals of the n-channels by analyzing the data. e. At this time, any two time differences and waveform amplitudes are used as the basis for determining the power-on timing, and the power-on timing of the device is measured.