A memristor and a method for preparing the same

Abstract

The present invention discloses a memristor and a preparation method thereof in the field of memory technology. The memristor comprises a bottom electrode, a dielectric layer and a top electrode which are sequentially arranged from bottom to top. The bottom electrode comprises an active electrode Ag, Cu or an oxygen-philic electrode W, Ti, TiN. The dielectric layer comprises a multilayer film in which at least two oxide layers are alternately deposited. The top electrode comprises inert electrodes Pt and Au. The memristor prepared by the present invention can improve the erasing speed of the memory and reduce energy consumption.

Description

Technical Field

[0001] The present invention belongs to the technical field of memory devices, and in particular relates to a memristor and a preparation method thereof. Background Art

[0002] As the size of CMOS logic and memory devices continues to shrink and gradually approaches the size limit, the "Moore's Law" of integrated circuit technology will also face severe challenges. Memristors are one of the cutting-edge topics in current memory research. Memristors are mainly composed of top electrodes, resistive dielectric layers, and bottom electrodes. The electrode materials can be mainly divided into three categories: active electrodes (copper, silver, etc.), inert electrodes (platinum, gold, etc.), and oxygen-philic electrodes (tungsten, titanium, etc.). Resistive dielectric layer materials can be divided into binary metal oxides, perovskite structure oxides, solid electrolyte materials, sulfur compound semiconductor materials, and organic materials. From the perspective of memristor structure, the overall electrical performance of single-layer dielectric layer memristors is generally much worse than that of double-layer or multi-layer dielectric layer memristors, which is mainly reflected in the switching speed and stability of the device. The resistive dielectric layer plays a vital role in the resistance change process of the memristor. However, the performance of the memristor still needs to be further improved. Therefore, how to reasonably select and prepare the resistive dielectric layer is crucial to improving the overall electrical performance of the memristor. The memristor prepared in the existing technology requires a cumbersome activation process during the test process, and the device has high energy consumption. Summary of the invention

[0003] The purpose of the present invention is to overcome the shortcomings of the prior art, provide a memristor and a preparation method thereof, solve the technical problem of high energy consumption in the prior art, and use of the present invention is conducive to reducing device voltage and low energy consumption.

[0004] The object of the present invention is achieved as follows: a memristor and a preparation method thereof, comprising a bottom electrode, a dielectric layer and a top electrode arranged in sequence from bottom to top, the bottom electrode comprising an active electrode Ag, Cu or an oxygen-philic electrode W, Ti, TiN, the dielectric layer comprising a multilayer film of at least two oxide layers deposited alternately, and the top electrode comprising an inert electrode Pt and Au.

[0005] As a further improvement of the present invention, the thickness of the bottom electrode is 30-200 nm.

[0006] As a further improvement of the present invention, the thickness of the dielectric layer is 4-30 nm.

[0007] As a further improvement of the present invention, the thickness of the top electrode is 30-200 nm.

[0008] As a further improvement of the present invention, the dielectric layer is any one of a hafnium oxide layer, a titanium oxide layer, a zirconium oxide layer and an aluminum oxide layer, or a combination of at least two of them.

[0009] As a further improvement of the present invention, the dielectric layer is a multilayer film obtained by alternately depositing any two materials of hafnium oxide, zirconium oxide, tantalum oxide, copper oxide, iron oxide, silicon oxide, titanium oxide and aluminum oxide.

[0010] As a further improvement of the present invention, the dielectric layer is prepared by atomic layer deposition, and different dielectric layers are alternated from bottom to top, dielectric layer one, dielectric layer two, dielectric layer one, dielectric layer two, dielectric layer one, dielectric layer two... in sequence, and the dielectric layer one and dielectric layer two are made of the two materials.

[0011] In order to further reduce the tunneling voltage, the thickness of the dielectric layer 1 gradually decreases, and the thickness of the dielectric layer 2 gradually increases.

[0012] A method for preparing a memristor comprises the following steps:

[0013] (1) Perform a standard cleaning process on the surface of the Si / SiO2 substrate, blow dry with a nitrogen gun after cleaning, use PMMA for coating, and electron beam expose and develop the bottom electrode pattern;

[0014] (2) growing the bottom electrode by thermal evaporation at a rate of 0.1-2 Å / s, then placing the sample in acetone to reveal the bottom electrode pattern;

[0015] (3) using electron beam exposure to prepare a top electrode pattern that is perpendicular to or intersecting the bottom electrode;

[0016] (4) The dielectric layer is prepared by atomic layer deposition at a growth temperature of 100-350 °C;

[0017] (5) Depositing Pt on the sample in step (4) for 10 min by radio frequency magnetron sputtering to a thickness of 10-100 nm, wherein the sputtering pressure of the radio frequency magnetron sputtering is set to 0.1-1 Pa, the atmosphere is Ar, the flow rate is 8-30 sccm, and the growth temperature is 20-100 °C. If the thickness of the deposited metal electrode is equal to the set thickness value, proceed to step (6);

[0018] (6) Based on step (5), Au is evaporated on the surface of the Pt electrode using thermal evaporation with a thickness of 10~100 nm and a growth rate of 0.1~2 Å / s.

[0019] As a further improvement of the present invention, ultrasonic cleaning is used in step (1), and acetone, isopropanol or ethanol, and deionized water are used for cleaning respectively.

[0020] As a further improvement of the present invention, in step (2), the growth rate of the bottom electrode is 1 Å / s; in step (4), the growth temperature is 180°C; in step (5), the sputtering pressure is set to 0.95 Pa, the flow rate is 20 sccm, the growth temperature is 20-25°C, and the thickness of Pt is 14 nm; in step (6), the thickness of Au is 45 nm.

[0021] Compared with the prior art, the top electrode, bottom electrode and dielectric layer materials selected in the present invention are all relatively dense nanometer-level thin film materials. The bottom electrode is made of titanium. Titanium metal has good oxygen affinity and can absorb oxygen atoms in the dielectric layer and form an interface layer between the titanium electrode and the dielectric layer, which plays a good buffering role in the device reset process, helps to complete the reset process thoroughly and quickly, and at the same time, greatly improves the stability and switching speed of the device; the dielectric layer is alternately deposited with hafnium oxide and titanium oxide, the thickness of the titanium oxide layer gradually decreases from the Ti electrode to the Pt electrode, and the thickness of the hafnium oxide layer gradually increases, and a structure in which the oxide layer changes gradually can be formed in the dielectric layer region, so that TiOx forms conductive filaments with shorter oxygen vacancy defects, and charges can easily tunnel through the HfOx layer at a lower voltage; the device does not require an activation process, which greatly reduces the complexity of device operation; a lower erase voltage is achieved, and the device has a wide range of application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Schematic diagram of the structure of the memristor in the present invention.

[0023] Figure 2 This is a rendering of the electrode pattern of the memristor in the present invention.

[0024] Figure 3 This is a scanning electron microscope image of the bottom electrode Ti of the memristor obtained in the present invention.

[0025] Figure 4 This is a scanning electron microscope image of the memristor dielectric layer prepared by the methods in Example 1 and Example 2 of the present invention.

[0026] Figure 5 This is a transmission electron microscope (TEM) image of the device cross section obtained in Example 1 of the present invention.

[0027] Figure 6 This is an energy dispersion spectrum (EDS) diagram of a local line scan of a device cross section obtained in Example 1 of the present invention.

[0028] Figure 7 This is a DC IV characteristic curve obtained by performing semi-logarithmic processing on the memristor prepared in Example 1 of the present invention.

[0029] Figure 8 The DC IV characteristic curves are obtained by performing double logarithmic processing on the high resistance state (HRS) and low resistance state (LRS) of the positive voltage scanning part of the device prepared in Example 1 of the present invention.

[0030] Fig. 9 This is a DC IV characteristic diagram obtained by performing semi-logarithmic processing on the memristor prepared in Example 2 of the present invention.

[0031] Fig.10 This is a DC IV characteristic diagram of the high resistance state (HRS) and low resistance state (LRS) of the positive voltage scanning part of the memristor prepared in Example 2 of the present invention subjected to double logarithmic processing.

[0032] Fig.11 This is a DC IV characteristic diagram obtained by performing semi-logarithmic processing on the memristor prepared in Example 3 of the present invention.

[0033] Fig.12 This is a DC IV characteristic diagram of the high resistance state (HRS) and low resistance state (LRS) of the positive voltage scanning part of the memristor prepared in Example 3 of the present invention subjected to double logarithmic processing.

[0034] Fig.13 The DC IV characteristic curves of the memristor prepared in Example 1 of the present invention with different scan voltage settings are shown. DETAILED DESCRIPTION

[0035] The present invention will be further described below in conjunction with the accompanying drawings.

[0036] A memristor comprises a bottom electrode, a dielectric layer and a top electrode which are sequentially arranged from bottom to top, wherein the bottom electrode comprises active electrodes Ag and Cu, and oxygen-philic electrodes W, Ti and TiN; the dielectric layer comprises an oxide layer which is alternately deposited with a gradient thickness; the top electrode comprises inert electrodes P and Au; the thickness of the bottom electrode is 30-200 nm, the thickness of the dielectric layer is 4-30 nm, the thickness of the top electrode is 30-200 nm, and the dielectric layer is a combination of at least two films alternately deposited from hafnium oxide layers with high dielectric constants, zirconium oxide, tantalum oxide, copper oxide, iron oxide, silicon oxide, titanium oxide layers, zirconium oxide layers and aluminum oxide layers with low dielectric constants.

[0037] In order to further reduce the required tunneling voltage, the dielectric layer alternates different dielectric layers from bottom to top, dielectric layer one, dielectric layer two, dielectric layer one, dielectric layer two, dielectric layer one, dielectric layer two... cycle in sequence, dielectric layer one and dielectric layer two are two materials, the thickness of dielectric layer one gradually decreases, and the thickness of dielectric layer two gradually increases. The dielectric layer is prepared by a deposition method; in this embodiment, when dielectric layer one is a titanium oxide layer and dielectric layer two is a hafnium oxide layer, the number of deposition turns of the dielectric layer from bottom to top is: 6*n, 2*0, 6*(n-1), 2*1...6*1, 2*(n-1), 6*0 and 14, multiples of 6 correspond to the number of deposition turns of the titanium oxide layer, and the others represent the number of deposition turns of the hafnium oxide layer, where n is an integer and ≥3, the deposition thickness of the hafnium oxide layer is 0.1~0.12nm / turn, titanium oxide layer: 0.045 nm / turn; in this design, TiO x The oxygen vacancy concentration in the HfO electrode decreases gradually from the Ti electrode to the Pt electrode. x can be used as a tunneling layer, so that TiO x Oxygen vacancies form conductive filaments and simultaneously lower the required tunneling voltage.

[0038] A method for preparing a memristor comprises the following steps:

[0039] (1) Perform a standard cleaning process on the surface of the Si / SiO2 substrate, blow dry with a nitrogen gun after cleaning, use PMMA for coating, and electron beam expose and develop the bottom electrode pattern;

[0040] (2) growing the bottom electrode by thermal evaporation at a rate of 0.1-2 Å / s, then placing the sample in acetone to reveal the bottom electrode pattern;

[0041] (3) using electron beam exposure to prepare a top electrode pattern that is perpendicular to or intersecting the bottom electrode;

[0042] (4) The dielectric layer is prepared by atomic layer deposition at a growth temperature of 100-350 °C;

[0043] (5) Depositing Pt on the sample in step (4) for 10 min by radio frequency magnetron sputtering to a thickness of 10-100 nm, wherein the sputtering pressure of the radio frequency magnetron sputtering is set to 0.1-1 Pa, the atmosphere is Ar, the flow rate is 8-30 sccm, and the growth temperature is 20-100 °C. If the thickness of the deposited metal electrode is equal to the set thickness value, proceed to step (6);

[0044] (6) Based on step (5), Au is evaporated on the surface of the Pt electrode using thermal evaporation with a thickness of 10-100 nm and a growth rate of 0.1-2 Å / s;

[0045] In step (1), ultrasonic cleaning is performed, followed by cleaning with acetone, isopropanol or ethanol, and deionized water. In step (2), magnetron sputtering can also be used to grow the bottom electrode Ti. In step (6), magnetron sputtering can also be used to evaporate Au on the surface of the Pt electrode. Example

[0046] A memristor comprises a bottom electrode, a dielectric layer and a top electrode arranged in sequence from bottom to top, wherein the bottom electrode is preferably titanium, the dielectric layer is preferably a combination of hafnium oxide and titanium oxide layers, and the top electrode is preferably Pt and Au.

[0047] A method for preparing a memristor comprises the following steps:

[0048] (1) A 1.2 cm*1.2 cm Si / SiO2 wafer was ultrasonically cleaned in acetone, isopropanol, and deionized water for 15 minutes each time, and then dried with nitrogen. The dried wafer was coated with PMMA with a molecular weight of 950 k at a speed of 3000 r / min for 1 min, and then baked on a heating table at 180 °C for 2 min. The final PMMA thickness was about 150 nm. Then, an electron beam was used to expose the pre-designed Ti bottom electrode pattern, develop (1 min), fix (30 s), and finally dried with a nitrogen gun and placed in a clean container;

[0049] (2) Thermally evaporated Ti electrode (60 nm), bulk vacuum 7.6x10 -4 Pa, evaporation source voltage 8.6 V, heating current 78 A, evaporation rate 1 Å / s, chamber pressure during evaporation at 5.1x10 -3 -5.4x10 -3 Fluctuates within the Pa range;

[0050] (3) Spin-coating the PMMA film again on the substrate on which the electrode was steamed in step (2) according to the operation in step (1), performing secondary electron beam exposure, development, and fixing, and drying with a nitrogen gun to reveal a top electrode Pt pattern, wherein the top electrode pattern is perpendicular to or intersecting with the bottom electrode pattern;

[0051] (4) Tetrakis(dimethylamino)hafnium was used as the hafnium oxide source, water was used as the oxygen source, the source heating temperature was 75°C, tetrakis(dimethylamino)titanium was used as the titanium source, water was used as the oxygen source, the source heating temperature was 75°C, the purification and carrier gas was nitrogen, the flow rate was 23.7sccm, the temperature of the reaction chamber was 180°C, and the dielectric layer was made using atomic layer deposition gradient doping number ratios as shown in the following table:

[0052]

[0053] Deposition sequence: 30 cycles of TiO x , 0-circle HfOx , 24 circles of TiO x , 2 turns HfO x ,…,0 TiO x , 14 turns HfO x Finally, the overall thickness of titanium oxide and hafnium oxide is guaranteed to be 8 nm. The gradient doping diagram is shown in Figure 2 As shown, from Figure 3 As can be seen from the figure, after the bottom electrode Ti is made by thermal evaporation, the surface morphology of the Ti electrode observed by SEM 8200 is dense and flat; the scanning electron microscope image after the dielectric layer deposition is completed is as follows Figure 4 As shown, Ti / TiO x :HfO x After finishing, observe the film formation. Figure 3 It can be seen that the film quality is good, dense and flat, ensuring the overall performance of the device;

[0054] (5) RF magnetron sputtering was used to deposit a Pt top electrode pattern on the sample on which the dielectric layer had been deposited. The sputtering power was 20 W and the bulk vacuum was 1.7x10 -4 Pa, the ignition pressure is 0.4 Pa, the sputtering pressure is 0.95 Pa, the sputtering time is 10 min, and the reaction chamber temperature is 20 °C. Finally, the thickness of Pt is measured by spectroscopic ellipsometer to be 14 nm, and the deposition rate of Pt is 1.4 nm / min.

[0055] (6) To ensure the overall thickness of the bottom electrode, Au of about 45 nm was grown on the Pt electrode described in (5) by thermal evaporation. The thermal evaporation body was vacuum 5x10 -4 Pa, working pressure is 4.3x10 -3 Pa, the evaporation current is between 75-80 A, which controls the deposition rate of Au and ultimately ensures that the Au film is uniform and firm;

[0056] (7) Stripping: Pick up the finished device with tweezers and place it in a beaker filled with acetone. Use a dropper to absorb the acetone solution and continuously blow the device surface. Change the acetone 4-5 times. First try to strip off the Au and Pt around the electrode. Then transfer the device to another beaker filled with acetone and seal it with a sealing film. Try to use a 70% power ultrasonic device for ultrasonic treatment for 2 minutes. Then use isopropyl alcohol and deionized water for ultrasonic cleaning for 10 minutes respectively. Finally, blow dry with a nitrogen gun. Finally, observe the intact device pattern through a microscope.

[0057] In order to further prove the device structure and cross-sectional composition, the transmission electron microscopy image and the energy dispersion spectrum of the local line scan are shown in Figure 5 , 6 As shown; Figure 5: Transmission electron microscope images of each component of the device cross section, A-A' represents the range of line scan, Figure 6 : The energy dispersion spectrum of the local line scan of the device cross section mainly explores the elemental composition and approximate film thickness of each part of the gradient doped dielectric layer. The actual thickness of Pt is smaller than the thickness during deposition, because it is related to the adhesion of the dielectric layer and the shedding during TEM sample preparation.

[0058] The developer in step (1) is isopropyl alcohol:tetramethylpentyl ketone, and the volume ratio thereof is 3:1. The fixing solution in step (1) is isopropyl alcohol, and an appropriate amount is sufficient. The model of the spectroscopic ellipsometer is SE-850. The heating temperature in step (3) is 180°C. The thickness of the well-coated film measured by the step profiler in step (3) is 140 nm-150 nm.

[0059] In the present invention, the terms used herein are defined as follows:

[0060] The term "PMMA" means: polymethyl methacrylate;

[0061] The term "HfO x ” means: hafnium oxide;

[0062] The term "TiO x ” means: titanium oxide;

[0063] The term "SiO2" means: silicon dioxide. Example

[0064] The difference from Example 1 is that steps (1) to (7) are retained, and the device prepared on this basis is annealed in high vacuum nitrogen by magnetron sputtering, with the temperature set to 400°C and the time set to 4 min. Example

[0065] The difference between this embodiment and embodiment 1 and embodiment 2 is that TiO x Replace with AlO x , also using a gradient multilayer structure, the overall dielectric layer thickness is also 8 nm, which further verifies that the gradient multilayer structure design is beneficial to reducing device energy consumption and improving storage density, and proves the universality of this method.

[0066] A method for preparing a memristor comprises the following steps:

[0067] (1) A 1.2 cm*1.2 cm Si / SiO2 wafer was ultrasonically cleaned in acetone, isopropanol, and deionized water for 15 minutes each time, and then dried with nitrogen. The dried wafer was coated with PMMA with a molecular weight of 950k at a speed of 3000 r / min for 1 min, and then baked on a heating table at 180 °C for 2 min. The final PMMA thickness was about 150 nm. Then, an electron beam was used to expose the pre-designed Ti bottom electrode pattern, develop (1 min), fix (30 s), and finally dried with a nitrogen gun and placed in a clean container.

[0068] (2) Magnetron sputtering of Ti electrode (100 nm), sputtering power of 150 W, bulk vacuum of 5x10 -4 Pa, the ignition pressure is 1.3 Pa, the sputtering pressure is 0.5 Pa, the sputtering time is 20 min, the reaction chamber temperature is 20 ℃, and a bias voltage of 30V is applied to ensure a dense film. Finally, the thickness of Ti is measured by a spectroscopic ellipsometer to be 100 nm, and the deposition rate of Ti is 5nm / min.

[0069] (3) Tetrakis(dimethylamino)hafnium was used as the hafnium oxide source, water was used as the oxygen source, the source heating temperature was 75 °C, trimethylaluminum was used as the aluminum source, water was used as the oxygen source, the source heating temperature was 25 °C, the purification and carrier gas was nitrogen, the flow rate was 23.7 sccm, the temperature of the reaction chamber was 180 °C, and the dielectric layer used atomic layer deposition gradient multilayer turns. The number of turns is as follows:

[0070]

[0071] Deposition sequence: 14 cycles of AlO x , 0-circle HfO x , 8 circles of AlO x , 2 turns HfO x ,…,0 circles of AlO x , 14 turns HfO x , ultimately ensuring that the overall thickness of aluminum oxide and hafnium oxide is 8 nm.

[0072] (4) According to step (1) in Example 1, the PMMA film is spin-coated again, and electron beam exposure, development, and fixing are performed for the second time. The film is dried with a nitrogen gun to reveal a top electrode Pt pattern, and the top electrode pattern is perpendicular to or intersecting with the bottom electrode pattern;

[0073] (5) A Pt top electrode pattern was deposited on the sample after the dielectric layer was deposited using RF magnetron sputtering with a sputtering power of 50 W and a bulk vacuum of 4.5x10 -4Pa, the ignition pressure is 1.3 Pa, the sputtering pressure is 0.5 Pa, the sputtering time is 20 min, and the reaction chamber temperature is 20 °C. Finally, the thickness of Pt is 80 nm as measured by the spectroscopic ellipsometer, and the deposition rate of Pt is 4 nm / min.

[0074] (6) Peeling: The method is the same as step (7) in Example 1. After peeling, the device is placed in a clean container for storage until testing.

[0075] The prepared memristor was subjected to the following electrical performance test: During the test, a semiconductor parameter tester was used to place the sample on a probe table, and two probes were respectively contacted with the electrodes to be tested. Figure 1 As shown, the Pt electrode is grounded, the Ti electrode is biased with positive and negative voltages, the voltage increases from 1 V, the scanning mode is set to bidirectional, the scanning speed is 10 mv / s, the clamping current is set to 1 mA, and when the device is activated, the scanning can be repeated; Figure 7 and Figure 8 As shown (corresponding to Example 1), from Figure 7 It can be seen that the voltage sweep range is -2-2 V. When the voltage is 1.2 V, the device resistance state begins to change from high resistance state to low resistance state and "1" state, and exhibits self-clamping characteristics, which is much smaller than the set clamping current of 1 mA. When negative voltage is added to the titanium bottom electrode, the device slowly changes from low resistance state to high resistance state and "0" state. Figure 8 In the DC IV positive voltage sweep part, the high and low configuration double logarithmic processing of the device is performed. The device operation mechanism is analyzed by fitting, and the size of the device's resistive switching window or the switching ratio can be intuitively seen. Figure 8 It can be seen that its on / off ratio is 10; Fig. 9 and Fig.10 Corresponding to Example 2, (the device preparation conditions are the same as those of Example 1, except that magnetron sputtering is used for annealing at 400°C in nitrogen in Example 2), the annealed device begins to transform into a low resistance state when a voltage less than 1V is used. Compared with Example 1, the SET voltage is reduced, and the device also exhibits self-clamping and does not require a cumbersome electrical activation process. Fig.10 It can be seen that the resistance switching window of the device is significantly increased to 80-100; Fig.11 and Fig.12As shown (corresponding to Example 3), the memristor prepared by the method in Example 3 further verifies the superiority of the gradient multilayer structure design. By optimizing the material combination, the energy consumption can be further reduced and the storage density can be improved, which can further verify the superiority of the gradient multilayer structure design. Since this paper mainly focuses on the combination of TiOx and HfOx, but is not limited to the combination of these two materials, Example 3 verifies the universality of this method. Fig.13 As shown, the dielectric layer adopts a gradient multilayer structure. When two different ranges of scanning voltages are used (-2~2 V, -2.5 V~2.5 V), two resistance states appear, which are more obvious during the Reset process, which is beneficial to improving the storage density of the device.

[0076] In summary, the performance of the memristor prepared using the method of Example 2 is optimal; wherein Voltage is voltage and Current is current.

[0077] Compared with the prior art, the top electrode, bottom electrode and dielectric layer materials used in the present invention are all relatively dense thin film materials with nanometer-level thickness. The bottom electrode is made of titanium. Titanium metal has good oxygen affinity and can absorb oxygen atoms in the dielectric layer and form an interface layer between the titanium electrode and the dielectric layer. It plays a good buffering role in the device resetting process, which helps to complete the resetting process thoroughly and quickly. At the same time, the stability and switching speed of the device are greatly improved. The dielectric layer uses hafnium oxide and titanium oxide to be alternately deposited to form a multilayer film, and the thickness of each film layer changes in a gradient, resulting in reduced device voltage and reduced energy consumption. The device is annealed in a nitrogen atmosphere to improve the switching ratio of the device. During the test process, it was unexpectedly found that the device does not require an activation process, which greatly reduces the complexity of device operation.

[0078] The present invention is not limited to the above-mentioned embodiments. On the basis of the technical solution disclosed in the present invention, technicians in this field can make some substitutions and deformations to some technical features therein according to the disclosed technical content without creative labor, and these substitutions and deformations are all within the protection scope of the present invention.

Claims

1. A memristor, comprising a bottom electrode, a dielectric layer and a top electrode arranged in sequence from bottom to top, characterized in that: The bottom electrode includes an active electrode Ag, Cu or an oxygen-philic electrode W, Ti, TiN, the top electrode includes an inert electrode Pt and Au, the dielectric layer is prepared by atomic layer deposition, and the dielectric layer is alternately formed from bottom to top, dielectric layer one, dielectric layer two, dielectric layer one, dielectric layer two, dielectric layer one, dielectric layer two... in sequence, the dielectric layer one and the dielectric layer two are two materials, the thickness of the dielectric layer one gradually decreases, and the thickness of the dielectric layer two gradually increases.

2. A memristor according to claim 1, characterized in that: The thickness of the bottom electrode is 30-200 nm.

3. A memristor according to claim 1, characterized in that: The thickness of the dielectric layer is 4-30 nm.

4. A memristor according to claim 1, characterized in that: The thickness of the top electrode is 30-200 nm.

5. A memristor according to any one of claims 1 to 4, characterized in that: The dielectric layer is a multilayer film obtained by alternately depositing any two materials of hafnium oxide, zirconium oxide, tantalum oxide, copper oxide, iron oxide, silicon oxide, titanium oxide and aluminum oxide.

6. A method for preparing the memristor according to claim 5, characterized in that: The following steps are involved: (1) Clean the surface of the Si / SiO2 substrate, blow dry it with a nitrogen gun after cleaning, use PMMA to coat, perform electron beam exposure and develop the bottom electrode pattern; (2) growing the bottom electrode by thermal evaporation at a rate of 0.1-2 Å / s, then placing the sample in acetone to reveal the bottom electrode pattern; (3) preparing a top electrode pattern intersecting with the bottom electrode by electron beam exposure; (4) The dielectric layer is prepared by atomic layer deposition at a growth temperature of 100-350 °C; (5) Depositing Pt on the sample in step (4) by radio frequency magnetron sputtering, the deposition time is 10 min, the thickness is 10-100 nm, the sputtering pressure of the radio frequency magnetron sputtering is set to 0.1-1 Pa, the atmosphere is Ar, the flow rate is 8-30 sccm, and the growth temperature is 20-100 °C. If the thickness of the deposited metal electrode is equal to the set thickness value, go to step (6); (6) Based on step (5), Au is evaporated on the surface of the Pt electrode using thermal evaporation with a thickness of 10~100 nm and a growth rate of 0.1~2 Å / s.

7. The method according to claim 6, characterized in that Ultrasonic cleaning is used in step (1), and the cleaning liquids are acetone, isopropanol or ethanol, and deionized water.

8. The method according to claim 6, characterized in that In step (2), the growth rate of the bottom electrode is 1 Å / s; in step (4), the growth temperature is 180°C; in step (5), the sputtering pressure is set to 0.95 Pa, the flow rate is 20 sccm, the growth temperature is 20-25°C, and the thickness of Pt is 14 nm; in step (6), the thickness of Au is 45 nm.

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