Antenna short circuit prevention circuit, method and computer readable storage medium

Abstract

The present invention proposes a circuit, method and computer-readable storage medium for preventing antenna short circuit faults. The circuit includes a processor module, a first charging module, a second charging module, an antenna module and a detection module. The processor module is used to send a power-off instruction to the first charging module and a charging instruction to the second charging module when receiving a fault signal sent by the detection module, and is used to send a charging instruction to the first charging module and a power-off instruction to the second charging module when receiving a running signal sent by the detection module. When an antenna short circuit fault is detected, the connection between the second power supply and the antenna module is cut off, and the first power supply and the antenna module are connected, so as to prevent the short circuit of the antenna module from causing a fault inside the television through the first charging module, and the first charging module can automatically start charging the antenna module after the short circuit fault is restored.

Description

Technical Field

[0001] The present invention relates to the field of television control, and in particular to a circuit and method for preventing antenna short circuit faults, and a computer-readable storage medium. Background Art

[0002] In the prior art, the external receiving antenna of the TV is connected to the high-frequency head terminal of the TV, and the TV broadcast signal is received and sent to the high-frequency head of the TV. The receiving antenna needs the TV to provide voltage power through the core wire of the high-frequency head. Since the receiving antenna is exposed to the outside, it is easy to short-circuit to the ground due to the influence of dust and water vapor in the air, causing the 5V power supply of the core wire of the high-frequency head of the TV to short-circuit to the ground, thereby causing the problem of TV failure. Summary of the invention

[0003] The main purpose of the present invention is to provide an antenna short circuit prevention circuit, method and computer readable storage medium, aiming to solve the problem of television malfunction caused by a receiving antenna short circuit to the ground in the prior art.

[0004] To achieve the above object, the present invention provides an antenna short circuit fault prevention circuit, the circuit comprising a processor module, a first charging module, a second charging module, an antenna module and a detection module, the output end of the processor module is respectively connected to the first charging module and the second charging module, the output end of the first charging module is connected to the antenna module, the output end of the second charging module is connected to the antenna module, the detection module is respectively connected to the processor module, the antenna module and the second charging module, wherein:

[0005] The detection module is used to send a fault signal to the processor module when a short circuit fault of the antenna module is detected, and is used to send a running signal to the processor module when a normal operation of the antenna module is detected;

[0006] The processor module is used to send a power-off instruction to the first charging module and a charging instruction to the second charging module when receiving a fault signal, and is used to send a charging instruction to the first charging module and a power-off instruction to the second charging module when receiving a running signal;

[0007] The first charging module is used to disconnect the second power supply and the antenna module when receiving a power-off instruction, and to connect the second power supply and the antenna module when receiving a charging instruction;

[0008] The second charging module is used to connect the first power supply and the antenna module when receiving a charging instruction, and disconnect the first power supply and the antenna module when receiving a power-off instruction.

[0009] Optionally, the first charging module includes a first triode, a second triode, an NMOS tube, a first resistor and a second resistor, wherein:

[0010] The base of the first transistor is connected to the first signal output end of the processor module, the base of the first transistor is also connected to the first power supply through the first resistor, the emitter of the first transistor is grounded, the collector of the first transistor is connected to the second power supply through the second resistor, the collector of the first transistor is also connected to the base of the second transistor, the emitter of the second transistor is grounded, the collector of the second transistor is connected to the gate of the NMOS tube, the drain of the NMOS tube is connected to the second power supply, and the source of the NMOS tube is connected to the antenna module.

[0011] Optionally, the processor module further includes a capacitor, wherein the capacitor is connected between the drain and the gate of the NMOS tube.

[0012] Optionally, the processor module further includes a fuse, wherein the fuse is connected between the source of the NMOS tube and the antenna module.

[0013] Optionally, the antenna module includes a tuner terminal and an active antenna, wherein a charging end of the tuner terminal is connected to a source of the NMOS tube, and the tuner terminal and the active antenna are electrically connected.

[0014] Optionally, the antenna module further includes an inductor, and the charging end of the high-frequency head terminal is connected to the source of the NMOS tube through the inductor.

[0015] Optionally, the detection module includes a fifth resistor, wherein a first end of the fifth resistor is grounded, and a second end of the fifth resistor is respectively connected to a charging end of the high-frequency head terminal, a signal input end of the processor module and the second charging module.

[0016] Optionally, the second charging module includes a third triode and a fourth resistor, wherein:

[0017] The base of the third triode is connected to the second signal output end of the processor module, the base of the third triode is also connected to the first power supply through the fourth resistor, the emitter of the third triode is connected to the first power supply, and the collector of the third triode is respectively connected to the charging end of the high-frequency head terminal and the second end of the fifth resistor.

[0018] Optionally, the second charging module further includes a third resistor, wherein the emitter of the third transistor is connected to the first power supply through the third resistor.

[0019] To achieve the above object, the present invention further provides a method for preventing antenna short circuit faults, the method being applied to the above-mentioned antenna short circuit fault prevention circuit, the method comprising the steps of:

[0020] Receive a detection signal sent by the detection module, and determine the type of the detection signal;

[0021] When the detection signal is a fault signal, sending a power-off instruction to the first charging module, and sending a charging instruction to the second charging module;

[0022] When the detection signal is an operation signal, a charging instruction is sent to the first charging module, and a power-off instruction is sent to the second charging module.

[0023] To achieve the above object, the present invention further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the method for preventing antenna short circuit failure as described above are implemented.

[0024] The present invention proposes a circuit, method and computer-readable storage medium for preventing antenna short circuit faults. The circuit includes a processor module, a first charging module, a second charging module, an antenna module and a detection module. The output end of the processor module is respectively connected to the first charging module and the second charging module, the output end of the first charging module is connected to the antenna module, and the output end of the second charging module is connected to the antenna module. The detection module is respectively connected to the processor module, the antenna module and the second charging module, wherein: the detection module is used to send a fault signal to the processor module when a short circuit fault of the antenna module is detected, and is used to detect that the antenna module is operating normally. Sending an operation signal to the processor module; the processor module is used to send a power-off instruction to the first charging module and a charging instruction to the second charging module when receiving a fault signal, and is used to send a charging instruction to the first charging module and a power-off instruction to the second charging module when receiving an operation signal; the first charging module is used to disconnect the second power supply and the antenna module when receiving a power-off instruction, and to connect the second power supply and the antenna module when receiving a charging instruction; the second charging module is used to connect the first power supply and the antenna module when receiving a charging instruction, and to disconnect the first power supply and the antenna module when receiving a power-off instruction. When an antenna short-circuit fault is detected, the connection between the second power supply and the antenna module is cut off, and the first power supply and the antenna module are connected, so as to avoid the short circuit of the antenna module from causing a fault inside the TV through the first charging module, and the first charging module can automatically start charging the antenna module after the short-circuit fault is restored. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0026] Figure 1 It is a functional module diagram of an embodiment of a circuit for preventing antenna short circuit fault of the present invention;

[0027] Figure 2 A circuit structure diagram of an embodiment of a circuit for preventing antenna short circuit faults according to the present invention;

[0028] Figure 3 FIG. 1 is a flow chart of a first embodiment of a method for preventing antenna short circuit failure according to the present invention.

[0029] Description of the accompanying drawings of an embodiment:

[0030] Label name Label name 100 Processor module R1~R5 The first resistor to the fifth resistor 200 First charging module Q1 The first three-stage tube 300 Second charging module Q2 Second and third tube 400 Antenna module Q3 NOMS tube 500 Detection module Q4 The third transistor F1 Fuse C1 capacitance L1 inductance J1 Tuner Terminal MAIN3V3 First Power MAIN5V Second power supply DETAILED DESCRIPTION

[0031] The technical solution in this embodiment will be described clearly and completely below in conjunction with the drawings in this embodiment. Obviously, the described embodiment is only a part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] It should be noted that all directional indications in this embodiment (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0033] In addition, in the present invention, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0034] In the present invention, unless otherwise clearly specified and limited, the terms "connection", "fixation", etc. should be understood in a broad sense. For example, "fixation" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0035] In addition, the technical solutions between the various embodiments of the present invention can be combined with each other, but it must be based on the fact that ordinary technicians in the field can implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention. It should be understood that the specific embodiments described here are only used to explain the present invention and are not used to limit the present invention.

[0036] The present invention provides a circuit for preventing antenna short circuit faults. Figure 1 , Figure 1 : This is a functional module diagram of the antenna short circuit fault prevention circuit of the present invention. The circuit includes a processor module 100, a first charging module 200, a second charging module 300, an antenna module 400 and a detection module 500. The output end of the processor module 100 is respectively connected to the first charging module 200 and the second charging module 300, the output end of the first charging module 200 is connected to the antenna module 400, and the output end of the second charging module 300 is connected to the antenna module 400. The detection module 500 is respectively connected to the processor module 100, the antenna module 400 and the second charging module 300, wherein:

[0037] The detection module 500 is used to send a fault signal to the processor module 100 when a short circuit fault of the antenna module 400 is detected, and to send a running signal to the processor module 100 when a normal operation of the antenna module 400 is detected;

[0038] The processor module 100 is used to send a power-off instruction to the first charging module 200 and a charging instruction to the second charging module 300 when receiving a fault signal, and is used to send a charging instruction to the first charging module 200 and a power-off instruction to the second charging module 300 when receiving a running signal;

[0039] The first charging module 200 is used to disconnect the second power supply MAIN5V and the antenna module 400 when receiving a power-off instruction, and to connect the second power supply MAIN5V and the antenna module 400 when receiving a charging instruction;

[0040] The second charging module 300 is used to connect the first power source MAIN3V3 and the antenna module 400 when receiving a charging instruction, and disconnect the first power source MAIN3V3 and the antenna module 400 when receiving a power-off instruction.

[0041] Further, refer to Figure 2 The first charging module 200 includes a first transistor Q1, a second transistor Q2, an NMOS transistor Q3, a first resistor R1 and a second resistor R2, wherein:

[0042] The base of the first transistor Q1 is connected to the first signal output terminal S1 of the processor module 100, and the base of the first transistor Q1 is also connected to the first power supply MAIN3V3 through the first resistor R1, the emitter of the first transistor Q1 is grounded, the collector of the first transistor Q1 is connected to the second power supply MAIN5V through the second resistor R2, the collector of the first transistor Q1 is also connected to the base of the second transistor Q2, the emitter of the second transistor Q2 is grounded, the collector of the second transistor Q2 is connected to the gate of the NMOS tube Q3, the drain of the NMOS tube Q3 is connected to the second power supply MAIN5V, and the source of the NMOS tube Q3 is connected to the antenna module 400.

[0043] Furthermore, the processor module 100 further includes a capacitor C1, wherein the capacitor C1 is connected between the drain and the gate of the NMOS transistor Q3.

[0044] Furthermore, the processor module 100 further includes a fuse F1 , wherein the fuse F1 is connected between the source of the NMOS transistor Q3 and the antenna module 400 .

[0045] Furthermore, the antenna module 400 includes a tuner terminal J1 and an active antenna, wherein the charging end of the tuner terminal J1 is connected to the source of the NMOS tube Q3, and the tuner terminal J1 and the active antenna are electrically connected.

[0046] Furthermore, the antenna module 400 further includes an inductor L1, and the charging end of the tuner terminal J1 is connected to the source of the NMOS tube Q3 through the inductor L1.

[0047] Furthermore, the detection module 500 includes a fifth resistor R5, wherein a first end of the fifth resistor R5 is grounded, and a second end of the fifth resistor R5 is respectively connected to a charging end of the tuner terminal J1, a signal input end of the processor module 100 and the second charging module 300.

[0048] Furthermore, the second charging module 300 includes a third transistor Q4 and a fourth resistor R4, wherein:

[0049] The base of the third transistor Q4 is connected to the second signal output terminal S2 of the processor module 100, and the base of the third transistor Q4 is also connected to the first power supply MAIN3V3 through the fourth resistor R4. The emitter of the third transistor Q4 is connected to the first power supply MAIN3V3, and the collector of the third transistor Q4 is respectively connected to the charging end of the tuner terminal J1 and the second end of the fifth resistor R5.

[0050] Furthermore, the second charging module 300 further includes a third resistor R3, wherein the emitter of the third transistor Q4 is connected to the first power source MAIN3V3 through the third resistor R3.

[0051] Combine the following Figure 2 To explain the principle:

[0052] Figure 2 The status of the active antenna connected to the high-frequency head terminal J1 is a short circuit fault to ground.

[0053] Normal working state: the active antenna connected to the high-frequency head terminal J1 is not grounded, the processor module 100 outputs a high level to the first charging module 200 through the first signal output terminal S1, the first transistor Q1 is turned on, the second transistor Q2 is turned off, the NMOS transistor Q3 is turned on, the first power supply MAIN3V3 charges the antenna module 400 through the NMOS transistor Q3, the capacitor C1 is used to adjust the switching timing of the NMOS transistor Q3, and the fuse F1 is used to disconnect when the circuit is short-circuited to prevent the circuit from being damaged. At the same time, the processor module 100 outputs a high level to the second charging module 300 through the second signal output terminal S2, the third transistor Q4 is turned off, and the second charging module 300 is disconnected from the antenna module 400.

[0054] Antenna short circuit state: When the state of the active antenna connected to the high-frequency head terminal J1 is short-circuited to the ground, the detection module 500 detects a low-level signal and sends a fault signal to the signal input end of the processor module 100. After receiving the fault signal, the processor module 100 outputs a low level to the first charging module 200 through the first signal output end S1, the first transistor Q1 is turned off, the second transistor Q2 is turned on, and the NMOS tube Q3 is turned off, disconnecting the first charging module 200 from the antenna module 400. At the same time, the processor module 100 outputs a low level to the second charging module 300 through the second signal output end S2, the third transistor Q4 is turned on, and the second power supply MAIN5V charges the antenna module 400 through the third transistor Q4. Since the third resistor R3 is provided, the short circuit will not affect the operation of the circuit system. When the fault is relieved, the detection module 500 detects a high-level signal from the second charging module 300 and sends an operation signal to the signal input end of the processor module 100. After receiving the operation signal, the processor module 100 outputs a high level to the first charging module 200 through the first signal output end S1, the first transistor Q1 is turned on, the second transistor Q2 is turned off, the NMOS tube Q3 is turned on, the first power supply MAIN3V3 charges the antenna module 400 through the NMOS tube Q3, the processor module 100 outputs a high level to the second charging module 300 through the second signal output end S2, the third transistor Q4 is turned off, and the second charging module 300 disconnects from the antenna module 400.

[0055] To achieve the above object, the present invention also provides a method for preventing antenna short circuit failure, referring to Figure 3 , Figure 3 This is a flow chart of a first embodiment of a method for preventing antenna short circuit failure according to the present invention. The method comprises the following steps:

[0056] Step S10, receiving a detection signal sent by the detection module, and determining the type of the detection signal;

[0057] The detection signal types include fault signals and operation signals. The fault signal is issued when the detection module detects that the state of the active antenna connected to the high-frequency head terminal in the antenna module is a short-circuit fault to the ground; the operation signal is issued when the detection module detects that the active antenna connected to the high-frequency head terminal in the antenna module is not a short-circuit fault to the ground.

[0058] Step S20, when the detection signal is a fault signal, sending a power-off instruction to the first charging module, and sending a charging instruction to the second charging module;

[0059] When the active antenna connected to the high-frequency head terminal is in the state of a short circuit to ground fault, the connection between the first charging module and the antenna module is disconnected to avoid damage to the internal components of the TV caused by the short circuit. The antenna module is charged through the second charging module, so that the antenna can continue to be charged while avoiding damage to the internal components of the TV.

[0060] Step S30: When the detection signal is an operation signal, a charging instruction is sent to the first charging module, and a power-off instruction is sent to the second charging module.

[0061] When the active antenna connected to the high-frequency head terminal is not short-circuited to the ground or is recovered from the short-circuit fault state, it is automatically restored to charging the antenna module through the first charging module, so that the antenna module can be charged with optimal power.

[0062] When an antenna short circuit fault is detected, the connection between the second power supply and the antenna module is cut off, and the first power supply and the antenna module are turned on, so as to prevent the short circuit of the antenna module from causing faults inside the TV through the first charging module, and the first charging module can automatically start charging the antenna module after the short circuit fault is restored.

[0063] The present invention also provides a computer-readable storage medium on which a computer program is stored. The computer-readable storage medium may be at least one of a ROM (Read-Only Memory) / RAM (Random Access Memory), a magnetic disk, and an optical disk, and the computer-readable storage medium includes a number of instructions for enabling a terminal device having a processor (which may be a television, a car, a mobile phone, a computer, a server, a terminal, or a network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0064] In the present invention, the terms "first", "second", "third", "fourth" and "fifth" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0065] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0066] Although the embodiments of the present invention have been shown and described above, the scope of protection of the present invention is not limited thereto. It is understood that the above embodiments are exemplary and cannot be understood as limiting the present invention. A person of ordinary skill in the art can change, modify and replace the above embodiments within the scope of the present invention, and these changes, modifications and replacements should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A circuit for preventing antenna short circuit fault, characterized in that: The circuit includes a processor module, a first charging module, a second charging module, an antenna module and a detection module. The output end of the processor module is connected to the first charging module and the second charging module respectively, the output end of the first charging module is connected to the antenna module, the output end of the second charging module is connected to the antenna module, and the detection module is connected to the processor module, the antenna module and the second charging module respectively, wherein: The detection module is used to send a fault signal to the processor module when a short circuit fault of the antenna module is detected, and is used to send a running signal to the processor module when a normal operation of the antenna module is detected; The processor module is used to send a power-off instruction to the first charging module and a charging instruction to the second charging module when receiving a fault signal, and is used to send a charging instruction to the first charging module and a power-off instruction to the second charging module when receiving a running signal; The first charging module is used to disconnect the second power supply and the antenna module when receiving a power-off instruction, and to connect the second power supply and the antenna module when receiving a charging instruction; The second charging module is used to connect the first power supply and the antenna module when receiving a charging instruction, and disconnect the first power supply and the antenna module when receiving a power-off instruction; Wherein, the first charging module includes a first triode, a second triode, an NMOS tube, a first resistor and a second resistor; The base of the first triode is connected to the first output end of the processor module, the base of the first triode is also connected to the first power supply through the first resistor, the emitter of the first triode is grounded, the collector of the first triode is connected to the second power supply through the second resistor, the collector of the first triode is also connected to the base of the second triode, the emitter of the second triode is grounded, the collector of the second triode is connected to the gate of the NMOS tube, the drain of the NMOS tube is connected to the second power supply, and the source of the NMOS tube is connected to the antenna module; The second charging module includes a third transistor and a fourth resistor; The base of the third triode is connected to the second output end of the processor module, the base of the third triode is also connected to the first power supply through the fourth resistor, the emitter of the third triode is connected to the first power supply, and the collector of the third triode is respectively connected to the charging end of the high-frequency head terminal and the second end of the fifth resistor.

2. The antenna short circuit protection circuit according to claim 1, characterized in that: The processor module further includes a capacitor, wherein the capacitor is connected between the drain and the gate of the NMOS tube.

3. The antenna short circuit protection circuit according to claim 1, characterized in that: The processor module further includes a fuse, wherein the fuse is connected between the source of the NMOS tube and the antenna module.

4. The antenna short circuit protection circuit according to claim 1, characterized in that: The antenna module comprises the tuner terminal and an active antenna, wherein the charging end of the tuner terminal is connected to the source of the NMOS tube, and the tuner terminal and the active antenna are electrically connected.

5. The antenna short circuit protection circuit according to claim 4, characterized in that: The detection module comprises the fifth resistor, wherein a first end of the fifth resistor is grounded, and a second end of the fifth resistor is respectively connected to a charging end of the tuner terminal, a signal input end of the processor module and the second charging module.

6. The antenna short circuit protection circuit according to claim 1, characterized in that: The second charging module further includes a third resistor, wherein the emitter of the third transistor is connected to the first power source through the third resistor.

7. A method for preventing antenna short circuit failure, characterized in that: The method is applied to the antenna short circuit fault prevention circuit according to any one of claims 1 to 6, and the method comprises the steps of: Receive a detection signal sent by the detection module, and determine the type of the detection signal; When the detection signal is a fault signal, sending a power-off instruction to the first charging module, and sending a charging instruction to the second charging module; When the detection signal is an operation signal, a charging instruction is sent to the first charging module, and a power-off instruction is sent to the second charging module.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by the processor, the steps of the method for preventing antenna short circuit failure according to claim 7 are implemented.

Images