IGBT drive interlock circuit and IGBT circuit

Abstract

The present invention discloses an IGBT drive interlocking circuit and an IGBT circuit. Two first signal channels are interlocked by a first interlocking circuit, and two second signal channels are interlocked by a second interlocking circuit. Since the first interlocking circuit and the second interlocking circuit form two-level drive interlocking protection, no matter what kind of abnormal driving signal is in the case, direct protection of the IGBT bridge arm can be achieved, effectively avoiding damage to the IGBT due to the direct connection of the IGBT bridge arm, and there is no problem of IGBT erroneous opening caused by external interference, imperfect software programming and other factors, thereby ensuring the safety of the IGBT.

Description

Technical Field

[0001] The present invention relates to the technical field of IGBT drive control, and in particular to an IGBT drive interlocking circuit and an IGBT circuit. Background Art

[0002] IGBT stands for Insulated Gate Bipolar Transistor, which is a composite fully controlled voltage-driven power semiconductor device composed of BJT (bipolar transistor) and MOS (insulated gate field effect transistor). Due to its advantages of low driving power and low saturation conduction voltage drop, it is very suitable for converter systems with a DC voltage of 600V and above, such as AC motors, inverters, switching power supplies, lighting circuits, traction drives, etc.

[0003] In the half-bridge, full-bridge and other circuit topologies that are widely used at present, IGBT plays a vital role. In the topological circuits it constitutes, due to the existence of the bridge arm, when designing the drive circuit, it is necessary to consider the protection of the IGBT to avoid the bridge arm shoot-through phenomenon. The bridge arm shoot-through will cause the bridge arm to short-circuit, and a large current will pass through the IGBT wafer instantly, thereby damaging the IGBT. In order to avoid the occurrence of the bridge arm shoot-through phenomenon, the existing conventional practice is to process the PWM signal used to drive the IGBT to turn on and off by software, and insert dead time between the complementary PWM signals output by the microprocessor (used to drive the IGBT of the upper bridge arm and the IGBT of the lower bridge arm respectively), so that the complementary PWM signals are not high or low at the same time. This processing method avoids the possibility of IGBT bridge arm shoot-through from the source, but in the actual circuit, due to the PCB routing and structural layout, the complementary PWM signal output by the microprocessor still needs to travel a certain distance to reach the IGBT gate pin. During the signal transmission process, the PWM signal is easily interfered by interference sources and power supply fluctuations, causing bridge arm shoot-through. Therefore, this control method still has defects. Summary of the invention

[0004] The main technical problem solved by the present invention is how to effectively avoid the phenomenon of IGBT being damaged due to IGBT bridge arm direct conduction in circuit topologies such as half-bridge and full-bridge.

[0005] According to the first aspect, an embodiment provides an IGBT drive interlock circuit, comprising: two first signal channels, two second signal channels, a first interlock circuit and a second interlock circuit;

[0006] The input end of each of the first signal channels is used to receive a first drive signal, to transmit the first drive signal and to perform level conversion on the first drive signal before outputting a second drive signal;

[0007] The input end of the first interlocking circuit is used to receive the first drive signal and the control enable signal, and the output end is connected to two first signal channels respectively, and is used to interlock the two first signal channels according to the levels of the input first drive signal and the control enable signal;

[0008] The input end of each second signal channel is connected to the output end of the corresponding first signal channel, and is used to transmit the second drive signal and output a third drive signal after performing level conversion processing on the second drive signal, wherein the third drive signal is used to drive the upper bridge arm IGBT or the lower bridge arm IGBT to turn off;

[0009] The second interlocking circuit is used to interlock the two second signal channels to prevent the third driving signals output by the two second signal channels from driving the upper bridge arm IGBT and the lower bridge arm IGBT to be turned on at the same time.

[0010] Further, the first interlock circuit is used to control the levels of the second drive signals output by the two first signal channels to be complementary when the levels of the two first drive signals are complementary and the control enable signal is at a high level, and the level of the second drive signal output by each first signal channel is the inverse of the level of the input first drive signal;

[0011] The first interlock circuit is further used for controlling the levels of the two second drive signals to be low when the levels of the two first drive signals are the same and the control enable signal is high;

[0012] The first interlock circuit is further configured to control the levels of the second drive signals output by the two first signal channels to be low when the control enable signal is at a low level and the levels of the two first drive signals are complementary.

[0013] Further, the second interlocking circuit is used to control the levels of the third driving signals output by the two second signal channels to be complementary when the levels of the two second driving signals are complementary, and the level of the third driving signal output by each second signal channel is the inverse of the level of the input second driving signal;

[0014] The second interlock circuit is also used to control the level of the third drive signal output by the two second signal channels to be high when the levels of the two second drive signals are both low or high, so that the third drive signal drives the upper bridge arm IGBT or the lower bridge arm IGBT to be turned off at the same time.

[0015] Further, the first signal transmission channel includes a first inverter, a first NAND gate and a second inverter;

[0016] The input end of the first inverter is used to receive the first drive signal, the output end of the first inverter is connected to the first input end of the first NAND gate, the second input end of the first NAND gate is connected to the output end of the first interlock circuit, the output end of the first NAND gate is connected to the input end of the second inverter, and the output end of the second inverter is connected to the output end of the first signal channel.

[0017] Further, the first interlocking circuit includes two first sub-interlocking modules, each of which is used to interlock one first signal transmission channel;

[0018] Each first sub-interlocking module includes a first diode and a second diode, the cathode of the first diode is used to receive a first drive signal, the anode of the second diode is used to receive a control enable signal, and the anodes of the first diode and the second diode are connected to the second input end of the first NAND gate of a first signal transmission channel.

[0019] Further, the second signal transmission channel includes a third inverter, a fourth inverter, a second NAND gate, a fifth inverter and a sixth inverter, the input end of the third inverter is connected to the input end of the second signal transmission channel, the output end of the third inverter is connected to the input end of the fourth inverter and one end of the second interlock circuit, the output end of the fourth inverter is connected to the first input end of the second NAND gate, the second input end of the second NAND gate is connected to the other end of the second interlock circuit, the output end of the second NAND gate is connected to the input end of the fifth inverter, the output end of the fifth inverter is connected to the input end of the sixth inverter, and the output end of the sixth inverter is connected to the output end of the second signal transmission channel.

[0020] Furthermore, the second interlock circuit includes two second sub-interlock modules, each second sub-interlock module includes a third diode and a fourth diode connected in parallel, the cathodes of the third diode and the fourth diode are connected to the output end of the third inverter in one second signal transmission channel, and the anodes of the third diode and the fourth diode are connected to the second input end of the second NAND gate in another second signal transmission channel.

[0021] Furthermore, it also includes two optocoupler driving circuits, the first input end of each optocoupler driving circuit is connected to the output end of a second signal transmission channel, the second input end of each optocoupler driving circuit is connected to a preset power supply, and the output end of each optocoupler driving circuit is connected to the upper bridge arm IGBT or the control end of the upper bridge arm IGBT.

[0022] Further, the first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter and the sixth inverter are all NOT gates.

[0023] According to a second aspect, an embodiment provides an IGBT circuit, comprising the IGBT drive interlock circuit described in the above embodiment and a target IGBT receiving a drive signal from the IGBT drive interlock circuit.

[0024] According to an IGBT drive interlock circuit and an IGBT circuit of the above-mentioned embodiment, two first signal channels are interlocked by a first interlock circuit, and two second signal channels are interlocked by a second interlock circuit. Due to the two-level drive interlock protection formed by the first interlock circuit and the second interlock circuit, no matter what kind of drive signal abnormality occurs, the direct-through protection of the IGBT bridge arm can be achieved, effectively avoiding damage to the IGBT due to the direct-through of the IGBT bridge arm, and there is no problem of IGBT mis-starting caused by external interference, imperfect software programming and other factors, thereby ensuring the safety of the IGBT. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A structural block diagram of an IGBT drive interlock circuit according to an embodiment;

[0026] Figure 2 A circuit diagram of a first signal transmission channel of an embodiment;

[0027] Figure 3 A circuit diagram of a second signal transmission channel according to an embodiment. DETAILED DESCRIPTION

[0028] The present invention is further described in detail below by specific embodiments in conjunction with the accompanying drawings. Wherein similar elements in different embodiments adopt associated similar element numbers. In the following embodiments, many detailed descriptions are for making the present application better understood. However, those skilled in the art can easily recognize that some features can be omitted in different situations, or can be replaced by other elements, materials, methods. In some cases, some operations related to the present application are not shown or described in the specification, this is to avoid the core part of the present application being overwhelmed by too much description, and for those skilled in the art, it is not necessary to describe these related operations in detail, and they can fully understand the related operations according to the description in the specification and the general technical knowledge in the art.

[0029] In addition, the features, operations or characteristics described in the specification can be combined in any appropriate manner to form various implementations. At the same time, the steps or actions in the method description can also be interchanged or adjusted in a manner that is obvious to those skilled in the art. Therefore, the various sequences in the specification and the drawings are only for the purpose of clearly describing a certain embodiment and are not meant to be a required sequence, unless otherwise specified that a certain sequence must be followed.

[0030] The serial numbers of the components in this document, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in this application, unless otherwise specified, include direct and indirect connections (couplings).

[0031] The full-bridge or half-bridge IGBT circuit includes an upper bridge arm branch and a lower bridge arm branch. The upper bridge arm branch and the lower bridge arm branch are respectively provided with at least one IGBT for controlling the conduction and shutdown of the corresponding branch. The IGBT is usually controlled to be turned on and off by an externally input drive signal. When the drive signal is at a high level, the corresponding IGBT is turned on, and when the drive signal is at a low level, the corresponding IGBT is turned off. When the circuit is working normally, the two drive signals of the IGBT on the upper bridge arm branch and the lower bridge arm branch are complementary. However, the two drive signals output by a control device such as a microprocessor may not be completely complementary or may be subject to external interference during transmission, resulting in the two drive signals not being completely complementary. This makes it possible for the IGBTs on the upper bridge arm branch and the lower bridge arm branch to be turned on at the same time, that is, the bridge arm direct-through phenomenon occurs.

[0032] In the embodiment of the present invention, the two first signal channels are interlocked by the first interlocking circuit, and the two second signal channels are interlocked by the second interlocking circuit. Due to the two-level drive interlocking protection formed by the first interlocking circuit and the second interlocking circuit, no matter what kind of drive signal abnormality occurs, the direct-through protection of the IGBT bridge arm is achieved, which effectively avoids the damage to the IGBT due to the direct-through of the IGBT bridge arm, and there is no problem of IGBT mis-starting caused by external interference, imperfect software programming and other factors, thereby ensuring the operating safety of the IGBT.

[0033] Please refer to Figure 1 , Figure 1 This is a structural block diagram of an IGBT drive interlock circuit of an embodiment. The IGBT drive interlock circuit provided in this embodiment includes two first signal channels 10, two second signal channels 20, a first interlock circuit 30, a second interlock circuit 40, two optocoupler drive circuits 50 and a preset power supply.

[0034] Wherein: the input end of each first signal channel 10 is connected to the first drive signal, which is used to transmit the first drive signal and output the second drive signal after level conversion processing on the first drive signal. In this embodiment, there are two first drive signals, both of which are PWM signals output by a microprocessor or other controller for driving the IGBT to turn on or off. Under normal working conditions, the levels of the two first drive signals should be complementary. In some abnormal conditions, due to programming errors of the microprocessor or other controller, the two first drive signals output by the microprocessor or other controller are both high or low in certain time periods.

[0035] The input end of the first interlock circuit 30 is connected to the first drive signal and the control enable signal, and the output end is respectively connected to the two first signal channels 10, and is used to interlock the two first signal channels 10 according to the levels of the input first drive signal and the control enable signal to prevent the second drive signal from being at a high level at the same time. The control enable signal in this embodiment is also a signal output by a control device such as a microprocessor, which is at a high level under normal working conditions.

[0036] The input end of each second signal channel 20 is connected to the output end of the corresponding first signal channel 10, and is used to transmit the second drive signal and output a third drive signal after level conversion processing on the second drive signal. The third drive signal is used to drive the upper bridge arm IGBT or the lower bridge arm IGBT to turn off.

[0037] The second interlocking circuit 40 is used to interlock the two second signal channels 20 to prevent the third driving signals output by the two second signal channels 20 from driving the upper bridge arm IGBT and the lower bridge arm IGBT to be turned on at the same time.

[0038] In one embodiment, please refer to Figure 2 , Figure 2 1 is a circuit diagram of a first signal transmission channel according to an embodiment. The first signal transmission channel 10 includes a first inverter 101 , a first NAND gate 102 and a second inverter 103 .

[0039] An input end of the first inverter 101 is connected to the first driving signal, an output end of the first inverter 102 is connected to a first input end of the first NAND gate 102, a second input end of the first NAND gate 102 is connected to an output end of the first interlock circuit 30, an output end of the first NAND gate 102 is connected to an input end of the second inverter 103, and an output end of the second inverter 103 is connected to an output end of the first signal channel 10.

[0040] Please refer to Figure 2 The first interlocking circuit 30 includes two first sub-interlocking modules, each of which is used to interlock one first signal transmission channel 10.

[0041] One of the first sub-interlocking modules includes a first diode D1 and a second diode D2, the cathode of the first diode D1 is connected to a first drive signal, the anode of the second diode D2 is connected to a control enable signal, and the anodes of the first diode D1 and the second diode D2 are connected to the second input end of a first NAND gate 102 of a first signal transmission channel 10.

[0042] Another first sub-interlocking module includes a fifth diode D5 and a sixth diode D6, the cathode of the fifth diode D5 is connected to another first drive signal, the anode of the sixth diode D6 is connected to the control enable signal, and the anodes of the fifth diode D5 and the sixth diode D6 are connected to the second input end of the first NAND gate 102 of another first signal transmission channel 10.

[0043] In one embodiment, if the levels of the two first drive signals are complementary and the control enable signal is at a high level, the first interlock circuit 30 is used to control the levels of the second drive signals output by the two first signal channels to be complementary, and the level of the second drive signal output by each first signal channel is the inverse of the level of the input first drive signal.

[0044] For example, the first drive signals input into the two first signal transmission channels are respectively a drive signal PU+ for driving the upper bridge arm IGBT and a drive signal PU- for driving the lower bridge arm IGBT, and the control enable signal is DRIVE1. At the initial moment, PU+ is at a low level, PU- is at a high level, and DRIVE1 is at a high level. PU+ is output at a high level through the first inverter 101 and enters the first input end of the first NAND gate 102. Since PU- and DRIVE1 are at a high level, the first diode D1 and the second diode D2 (the fifth diode D5 and the sixth diode D6) are in a reverse cut-off state, and the second input end of the first NAND gate 102 is at a high level, and the NAND logic of the first NAND gate 102 is valid, and the output signal of the output end is at a low level. After the inversion logic of the second inverter 103, the level of the second drive signal GDU+ is obtained to be high. Similarly, at this time, the second drive signal GDU- in the other path is at a low level.

[0045] In the embodiment of the present invention, the first interlocking circuit 30 is used to ensure that the IGBT bridge arm cannot be directly turned on in the following abnormal situations.

[0046] In one embodiment, if the levels of the two first driving signals are the same and the control enable signal is at a high level, the first interlock circuit 30 is further configured to control the levels of the two second driving signals to be at a low level.

[0047] For example, PU+ is high level, PU- is high level, DRIVE1 is high level, and the above analysis process is the same, and the GDU+ signal is low level state, and the GDU- signal is low level state. Alternatively, PU+ is low level, PU- is low level, DRIVE1 is high level, and the above analysis process is the same, and the GDU+ signal is low level state, and the GDU- signal is low level state.

[0048] In one embodiment, if the control enable signal is at a low level and the levels of the two first drive signals are complementary, the first interlock circuit 30 is further used to control the levels of the second drive signals output by the two first signal channels to be at a low level.

[0049] For example, the DRIVE1 signal is in a low level state (PU+ and PU- signals are complementary signals), and after passing through the first inverter 101, the first NAND gate 102 and the second inverter 103, the obtained GDU+ and GDU- signals are both low level signals.

[0050] The first interlocking circuit 30 in this embodiment also includes a first capacitor C1 and a first resistor R1, wherein the anode of the first diode D1 is also connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is grounded, and the anode of the fifth diode D5 is also connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to a preset power supply.

[0051] In this embodiment, the first signal transmission channel 10 further includes a second resistor R2, a third resistor R3, a fourth resistor R4 and a fifth resistor R5, wherein the input end of the first signal transmission channel 10 is connected to one end of the second resistor R2 and the third resistor R3 respectively, the other end of the second resistor R2 is connected to a preset power supply, the other end of the third resistor R3 is connected to the input end of the first inverter 101, the output end of the first inverter 101 is connected to one end of the fourth resistor R4 and the first input end of the first NAND gate 102 respectively, the other end of the fourth resistor R4 is connected to the preset power supply, the second input end of the first NAND gate 102 is connected to the positive electrode of the first diode D1 (fifth diode D50), the output end of the first NAND gate 102 is connected to the input end of the second inverter 103, and the output end of the second inverter 103 is connected to the output end of the first signal transmission channel through the fifth resistor R5. In this embodiment, the structure of another first signal transmission channel is the same as that of the first signal transmission channel, except that the fourth resistor R4 of the first signal transmission channel is replaced by the second capacitor C2, and the second capacitor C2 is grounded.

[0052] In one embodiment, please refer to Figure 3 , Figure 3The present invention is a circuit diagram of a second signal transmission channel of an embodiment, wherein the second signal transmission channel 20 comprises a third inverter 201, a fourth inverter 202, a second NAND gate 203, a fifth inverter 204 and a sixth inverter 205, wherein the input end of the third inverter 201 is connected to the input end of the second signal transmission channel 20, the output end of the third inverter 201 is connected to the input end of the fourth inverter 202 and one end of the second interlock circuit 40, the output end of the fourth inverter 202 is connected to the first input end of the second NAND gate 203, the second input end of the second NAND gate 203 is connected to the other end of the second interlock circuit 40, the output end of the second NAND gate 203 is connected to the input end of the fifth inverter 204, the output end of the fifth inverter 204 is connected to the input end of the sixth inverter 205, and the output end of the sixth inverter 205 is connected to the output end of the second signal transmission channel 20.

[0053] Please refer to Figure 3 , the second interlocking circuit 40 includes two second sub-interlocking modules.

[0054] One of the second sub-interlocking modules includes a third diode D3 and a fourth diode D4 connected in parallel, the cathodes of the third diode D3 and the fourth diode D4 are connected to the output end of the third inverter 201 in one second signal transmission channel 20, and the anodes of the third diode D3 and the fourth diode D4 are connected to the second input end of the second NAND gate 203 in another second signal transmission channel 20.

[0055] Another second sub-interlocking module includes a seventh diode D7 and an eighth diode D8 connected in parallel, wherein the cathodes of the seventh diode D7 and the eighth diode D8 are connected to the output end of the third inverter 201 in another second signal transmission channel 20, and the anodes of the seventh diode D7 and the eighth diode D8 are connected to the second input end of the second NAND gate 203 in another second signal transmission channel 20.

[0056] In one embodiment, if the levels of the two second drive signals are complementary, the second interlock circuit 40 is used to control the levels of the third drive signals output by the two second signal channels 20 to be complementary, and the level of the third drive signal output by each second signal channel 20 is the inverse of the level of the input second drive signal.

[0057] For example, GDU+ is high level, GDU- is low level, GDU+ is converted to high level state through two-stage reverse logic of the third inverter 201 and the fourth inverter 202; GDU- signal is also converted to low level state through two-stage reverse logic of the third inverter 201 and the fourth inverter 202. Since the third diode D3 and the fourth diode D4 are forward-conducted when the first input of the second NAND gate is in low level state, the second input of the second NAND gate is in low level state, and the output of the second NAND gate is low level at this time. Through the two-stage NOT gate logic of the fifth inverter and the sixth inverter, the upper bridge drive control signal (one third drive signal) is obtained as a low level signal, the upper bridge drive circuit is turned on, and the upper bridge arm is turned on; similarly, the lower bridge drive control signal (another third drive signal) is obtained as a high level signal, the lower bridge drive circuit is not turned on, and the lower bridge arm is not turned on.

[0058] In one embodiment, when the levels of the two second drive signals are both low or high, the second interlock circuit 40 is also used to control the level of the third drive signal output by the two second signal channels to be high, so that the third drive signal drives the upper bridge arm IGBT or the lower bridge arm IGBT to be turned off at the same time.

[0059] For example, if both GDU+ and GDU- signals are in high-level states, the final third drive signal is a high-level signal, so the upper bridge of the IGBT cannot be turned on; similarly, the lower bridge cannot be turned on. Alternatively, if both GDU+ and GDU- are in low-level states, the final third drive signal for driving the upper bridge branch is a high-level signal, and the third drive signal for driving the lower bridge branch is also a high-level signal. Therefore, the drive circuits of the upper and lower bridges are not conducting, and the upper and lower bridge arms of the IGBT are not conducting.

[0060] The second signal transmission channel 20 in this embodiment further includes a third capacitor C3, a fourth capacitor C4, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8 and a ninth resistor R9. The input end of the second signal transmission channel 20 is respectively connected to one end of the seventh resistor R7 and the input end of the third inverter 201 through the sixth resistor R6, the other end of the seventh resistor R7 is grounded, the third capacitor C3 is connected in parallel to both ends of the seventh resistor R7, one end of the fourth capacitor C4 is connected to the second input end of the second NAND gate 203, the other end of the fourth capacitor C4 is grounded, one end of the eighth resistor R8 is also connected to the second input end of the second NAND gate 203, the other end of the eighth resistor R8 is connected to a preset power supply, the output end of the second NAND gate 203 is connected to one end of the ninth resistor R9 after passing through the fifth inverter 204 and the sixth inverter 205 in sequence, and the other end of the ninth resistor R9 is connected to the output end of the second signal transmission channel 20.

[0061] In this embodiment, the first inverter 101 , the second inverter 102 , the third inverter 201 , the fourth inverter 202 , the fifth inverter 204 and the sixth inverter 205 are all NOT gates.

[0062] Since the driving of the IGBT needs to be carried out through an optocoupler driving circuit, the present embodiment also includes two optocoupler driving circuits 50, the first input end of each optocoupler driving circuit 50 is connected to the output end of a second signal transmission channel 20, the second input end of each optocoupler driving circuit 50 is connected to a preset power supply, and the output end of each optocoupler driving circuit 50 is connected to the upper bridge arm IGBT or the control end of the upper bridge arm IGBT.

[0063] The optocoupler driving circuit 50 of the present embodiment includes an optocoupler chip U1, a tenth resistor R10 and a fifth capacitor C5, wherein one end of the tenth resistor R10 is connected to the VIN-end (first input end) of the optocoupler chip U1, the other end of the tenth resistor R10 is respectively connected to the preset power supply and the VIN+end (second input end) of the optocoupler chip U1, the fifth capacitor C5 is connected in parallel to the two ends of the tenth resistor R10, the VO end of the optocoupler chip U1 is connected to the output end of the optocoupler driving circuit 50, and is connected to the control end of the IGBT to drive the IGBT to turn on and off. The model of the optocoupler chip U1 in the present embodiment is M57962.

[0064] The preset power sources in this embodiment are all +5V DC voltage sources, and the connections mentioned in this embodiment are circuit or signal connections.

[0065] This embodiment further provides an IGBT circuit, comprising the IGBT drive interlock circuit described in the above embodiment and a target IGBT receiving a drive signal from the IGBT drive interlock circuit. The specific implementation of the IGBT drive interlock circuit has been described in detail in the above embodiment and will not be repeated here.

[0066] The above specific examples are used to illustrate the present invention, which is only used to help understand the present invention and is not intended to limit the present invention. For those skilled in the art, according to the concept of the present invention, some simple deductions, modifications or substitutions can be made.

Claims

1. An IGBT drive interlock circuit, characterized in that: include: Two first signal channels, two second signal channels, a first interlocking circuit and a second interlocking circuit; The input end of each of the first signal channels is used to receive a first drive signal, to transmit the first drive signal and to perform level conversion on the first drive signal before outputting a second drive signal; The input end of the first interlocking circuit is used to receive the first drive signal and the control enable signal, and the output end is connected to two first signal channels respectively, and is used to interlock the two first signal channels according to the levels of the input first drive signal and the control enable signal; The input end of each second signal channel is connected to the output end of the corresponding first signal channel, and is used to transmit the second drive signal and output a third drive signal after performing level conversion processing on the second drive signal, wherein the third drive signal is used to drive the upper bridge arm IGBT or the lower bridge arm IGBT to turn off; The second interlocking circuit is used to interlock the two second signal channels to prevent the third driving signals output by the two second signal channels from driving the upper bridge arm IGBT and the lower bridge arm IGBT to be turned on at the same time; The first signal transmission channel includes a first inverter, a first NAND gate and a second inverter; The input end of the first inverter is used to receive the first drive signal, the output end of the first inverter is connected to the first input end of the first NAND gate, the second input end of the first NAND gate is connected to the output end of the first interlock circuit, the output end of the first NAND gate is connected to the input end of the second inverter, and the output end of the second inverter is connected to the output end of the first signal channel.

2. The IGBT drive interlock circuit according to claim 1, characterized in that: The first interlock circuit is used to control the levels of the second drive signals output by the two first signal channels to be complementary when the levels of the two first drive signals are complementary and the control enable signal is at a high level, and the level of the second drive signal output by each first signal channel is the inverse of the level of the input first drive signal; The first interlock circuit is further used for controlling the levels of the two second drive signals to be low when the levels of the two first drive signals are the same and the control enable signal is high; The first interlock circuit is further configured to control the levels of the second drive signals output by the two first signal channels to be low when the control enable signal is at a low level and the levels of the two first drive signals are complementary.

3. The IGBT drive interlock circuit according to claim 1, characterized in that: The second interlocking circuit is used to control the levels of the third driving signals output by the two second signal channels to be complementary when the levels of the two second driving signals are complementary, and the level of the third driving signal output by each second signal channel is the inverse of the level of the input second driving signal; The second interlock circuit is also used to control the level of the third drive signal output by the two second signal channels to be high when the levels of the two second drive signals are both low or high, so that the third drive signal drives the upper bridge arm IGBT or the lower bridge arm IGBT to be turned off at the same time.

4. The IGBT drive interlock circuit according to claim 1, characterized in that: The first interlocking circuit includes two first sub-interlocking modules, each of which is used to interlock a first signal transmission channel; Each first sub-interlocking module includes a first diode and a second diode, the cathode of the first diode is connected to receive a first drive signal, the anode of the second diode is used to receive a control enable signal, and the anodes of the first diode and the second diode are connected to the second input end of the first NAND gate of a first signal transmission channel.

5. The IGBT drive interlock circuit according to claim 1, characterized in that: The second signal transmission channel includes a third inverter, a fourth inverter, a second NAND gate, a fifth inverter and a sixth inverter, wherein the input end of the third inverter is connected to the input end of the second signal transmission channel, the output end of the third inverter is connected to the input end of the fourth inverter and one end of the second interlock circuit, the output end of the fourth inverter is connected to the first input end of the second NAND gate, the second input end of the second NAND gate is connected to the other end of the second interlock circuit, the output end of the second NAND gate is connected to the input end of the fifth inverter, the output end of the fifth inverter is connected to the input end of the sixth inverter, and the output end of the sixth inverter is connected to the output end of the second signal transmission channel.

6. The IGBT drive interlock circuit according to claim 5, characterized in that: The second interlock circuit includes two second sub-interlock modules, each of which includes a third diode and a fourth diode connected in parallel, wherein the cathodes of the third diode and the fourth diode are connected to the output end of the third inverter in one second signal transmission channel, and the anodes of the third diode and the fourth diode are connected to the second input end of the second NAND gate in another second signal transmission channel.

7. The IGBT drive interlock circuit according to any one of claims 1 to 6, characterized in that: It also includes two optocoupler drive circuits, wherein the first input end of each optocoupler drive circuit is connected to the output end of a second signal transmission channel, the second input end of each optocoupler drive circuit is connected to a preset power supply, and the output end of each optocoupler drive circuit is connected to the upper bridge arm IGBT or the control end of the upper bridge arm IGBT.

8. The IGBT drive interlock circuit according to any one of claims 1 to 6, characterized in that: The first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter and the sixth inverter are all NOT gates.

9. An IGBT circuit, characterized in that: The invention comprises the IGBT drive interlock circuit according to any one of claims 1 to 8 and a target IGBT receiving a drive signal of the IGBT drive interlock circuit.

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