Image sensor and method of forming the same

Abstract

Various embodiments of the present invention are directed to an image sensor including a light pipe structure. A light detector is disposed in a semiconductor substrate. A gate electrode is disposed on the semiconductor substrate and adjacent to the light detector. An inter-level dielectric layer overlies the semiconductor substrate. A conductive contact is disposed in the inter-level dielectric layer such that a bottom surface of the conductive contact is lower than a top surface of the gate electrode. The light pipe structure overlies the light detector such that a bottom surface of the light pipe structure is recessed below a top surface of the conductive contact.

Description

Technical Field

[0001] The embodiments of the present invention relate to an image sensor, a complementary metal oxide semiconductor image sensor and a method for forming the same. Background Art

[0002] Integrated Circuits (ICs) with image sensors are used in a wide variety of modern electronic devices, such as cameras and cell phones. Complementary metal-oxide semiconductor (CMOS) devices have become popular IC image sensors. Compared with charge-coupled devices (CCDs), CMOS image sensors are becoming increasingly popular due to their low power consumption, small size, fast data processing, direct data output, and low manufacturing cost. Some types of CMOS image sensors include front-side illuminated (FSI) image sensors and back-side illuminated (BSI) image sensors. Summary of the invention

[0003] In some embodiments, the present application provides an image sensor, the image sensor comprising: a semiconductor substrate; a photodetector disposed in the semiconductor substrate; a gate electrode overlying the semiconductor substrate and adjacent to the photodetector; an inter-level dielectric (ILD) layer overlying the semiconductor substrate; a conductive contact located in the inter-level dielectric layer, wherein a bottom surface of the conductive contact is lower than a top surface of the gate electrode; and a light pipe structure overlying the photodetector, wherein a bottom surface of the light pipe structure is recessed to be lower than a top surface of the conductive contact.

[0004] In some embodiments, the present application provides a complementary metal oxide semiconductor (CMOS) image sensor, the complementary metal oxide semiconductor image sensor comprising: a substrate; a photodetector disposed in the substrate; an interconnect structure comprising an inter-level dielectric (ILD) layer, an inter-metal dielectric (IMD) structure overlying the ILD layer, and conductive lines in the IMD structure, wherein the interconnect structure overlies the substrate and is selectively electrically coupled to the photodetector; and a light pipe structure overlying the photodetector and extending continuously from a top of the IMD structure to a point below a bottom surface of a bottommost conductive line of the interconnect structure.

[0005] In some embodiments, the present application provides a method for forming an image sensor, the method comprising: forming a photodetector in a semiconductor substrate; forming a lower interconnect portion of an interconnect structure above the photodetector; performing a first removal process to define a first opening in the lower interconnect portion overlying the photodetector; forming a lower etch stop layer to line the first opening, wherein the lower etch stop layer has a U-shape in the first opening; forming an upper interconnect portion of the interconnect structure over the lower etch stop layer; and forming a light pipe structure overlying the photodetector, wherein the U-shape of the lower etch stop layer extends continuously along sidewalls and a bottom surface of the light pipe structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 Cross-sectional views of some embodiments of image sensors including a light pipe structure overlying a light detector are illustrated, wherein a bottom surface of the light pipe structure extends below a bottom-most conductive line.

[0008] Figure 2A and Figure 2B illustrate Figure 1 Cross-sectional views of various alternative embodiments of image sensors are shown, wherein the image sensors further include bond pads overlying the conductive layer stack.

[0009] Figure 3 Cross-sectional views illustrating some embodiments of an image sensor including a light pipe structure positioned above a photodetector and further including a transistor adjacent to the photodetector, wherein the transistor is electrically coupled to an overlying bond pad via an interconnect structure.

[0010] Figures 4 to 15 A series of cross-sectional views illustrating some embodiments of a method for forming an image sensor including a light pipe structure over a photodetector and also including a transistor adjacent to the photodetector.

[0011] Fig.16 illustrate Figures 4 to 15 Block diagram of some embodiments of the illustrated method. DETAILED DESCRIPTION

[0012] The present invention provides many different embodiments or examples to implement different features of the present invention. Specific examples of components and arrangements are described below to make the present invention concise. Of course, these are only examples and are not intended to be limiting. For example, in the following description, a first feature formed on or formed on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature cannot be directly contacted. In addition, the present invention may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not essentially specify the relationship between the various embodiments and / or configurations described.

[0013] Additionally, for ease of description, spatially relative terms such as "below," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or feature, as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0014] A front side illuminated (FSI) image sensor may, for example, include light pipe structures that overlie the photodetectors, respectively. The light pipe structures are configured to direct incident radiation to the photodetectors below by total internal reflection (TIR), thereby improving the quantum efficiency (QE) of the image sensor. The photodetectors are disposed within a semiconductor substrate. An interconnect structure overlies the semiconductor substrate. The interconnect structure includes an alternating stack of wiring layers (e.g., horizontal wiring) and via layers (e.g., vertical wiring), the alternating stacks disposed within the interconnect dielectric structure.

[0015] The light pipe structure may be formed by first fully forming or substantially forming the interconnect structure, and then performing an etching process (e.g., a dry etching process) through the interconnect dielectric structure, thereby forming an opening above each photodetector. The light pipe structure may then be formed in the opening. However, because the opening extends deeply into the interconnect structure, the etching may be performed, for example, by a plasma etch having a high power and, therefore, a high electric field strength. This may cause electrons to accumulate on the semiconductor substrate, thereby increasing dark current and / or increasing the number of white pixels present in the image sensor. Furthermore, physical bombardment from ions in the plasma may damage the interconnect dielectric structure and / or damage the crystalline structure of the semiconductor substrate, thereby reducing the structural integrity of the interconnect dielectric structure and / or further increasing dark current and / or the number of white pixels. Furthermore, the high power and long duration etching process may result in the light pipe structures having very different heights. Thus, each of the light pipe structures extends from the top of the interconnect structure to a different point above the semiconductor substrate, which may result in each light pipe structure having a different height. It has been recognized that height differences between light pipe structures can lead to non-uniformity between photodetectors (eg, a first photodetector may receive less incident radiation than an adjacent second photodetector) and can reduce the overall quantum efficiency of the image sensor.

[0016] Various embodiments of the present application are directed to a method of forming a light pipe structure that improves quantum efficiency of an image sensor and reduces dark current and / or the number of white pixels. In some embodiments, the method includes: forming a lower interconnect portion of an interconnect structure above a photodetector; and then performing a first low-power etch in the lower interconnect portion to form an opening. Forming a lower etch stop layer to line the opening, and the lower etch stop layer has a U-shaped profile in the opening. Forming an upper interconnect portion of an interconnect dielectric structure above the lower etch stop layer and the lower interconnect portion. Performing a second etch process in the upper interconnect portion to form a light pipe opening overlying the photodetector. Forming an upper etch stop layer to line the sidewalls of the light pipe opening. Performing a wet etch process to expand the light pipe opening and remove excess material of the upper interconnect portion overlying the lower etch stop layer. Forming the light pipe structure in the light pipe opening so that a bottom surface of the light pipe structure is lower than a bottommost wiring layer of the interconnect structure. Using a low power etching process to form the opening and forming a lower etch stop layer within the opening can reduce damage to the crystalline structure of the semiconductor substrate, thereby reducing dark current and / or the number of white pixels in the image sensor. In addition, the wet etching process can form the light pipe opening while avoiding plasma damage that can occur during dry etching processes, thereby reducing the accumulation of electrons on the semiconductor substrate. In addition, the bottom surface of the light pipe structure extends below the bottommost wiring layer to improve the quantum efficiency and uniformity between light detectors in the image sensor.

[0017] refer to Figure 1 , a cross-sectional view of some embodiments of image sensor 100 including light pipe structure 115 overlying light detector 104 is provided, wherein a bottom surface 115 b of light pipe structure 115 extends below bottom-most conductive line 112 .

[0018] Light pipe structure 115 overlies light detector 104 within semiconductor substrate 102. In some embodiments, semiconductor substrate 102 may be, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or some other suitable substrate having a first doping type (e.g., p-type). In other embodiments, semiconductor substrate 102 may include three layers (e.g., silicon overlying an oxide and silicon below the oxide) such that a topmost layer of the three layers is epitaxial silicon that is doped n-type. Light detector 104 has a second doping type (e.g., n-type) that is opposite to the first doping type. Light detector 104 is configured to absorb incident radiation 120 (e.g., photons) and generate an electrical signal corresponding to incident radiation 120. In some embodiments, a depletion region is formed along a boundary of light detector 104 (e.g., due to a pn junction between light detector 104 and an adjacent doped region of semiconductor substrate 102).

[0019] Floating diffusion node 106 is disposed in semiconductor substrate 102 laterally offset from photodetector 104. Floating diffusion node 106 is located in semiconductor substrate 102 having a second doping type (e.g., n-type). Transfer transistor 110 is disposed on semiconductor substrate 102 and laterally between photodetector 104 and floating diffusion node 106. Transfer transistor 110 can, for example, selectively form a conductive channel between photodetector 104 and floating diffusion node 106 to transfer charges accumulated in photodetector 104 to floating diffusion node 106. The accumulated charges can, for example, be generated by absorbing incident radiation 120.

[0020] An interconnect structure 107 overlies the semiconductor substrate 102. The interconnect structure 107 includes conductive vias (e.g., conductive contacts 108), conductive lines (e.g., bottommost conductive lines 112), and dielectric layers and / or dielectric structures (e.g., lower inter-level dielectric (ILD) structures 109). The lower ILD structure 109 overlies the semiconductor substrate 102 and the transfer transistor 110. The conductive contact 108 overlies the floating diffusion node 106 and extends through the lower ILD structure 109 to electrically couple the floating diffusion node 106 to the bottommost conductive line 112. In some embodiments, silicide may be disposed between the conductive contact 108 and the semiconductor substrate 102 (not shown). A lower etch stop structure 114 is disposed between the lower ILD structure 109 and the overlying upper ILD structure 116. The lower etch stop structure 114 has a U-shaped profile directly above the photodetector 104. The upper etch stop structure 118 extends through the upper ILD structure 116 to the lower etch stop structure 114 .

[0021] Light pipe structure 115 extends from the top of interconnect structure 107 to below the bottom surface of bottom-most conductive line 112. In some embodiments, light pipe structure 115 includes a first dielectric material having a first refractive index (e.g., greater than 2.6), lower etch stop structure 114 includes a second dielectric material having a second refractive index (e.g., approximately 2.6), and upper etch stop structure 118 includes a third dielectric material having a third refractive index (e.g., approximately 2). In some embodiments, the first refractive index is greater than the second and third refractive indices. Because the first refractive index is greater than the second and third refractive indices, incident radiation 120 is confined into light pipe structure 115 (e.g., due to total internal reflection) and directed toward light detector 104. Additionally, because the second and third refractive indices are less than the first refractive index, most incident radiation 120 disposed on interconnect structure 107 directly above light detector 104 is directed into light pipe structure 115 and refracted toward light detector 104.

[0022] Bottom surface 115b of light pipe structure 115 extends below top surface of conductive contact 108 by distance d1. In some embodiments, distance d1 is in a range of about 50 angstroms to about 1500 angstroms. In some embodiments, if distance d1 is small (e.g., less than about 50 angstroms), the height of light pipe structure 115 is reduced. This may partially reduce incident radiation 120 disposed on photodetector 104, thereby reducing quantum efficiency (QE) of image sensor 100. In other embodiments, if distance d1 is large (e.g., greater than about 1500 angstroms), physical bombardment (e.g., ions from a plasma used during formation of light pipe structure 115) may damage interconnect structure 107 and / or damage the crystalline structure of semiconductor substrate 102. This may partially reduce the structural integrity of interconnect structure 107, increase dark current in photodetector 104 and / or white pixels in image sensor 100. In another embodiment, the lower ILD structure 109 includes a fourth dielectric material (e.g., an oxide, such as silicon oxide) having a fourth refractive index (e.g., approximately 1.46) that is less than the first refractive index. In other embodiments, the upper ILD structure 116 includes an oxide having a fifth dielectric material having a refractive index of approximately 1.3.

[0023] In some embodiments, Figure 1 18, light pipe structure 115 extends continuously along the substantially straight inner sidewalls of upper etch stop structure 118. In further embodiments, the top surface of light pipe structure 115 is substantially aligned with the top surface of upper etch stop structure 118. The upper surface of light pipe structure 115 directly contacts the bottom surface of upper etch stop structure 118. Lower etch stop structure 114 extends continuously along and cups around the outermost sidewalls and bottom surface 115b of light pipe structure 115. In some embodiments, the outermost sidewalls of light pipe structure 115 are laterally located between the outer sidewalls of light detector 104. Bottom surface 115b of light pipe structure 115 and the top surface of light detector 104 can be separated, for example, by a lower segment of lower etch stop structure 114 and lower ILD structure 109. The light pipe structure 115 is recessed into the lower ILD structure 109 such that a bottom surface 115b of the light pipe structure 115 is lower than a top surface of the lower ILD structure 109. The lower ILD structure 109 extends continuously along the outermost sidewall and the bottom surface 115b of the light pipe structure 115 and cup-shapedly surrounds the outermost sidewall and the bottom surface 115b. The transfer transistor 110 is laterally disposed between the light pipe structure 115 and the conductive contact 108. The bottom surface 115b of the light pipe structure 115 is laterally disposed above a top surface of the transfer transistor 110. The light pipe structure 115 is laterally located between the outer sidewall of the light detector 104 and the transfer transistor 110.

[0024] refer to Figure 2A , provide the basis Figure 1 A cross-sectional view of an image sensor 200 a of some alternative embodiments of image sensor 100 is shown, wherein bonding pad 220 overlies transfer transistor 110 .

[0025] Image sensor 200a includes interconnect structure 107 overlying semiconductor substrate 102. Deep isolation structure 202 is disposed in semiconductor substrate 102 adjacent to photodetector 104. In some embodiments, deep isolation structure 202 may be, for example, a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, etc. In other embodiments, deep isolation structure 202 includes a dielectric material and / or extends from front side surface 102f of semiconductor substrate 102 to back side surface 102b of semiconductor substrate 102. Deep isolation structure 202 is configured to electrically isolate photodetector 104 from adjacent semiconductor devices (e.g., adjacent photodetectors) (not shown).

[0026] Transfer transistor 110 is disposed between floating diffusion node 106 and photodetector 104. In some embodiments, transfer transistor 110 includes a transfer gate electrode 234 overlying a transfer gate dielectric 232, and further includes sidewall spacers 230 adjacent to transfer gate electrode 234 and transfer gate dielectric 232. In the aforementioned embodiments, a voltage may be applied to transfer gate electrode 234 to control the transfer of charge accumulated in photodetector 104 (e.g., via absorption of incident radiation) to floating diffusion node 106.

[0027] The interconnect structure 107 overlies the front surface 102f of the semiconductor substrate 102 so that the image sensor 200a can be configured as a front side illuminated (FSI) image sensor, for example. In some embodiments, the interconnect structure 107 includes a conductive contact 108 disposed in the interconnect dielectric structure 201, a bonding pad 220, the interconnect dielectric structure 201, conductive wiring layers 210a to 210d, and a conductive via 208. The conductive contact 108 is disposed between the bottommost conductive wiring layer 210a and the floating diffusion node 106. The conductive via 208 is disposed between the conductive wiring layers 210a to 210d. The interconnect dielectric structure 201 includes a plurality of dielectric layers. The interconnect dielectric structure 201 includes a lower ILD structure 109, a lower etch stop structure 114, inter-wiring buffer layers 204a to 204d, an upper etch stop structure 118, inter-metal dielectric (IMD) layers 206a to 206d, and passivation layers 214a to 214b. In some embodiments, the bottom surface of the upper etch stop structure 118 is disposed lower than the upper surface of the bottommost conductive wiring layer 210a.

[0028] In some embodiments, the lower ILD structure 109 may be, for example, or include one or more dielectric materials (e.g., oxide, silicon oxide, low-k dielectric, etc.), and / or may have a thickness in the range of about 2500 angstroms to 5000 angstroms, for example. As used herein, a low-k dielectric is a dielectric material having a dielectric constant less than 3.9. In further embodiments, the lower etch stop structure 114 may be, for example, or include silicon carbide, etc., and / or may have a thickness in the range of about 200 angstroms to 500 angstroms, for example. In other embodiments, the inter-wiring buffer layers 204a to 204c may be, for example, or include silicon carbide, etc., respectively, and / or may have a thickness in the range of about 200 angstroms to 500 angstroms, respectively. In some embodiments, the upper etch stop structure 118 and the inter-wiring buffer layer 204d may be, for example, or include silicon nitride, respectively, and / or may have a thickness in the range of about 250 angstroms to 750 angstroms, for example. In further embodiments, the IMD layers 206a-206d may be or include oxide, silicon oxide, low-k dielectric, etc., respectively, and / or may have a thickness in the range of about 1000 to 3000 angstroms, respectively, for example. In other embodiments, the passivation layers 214a-214b may be or include oxide, silicon oxide, low-k dielectric, silicon nitride, etc., respectively, for example, and / or may have a thickness in the range of about 500 to 2000 angstroms, respectively. In some embodiments, the conductive contacts 108, the conductive vias 208, and the conductive wiring layers 210a-210d may be or include metal materials, such as copper, tungsten, aluminum, etc., for example.

[0029] Conductive vias 208 and conductive wiring layers 210a to 210d extend through the interconnect dielectric structure 201 and facilitate electrical coupling between the underlying contact region (e.g., floating diffusion node 106) and / or the underlying semiconductor device (e.g., transfer transistor 110) and the overlying metal layer (e.g., bonding pad 220). In some embodiments, bonding pad 220 can electrically couple the uppermost conductive wiring layer 210d to a semiconductor device disposed on an external device (not shown). Solder bumps 222 are disposed on bonding pad 220 to facilitate coupling between bonding pad 220 and an external input / output (I / O) pin of the integrated chip package. Pad dielectric layer 218 is disposed between bonding pad 220 and the uppermost conductive wiring layer 210d.

[0030] The conductive contact 108 overlies the floating diffusion node 106 and can facilitate the transfer of charge at the floating diffusion node 106 to an overlying metal layer (e.g., the bonding pad 220). In some embodiments, the bottom surface of the conductive contact 108 is aligned with the front side surface 102f of the semiconductor substrate 102 and directly contacts the front side surface 102f. In other embodiments, the bottom surface of the conductive contact 108 extends below the front side surface 102f of the semiconductor substrate 102 (not shown). In other embodiments, the bottom surface of the conductive contact 108 is higher than the front side surface 102f of the semiconductor substrate 102 and can be electrically coupled to the semiconductor substrate through, for example, silicide, doped silicon and / or polysilicon (not shown). The bottom surface 115b of the light pipe structure 115 extends below the top surface of the conductive contact 108. In some embodiments, different conductive contacts overlie the transfer gate electrode 234 so that the bottom surface 115b of the light pipe structure 115 extends below the top surface of the different conductive contacts (not shown).

[0031] The light pipe structure 115 extends through the interconnect dielectric structure 201 and terminates below the bottom surface of the bottommost conductive wiring layer 210a. In some embodiments, the light pipe structure 115 has a first width W1 and a second width W2, the first width W1 being greater than the second width W2. Incident radiation disposed on the interconnect structure 107 directly above the photodetector 104 is confined into the light pipe structure 115 (e.g., due to total internal reflection) and directed to the photodetector 104. The bottom surface 115b of the light pipe structure 115 is disposed below the bottom surface of the bottommost conductive wiring layer 210a by a distance d1. As a result, the thickness t1 of the lower ILD structure 109 between the bottom surface of the lower etch stop structure 114 and the front side surface 102f of the semiconductor substrate 102 is reduced. This partially reduces the reflection and / or absorption of the incident radiation by the lower ILD structure 109, thereby improving the quantum efficiency of the image sensor 200a.

[0032] A first width W1 is defined between opposing sidewalls 114s1, 114s2 of lower etch stop structure 114. In some embodiments, first width W1 is in a range of about 1 micron to 3.5 microns. A second width W2 is defined between opposing sidewalls 118s1, 118s2 of upper etch stop structure 118. In some embodiments, second width W2 is in a range of about 1 micron to 3 microns. In other embodiments, if second width W2 is 1 micron or greater, incident radiation disposed on photodetector 104 is increased while incident radiation reflected away from photodetector 104 by interconnect structure 107 is reduced. This may, in part, improve the overall quantum efficiency of image sensor 200a. In other embodiments, if second width W2 is 3 microns or less, incident radiation disposed on photodetector 104 is further increased while reducing the cost associated with forming light pipe structure 115. This may, in part, further improve the overall quantum efficiency of image sensor 200a. In some embodiments, the absolute value of the difference between the first width W1 and the second width W2 (ie, |W1-W2|) is less than 0.5 microns. In other embodiments, if the difference is greater than, for example, 0.5 microns, the structural integrity of the light pipe structure 115 may be reduced.

[0033] Additionally, in some embodiments, photodetectors 104 may be located in an array of photodetectors such that the array includes a plurality of photodetectors arranged in rows and columns. Light pipe structures directly overlie each photodetector in the array. The light pipe structures may each be configured as light pipe structures 115 such that a bottom surface of each light pipe structure extends through interconnect dielectric structure 201 and terminates below a bottom surface of bottommost conductive wiring layer 210a. This may partially improve uniformity of the photodetectors across the array (e.g., a first photodetector may receive approximately the same amount of incident radiation as an adjacent second photodetector), thereby improving the overall quantum efficiency of image sensor 200a.

[0034] The anti-reflection layer 216 contacts the light pipe structure 115 and is configured to reduce the amount of incident radiation reflected by the interconnect structure 107. In some embodiments, the anti-reflection layer 216 can be or include, for example, an oxide, a high-k dielectric, a nitride, etc. A color filter 226 is disposed on the anti-reflection layer 216. The color filter 226 is configured to transmit incident radiation of a particular wavelength and block radiation of other wavelengths. In addition, the microlens 224 overlies the color filter 226 and is configured to focus the incident radiation toward the light detector 104.

[0035] refer to Figure 2B , provide the basis Figure 2A1 and 1 , and a cross-sectional view of an image sensor 200b of some alternative embodiments of the image sensor 200a is shown, wherein the lower etch stop structure 114 includes a first lower etch stop layer 114a and a second lower etch stop layer 114b, wherein the first lower etch stop layer 114a is located below the second lower etch stop layer 114b. The second lower etch stop layer 114b has a U-shaped profile directly above the photodetector 104. The lower etch stop structure 114 overlies the second bottommost conductive wiring layer 210b. The bottom surface of the upper etch stop structure 118 is disposed above the top surface of the bottommost conductive wiring layer 210a. The upper etch stop structure 118 has a first thickness t between the top surface of the bottommost conductive wiring layer 210a and the top surface of the lower etch stop structure 114. et1 In some embodiments, the first thickness t et1 In addition, the upper etch stop structure 118 has a second thickness t above the bottom surface of the second bottommost conductive wiring layer 210b. et2 In some embodiments, the second thickness t et2 In the range of about 250 angstroms to 750 angstroms.

[0036] refer to Figure 3 , provide the basis Figure 2A A cross-sectional view of an image sensor 300 of some alternative embodiments of the image sensor 200a is shown, wherein a reset transistor 304 is disposed between the floating diffusion node 106 and the contact region 302. In some embodiments, the reset transistor 304 includes a reset gate electrode overlying a reset gate dielectric and further includes sidewall spacers adjacent to the reset gate electrode and the reset gate dielectric. In some embodiments, the contact region 302 is electrically coupled to a power source (e.g., a direct current (DC) power source) that supplies a reset voltage (e.g., 5 volts) via the interconnect structure 107. In other embodiments, the reset gate voltage is applied to the reset gate electrode to apply the reset voltage to the floating diffusion node 106. The conductive contact 108, the conductive wiring layers 210a to 210d, the conductive via 208, and the bonding pad 220 overlie the contact region 302 and may, for example, be configured to electrically couple the contact region 302 to a power source (not shown). The shallow isolation structure 306 is adjacent to the contact region 302 and is configured to electrically isolate the contact region 302 from adjacent semiconductor devices, adjacent contact regions, and / or adjacent source / drain regions (not shown). In some embodiments, the shallow isolation structure 306 may be, for example, a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, etc.

[0037] refer to Figure 4 , provide the basis Figure 3A cross-sectional view of an image sensor 400 of some alternative embodiments of the image sensor 300 is shown, wherein the lower etch stop structure 114 includes a first lower etch stop layer 114a and a second lower etch stop layer 114b, the first lower etch stop layer 114a being located below the second lower etch stop layer 114b. The upper etch stop structure 118 includes a first upper etch stop layer 118a and a second upper etch stop layer 118b, the first upper etch stop layer 118a being located below the second upper etch stop layer 118b. In addition, the interconnect pillar 402 including the conductive wiring layers 210a to 210d, the conductive via 208, the bonding pad 220, and the solder bump 222 is laterally offset from the transfer transistor 110 and the reset transistor 304. In some embodiments, the bonding pad 220 is electrically coupled to the floating diffusion node 106 through the interconnect structure 107. The inter-wiring buffer layer 204d is disposed between the bonding pad 220 and the conductive via 208. In some embodiments, the inter-wiring buffer layer 204d and the upper etch stop structure 118 include the same material.

[0038] Figures 5 to 15 Cross-sectional views 500 to 1500 illustrate some embodiments of methods of forming image sensor devices according to aspects of the present invention. Although described with reference to a method Figures 5 to 15 500 to 1500, but it should be understood that Figures 5 to 15 The structure shown in is not limited to the method described, but can exist independently of the method described. Figures 5 to 15 The above description is described as a series of actions, but it should be understood that these actions are not limited, and the order of the actions described in other embodiments may be changed, and the disclosed method is also applicable to other structures. In other embodiments, some of the actions described and / or illustrated may be omitted in whole or in part. In some embodiments, Figures 5 to 15 It can be used, for example, to form Figure 4 An image sensor 400 is shown.

[0039] like Figure 5As shown in the cross-sectional view 500 of FIG. 5 , a semiconductor substrate 102 is provided, and a deep isolation structure 202 and a shallow isolation structure 306 are formed on the front side surface 102 f of the semiconductor substrate 102. In some embodiments, the semiconductor substrate 102 (for example) may be a bulk substrate (for example, a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or some other suitable substrate. In some embodiments, before forming the deep isolation structure 202 and the shallow isolation structure 306, a first implantation process is performed to dope the semiconductor substrate 102 having a first doping type (for example, P-type). In some embodiments, the process of forming the deep isolation structure 202 and / or the shallow isolation structure 306 may include: 1) selectively etching the semiconductor substrate 102 to form a trench extending from the front side surface 102 f of the semiconductor substrate 102 into the semiconductor substrate 102; and 2) filling the trench with a dielectric material (e.g., by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, sputtering, etc.). In other embodiments, the semiconductor substrate 102 is selectively etched by forming a masking layer (not shown) on the front side surface 102 f of the semiconductor substrate 102, and then exposing the semiconductor substrate 102 to an etchant configured to selectively remove unmasked portions of the semiconductor substrate 102. In other embodiments, the dielectric material may include an oxide (e.g., silicon oxide), a nitride, etc.

[0040] Figure 51 , a photodetector 104 is formed in the semiconductor substrate 102. The photodetector 104 is a region of the semiconductor substrate 102 having a second doping type (e.g., N-type) opposite to the first doping type. In some embodiments, the photodetector 104 may be formed by a selective ion implantation process that utilizes a masking layer (not shown) on the front side surface 102 f of the semiconductor substrate 102 to selectively implant ions into the semiconductor substrate 102. In addition, a transfer transistor 110 and a reset transistor 304 are formed on the front side surface 102 f of the semiconductor substrate 102. In some embodiments, the process of forming the transfer transistor 110 and / or the reset transistor 304 includes depositing and / or growing (e.g., by CVD, PVD, ALD, thermal oxidation, sputtering, etc.) a gate dielectric layer on the front side surface 102 f of the semiconductor substrate 102. Next, a gate electrode layer may be deposited on the gate dielectric layer. Subsequently, the gate dielectric layer and the gate electrode layer are patterned (e.g., by a photolithography / etching process) to form a gate dielectric and a gate electrode, respectively. In addition, a spacer may be formed, for example, by the following steps: 1) depositing (e.g., by CVD, PVD, ALD, sputtering, etc.) a spacer layer on the front side surface 102f of the semiconductor substrate 102, the gate dielectric, and the gate electrode; and 2) etching back the spacer layer to remove the spacer layer from the horizontal surface. In other embodiments, the spacer layer may include a nitride, an oxide, or some other dielectric. In other embodiments, the gate electrode layer may include, for example, polysilicon, aluminum, etc. In other embodiments, the gate dielectric layer may include, for example, an oxide, a high-k dielectric, etc.

[0041] Figure 5 3, a contact region 302 and a floating diffusion node 106 are formed in the semiconductor substrate 102 on the side opposite to the reset transistor 304. In some embodiments, the contact region 302 and the floating diffusion node 106 are regions of the semiconductor substrate 102 having a second doping type (e.g., N-type). In some embodiments, the contact region 302 and the floating diffusion node 106 may be formed by a selective ion implantation process that selectively implants n-type dopants (e.g., phosphorus) into the semiconductor substrate 102 using a masking layer (not shown) disposed on the front side surface 102 f of the semiconductor substrate 102. In addition, a lower inter-level dielectric (ILD) structure 109 is formed over the front side surface 102 f of the semiconductor substrate 102. In some embodiments, the lower ILD structure 109, for example, may be or include one or more dielectric materials, such as oxide, silicon oxide, low-k dielectric, etc., and / or may, for example, have a thickness in the range of about 2500 angstroms to 5000 angstroms. The formation of the lower ILD structure 109 may, for example, include deposition followed by planarization to level the top surface of the lower ILD structure 109 .

[0042] In addition, a conductive contact 108 is formed in the lower ILD structure 109 over the contact region 302 and the floating diffusion node 106. In some embodiments, the conductive contact 108 is formed by a single damascene process. In some embodiments, the conductive contact 108 is formed over the transfer transistor 110 and the reset transistor 304 (not shown). In some embodiments, the single damascene process includes: patterning a dielectric layer and / or a dielectric structure (e.g., the lower ILD structure 109) to have an opening for a single conductive feature layer (e.g., a contact layer, a via layer, or a wiring layer); and filling the opening with a conductive material to form the single conductive feature layer. In other embodiments, a planarization process (e.g., a chemical mechanical planarization (CMP) process) is performed to align the top surface of the ILD structure 109 with the top surface of the conductive contact 108. In addition, an inter-wiring buffer layer 204a is formed over the lower ILD structure 109, and an inter-metal dielectric (IMD) layer 206a is formed over the inter-wiring buffer layer 204a. In some embodiments, the ILD structure 109, the inter-wiring buffer layer 204a, and / or the IMD layer 206a may be formed, for example, using CVD, PVD, ALD, and / or sputtering. In other embodiments, the inter-wiring buffer layer 204a may be, for example, or include silicon carbide, etc., and / or may have a thickness in the range of about 200 angstroms to 500 angstroms, for example. In other embodiments, the IMD layer 206a may be, for example, or include oxide, silicon oxide, a low-k dielectric, etc., and / or may have a thickness in the range of about 1000 angstroms to 3000 angstroms, for example.

[0043] like Figure 6 As shown in the cross-sectional view 600 of FIG. 1 , a bottommost conductive wiring layer 210 a is formed on the lower ILD structure 109. In some embodiments, the bottommost conductive wiring layer 210 a is formed, for example, by a single damascene process. In some embodiments, the bottommost conductive wiring layer 210 a (for example) may be or include a metal material, such as copper, tungsten, aluminum, etc.

[0044] like Figure 7As shown in the cross-sectional view 700 of FIG. 1 , a first lower etch stop layer 114 a is formed on the IMD layer 206 a. Subsequently, an etching process is performed to define a first opening 702 above the photodetector 104. In some embodiments, the etching process includes: forming a masking layer on the first lower etch stop layer 114 a; selectively exposing a layer below the masking layer to one or more etchants; and removing the masking layer (not shown). In some embodiments, the etching process removes a portion of the ILD structure 109 so that the upper surface of the ILD structure 109 is recessed below the bottom surface of the bottommost conductive wiring layer 210 a by a recessed distance r1. In some embodiments, the recessed distance r1 is, for example, in a range of about 500 angstroms to 2000 angstroms. A thickness t1 of the ILD structure 109 is defined between the upper surface of the ILD structure 109 and the top surface of the semiconductor substrate 102. In some embodiments, the thickness t1 is, for example, in a range of about 500 angstroms to 2000 angstroms. Reducing the thickness t1 of the ILD structure 109 above the photodetector 104 may, for example, increase the amount of incident radiation that the photodetector 104 may receive, thereby improving the quantum efficiency of the photodetector 104 .

[0045] In some embodiments, the etching process used to form the first opening 702 may be, for example, a low-power dry etching process (e.g., the low-power etching process may have a low power in the range of about 200 to 400 watts (W)). In addition, the one or more etchants used in the low-power etching process may be, for example, or include fluorine-based chemicals (e.g., octafluorocyclobutane (C4F8), hexafluorocyclobutene (C4F6)), argon, helium, etc. The use of the low-power dry etching process and the one or more etchants may reduce damage to the semiconductor substrate 102 and / or reduce the accumulation of electrons on the semiconductor substrate 102. This may partially reduce the presence of dark current and / or the presence of white pixels in the photodetector 104.

[0046] like Figure 8 As shown in the cross-sectional view 800 of FIG. 8 , above the first lower etch stop layer 114 a and in the first opening ( Figure 7 In some embodiments, the first lower etch stop layer 114a and the second lower etch stop layer 114b are formed in the lower etch stop structure 114. In other embodiments, the first lower etch stop layer 114a and the second lower etch stop layer 114b each include silicon carbide and are each formed with a thickness in the range of about 200 angstroms to about 500 angstroms. The second lower etch stop layer 114b has a U-shaped section 114bu directly overlying the light detector 104.

[0047] like Fig. 9As shown in the cross-sectional view 900 of FIG. 1 , a second IMD layer 206 b is formed on the lower etch stop structure 114. In some embodiments, the second IMD layer 206 b comprises the same material as the IMD layer 206 a. The second IMD layer 206 b fills the U-shaped section ( Figure 8 The formation of the second IMD layer 206b may, for example, include deposition followed by planarization to flatten the top surface of the second IMD layer 206b.

[0048] like Fig.10 As shown in the cross-sectional view 1000 of , the conductive layers and dielectric layers of the interconnect structure 107 are formed on the semiconductor substrate 102. The interconnect dielectric structure 201 includes inter-wiring buffer layers 204a to 204d, IMD layers 206a to 206d, passivation layers 214a to 214b, and a first upper etch stop layer 118a. In some embodiments, the dielectric layers in the interconnect dielectric structure 201 can be formed, for example, by CVD, PVD, ALD, thermal oxidation, sputtering, etc. In some embodiments, the first upper etch stop layer 118a (for example) can be or include silicon nitride, and / or can be formed, for example, with a thickness in the range of about 250 angstroms to 750 angstroms. The conductive layers of the interconnect structure 107 include conductive wiring layers 210a to 210d and conductive vias 208 formed in the interconnect dielectric structure 201. In some embodiments, the conductive wiring layers 210a to 210d and / or the conductive vias 208 may be formed, for example, by a single damascene process or a dual damascene process. In some embodiments, the dual damascene process includes: depositing a dielectric layer; patterning the dielectric layer to have openings for two conductive feature layers (e.g., a via layer and a wiring layer); and filling the openings with a conductive material to form the two conductive feature layers. The dielectric layer may, for example, correspond to one of the layers in the interconnect dielectric structure 201. In another embodiment, a bonding pad 220 is formed over the interconnect pillar 402. A pad dielectric layer 218 is formed between the bonding pad 220 and the uppermost conductive wiring layer 210d. A solder bump 222 is formed over the bonding pad 220. The interconnect pillar 402 is laterally offset from the transfer transistor 110 and the reset transistor 304. In some embodiments, the bonding pad 220 , the pad dielectric layer 218 , and the solder bump 222 may be formed over the transfer transistor 110 and / or the reset transistor 304 (not shown).

[0049] In some embodiments, the process of forming the bonding pad 220 and the pad dielectric layer 218 may include: 1) patterning the passivation layers 214a to 214b and the first upper etch stop layer 118a to define a bonding pad opening (not shown); 2) lining the bonding pad opening with the pad dielectric layer 218; 3) selectively etching (e.g., through a masking layer (not shown)) the pad dielectric layer 218 to form an opening exposing the upper surface of the uppermost conductive wiring layer 210d, and removing the pad dielectric layer 218 from the sidewalls of the bonding pad opening; 4) selectively forming the bonding pad 220 on the pad dielectric layer 218 so that the sidewalls of the bonding pad 220 are laterally offset from the sidewalls of the bonding pad opening by a non-zero distance. In some embodiments, step 4) in the above process can be achieved by forming the bonding pad 220 on the pad dielectric layer 218 and then selectively etching the bonding pad 220 through a masking layer (not shown).

[0050] like Fig.11 As shown in cross-sectional view 1100 of FIG. 1 , an etching process is performed to define a second opening 1102 in interconnect dielectric structure 201 above photodetector 104. In some embodiments, the etching process includes: forming a masking layer over first upper etch stop layer 118a; selectively exposing a layer below the masking layer to one or more etchants; and subsequently removing the masking layer (not shown). In some embodiments, the etching process removes a portion of second IMD layer 206b and a portion of second lower etch stop layer 114b such that an upper surface of second IMD layer 206b is recessed below a top surface of bottommost conductive wiring layer 210a by a recessed distance r2. In some embodiments, the recessed distance r2 is in a range of approximately 100 angstroms to 400 angstroms.

[0051] In some embodiments, the etching process used to form the second opening 1102 may be, for example, a high-power dry etching process (e.g., the high-power dry etching process may have a high power in the range of about 1000 to 2500 watts). In addition, the one or more etchants utilized in the high-power dry etching process may be, for example, or include fluorine-based chemicals (e.g., octafluorocyclobutane (C4F8), hexafluorocyclobutene (C4F6)), argon, helium, etc. The thickness and configuration of the lower etch stop structure 114 and / or the second IMD layer 206b reduce the accumulation of electrons on the semiconductor substrate 102 and / or reduce damage to the crystalline structure of the semiconductor substrate 102 during the high-power etching process. This may partially reduce the presence of dark current and / or the presence of white pixels in the photodetector 104.

[0052] like Fig.12 As shown in the cross-sectional view 1200 of FIG. 1 , above the first upper etch stop layer 118 a and in the second opening ( Fig.111102). In some embodiments, the first upper etch stop layer 118a and the second upper etch stop layer 118b define an upper etch stop structure 118. In other embodiments, the first upper etch stop layer 118a and the second upper etch stop layer 118b each include silicon nitride and / or are each formed with a thickness in a range of about 250 angstroms to 750 angstroms. The second upper etch stop layer 118b has a U-shaped section 118bu directly overlying the light detector 104.

[0053] like Fig.13 As shown in the cross-sectional view 1300 of FIG. 1 , an etching process is performed to remove the bottom section of the upper etch stop structure 118 and expose the second IMD layer 206 b. In some embodiments, the etching process includes: forming a masking layer over the second upper etch stop layer 118 b; selectively exposing the second upper etch stop layer 118 b to one or more etchants according to the masking layer; and subsequently removing the masking layer (not shown). In alternative embodiments, the etching process includes etching back and thus does not rely on a masking layer. The etching process exposes the upper surface of the lower section 206 b1 of the second IMD layer 206 b.

[0054] In some embodiments, for removing the U-shaped section ( Fig.12 The etching process of the lower section of the second upper etch stop layer 118b1 may be, for example, a low-power dry etching process (e.g., the low-power dry etching process may have a low power in the range of about 200 to 400 watts). In addition, the one or more etchants utilized in the lower power etching process may be, for example, or include fluoromethane (e.g., CHF, CHF3, etc.). The use of the low-power dry etching process and the one or more etchants may reduce the accumulation of electrons on the semiconductor substrate 102. This may partially reduce the presence of dark current and / or the presence of white pixels in the photodetector 104. In addition, the second upper etch stop layer 118b1 may be configured to protect the interconnect dielectric structure 201 from the low-power dry etching process, thereby reducing the physical bombardment of the one or more etchants ions on the dielectric layer in the interconnect dielectric structure 201.

[0055] like Fig.14 As shown in the cross-sectional view 1400 of FIG. 14, an etching process is performed to remove the lower section of the second IMD layer 206b ( Fig.13206b1), thereby defining the light pipe opening 1402. In some embodiments, the etching process is a wet etching process. In addition, the wet etching process may, for example, utilize one or more etchants (e.g., hydrogen fluoride). In some embodiments, the second upper etch stop layer 118b covers the solder bump 222, so that during the wet etching process, the second upper etch stop layer 118b covers the solder bump 222 and the bonding pad 220 and protects the solder bump 222 and the bonding pad 220 from the one or more etchants. In addition, the wet etching process can form the light pipe opening 1402 while avoiding plasma damage that may occur during the dry etching process, thereby further reducing the accumulation of electrons on the semiconductor substrate 102.

[0056] like Fig.15 As shown in the cross-sectional view 1500, at the light pipe opening ( Fig.14 1402). A bottom surface 115b of the light pipe structure 115 extends below a bottom surface of the bottommost conductive wiring layer 210a by a distance d1. In some embodiments, the distance d1 is in a range of about 50 angstroms to about 1500 angstroms. In some embodiments, if the distance d1 is small (e.g., less than about 50 angstroms), the height of the light pipe structure 115 is reduced. This may partially reduce the incident radiation 120 disposed on the photodetector 104, thereby reducing the quantum efficiency (QE) of the image sensor 100. In other embodiments, if the distance d1 is large (e.g., greater than about 1500 angstroms), physical bombardment (e.g., caused by ions of a plasma used during the formation of the light pipe structure 115) may damage the crystalline structure of the interconnect structure 107 and / or the semiconductor substrate 102. This may partially reduce the structural integrity of the interconnect structure 107, increase the dark current in the photodetector 104 and / or the number of white pixels in the image sensor 100. In some embodiments, the low power dry etching process and lower etch stop structure 114 facilitate a high degree of control over the height of light pipe structure 115. Furthermore, this process can be done to obtain multiple light pipe structures 115 so that each light pipe structure 115 can have approximately the same height, for example.

[0057] Fig.15It is also shown in the figure that after forming the light pipe structure 115, a removal process is performed to remove the second upper etch stop layer 118b on and / or around the bonding pad 220. In some embodiments, the removal process includes: forming a masking layer on the second upper etch stop layer 118b; performing an etching process according to the masking layer; and then removing the masking layer (not shown). In other embodiments, the removal process includes reducing the thickness of the second upper etch stop layer 118b overlying the passivation layers 214a to 214b. In addition, an anti-reflection layer 216 is formed on the light pipe structure 115. A color filter 226 (e.g., a red filter, a blue filter, a green filter, etc.) is formed on the anti-reflection layer 216. In addition, a microlens 224 is formed on the color filter 226.

[0058] Fig.16 A method 1600 of forming an image sensor device according to the present invention is described, the image sensor device including a light pipe structure located above a light detector and a transistor adjacent to the light detector. Although method 1600 is described and / or illustrated as a series of acts or events, it should be understood that the method is not limited to the described order or acts. Thus, in some embodiments, the acts may be performed in a different order than described and / or may be performed simultaneously. Furthermore, in some embodiments, the described acts or events may be subdivided into multiple acts or events, which may be performed at different times or simultaneously with other acts or sub-acts. In some embodiments, some described acts or events may be omitted, and other acts or events not described may be included.

[0059] At act 1602, a photodetector is formed in a semiconductor substrate, and a plurality of pixel devices are formed over the semiconductor substrate. Figure 5 Cross-sectional view 500 corresponding to some embodiments of act 1602 is illustrated.

[0060] At act 1604, an inter-layer dielectric (ILD) structure is formed over the semiconductor substrate. Figure 5 Cross-sectional view 500 corresponding to some embodiments of act 1604 is illustrated.

[0061] At act 1606, a conductive contact is formed over the semiconductor substrate such that the conductive contact extends through the ILD structure to the pixel device. Figure 5 Cross-sectional view 500 corresponding to some embodiments of act 1606 is illustrated.

[0062] At act 1608, a first etch stop layer and a first intermetal dielectric (IMD) layer are formed over the ILD structure. Figure 5Cross-sectional view 500 corresponding to some embodiments of act 1608 is illustrated.

[0063] At act 1610, a bottommost conductive wiring layer is formed over the conductive contacts, the bottommost conductive wiring layer being recessed into the first IMD layer. Figure 6 Cross-sectional view 600 corresponding to some embodiments of act 1610 is illustrated.

[0064] At act 1612, a second etch stop layer is formed over the bottommost conductive wiring layer and the first IMD layer. Figure 7 Cross-sectional view 700 corresponding to some embodiments of act 1612 is illustrated.

[0065] At act 1614 , a first etching process is performed to define a first opening above the photodetector such that the first etching process removes a portion of the ILD structure. Figure 7 Cross-sectional view 700 corresponding to some embodiments of act 1614 is illustrated.

[0066] At act 1616, another etch stop layer having the same material as the second etch stop layer is formed in the first opening such that the second etch stop layer includes the another etch stop layer and has a U-shape over the photodetector. Figure 8 Cross-sectional view 800 corresponding to some embodiments of act 1616 is illustrated.

[0067] At act 1618, a dielectric layer, an etch stop layer, conductive vias, and a conductive wiring layer are formed over the semiconductor substrate. Fig. 9 and Fig.10 Cross-sectional view 900 and cross-sectional view 1000 corresponding to some embodiments of act 1618 are described.

[0068] At act 1620, a second etching process is performed to form a second opening directly over the U-shape of the second etch stop layer. Fig.11 Cross-sectional view 1100 corresponding to some embodiments of act 1620 is illustrated.

[0069] At act 1622, a topmost etch stop layer is formed in the second opening. Fig.12 Cross-sectional view 1200 corresponding to some embodiments of act 1622 is illustrated.

[0070] At act 1624, a removal process is performed to expose the upper surface of the second etch stop layer and define the light pipe opening. Fig.13 and Fig.14 Cross-sectional view 1300 and cross-sectional view 1400 corresponding to some embodiments of act 1624 are described.

[0071] At act 1626, a light pipe structure is formed in the light pipe opening. Fig.15Cross-sectional view 1500 corresponding to some embodiments of act 1626 is illustrated.

[0072] At act 1628, an anti-reflective layer, color filters, and micro-lenses are formed over the light pipe structure. Fig.15 Cross-sectional view 1500 corresponding to some embodiments of act 1628 is illustrated.

[0073] Therefore, in some embodiments, the present application provides an image sensor device, the image sensor device comprising a light pipe structure located above a photodetector and a transistor adjacent to the photodetector. The bottom surface of the light pipe structure is lower than the bottom surface of the bottommost wire in the interconnect structure.

[0074] In some embodiments, the present application provides an image sensor, the image sensor comprising: a semiconductor substrate; a photodetector disposed in the semiconductor substrate; a gate electrode overlying the semiconductor substrate and adjacent to the photodetector; an inter-level dielectric (ILD) layer overlying the semiconductor substrate; a conductive contact located in the inter-level dielectric layer, wherein a bottom surface of the conductive contact is lower than a top surface of the gate electrode; and a light pipe structure overlying the photodetector, wherein a bottom surface of the light pipe structure is recessed to be lower than a top surface of the conductive contact.

[0075] In some embodiments, the outer sidewall of the light pipe structure is laterally located between the outer sidewalls of the light detectors. In some embodiments, the image sensor further comprises: an intermetal dielectric (IMD) structure overlying the interlevel dielectric layer; a conductive line overlying the conductive contact and located within the IMD structure; and a conductive via located within the IMD structure, wherein the conductive via is located between the conductive lines; wherein the bottom surface of the light pipe structure is lower than the bottommost conductive line. In some embodiments, the IMD structure comprises a lower etch stop layer, wherein the lower etch stop layer is interposed between the IMD layer and the light pipe structure. In some embodiments, the IMD structure comprises an upper etch stop layer, wherein the upper etch stop layer continuously extends from a top surface of the IMD structure to be lower than a top surface of the bottommost conductive line, and wherein the light pipe structure has a horizontal sidewall segment, a first vertical sidewall segment above the horizontal sidewall segment, and a second vertical sidewall segment below the horizontal sidewall segment. In some embodiments, the upper etch stop layer has a first sidewall adjacent to the first vertical sidewall segment of the light pipe structure, and also has a second sidewall adjacent to the second vertical sidewall segment of the light pipe structure. In some embodiments, the light pipe structure has two separated widths, wherein the width of the light pipe structure increases from top to bottom. In some embodiments, the top surface of the gate electrode is lower than the bottom surface of the light pipe structure. In some embodiments, the bottom surface of the light pipe structure is lower than the top surface of the inter-level dielectric layer.

[0076] In some embodiments, the present application provides a complementary metal oxide semiconductor (CMOS) image sensor, the complementary metal oxide semiconductor image sensor comprising: a substrate; a photodetector disposed in the substrate; an interconnect structure comprising an inter-level dielectric (ILD) layer, an inter-metal dielectric (IMD) structure overlying the ILD layer, and conductive lines in the IMD structure, wherein the interconnect structure overlies the substrate and is selectively electrically coupled to the photodetector; and a light pipe structure overlying the photodetector and extending continuously from a top of the IMD structure to a point below a bottom surface of a bottommost conductive line of the interconnect structure.

[0077] In some embodiments, the IMD structure includes a plurality of etch stop layers and a plurality of dielectric layers, wherein a lower etch stop layer has a U-shaped profile directly above the photodetector, and wherein the U-shaped profile extends continuously along an outer sidewall and a bottom surface of the light pipe structure. In some embodiments, the IMD structure includes an upper etch stop layer, the upper etch stop layer extending from the top of the IMD structure to the lower etch stop layer, and wherein the upper etch stop layer is located between the light pipe structure and the plurality of dielectric layers. In some embodiments, the light pipe structure has a first width and a second width, the second width overlying the first width, and wherein the first width is greater than the second width. In some embodiments, the light pipe structure has a first refractive index, the first refractive index is greater than a second refractive index of the upper etch stop layer, and wherein the second refractive index is less than a third refractive index of the lower etch stop layer. In some embodiments, the complementary metal oxide semiconductor image sensor further comprises: a transfer transistor overlying the substrate and laterally offset from the photodetector; wherein the interconnect structure comprises a conductive contact within the inter-level dielectric layer, wherein a bottom surface of the conductive contact is lower than a top surface of the transfer transistor, and a bottom surface of the light pipe structure extends below a top surface of the conductive contact. In some embodiments, the bottom surface of the light pipe structure is between the top surface of the conductive contact and the top surface of the transfer transistor.

[0078] In some embodiments, the present application provides a method for forming an image sensor, the method comprising: forming a photodetector in a semiconductor substrate; forming a lower interconnect portion of an interconnect structure above the photodetector; performing a first removal process to define a first opening in the lower interconnect portion overlying the photodetector; forming a lower etch stop layer to line the first opening, wherein the lower etch stop layer has a U-shape in the first opening; forming an upper interconnect portion of the interconnect structure over the lower etch stop layer; and forming a light pipe structure overlying the photodetector, wherein the U-shape of the lower etch stop layer extends continuously along sidewalls and a bottom surface of the light pipe structure.

[0079] In some embodiments, forming the lower interconnect portion includes forming a bottommost conductive line above the semiconductor substrate, and wherein a bottom surface of the light pipe structure extends below the bottommost conductive line. In some embodiments, the first removal process includes performing a dry etch on the lower interconnect portion, and wherein forming the light pipe structure includes performing a wet etch on the upper interconnect portion. In some embodiments, forming the light pipe structure includes: performing a dry etch in the interconnect structure to define a light pipe opening overlying the photodetector; forming an upper etch stop layer in the light pipe opening along a sidewall of the interconnect structure; performing a wet etch process on the interconnect structure to expand the light pipe opening; and forming the light pipe structure in the light pipe opening.

[0080] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art will appreciate that they can easily use the present invention as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that these equivalent constructions do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. An image sensor, comprising: Semiconductor substrate; a light detector disposed in the semiconductor substrate; a gate electrode overlying the semiconductor substrate and adjacent to the light detector; an inter-level dielectric layer, overlying the semiconductor substrate; a conductive contact located in the inter-level dielectric layer, wherein a bottom surface of the conductive contact is lower than a top surface of the gate electrode; a light pipe structure overlying the light detector, wherein a bottom surface of the light pipe structure is recessed below a top surface of the conductive contact, wherein the light pipe structure has two separate widths, wherein the width of the light pipe structure increases from top to bottom; and An intermetallic dielectric structure overlies the interlevel dielectric layer, wherein the intermetallic dielectric structure includes a lower etch stop layer that extends continuously from above the conductive contact, along the sidewalls of the light pipe structure, to a point below the bottom surface of the light pipe structure.

2. The image sensor of claim 1, wherein an outer sidewall of the light pipe structure is laterally located between outer sidewalls of the light detectors.

3. The image sensor according to claim 1, further comprising: A conductive wire overlying the conductive contact and located within the intermetallic dielectric structure; as well as a conductive via located within the intermetal dielectric structure, wherein the conductive via is located between the conductive lines, The bottom surface of the light pipe structure is lower than the bottommost wire. 4 . The image sensor of claim 3 , wherein the lower etch stop layer is vertically sandwiched between an upper surface of the inter-level dielectric layer and the bottom surface of the light pipe structure.

5. The image sensor of claim 3 , wherein the intermetal dielectric structure comprises an upper etch stop layer that extends continuously from a top surface of the intermetal dielectric structure to below a top surface of the bottommost conductive line, and wherein the light pipe structure has a horizontal sidewall segment, a first vertical sidewall segment above the horizontal sidewall segment, and a second vertical sidewall segment below the horizontal sidewall segment. 6 . The image sensor of claim 5 , wherein the upper etch stop layer has a first sidewall adjacent to the first vertical sidewall segment of the light pipe structure, and further has a second sidewall adjacent to the second vertical sidewall segment of the light pipe structure. 7 . The image sensor of claim 1 , wherein a top surface of the gate electrode is lower than the bottom surface of the light pipe structure. 8 . The image sensor of claim 1 , wherein the bottom surface of the light pipe structure is lower than a top surface of the inter-level dielectric layer.

9. A complementary metal oxide semiconductor image sensor, comprising: substrate; a light detector disposed in the substrate; an interconnect structure including an inter-level dielectric layer, an inter-metal dielectric structure overlying the inter-level dielectric layer, and a conductive line within the inter-metal dielectric structure, wherein the interconnect structure overlies the substrate and is selectively electrically coupled to the photodetector; a light pipe structure overlying the photodetector and extending continuously from a top of the IMD structure to a point below a bottom surface of a bottommost conductor of the interconnect structure, wherein the light pipe structure has two separate widths, wherein the width of the light pipe structure increases from top to bottom; and A lower etch stop layer is disposed in the intermetal dielectric structure, wherein the lower etch stop layer has a U-shaped profile located above the photodetector, and wherein the U-shaped profile continuously extends along the outer sidewall and bottom surface of the light pipe structure. 10 . The complementary metal oxide semiconductor image sensor of claim 9 , wherein the lower etch stop layer continuously extends from a top surface of the bottommost conductive line to the bottom surface below the bottommost conductive line. 11 . The complementary metal oxide semiconductor image sensor of claim 9 , wherein the intermetal dielectric structure comprises an upper etch stop layer extending from the top of the intermetal dielectric structure to the lower etch stop layer.

12. The complementary metal oxide semiconductor image sensor of claim 11, wherein the light pipe structure has a first refractive index greater than a second refractive index of the upper etch stop layer, and wherein the second refractive index is less than a third refractive index of the lower etch stop layer.

13. The complementary metal oxide semiconductor image sensor according to claim 9, further comprising: a transfer transistor overlying the substrate and laterally offset from the light detector; The interconnect structure includes a conductive contact located in the inter-level dielectric layer, wherein the bottom surface of the conductive contact is lower than the top surface of the transfer transistor, and the bottom surface of the light pipe structure extends to be lower than the top surface of the conductive contact.

14. The complementary metal oxide semiconductor image sensor of claim 13, wherein the bottom surface of the light pipe structure is located between the top surface of the conductive contact and the top surface of the transfer transistor.

15. A method of forming an image sensor, the method comprising: forming a light detector in a semiconductor substrate; forming a lower interconnect portion of an interconnect structure above the photodetector; performing a first removal process to define a first opening in the lower interconnect portion overlying the light detector; forming a lower etch stop layer to line the first opening, wherein the lower etch stop layer has a U-shape in the first opening; forming an upper interconnect portion of the interconnect structure on the lower etch stop layer; as well as A light pipe structure is formed overlying the photodetector, wherein the U-shape of the lower etch stop layer extends continuously along sidewalls and a bottom surface of the light pipe structure, wherein the light pipe structure has two separate widths, wherein the width of the light pipe structure increases from top to bottom.

16. The method of forming an image sensor according to claim 15, wherein forming the lower interconnect portion comprises forming a bottommost conductive line above the semiconductor substrate, and wherein a bottom surface of the light pipe structure extends below the bottommost conductive line. 17 . The method of forming an image sensor according to claim 15 , wherein the first removal process comprises performing a dry etching on the lower interconnect portion, and wherein forming the light pipe structure comprises performing a wet etching on the upper interconnect portion.

18. The method of forming an image sensor according to claim 15, wherein forming the light pipe structure comprises: performing dry etching in the interconnect structure to define a light pipe opening overlying the light detector; forming an upper etch stop layer in the light pipe opening along the sidewalls of the interconnect structure; performing a wet etching process on the interconnect structure to expand the light pipe opening; as well as The light pipe structure is formed in the light pipe opening.

19. An image sensor, comprising: Semiconductor substrate; a light detector disposed in the semiconductor substrate; a transfer transistor overlying the substrate and laterally offset from the light detector; an interconnect structure comprising an inter-level dielectric layer, an inter-metal dielectric structure overlying the inter-level dielectric layer, a conductive line within the inter-metal dielectric structure, and a conductive contact within the inter-level dielectric layer, wherein the interconnect structure overlies the semiconductor substrate and is electrically coupled to the transfer transistor, wherein the inter-metal dielectric structure comprises a lower etch stop layer and an upper etch stop layer, wherein the lower etch stop layer extends horizontally from above a bottommost conductive line of the conductive lines to an outer sidewall of the photodetector, and wherein the upper etch stop layer extends from a top of the inter-metal dielectric structure to a point below a top surface of the bottommost conductive line of the conductive lines, wherein the upper etch stop layer comprises a first material, the lower etch stop layer comprises a second material different from the first material, and wherein the conductive contact extends from a top surface of the inter-level dielectric layer to a point below a top surface of the transfer transistor; as well as a light pipe structure disposed within the interconnect structure and overlying the photodetector, wherein a bottom surface of the light pipe structure is vertically spaced between a top surface of the conductive contact and a top surface of the transfer transistor, wherein the upper etch stop layer continuously extends along and contacts opposite sidewalls of the light pipe structure, and wherein the lower etch stop layer is disposed between the light pipe structure and the inter-level dielectric layer, wherein the light pipe structure has two separate widths, wherein the width of the light pipe structure increases from top to bottom. 20 . The image sensor of claim 19 , wherein a width of the light pipe structure increases discretely from a top surface of the interconnect structure in a direction toward the semiconductor substrate.

21. The image sensor of claim 19, wherein a refractive index of the light pipe structure is greater than a refractive index of the upper etch stop layer and a refractive index of the lower etch stop layer, respectively.

22. The image sensor of claim 19, wherein the lower etch stop layer comprises a first inner sidewall on a second inner sidewall, wherein the second inner sidewall is laterally offset from the first inner sidewall in a direction toward the light pipe structure, wherein the first inner sidewall contacts a sidewall of the upper etch stop layer, and the second inner sidewall contacts a sidewall of the light pipe structure.

Images