Wiring structure and method for manufacturing the same

Abstract

The present disclosure relates to a wiring structure and a method for manufacturing a wiring structure. The wiring structure includes an upper conductive structure, a lower conductive structure, a lower encapsulant, and an intermediate layer. The upper conductive structure includes at least one upper dielectric layer, and at least one upper circuit layer in contact with the upper dielectric layer. The lower conductive structure includes at least one lower dielectric layer, and at least one lower circuit layer in contact with the lower dielectric layer. The lower encapsulant surrounds a peripheral side surface of the lower conductive structure. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure to join the upper conductive structure and the lower conductive structure together. The upper conductive structure is electrically connected to the lower conductive structure.

Description

Technical Field

[0001] This disclosure relates to a wiring structure and a manufacturing method, and to a wiring structure comprising at least two conductive structures attached or bonded together by an intermediate layer, and a method for manufacturing said wiring structure. Background Technology

[0002] With the rapid development of the electronics industry and the advancement of semiconductor processing technology, semiconductor chips are integrated with an increasing number of electronic components to achieve improved electrical performance and additional functionality. Consequently, semiconductor chips have more input / output (I / O) connections. To manufacture semiconductor packages containing semiconductor chips with an increased number of I / O connections, the size of the circuit layers in the semiconductor substrate used to carry the semiconductor chips can be correspondingly increased. Therefore, the thickness and warpage of the semiconductor substrate can be correspondingly increased, and the yield of the semiconductor substrate can be reduced. Summary of the Invention

[0003] In some embodiments, a wiring structure includes: (a) an upper conductive structure including at least one upper dielectric layer and at least one upper circuit layer in contact with the upper dielectric layer; (b) a lower conductive structure including at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer; (c) a lower encapsulation surrounding a peripheral side surface of the lower conductive structure; and (d) an intermediate layer disposed between the upper conductive structure and the lower conductive structure, and bonding the upper conductive structure and the lower conductive structure together, wherein the upper conductive structure is electrically connected to the lower conductive structure.

[0004] In some embodiments, a method for manufacturing a wiring structure includes: (a) providing a lower substrate including at least one lower conductive structure, wherein the lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer; (b) providing a plurality of upper strips, wherein each of the upper strips includes at least one upper conductive structure, and the upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer; (c) attaching the upper strips side-by-side to the lower substrate, wherein the position of the upper conductive structure of the upper strip corresponds to the position of the lower conductive structure of the lower substrate; (d) electrically connecting the upper conductive structure of the upper strip to the lower conductive structure of the lower substrate; and (e) performing a single-step process to form a plurality of wiring structures.

[0005] In some embodiments, a method for manufacturing a wiring structure includes: (a) providing a plurality of lower conductive structures, each of which includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer; (b) forming a lower encapsulation to encapsulate the plurality of known good lower conductive structures to form a lower module; (c) providing a plurality of upper conductive structures, each of which includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer of the upper conductive structure; (d) attaching the upper conductive structures to the known good lower conductive structures of the lower module respectively; (e) electrically connecting the upper conductive structures to the known good lower conductive structures of the lower module; and (f) performing a single-step process to form the plurality of wiring structures. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, various aspects of some embodiments of this disclosure will become readily apparent from the following detailed description. It should be noted that the various structures may not be drawn to scale, and the dimensions of the various structures may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 A perspective view illustrating a wiring structure according to some embodiments of the present disclosure.

[0008] Figure 2 illustrate Figure 1 A top view of the wiring structure.

[0009] Figure 3 illustrate Figure 1 An exploded view of the wiring structure.

[0010] Figure 4 illustrate Figure 1 A cross-sectional view of a portion of the wiring structure.

[0011] Figure 5 Cross-sectional views illustrating wiring structures according to some embodiments of the present disclosure are provided.

[0012] Figure 6 Cross-sectional views illustrating wiring structures according to some embodiments of the present disclosure are provided.

[0013] Figure 7 Cross-sectional views illustrating wiring structures according to some embodiments of the present disclosure are provided.

[0014] Figure 8 Cross-sectional views illustrating wiring structures according to some embodiments of the present disclosure are provided.

[0015] Figure 9 Cross-sectional views illustrating wiring structures according to some embodiments of the present disclosure are provided.

[0016] Figure 10 Cross-sectional views illustrating wiring structures according to some embodiments of the present disclosure are provided.

[0017] Figure 11 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0018] Figure 12 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0019] Figure 13 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0020] Figure 14 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0021] Figure 15 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0022] Figure 16 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0023] Figure 17 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0024] Figure 18 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0025] Figure 19 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0026] Figure 20 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0027] Figure 21 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0028] Figure 22 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0029] Figure 23This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0030] Figure 24 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0031] Figure 25 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0032] Figure 26 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0033] Figure 27 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0034] Figure 28 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0035] Figure 29 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0036] Figure 30 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0037] Figure 31 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0038] Figure 32 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0039] Figure 33 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0040] Figure 34 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0041] Figure 35 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0042] Figure 36This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0043] Figure 37 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0044] Figure 38 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0045] Figure 39 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0046] Figure 40 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0047] Figure 41 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0048] Figure 42 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0049] Figure 43 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0050] Figure 44 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0051] Figure 45 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0052] Figure 46 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0053] Figure 47 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0054] Figure 48 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0055] Figure 49This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0056] Figure 50 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0057] Figure 51 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0058] Figure 52 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0059] Figure 53 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0060] Figure 54 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0061] Figure 55 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0062] Figure 56 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0063] Figure 57 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0064] Figure 58 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0065] Figure 59 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0066] Figure 60 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0067] Figure 61 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0068] Figure 62This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0069] Figure 63 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0070] Figure 64 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0071] Figure 65 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. Detailed Implementation

[0072] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar components. Embodiments of this disclosure will be readily understood from the detailed description taken in conjunction with the accompanying drawings.

[0073] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to illustrate certain aspects of this disclosure. These are, of course, merely examples and are not intended to be limiting. For instance, in the following description, references to the formation of a first feature on or on a second feature may include embodiments in which the first and second features are formed or disposed in direct contact, and may also include embodiments in which additional features are formed or disposed between the first and second features such that the first and second features do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for the purpose of simplicity and clarity and does not, in itself, define a relationship between the various embodiments and / or configurations discussed.

[0074] To meet the requirement of increased I / O count, the number of dielectric layers in the substrate should be increased. In some comparative embodiments, the manufacturing process of the core substrate may include the following stages. First, a core with two copper foils disposed on both sides of the core is provided. Next, multiple dielectric layers and multiple circuit layers are formed or stacked on the two copper foils. One circuit layer may be embedded in a corresponding dielectric layer. Therefore, the core substrate may include multiple stacked dielectric layers and multiple circuit layers embedded in the dielectric layers on both sides of the core. Since the linewidth / line space (L / S) of the circuit layers in this core substrate may be greater than or equal to 10 micrometers (μm) / 10 μm, the number of dielectric layers in this core substrate is relatively large. Although the manufacturing cost of such a core substrate is low, the manufacturing yield of the circuit layers and dielectric layers in this core substrate is also low, therefore, the yield of this core substrate is low. In addition, each dielectric layer is relatively thick, and therefore the core substrate is relatively thick. In some comparative embodiments, if the package has 10,000 I / O counts, then this core substrate may contain twelve circuit layers and dielectric layers. The manufacturing yield of one layer of this core substrate (containing one circuit layer and one dielectric layer) can be 90%. Therefore, the yield of this core substrate can be (0.9). 12 =28.24%. Furthermore, the warpage of the twelve circuit and dielectric layers can accumulate, and therefore the top layers may exhibit severe warpage. Consequently, the yield of this core substrate can be further reduced.

[0075] To address the aforementioned issues, in some comparative embodiments, a coreless substrate is provided. The coreless substrate may comprise multiple dielectric layers and multiple fan-out circuit layers. In some embodiments, the fabrication process of the coreless substrate may include the following stages: First, a carrier is provided. Subsequently, multiple dielectric layers and multiple fan-out circuit layers are formed or stacked on the surface of the carrier. One fan-out circuit layer may be embedded in a corresponding dielectric layer. Next, the carrier is removed. Thus, the coreless substrate may comprise multiple stacked dielectric layers and multiple fan-out circuit layers embedded within the dielectric layers. Since the linewidth / spacing (L / S) of the fan-out circuit layers in this coreless substrate can be less than or equal to 2 μm / 2 μm, the number of dielectric layers in this coreless substrate can be reduced. Furthermore, the fabrication yield of the fan-out circuit layers and dielectric layers in this coreless substrate is high. For example, the fabrication yield of one layer (comprising one fan-out circuit layer and one dielectric layer) in this coreless substrate can be 99%. However, the fabrication cost of this coreless substrate is relatively high.

[0076] At least some embodiments of this disclosure provide wiring structures with an advantageous trade-off between yield and manufacturing cost. In some embodiments, the wiring structure includes an upper conductive structure and a lower conductive structure bonded to the upper conductive structure via an intermediate layer. At least some embodiments of the invention further provide techniques for manufacturing the wiring structures.

[0077] Figure 1 A perspective view illustrating a wiring structure 1 according to some embodiments of the present disclosure. Figure 2 illustrate Figure 1 A top view of wiring structure 1. Figure 3 illustrate Figure 1 An exploded view of the wiring structure 1. Figure 4 illustrate Figure 1 A cross-sectional view of a portion of the wiring structure 1. The wiring structure 1 includes multiple upper strips 2, a lower substrate 3, an intermediate layer 12, and at least one upper through via 14.

[0078] like Figures 1 to 3 As shown, upper strips 2 are arranged side-by-side on a lower substrate 3. In some embodiments, the upper strips 2 are attached to the lower substrate 3 via an intermediate layer 12. Each of the upper strips 2 includes at least one upper conductive structure 2a. For example, each of the upper strips 2 may include a plurality of upper conductive structures 2a arranged in a row. Note that the upper strips 2 are strip-shaped before the individual separation process and may also be referred to as upper conductive structures. After the individual separation process, the upper conductive structures 2a may be die units.

[0079] like Figure 4As shown, the upper conductive structure 2a includes at least one dielectric layer (including, for example, two first dielectric layers 20 and a second dielectric layer 26) and at least one circuit layer (including, for example, three first circuit layers 24 and a second circuit layer 28 formed of metal, metal alloy or other conductive material), which is in contact with the dielectric layers (e.g., the first dielectric layer 20 and the second dielectric layer 26). In some embodiments, the upper conductive structure 2a may resemble a coreless substrate. The upper conductive structure 2a may also be referred to as a "stacked structure" or a "high-density conductive structure" or a "high-density stacked structure". The circuit layer of the upper conductive structure 2a (including, for example, three circuit layers 24) may also be referred to as a "high-density circuit layer". In some embodiments, the density of circuit lines (including, for example, traces or pads) in the high-density circuit layer is greater than the density of circuit lines in the low-density circuit layer. That is, the count of circuit lines (including, for example, traces or pads) per unit area of ​​the high-density circuit layer is greater than the count of circuit lines per unit area of ​​the low-density circuit layer, for example, about 1.2 times or more, about 1.5 times or more, or about 2 times or more. Alternatively or in combination, the linewidth / spacing (L / S) of the high-density circuit layer is smaller than that of the low-density circuit layer, for example, about 90% or less, about 50% or less, or about 20% or less. Furthermore, a conductive structure containing a high-density circuit layer may be referred to as a "high-density conductive structure," and a conductive structure containing a low-density circuit layer may be referred to as a "low-density conductive structure."

[0080] The upper conductive structure 2a has a top surface 21 and a bottom surface 22 opposite to the top surface 21, and defines at least one through hole 23, each of which is a single continuous through hole. The upper conductive structure 2a includes a plurality of dielectric layers (e.g., the two first dielectric layers 20 and the second dielectric layer 26), a plurality of circuit layers (e.g., the three first circuit layers 24 and the second circuit layer 28), and at least one inner via 25. The dielectric layers (e.g., the first dielectric layer 20 and the second dielectric layer 26) are stacked on top of each other. For example, the second dielectric layer 26 is disposed on the first dielectric layer 20, and therefore, the second dielectric layer 26 is the topmost dielectric layer. In some embodiments, the material of the dielectric layers (e.g., the first dielectric layer 20 and the second dielectric layer 26) is transparent and can be seen through by the human eye or a machine. That is, the human eye or a machine can identify or detect markings disposed adjacent to the bottom surface 22 of the upper conductive structure 2a from the top surface 21 of the upper conductive structure 2a. In some embodiments, the transparent material of the dielectric layer has a transmittance of at least about 60%, at least about 70%, or at least about 80% for wavelengths in the visible range (or other relevant wavelengths for detecting the marker).

[0081] Furthermore, each of the first dielectric layers 20 has a top surface 201 and a bottom surface 202 opposite to the top surface 201, and defines a through-hole 203 having an inner surface 2031. The second dielectric layer 26 has a top surface 261 and a bottom surface 262 opposite to the top surface 261, and defines a through-hole 263 having an inner surface 2631. The bottom surface 262 of the second dielectric layer 26 is disposed adjacent to and in contact with the top surface 201 of the first dielectric layer 20. Therefore, the top surface 21 of the upper conductive structure 2a is the top surface 261 of the second dielectric layer 26, and the bottom surface 22 of the upper conductive structure 2a is the bottom surface 202 of the bottommost first dielectric layer 20.

[0082] like Figure 4 As shown, each of the vias 203 in the first dielectric layer 20 tapers downwardly from the top surface 21 to the bottom surface 22 of the upper conductive structure 2a; that is, the size of the top portion of the via 203 is larger than the size of the bottom portion. The vias 263 in the second dielectric layer 26 also taper downwards; that is, the size of the top portion of the via 263 is larger than the size of the bottom portion. Furthermore, the vias 263 in the second dielectric layer 26 are aligned with and communicate with the vias 203 in the first dielectric layer 20. The bottom portion of the vias 263 in the second dielectric layer 26 is positioned adjacent to or connected to the top portion of the vias 203 in the first dielectric layer 20 beneath the second dielectric layer 26. The size of the bottom portion of the vias 263 in the second dielectric layer 26 is substantially equal to the size of the top portion of the vias 203 in the first dielectric layer 20 beneath the second dielectric layer 26. Therefore, the inner surface 2631 of the via 263 of the second dielectric layer 26 is coplanar or aligned with the inner surface 2031 of the via 203 of the first dielectric layer 20. Note that the aforementioned "coplanar" surfaces do not need to be flat. In some embodiments, the inner surface 2631 of the via 263 of the second dielectric layer 26 and the inner surface 2031 of the via 203 of the first dielectric layer 20 may be curved surfaces and are portions of the inner surface 231 of a single continuous via 23 for accommodating the upper through-hole 14. The via 263 of the second dielectric layer 26 and the via 203 of the first dielectric layer 20 are configured together to form or define a portion of a single via 23. Figure 4As shown, the cross-sectional views of one side of the inner surface 2631 of the via 263 in the second dielectric layer 26 and the inner surface 2031 of the via 203 in the first dielectric layer 20 are generally straight segments. That is, the cross-sectional views of one side of the inner surface 2631 of the via 263 in the second dielectric layer 26 and the inner surface 2031 of the via 203 in the first dielectric layer 20 can extend along the same generally straight line. A single via 23 extends through the upper conductive structure 2a; that is, a single via 23 extends from the top surface 21 of the upper conductive structure 2a to the bottom surface 22 of the upper conductive structure 2a. The single via 23 gradually decreases in size downwards.

[0083] The first circuit layer 24 may be a fan-out circuit layer or a redistribution layer (RDL), and the L / S ratio of the first circuit layer 24 may be less than or equal to about 2 μm / about 2 μm, or less than or equal to about 1.8 μm / about 1.8 μm. Each of the first circuit layers 24 has a top surface 241 and a bottom surface 242 opposite to the top surface 241. In some embodiments, the first circuit layer 24 is embedded in a corresponding first dielectric layer 20, and the top surface 241 of the first circuit layer 24 may be substantially coplanar with the top surface 201 of the first dielectric layer 20. In some embodiments, each first circuit layer 24 may include a seed layer 243 and a conductive metal material 244 disposed on the seed layer 243. Figure 4 As shown, the bottommost first circuit layer 24 is disposed on and extends from the bottom surface 22 of the upper conductive structure 2a (i.e., the bottom surface 202 of the bottommost first dielectric layer 20). Additionally, the second circuit layer 28 is disposed on and extends from the top surface 21 of the upper conductive structure 2a (e.g., the top surface 261 of the second dielectric layer 26). The L / S ratio of the second circuit layer 28 may be greater than or equal to the L / S ratio of the first circuit layer 24. Figure 4 As illustrated in the embodiments, the second dielectric layer 26 omits horizontally connected or extended circuit layers.

[0084] The upper conductive structure 2a includes a plurality of through-holes 25. Some of the through-holes 25 are disposed between two adjacent first circuit layers 24 for electrically connecting the two first circuit layers 24. Some of the through-holes 25 are disposed between the first circuit layer 24 and the second circuit layer 28 for electrically connecting the first circuit layer 24 and the second circuit layer 28. In some embodiments, each through-hole 25 may include a seed layer 251 and a conductive metal material 252 disposed on the seed layer 251. In some embodiments, each through-hole 25 and the corresponding first circuit layer 24 may be integrally formed as a monolithic or single-piece structure. Each through-hole 25 gradually decreases in size upwards from the bottom surface 22 of the upper conductive structure 2a toward the top surface 21. That is, the size (e.g., width) of the top portion of the through-hole 25 is smaller than the size (e.g., width) of the bottom portion of the through-hole 25 closer to the bottom surface 22. In some embodiments, the maximum width of the through-hole 25 (e.g., in the bottom portion) may be less than or equal to about 25 μm, such as about 25 μm, about 20 μm, about 15 μm or about 10 μm.

[0085] like Figures 1 to 3 As shown, the lower substrate 3 includes at least one lower conductive structure 3a. For example, the lower substrate 3 may include a plurality of lower conductive structures 3a arranged in an array. Alternatively, the lower substrate 3 may be panel type. Note that the lower substrate 3 is substrate type before the die-casting process and may also be referred to as the lower conductive structure. After the die-casting process, the lower conductive structure 3a may be a die unit. The position of the upper conductive structure 2a corresponds to the position of the lower conductive structure 3a. In some embodiments, the upper conductive structure 2a may be positioned directly above the lower conductive structure 3a, and the central axis of the upper conductive structure 2a may be aligned with the central axis of the lower conductive structure 3a.

[0086] like Figure 4As shown, the lower conductive structure 3a includes at least one dielectric layer (including, for example, a first upper dielectric layer 30, a second upper dielectric layer 36, a first lower dielectric layer 30a, and a second lower dielectric layer 36a), and at least one circuit layer (including, for example, a first upper circuit layer 34 formed of metal, metal alloy, or other conductive material; two second upper circuit layers 38, 38'; a first lower circuit layer 34a and two second lower circuit layers 38a; 38a'), which is in contact with the dielectric layers (e.g., the first upper dielectric layer 30, the second upper dielectric layer 36, the first lower dielectric layer 30a, and the second lower dielectric layer 36a). In some embodiments, the lower conductive structure 3a may resemble a core substrate further including a core portion 37. The lower conductive structure 3a may also be referred to as a "stacked structure," a "low-density conductive structure," or a "low-density stacked structure." The circuit layer of the lower conductive structure 3a (including, for example, a first upper circuit layer 34; two second upper circuit layers 38, 38'; a first lower circuit layer 34a; and two second lower circuit layers 38a, 38a') can also be referred to as a "low-density circuit layer". For example... Figure 4 As shown, the lower conductive structure 3a has a top surface 31 and a bottom surface 32 opposite to the top surface 31. The lower conductive structure 3a includes a plurality of dielectric layers (e.g., a first upper dielectric layer 30, a second upper dielectric layer 36, a first lower dielectric layer 30a and a second lower dielectric layer 36a); a plurality of circuit layers (e.g., a first upper circuit layer 34; two second upper circuit layers 38, 38'; a first lower circuit layer 34a, and two second lower circuit layers 38a, 38a'); and at least one through-hole (including, for example, a plurality of upper interconnect through-holes 35 and a plurality of lower interconnect through-holes 35a).

[0087] The core portion 37 has a top surface 371 and a bottom surface 372 opposite to the top surface 371, and defines a plurality of through holes 373 extending through the core portion 37. Interconnect vias 39 are disposed or formed in each through hole 373 for vertical connection. In some embodiments, each interconnect via 39 includes a base metal layer 391 and an insulating material 392. The base metal layer 391 is disposed or formed on the sidewall of the through hole 373 and defines a central through hole. The insulating material 392 fills the central through hole defined by the base metal layer 391. In some embodiments, the insulating material may be omitted from the interconnect via 39, and it may comprise a bulk metal material filling the through hole 373.

[0088] A first upper dielectric layer 30 is disposed on the top surface 371 of the core portion 37, and has a top surface 301 and a bottom surface 302 opposite to the top surface 301. Therefore, the bottom surface 302 of the first upper dielectric layer 30 contacts the top surface 371 of the core portion 37. A second upper dielectric layer 36 is stacked or disposed on the first upper dielectric layer 30, and has a top surface 361 and a bottom surface 362 opposite to the top surface 361. Therefore, the bottom surface 362 of the second upper dielectric layer 36 contacts the top surface 301 of the first upper dielectric layer 30, and the second upper dielectric layer 36 is the topmost dielectric layer. Additionally, a first lower dielectric layer 30a is disposed on the bottom surface 372 of the core portion 37, and has a top surface 301a and a bottom surface 302a opposite to the top surface 301a. Therefore, the top surface 301a of the first lower dielectric layer 30a contacts the bottom surface 372 of the core portion 37. A second lower dielectric layer 36a is stacked or disposed on a first lower dielectric layer 30a, and has a top surface 361a and a bottom surface 362a opposite to the top surface 361a. Therefore, the top surface 361a of the second lower dielectric layer 36a contacts the bottom surface 302a of the first lower dielectric layer 30a, and the second lower dielectric layer 36a is the bottommost dielectric layer. Figure 4 As shown, the top surface 31 of the lower conductive structure 3a is the top surface 361 of the second upper dielectric layer 36, and the bottom surface 32 of the lower conductive structure 3a is the bottom surface 362a of the second lower dielectric layer 36a.

[0089] The thickness of each of the dielectric layers (e.g., the first dielectric layer 20 and the second dielectric layer 26) in the upper conductive structure 2a is less than or equal to about 40%, less than or equal to about 35%, and less than or equal to about 30% of the thickness of each of the dielectric layers (e.g., the first upper dielectric layer 30, the second upper dielectric layer 36, the first lower dielectric layer 30a, and the second lower dielectric layer 36a) in the lower conductive structure 3a. For example, the thickness of each of the dielectric layers (e.g., the first dielectric layer 20 and the second dielectric layer 26) in the upper conductive structure 2a may be less than or equal to about 7 μm, and the thickness of each of the dielectric layers (e.g., the first upper dielectric layer 30, the second upper dielectric layer 36, the first lower dielectric layer 30a, and the second lower dielectric layer 36a) in the lower conductive structure 3a may be about 40 μm.

[0090] The L / S ratio of the first upper circuit layer 34 may be greater than or equal to about 10 μm / about 10 μm. Therefore, the L / S ratio of the first upper circuit layer 34 may be greater than or equal to about five times the L / S ratio of the first circuit layer 24 of the upper conductive structure 2a. The first upper circuit layer 34 has a top surface 341 and a bottom surface 342 opposite to the top surface 341. In some embodiments, the first upper circuit layer 34 is formed or disposed on the top surface 371 of the core portion 37 and is covered by the first upper dielectric layer 30. The bottom surface 342 of the first upper circuit layer 34 contacts the top surface 371 of the core portion 37. In some embodiments, the first upper circuit layer 34 may include a first metal layer 343, a second metal layer 344, and a third metal layer 345. The first metal layer 343 is disposed on the top surface 371 of the core portion 37 and may be formed of copper foil (e.g., may constitute part of copper foil). The second metal layer 344 is disposed on the first metal layer 343 and may be an electroplated copper layer. The third metal layer 345 is disposed on the second metal layer 344 and may be another electroplated copper layer. In some embodiments, the third metal layer 345 may be omitted.

[0091] The L / S ratio of the second upper circuit layer 38 can be greater than or equal to about 10 μm / about 10 μm. Therefore, the L / S ratio of the second upper circuit layer 38 can be substantially equal to the L / S ratio of the first upper circuit layer 34, and can be greater than or equal to about five times the L / S ratio of the first circuit layer 24 of the upper conductive structure 2a. The second upper circuit layer 38 has a top surface 381 and a bottom surface 382 opposite to the top surface 381. In some embodiments, the second upper circuit layer 38 is formed or disposed on the top surface 301 of the first upper dielectric layer 30 and is covered by the second upper dielectric layer 36. The bottom surface 382 of the second upper circuit layer 38 contacts the top surface 301 of the first upper dielectric layer 30. In some embodiments, the second upper circuit layer 38 is electrically connected to the first upper circuit layer 34 through an upper interconnect via 35. In other words, the upper interconnect via 35 is disposed between the second upper circuit layer 38 and the first upper circuit layer 34 for electrically connecting the second upper circuit layer 38 and the first upper circuit layer 34. In some embodiments, the second upper circuit layer 38 and the upper interconnect via 35 are integrally formed as a single block or single piece structure. Each upper interconnect via 35 gradually decreases in size downwards from the top surface 31 of the lower conductive structure 3a toward the bottom surface 32.

[0092] Additionally, in some embodiments, the second upper circuit layer 38' is disposed on and extends from the top surface 361 of the second upper dielectric layer 36. In some embodiments, the second upper circuit layer 38 is electrically connected to the second upper circuit layer 38' via an upper interconnect via 35. That is, the upper interconnect via 35 is disposed between the second upper circuit layers 38 and 38' for electrically connecting the second upper circuit layers 38 and 38'. In some embodiments, the second upper circuit layer 38' and the upper interconnect via 35 are integrally formed as a single piece or monolithic structure.

[0093] The L / S ratio of the first lower circuit layer 34a can be greater than or equal to about 10 μm / about 10 μm. Therefore, the L / S ratio of the first lower circuit layer 34a can be greater than or equal to about five times the L / S ratio of the first circuit layer 24 of the upper conductive structure 2a. The first lower circuit layer 34a has a top surface 341a and a bottom surface 342a opposite to the top surface 341a. In some embodiments, the first lower circuit layer 34a is formed or disposed on the bottom surface 372 of the core portion 37 and is covered by a first lower dielectric layer 30a. The top surface 341a of the first lower circuit layer 34a contacts the bottom surface 372 of the core portion 37. In some embodiments, the first lower circuit layer 34a may include a first metal layer 343a, a second metal layer 344a and a third metal layer 345a. The first metal layer 343a is disposed on the bottom surface 372 of the core portion 37 and may be formed of copper foil. The second metal layer 344a is disposed on the first metal layer 343a and may be an electroplated copper layer. The third metal layer 345a is disposed on the second metal layer 344a and may be another electroplated copper layer. In some embodiments, the third metal layer 345a may be omitted.

[0094] The L / S ratio of the second lower circuit layer 38a can be greater than or equal to about 10 μm / about 10 μm. Therefore, the L / S ratio of the second lower circuit layer 38a can be substantially equal to the L / S ratio of the first upper circuit layer 34, and can be greater than or equal to about five times the L / S ratio of the first circuit layer 24 of the upper conductive structure 2a. The second lower circuit layer 38a has a top surface 381a and a bottom surface 382a opposite to the top surface 381a. In some embodiments, the second lower circuit layer 38a is formed or disposed on the bottom surface 302a of the first lower dielectric layer 30a and is covered by the second lower dielectric layer 36a. The top surface 381a of the second lower circuit layer 38a contacts the bottom surface 302a of the first lower dielectric layer 30a. In some embodiments, the second lower circuit layer 38a is electrically connected to the first lower circuit layer 34a through a lower interconnect via 35a. In other words, the lower interconnect via 35a is disposed between the second lower circuit layer 38a and the first lower circuit layer 34a for electrically connecting the second lower circuit layer 38a and the first lower circuit layer 34a. In some embodiments, the second lower circuit layer 38a and the lower interconnect via 35a are integrally formed as a single piece or a single component. The lower interconnect via 35a gradually decreases in size upwards along the direction from the bottom surface 32 of the lower conductive structure 3a toward the top surface 31.

[0095] Additionally, in some embodiments, the second lower circuit layer 38a' is disposed on and extends from the bottom surface 362a of the second lower dielectric layer 36a. In some embodiments, the second lower circuit layer 38a' is electrically connected to the second lower circuit layer 38a via a lower interconnect via 35a. That is, the upper interconnect via 35a is disposed between the second lower circuit layers 38a and 38a' for electrically connecting the second lower circuit layers 38a and 38a'. In some embodiments, the second lower circuit layer 38a' and the lower interconnect via 35a are integrally formed as a single piece or a single component structure.

[0096] In some embodiments, each interconnect via 39 electrically connects the first upper circuit layer 34 and the first lower circuit layer 34a. The base metal layer 391 of the interconnect via 39, the second metal layer 344 of the first upper circuit layer 34, and the second metal layer 344a of the first lower circuit layer 34a can be integrally formed as a single block or a single piece structure.

[0097] An intermediate layer 12 is inserted or disposed between the upper strip 2 and the lower substrate 3 to bond the upper strip 2 and the lower substrate 3 together. That is, the intermediate layer 12 adheres to the bottom surface 22 of the upper conductive structure 2a and the top surface 31 of the lower conductive structure 3a. In some embodiments, the intermediate layer 12 may be an adhesive layer cured from an adhesive material (e.g., a cured adhesive material, such as an adhesive polymer). The intermediate layer 12 has a top surface 121 and a bottom surface 122 opposite to the top surface 121, and defines at least one through-hole 123 having an inner surface 1231. The top surface 121 of the intermediate layer 12 contacts the bottom surface 22 of the upper conductive structure 2a (that is, the bottom surface 22 of the upper conductive structure 2a is attached to the top surface 121 of the intermediate layer 12), and the bottom surface 122 of the intermediate layer 12 contacts the top surface 31 of the lower conductive structure 3a. Therefore, the bottom first circuit layer 24 of the upper conductive structure 2a and the top circuit layer 38' (e.g., the second upper circuit layer 38') of the lower conductive structure 3a are embedded in the intermediate layer 12. In some embodiments, the bonding force between two adjacent dielectric layers (e.g., two adjacent first dielectric layers 20) of the upper conductive structure 2a is greater than the bonding force between the dielectric layer (e.g., the bottom first dielectric layer 20) of the upper conductive structure 2a and the intermediate layer 12. The surface roughness of the boundary between two adjacent dielectric layers (e.g., two adjacent first dielectric layers 20) of the upper conductive structure 2a is greater than the surface roughness of the boundary between the dielectric layer (e.g., the bottom first dielectric layer 20) of the upper conductive structure 2a and the intermediate layer 12, for example, in terms of root mean squared surface roughness, about 1.1 times or more, about 1.3 times or more, or about 1.5 times or more.

[0098] In some embodiments, the material of the intermediate layer 12 is transparent and can be seen through by the human eye or a machine. That is, the human eye or a machine can identify or detect markings placed adjacent to the top surface 31 of the lower conductive structure 3a from the top surface 21 of the upper conductive structure 2a. In addition, the material of the intermediate layer 12 may include an insulating film, such as an Ajinomoto build-up film (ABF).

[0099] The via 123 extends through the intermediate layer 12. In some embodiments, the via 123 of the intermediate layer 12 may extend through the bottom first circuit layer 24 of the upper conductive structure 2a and terminate at or on the top circuit layer of the lower conductive structure 3a (e.g., the second upper circuit layer 38'). That is, the via 123 of the intermediate layer 12 does not extend through the top circuit layer of the lower conductive structure 3a (e.g., the second upper circuit layer 38'). The via 123 of the intermediate layer 12 may expose a portion of the top circuit layer of the lower conductive structure 3a (e.g., the top surface of the second upper circuit layer 38').

[0100] like Figure 4 As shown, the through-hole 123 of the intermediate layer 12 gradually decreases in size downwards from the top surface 121 to the bottom surface 122 of the intermediate layer 12; that is, the size of the top portion of the through-hole 123 is larger than the size of the bottom portion of the through-hole 123. Furthermore, the through-hole 123 of the intermediate layer 12 is aligned with and communicates with the through-hole 203 of the first dielectric layer 20 and the through-hole 263 of the second dielectric layer 26. The bottom portion of the through-hole 203 of the bottommost first dielectric layer 20 is positioned adjacent to or connected to the top portion of the through-hole 123 of the intermediate layer 12. The size of the bottom portion of the through-hole 203 of the bottommost first dielectric layer 20 is substantially equal to the size of the top portion of the through-hole 123 of the intermediate layer 12. Therefore, the inner surface 1231 of the through-hole 123 of the intermediate layer 12 is coplanar or aligned with the inner surface 2031 of the through-hole 203 of the first dielectric layer 20 and the inner surface 2631 of the through-hole 263 of the second dielectric layer 26. In some embodiments, the inner surface 1231 of the through-hole 123 of the intermediate layer 12 may be a curved surface and is part of the inner surface 231 of a single continuous through-hole 23 for receiving the upper through-hole 14. The through-hole 123 of the intermediate layer 12, the through-hole 203 of the first dielectric layer 20, and the through-hole 263 of the second dielectric layer 26 are configured together to form or define a single through-hole 23. Therefore, a single through-hole 23 includes the through-hole 123 of the intermediate layer 12, the through-hole 203 of the first dielectric layer 20, and the through-hole 263 of the second dielectric layer 26.

[0101] like Figure 4As shown, the cross-sectional views of one side of the via 123 of the intermediate layer 12, the inner surface 2031 of the via 203 of the first dielectric layer 20, and the inner surface 2631 of the via 263 of the second dielectric layer 26 are generally straight segments. That is, the cross-sectional views of one side of the inner surface 1231 of the via 123 of the intermediate layer 12, the inner surface 2031 of the via 203 of the first dielectric layer 20, and the inner surface 2631 of the via 263 of the second dielectric layer 26 can extend along the same generally straight line. A single via 23 extends through the upper conductive structure 2a and the intermediate layer 12; that is, a single via 23 extends from the top surface 21 of the upper conductive structure 2a to the bottom portion of the intermediate layer 12 to expose a portion of the topmost circuit layer of the lower conductive structure 3a (e.g., the top surface of the second upper circuit layer 38'). The single via 23 gradually decreases in size downwards. The maximum width of a single through-hole 23 (e.g., at the top portion) can be from about 25 μm to about 60 μm.

[0102] An upper through-hole 14 is formed or disposed in a corresponding single through-hole 23 and is made of metal, metal alloy, or other conductive material. Therefore, the upper through-hole 14 extends through at least a portion of the upper conductive structure 2a and the intermediate layer 12, and is electrically connected to the topmost circuit layer of the lower conductive structure 3a (e.g., the top surface of the second upper circuit layer 38'). Figure 4As shown, the upper through-hole 14 extends through and contacts the bottom first circuit layer 24 of the upper conductive structure 2a, and terminates at or on a portion of the top circuit layer of the lower conductive structure 3a (e.g., the top surface of the second upper circuit layer 38'), and contacts said portion. The upper through-hole 14 extends from the top surface 21 of the upper conductive structure 2a to the bottom surface 122 of the intermediate layer 12. Therefore, the upper through-hole 14 extends to contact a portion of the lower conductive structure 3a, and the upper through-hole 14 does not extend through the lower conductive structure 3a. In some embodiments, the low-density circuit layer (e.g., the second upper circuit layer 38') of the low-density conductive structure (e.g., the lower conductive structure 3a) is electrically connected to the high-density circuit layer (e.g., the bottom first circuit layer 24) of the high-density conductive structure (e.g., the upper conductive structure 2a) only through the upper through-hole 14 extending through the high-density circuit layer (e.g., the bottom first circuit layer 24) of the high-density conductive structure (e.g., the upper conductive structure 2a). The length (along the longitudinal axis) of the upper through-hole 14 is greater than the thickness of the high-density conductive structure (e.g., the upper conductive structure 2a). Furthermore, the upper through-hole 14 gradually decreases in size downwards; that is, the size of the top portion of the upper through-hole 14 is greater than the size of the bottom portion. Therefore, the decreasing direction of the inner through-hole 25 of the upper conductive structure 2a differs from the decreasing direction of the upper through-hole 14. In some embodiments, the upper through-hole 14 is a monolithic or one-piece structure with a homogeneous material composition, and the peripheral surface of the upper through-hole 14 is a generally continuous surface without boundaries. The upper through-hole 14 and the second circuit layer 28 can be integrally formed as a monolithic or one-piece structure. In some embodiments, the maximum width of the upper through-hole 14 can be less than about 40 μm, for example, about 30 μm or about 20 μm.

[0103] like Figures 1 to 4As illustrated in the embodiments, the wiring structure 1 is a combination of an upper stripe 2 and a lower substrate 3 (i.e., an upper conductive structure 2a and a lower conductive structure 3a), wherein the first circuit layer 24 of the upper stripe 2 (i.e., the upper conductive structure 2a) has fine pitch, high yield, and low thickness; and the circuit layers of the lower substrate 3 (i.e., the lower conductive structure 3a) (e.g., a first upper circuit layer 34; second upper circuit layers 38, 38'; a first lower circuit layer 34a and second lower circuit layers 38a, 38a') have low manufacturing costs. Therefore, the wiring structure 1 has an advantageous trade-off between yield and manufacturing cost, and the wiring structure 1 has a relatively low thickness. In some embodiments, if the package has 10,000 I / O counts, then the wiring structure 1 comprises three layers of the first circuit layer 24 of the upper strip 2 (i.e., the upper conductive structure 2a) and six layers of circuit layers (e.g., the first upper circuit layer 34; the second upper circuit layers 38, 38'; the first lower circuit layer 34a and the second lower circuit layers 38a, 38a') of the lower substrate 3 (i.e., the lower conductive structure 3a). The manufacturing yield of one layer of the first circuit layer 24 of the upper strip 2 (i.e., the upper conductive structure 2a) can be 99%, and the manufacturing yield of one layer of the circuit layers of the lower substrate 3 (i.e., the lower conductive structure 3a) (e.g., the first upper circuit layer 34; the second upper circuit layers 38, 38'; the first lower circuit layer 34a and the second lower circuit layers 38a, 38a') can be 90%. Therefore, the yield of the wiring structure 1 can be improved.

[0104] Furthermore, the warpage of the upper strip 2 (i.e., the upper conductive structure 2a) and the warpage of the lower substrate 3 (i.e., the lower conductive structure 3a) are separate and do not affect each other. In some embodiments, the warpage shape of the upper strip 2 (i.e., the upper conductive structure 2a) may differ from the warpage shape of the lower substrate 3 (i.e., the lower conductive structure 3a). For example, the warpage of the upper strip 2 (i.e., the upper conductive structure 2a) may be convex, and the warpage of the lower substrate 3 (i.e., the lower conductive structure 3a) may be concave. In some embodiments, the warpage shape of the upper strip 2 (i.e., the upper conductive structure 2a) may be the same as the warpage shape of the lower substrate 3 (i.e., the lower conductive structure 3a); however, the warpage of the lower substrate 3 (i.e., the lower conductive structure 3a) will not accumulate on the warpage of the upper strip 2 (i.e., the upper conductive structure 2a). Therefore, the yield of the wiring structure 1 can be further improved.

[0105] Furthermore, during the manufacturing process, the lower substrate 3 (i.e., the lower conductive structure 3a) and the upper strip 2 (i.e., the upper conductive structure 2a) can be individually tested before being bonded together. Therefore, known good lower substrate 3 (i.e., the lower conductive structure 3a) and known good upper strip 2 (i.e., the upper conductive structure 2a) can be selectively bonded together. Defective (or unqualified) lower substrate 3 (i.e., the lower conductive structure 3a) and defective (or unqualified) upper strip 2 (i.e., the upper conductive structure 2a) can be discarded. Therefore, the yield of the wiring structure 1 can be further improved.

[0106] Furthermore, during the manufacturing process, the relative positions of the upper strips 2 are separate and do not affect each other. In some embodiments, if one or more of the upper strips 2 can be displaced relative to a predetermined position on the lower substrate 3, the other upper strips 2 can still be positioned on the predetermined position on the lower substrate 3. Additionally, the design of the upper strips 2 can increase the effective area of ​​the lower substrate 3. That is, compared to a panel-type upper conductive structure, the lower substrate 3 can carry more upper strips 2 (or upper conductive structures 2a).

[0107] Figure 5 This illustration shows a cross-sectional view of a wiring structure 1a according to some embodiments of the present disclosure. The wiring structure 1a is similar to... Figure 4 The wiring structure 1 shown differs in the structure of the upper conductive structure 2a and the lower conductive structure 3a. For example... Figure 5 As shown, both the upper conductive structure 2a and the lower conductive structure 3a are bare die units after the single-layer process. Furthermore, the peripheral surface 27 of the upper conductive structure 2a, the peripheral surface 125 of the intermediate layer 12, and the peripheral surface 33 of the lower conductive structure 3a are substantially coplanar. That is, the size of the upper conductive structure 2a is equal to the size of the lower conductive structure 3a.

[0108] Figure 6 This illustration shows a cross-sectional view of a wiring structure 1b according to some embodiments of the present disclosure. The wiring structure 1b is similar to... Figure 5The wiring structure 1a shown differs in that it has at least one through-hole 16. The through-hole 16 is disposed in a single continuous via 17. The single via 17 extends through the upper conductive structure 2a, the intermediate layer 12, and the lower conductive structure 3a (including the second lower circuit layer 38a'); that is, the single via 17 extends from the top surface 21 of the upper conductive structure 2a to the bottom surface 32 of the lower conductive structure 3a. The maximum width of the single via 17 can be from about 100 μm to about 1000 μm. In some embodiments, the single via 17 can be formed by mechanical drilling. Therefore, the via 17 may not gradually decrease in size, and the inner surface 171 of the via 17 may be substantially perpendicular to the top surface 21 of the upper conductive structure 2a and / or the bottom surface 32 of the lower conductive structure 3a.

[0109] Each through-hole 16 is formed or disposed in a corresponding through-hole 17 and is made of metal, metal alloy, or other conductive material. Therefore, the through-hole 16 extends through the upper conductive structure 2a, the intermediate layer 12, and the lower conductive structure 3a. For example... Figure 6 As shown, the via 16 extends through and contacts the bottommost circuit layer 24 of the upper conductive structure 2a, the topmost circuit layer (e.g., the second upper circuit layer 38') of the lower conductive structure 3a, and the bottommost circuit layer (e.g., the second lower circuit layer 38a') of the lower conductive structure 3a. In some embodiments, the low-density circuit layer (e.g., the second upper circuit layer 38') of the low-density conductive structure (e.g., the lower conductive structure 3a) is electrically connected to the high-density circuit layer (e.g., the first circuit layer 24) of the high-density conductive structure (e.g., the upper conductive structure 2a) only through the via 16. In some embodiments, the via 16 is a monolithic structure or a one-piece structure with a homogeneous material composition, and the peripheral surface 163 of the via 16 is a generally continuous surface without boundaries. The via 16 and the outer circuit layer 28 may be integrally formed.

[0110] Figure 7 This illustration shows a cross-sectional view of a wiring structure 1c according to some embodiments of the present disclosure. The wiring structure 1c is similar to... Figure 5The wiring structure 1a shown differs in the structure of the upper conductive structure 2c, the lower conductive structure 3c, and the lower encapsulant 80. The size of the upper conductive structure 2c is approximately equal to the size of the lower conductive structure 3c. Therefore, the width W2 of the upper conductive structure 2c is approximately equal to the width W3 of the lower conductive structure 3c. The peripheral side surface 27 of the upper conductive structure 2c is approximately coplanar with the peripheral side surface 33 of the lower conductive structure 3c. The lower encapsulant 80 surrounds the peripheral side surface 33 of the lower conductive structure 3c. In some embodiments, the lower encapsulant 80 may be a molding compound and may cover and contact the peripheral side surface 33 of the lower conductive structure 3c. Therefore, the peripheral side surface 27 of the upper conductive structure 2c is not coplanar with the peripheral side surface 803 of the lower encapsulant 80 (e.g., it is recessed inward or otherwise displaced from it). Additionally, a portion of the intermediate layer 12 covers the top surface 801 of the lower encapsulant 80. Therefore, the peripheral surface 27 of the upper conductive structure 2c is not coplanar with the peripheral surface 125 of the intermediate layer 12 (e.g., it is recessed inward or otherwise displaced from it). In some embodiments, during the manufacturing process, a plurality of lower conductive structures 3c may be known good die cells and reconstituted and encapsulated in a lower encapsulation 80. Then, the plurality of known good upper conductive structures 2c are respectively attached to the lower conductive structures 3c. Next, a single-parting process is performed along the lower encapsulation 80. Therefore, a portion of the lower encapsulation 80 remains on the peripheral surface 33 of the lower conductive structure 3c.

[0111] Figure 8 This illustration shows a cross-sectional view of a wiring structure 1d according to some embodiments of the present disclosure. The wiring structure 1d is similar to... Figure 7 The wiring structure 1c shown differs in the structure of the upper conductive structure 2d. The size of the upper conductive structure 2d is smaller than the size of the lower conductive structure 3c. Therefore, the width W2' of the upper conductive structure 2d is smaller than the width W3 of the lower conductive structure 3c. The peripheral surface 27 of the upper conductive structure 2d is not coplanar with the peripheral surface 33 of the lower conductive structure 3c (e.g., it is recessed inward or otherwise displaced from it).

[0112] Figure 9 This illustration shows a cross-sectional view of a wiring structure 1e according to some embodiments of the present disclosure. The wiring structure 1e is similar to... Figure 7The wiring structure 1c shown differs in that it further includes an upper encapsulation 82. The upper encapsulation 82 surrounds the peripheral side surface 27 of the upper conductive structure 2c. In some embodiments, the upper encapsulation 82 may be a molding compound and may cover and contact the peripheral side surface 27 of the upper conductive structure 2c. Therefore, the peripheral side surface 823 of the upper encapsulation 82 is substantially coplanar with the peripheral side surface 803 of the lower encapsulation 80. Additionally, the upper encapsulation 82 may cover and contact a portion of the top surface of the intermediate layer 12. In some embodiments, during the manufacturing process, a plurality of lower conductive structures 3c may be known good die cells and reconstructed and encapsulated in the lower encapsulation 80, and a plurality of upper conductive structures 2c may be known good die cells and reconstructed and encapsulated in the upper encapsulation 82. The upper conductive structure 2c having the upper encapsulation 82 is then attached to the lower conductive structure 3c having the lower encapsulation 80. Next, a separation process is performed along the upper encapsulation 82 and the lower encapsulation 80. Therefore, a portion of the upper encapsulation 82 remains on the peripheral surface 27 of the upper conductive structure 2c, and a portion of the lower encapsulation 80 remains on the peripheral surface 33 of the lower conductive structure 3c.

[0113] Figure 10 This illustration shows a cross-sectional view of a wiring structure 1f according to some embodiments of the present disclosure. The wiring structure 1f is similar to... Figure 9 The wiring structure 1e shown differs in the structure of the upper conductive structure 2f. The size of the upper conductive structure 2f is smaller than the size of the lower conductive structure 3c. Therefore, the width W2' of the upper conductive structure 2f is smaller than the width W3 of the lower conductive structure 3c. The peripheral surface 27 of the upper conductive structure 2f is not coplanar with the peripheral surface 33 of the lower conductive structure 3c (e.g., it is recessed inward or otherwise displaced from it).

[0114] Figures 11 to 51 This invention describes a method for manufacturing a wiring structure according to some embodiments of the present disclosure. In some embodiments, the method is used to manufacture... Figure 4 The wiring structure 1 shown, and / or Figure 5 The wiring structure 1a shown is illustrated.

[0115] See Figures 11 to 31 A lower substrate 3 is provided. The lower substrate 3 is manufactured as follows. See Figure 11 A core portion 37 is provided having a top copper foil 50 and a bottom copper foil 52. The core portion 37 has a top surface 371 and a bottom surface 372 opposite to the top surface 371. The top copper foil 50 is disposed on the top surface 371 of the core portion 37, and the bottom copper foil 52 is disposed on the bottom surface 372 of the core portion 37.

[0116] See Figure 12Multiple through holes 373 are formed by drilling techniques (such as laser drilling or mechanical drilling) or other suitable techniques to extend through the core portion 37, the top copper foil 50 and the bottom copper foil 52.

[0117] See Figure 13 A second metal layer 54 is formed or disposed on the top copper foil 50, the bottom copper foil 52, and the sidewalls of the through-hole 373 by means of electroplating or other suitable techniques. A portion of the second metal layer 54 on the sidewall of each through-hole 373 defines a central through-hole.

[0118] See Figure 14 Insulating material 392 is placed to fill the central through hole defined by the second metal layer 54.

[0119] See Figure 15 The top third metal layer 56 and the bottom third metal layer 56a are formed or disposed on the second metal layer 54 by electroplating or other suitable techniques. The third metal layers 56 and 56a cover the insulating material 392.

[0120] See Figure 16 A top photoresist layer 57 is formed or disposed on a top third metal layer 56, and a bottom photoresist layer 57a is formed or disposed on a bottom third metal layer 56a. The photoresist layers 57 and 57a are then patterned by exposure and development.

[0121] See Figure 17 The portions of the top copper foil 50, the second metal layer 54, and the top third metal layer 56 not covered by the top photoresist layer 57 are removed using etching or other suitable techniques. The portions of the top copper foil 50, the second metal layer 54, and the top third metal layer 56 covered by the top photoresist layer 57 are retained to form the first upper circuit layer 34. Simultaneously, the portions of the bottom copper foil 52, the second metal layer 54, and the bottom third metal layer 56a not covered by the bottom photoresist layer 57a are removed using etching or other suitable techniques. The portions of the bottom copper foil 52, the second metal layer 54, and the bottom third metal layer 56a covered by the bottom photoresist layer 57a are retained to form the first lower circuit layer 34a. Meanwhile, the portions of the second metal layer 54 and the insulating material 392 disposed in the via 373 form interconnect vias 39. The interconnect vias 39 electrically connect the first upper circuit layer 34 and the first lower circuit layer 34a.

[0122] refer to Figure 18 The top photoresist layer 57 and the bottom photoresist layer 57a are removed by stripping techniques or other suitable techniques.

[0123] See Figure 19A first upper dielectric layer 30 is formed or disposed on the top surface 371 of the core portion 37 using lamination or other suitable techniques to cover the top surface 371 of the core portion 37 and the first upper circuit layer 34. Simultaneously, a first lower dielectric layer 30a is formed or disposed on the bottom surface 372 of the core portion 37 using lamination or other suitable techniques to cover the bottom surface 372 of the core portion 37 and the first lower circuit layer 34a.

[0124] See Figure 20 At least one via 303 is formed by drilling or other suitable techniques to extend through the first upper dielectric layer 30 to expose a portion of the first upper circuit layer 34. Simultaneously, at least one via 303a is formed by drilling or other suitable techniques to extend through the first lower dielectric layer 30a to expose a portion of the first lower circuit layer 34a.

[0125] See Figure 21 A top metal layer 58 is formed on the first upper dielectric layer 30 and in the via 303 using electroplating or other suitable techniques to form the upper interconnect via 35. Simultaneously, a bottom metal layer 60 is formed on the first lower dielectric layer 30a and in the via 303a using electroplating or other suitable techniques to form the lower interconnect via 35a.

[0126] See Figure 22 A top photoresist layer 59 is formed or disposed on a top metal layer 58, and a bottom photoresist layer 59a is formed or disposed on a bottom metal layer 60. The photoresist layers 59 and 59a are then patterned by exposure and development.

[0127] See Figure 23 The portions of the top metal layer 58 not covered by the top photoresist layer 59 are removed using etching or other suitable techniques. The portions of the top metal layer 58 covered by the top photoresist layer 59 are retained to form the second upper circuit layer 38. Simultaneously, the portions of the bottom metal layer 60 not covered by the bottom photoresist layer 59a are removed using etching or other suitable techniques. The portions of the bottom metal layer 60 covered by the bottom photoresist layer 59a are retained to form the second lower circuit layer 38a.

[0128] See Figure 24 The top photoresist layer 59 and the bottom photoresist layer 59a are removed by stripping techniques or other suitable techniques.

[0129] See Figure 25A second upper dielectric layer 36 is formed or disposed on the top surface 301 of the first upper dielectric layer 30 using lamination or other suitable techniques to cover the top surface 301 of the first upper dielectric layer 30 and the second upper circuit layer 38. Simultaneously, a second lower dielectric layer 36a is formed or disposed on the bottom surface 302a of the first lower dielectric layer 30a using lamination or other suitable techniques to cover the bottom surface 302a of the first lower dielectric layer 30a and the second lower circuit layer 38a.

[0130] See Figure 26 At least one via 363 is formed by drilling or other suitable techniques to extend through the second upper dielectric layer 36 to expose a portion of the second upper circuit layer 38. Simultaneously, at least one via 363a is formed by drilling or other suitable techniques to extend through the second lower dielectric layer 36a to expose a portion of the second lower circuit layer 38a.

[0131] See Figure 27 A top metal layer 62 is formed on the second upper dielectric layer 36 and in the via 363 using electroplating or other suitable techniques to form the upper interconnect via 35. Simultaneously, a bottom metal layer 64 is formed on the second lower dielectric layer 36a and in the via 363a using electroplating or other suitable techniques to form the lower interconnect via 35a.

[0132] See Figure 28 A top photoresist layer 63 is formed or disposed on a top metal layer 62, and a bottom photoresist layer 63a is formed or disposed on a bottom metal layer 64. The photoresist layers 63 and 63a are then patterned by exposure and development.

[0133] See Figure 29 The portions of the top metal layer 62 not covered by the top photoresist layer 63 are removed using etching or other suitable techniques. The portions of the top metal layer 62 covered by the top photoresist layer 63 are retained to form the second upper circuit layer 38'. Simultaneously, the portions of the bottom metal layer 64 not covered by the bottom photoresist layer 63a are removed using etching or other suitable techniques. The portions of the bottom metal layer 64 covered by the bottom photoresist layer 63a are retained to form the second lower circuit layer 38a'.

[0134] See Figure 30 The top photoresist layer 63 and the bottom photoresist layer 63a are removed by stripping techniques or other suitable techniques. Simultaneously, a lower substrate 3 having at least one lower conductive structure 3a is formed.

[0135] See Figure 30 and Figure 31 ,in Figure 31 illustrate Figure 30 A perspective view of the lower substrate 3. The lower substrate 3 includes at least one lower conductive structure 3a. For example, the lower substrate 3 may include multiple lower conductive structures 3a arranged in an array. The lower substrate 3 includes multiple strip regions 3'. The electrical characteristics (e.g., open circuit / short circuit) of the lower substrate 3 (i.e., the lower conductive structure 3a of the strip region 3') are then tested.

[0136] See Figures 32 to 44 Multiple upper strips 2 are provided. The upper strips 2 are manufactured as follows. See [link / reference]. Figure 32 A carrier 65 is provided. The carrier 65 can be a glass carrier and can be a wafer type or a panel type.

[0137] See Figure 33 The release layer 66 is applied to the bottom surface of the carrier 65.

[0138] See Figure 34 A conductive layer 67 (e.g., a seed layer) is formed or disposed on the release layer 66 using physical vapor deposition (PVD) or other suitable techniques.

[0139] See Figure 35 A second dielectric layer 26 is formed on the conductive layer 67 by coating technology or other suitable technology.

[0140] See Figure 36 At least one via 264 is formed by exposure and development techniques or other suitable techniques to extend through the second dielectric layer 26 to expose a portion of the conductive layer 67.

[0141] See Figure 37 Seed layers 68 are formed on the bottom surface 262 of the second dielectric layer 26 and in the vias 264 using PVD technology or other suitable techniques.

[0142] refer to Figure 38 A photoresist layer 69 is formed on the seed layer 68. Then, the photoresist layer 69 is patterned to expose portions of the seed layer 68 using exposure and development techniques or other suitable techniques. The photoresist layer 69 defines a plurality of openings 691. At least one opening 691 of the photoresist layer 69 corresponds to and is aligned with a via 264 of the second dielectric layer 26.

[0143] See Figure 39 Conductive material 70 (e.g., metallic material) is placed in the opening 691 of the photoresist layer 69 and on the seed layer 68 by electroplating or other suitable techniques.

[0144] See Figure 40 The photoresist layer 69 is removed by stripping techniques or other suitable techniques.

[0145] See Figure 41 The portion of the seed layer 68 not covered by the conductive material 70 is removed by etching or other suitable techniques. Simultaneously, a circuit layer 24 and at least one through-hole 25 are formed. The circuit layer 24 may be a fan-out circuit layer or an RDL, and the L / S ratio of the circuit layer 24 may be less than or equal to about 2 μm / about 2 μm, or less than or equal to about 1.8 μm / about 1.8 μm. The through-hole 25 is disposed in a via 264 of the second dielectric layer 26. In some embodiments, the through-hole 25 gradually decreases in size upwards.

[0146] See Figure 42 By repeating Figures 35 to 41 The process involves forming multiple first dielectric layers 20 and multiple circuit layers 24 in stages. In some embodiments, each circuit layer 24 is embedded in a corresponding first dielectric layer 20, and the top surface 241 of the circuit layer 24 may be substantially coplanar with the top surface 201 of the first dielectric layer 20. Simultaneously, a conductive structure 2' is formed. Next, the electrical characteristics (e.g., open / short circuit) of the conductive structure 2' are tested. Note that the conductive structure 2' may be wafer-type or panel-type.

[0147] See Figure 43 and Figure 44 ,in Figure 44 illustrate Figure 43 A perspective view of the upper strip 2. The conductive structure 2' and the carrier 65 are cut to form a plurality of upper strips 2 having a plurality of carrier strips 65a. Each of the upper strips 2 includes at least one upper conductive structure 2a. For example, each of the upper strips 2 may include a plurality of upper conductive structures 2a arranged in a row. Note that the upper strips 2 are strip-type.

[0148] See Figure 45 An adhesive layer (for forming the intermediate layer 12) is formed or applied on the top surface 31 of the lower substrate 3. The material of the adhesive layer may include an insulating film, such as ABF. In some embodiments, the lower substrate 3 may have a plurality of diced lines 87.

[0149] See Figure 46The upper strip 2 and the carrier strip 65a are attached side-by-side to the strip region 3' of the lower substrate 3 via an adhesive layer (for forming an intermediate layer 12). The upper strip 2 faces the lower substrate 3. The positions of the upper conductive structure 2a and the carrier strip 65a of the upper strip 2 correspond to the positions of the lower conductive structure 3a of the lower substrate 3. That is, the upper conductive structure 2a is positioned directly above the lower conductive structure 3a. In some embodiments, the known good upper strip 2' is selectively attached to the known good strip region 3' of the lower substrate 3. For example, the wiring structure 1a ( Figure 5 The desired yield can be set to 80%. That is, the yield of (upper strip 2) × (yield of strip region 3' of lower substrate 3) is set to be greater than or equal to 80%. If the yield of upper strip 2 is less than the predetermined yield (e.g., 80%) (which is designated as a defective or unqualified component), then the defective (or unqualified) upper strip 2 is discarded. If the yield of upper strip 2 is greater than or equal to the predetermined yield, such as 80% (which is designated as a known good or qualified component), then the known good upper strip 2 can be used. In addition, if the yield of strip region 3' of lower substrate 3 is less than the predetermined yield (e.g., 80%) (which is designated as a defective or unqualified component), then the defective (or unqualified) strip region 3' is marked, and it will not be bonded to any upper strip 2. If the yield of the strip region 3' of the lower substrate 3 is greater than or equal to a predetermined yield (e.g., 80%) (which is designated as a known good component or a qualified component), then the known good upper strip 2 can be bonded to the known good strip region 3' of the lower substrate 3. Note that the upper strip 2 with a yield of 80% will not be bonded to the strip region 3' of the lower substrate 3 with a yield of 80%, because the wiring structure 1a ( Figure 5 The yield obtained is 64%, which is lower than the desired yield of 80%. The upper strip 2 with a yield of 80% can be bonded to the strip region 3' of the lower substrate 3 with a yield of 100%; therefore, the wiring structure 1a ( Figure 5 The yield obtained can be 80%. Furthermore, the upper strip 2, with a yield of 90%, can be bonded to the strip region 3' of the lower substrate 3, which has a yield greater than 90%, because the wiring structure 1a ( Figure 5 The yield rate can be greater than 80%.

[0150] Furthermore, the relative positions of the upper strips 2 are separate and will not affect each other. In some embodiments, if one or some of the upper strips 2 are displaced relative to a predetermined position on the lower substrate 3, the other upper strips 2 can still be positioned on the predetermined position on the lower substrate 3.

[0151] Next, the adhesive layer is cured to form the intermediate layer 12.

[0152] refer to Figure 47Remove the carrier strip 65a, release layer 66, and conductive layer 67 to expose a portion of the internal through-hole 25.

[0153] See Figure 48 At least one via 23 is formed by drilling (e.g., laser drilling) to extend through at least a portion of the upper conductive structure 2a and the intermediate layer 12, thereby exposing a circuit layer of the lower conductive structure 3a (e.g., a second upper circuit layer 38'). The via 23 may include vias 263 of the second dielectric layer 26, a plurality of vias 203 of the first dielectric layer 20, and vias 123 of the intermediate layer 12. In some embodiments, the via 23 extends through the bottommost first circuit layer 24 of the upper conductive structure 2a and terminates at or on the topmost circuit layer of the lower conductive structure 3a (i.e., the second upper circuit layer 38'). That is, the via 23 does not extend through the topmost circuit layer of the lower conductive structure 3a (e.g., the second upper circuit layer 38'). The via 23 may expose a portion of the topmost circuit layer of the lower conductive structure 3a (e.g., the top surface of the second upper circuit layer 38'). Figure 48 As shown, the through-hole 23 gradually decreases in size downwards; that is, the size of the top portion of the through-hole 23 is larger than the size of the bottom portion of the through-hole 23. In addition, the inner surface 1231 of the through-hole 123 of the intermediate layer 12 is coplanar or aligned with the inner surface 2031 of the through-hole 203 of the first dielectric layer 20 and the inner surface 2631 of the through-hole 263 of the second dielectric layer 26.

[0154] See Figure 49 A metal layer 72 is formed on the top surface 21 of the upper conductive structure 2a and in the through-hole 23 by electroplating or other suitable techniques to form at least one upper through-hole 14 in the through-hole 23. Therefore, the upper conductive structure 2a of the upper strip 2 is electrically connected to the lower conductive structure 3a of the lower substrate 3 through the upper through-hole 14.

[0155] See Figure 50 A top photoresist layer 73 is formed or disposed on the metal layer 72, and a bottom photoresist layer 73a is formed or disposed on the bottom surface 32 of the lower conductive structure 3a. Next, the top photoresist layer 73 is patterned using exposure and development techniques or other suitable techniques.

[0156] See Figure 51 The portions of metal layer 72 not covered by the top photoresist layer 73 are removed using etching or other suitable techniques. The portions of metal layer 72 covered by the top photoresist layer 73 are retained to form the second circuit layer 28. Next, the top photoresist layer 73 and the bottom photoresist layer 73a are removed using stripping or other suitable techniques to obtain... Figures 1 to 4 Wiring structure 1.

[0157] In some embodiments, the lower conductive structure 3a and the intermediate layer 12 are individually separated along the cutting line 87 to obtain... Figure 5 Multiple wiring structures 1a.

[0158] Figures 52 to 59 This invention describes a method for manufacturing a wiring structure according to some embodiments of the present disclosure. In some embodiments, in Figure 7 The diagram illustrates a method for manufacturing wiring structure 1c. The initial stages of the described process are... Figures 11 to 31 The stages shown are the same or similar. Figure 52 Depicting Figure 31 The stage following the stage described in the text.

[0159] See Figure 52 The diagram shows a top view of the lower substrate 3. After the testing process, the lower conductive structure 3a that passes the test is marked as a known good die cell or a qualified die cell. Meanwhile, the lower conductive structure 3a' that fails the test is marked as a known bad die cell or a non-qualified die cell.

[0160] See Figure 53 The known good lower conductive structure 3a is separated and picked up from the lower substrate 3 to form multiple openings 84 in the lower substrate 3. Meanwhile, the known poor lower conductive structure 3a' is retained in the lower substrate 3 and can be discarded.

[0161] See Figure 54 The known good lower conductive structure 3a is reconstructed and rearranged into an array. Then, a lower encapsulation 80 (e.g., a molding compound) is formed to encapsulate the known good lower conductive structure 3a to form a lower module 86.

[0162] The subsequent stages of the process described and Figures 32 to 42 The stages described herein are the same or similar. Figure 55 Depicting Figure 42 The stage following the stage described in the text. See also... Figure 55 , Figure 42 The conductive structure 2' and the carrier 65 are cut to form multiple upper conductive structures 2a. Note that each of the upper conductive structures 2a is a bare die unit.

[0163] See Figure 56 , Figure 57 and Figure 58 ,in Figure 57 illustrate Figure 56 The 3D image, and Figure 58 illustrate Figure 56A partial cross-sectional view. The upper conductive structure 2a and the carrier 65 are attached to the lower module 86 via an adhesive layer (to form the intermediate layer 12). The upper conductive structure 2a faces the lower module 86. The adhesive layer is then cured to form the intermediate layer 12. Next, the carrier strip 65, the release layer 66, and the conductive layer 67 are removed to expose a portion of the internal through-hole 25. Figure 56 and Figure 58 As shown, the lower module 86 may contain multiple intersecting cutting lines 87.

[0164] See Figure 59 At least one upper through-hole 14 is formed to extend through the upper conductive structure 2a and the intermediate layer 12. Therefore, the upper conductive structure 2a is electrically connected to the lower conductive structure 3a of the lower module 86 through the upper through-hole 14.

[0165] Next, a single-splitting process is performed to separate the lower module 86 along the cutting line 87 to form... Figure 7 Multiple wiring structures 1c.

[0166] Figures 60 to 65 This invention describes a method for manufacturing a wiring structure according to some embodiments of the present disclosure. In some embodiments, in Figure 9 The diagram illustrates a method for manufacturing wiring structure 1e. The initial stage of the described process is as follows: Figures 11 to 31 , Figures 52 to 54 as well as Figures 32 to 42 The stages described in the text are the same or similar. Figure 60 Depicting Figure 42 The stage following the stage described in the text.

[0167] See Figure 60 The diagram shows a top view of the conductive structure 2'. After the testing process, the upper conductive structure 2a that passes the test is marked as a known good die cell or a qualified die cell. Meanwhile, the upper conductive structure 2a' that fails the test is marked as a known bad die cell or a non-qualified die cell.

[0168] See Figure 61 The known good upper conductive structure 2a is separated from the conductive structure 2' and picked up to form multiple openings 88 in the conductive structure 2'. Meanwhile, the known bad upper conductive structure 2a' is retained in the conductive structure 2' and can be discarded.

[0169] See Figure 62 The known good upper conductive structure 2a is reconstructed and rearranged into an array. Then, an upper encapsulation 82 (e.g., a molding compound) is formed to encapsulate the known good upper conductive structure 2a to form the upper module 90.

[0170] See Figure 63 and Figure 64 ,in Figure 64 illustrate Figure 63 A partial cross-sectional view. The upper module 90 is attached to the lower module 86 via an adhesive layer (to form the intermediate layer 12). Thus, the known good upper conductive structure 2a is attached to the known good lower conductive structure 3a. Next, the adhesive layer is cured to form the intermediate layer 12.

[0171] See Figure 65 At least one upper through-hole 14 is formed to extend through the upper conductive structure 2a and the intermediate layer 12. Therefore, the upper conductive structure 2a of the upper module 90 is electrically connected to the lower conductive structure 3a of the lower module 86 through the upper through-hole 14.

[0172] Next, a single-splitting process is performed along the cutting line to separate the lower module 86, the middle layer 12, and the upper module 90, thus forming... Figure 9 Multiple wiring structures 1e.

[0173] Unless otherwise stated, spatial descriptions such as “above,” “below,” “up,” “left,” “right,” “lower,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “above,” “below,” etc., are relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, provided that the advantages of the embodiments of this disclosure are not deviated from by such arrangements.

[0174] As used herein, the terms “approximately,” “generally,” “substantially,” and “about” are used to describe and account for minor variations. When used in conjunction with an event or situation, the terms may refer to a situation in which the event or situation has clearly occurred or is very close to occurring. For example, when used in conjunction with a numerical value, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if a first value is within a range of variation less than or equal to ±10% of a second value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the first value may be considered “generally” the same as or equal to the second value. For example, “generally” vertical can refer to the range of angular variation relative to 90° that is less than or equal to ±10° (e.g., less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°).

[0175] If the displacement between two surfaces is no greater than 5 µm, 2 µm, 1 µm, or 0.5 µm, then the two surfaces can be considered coplanar or substantially coplanar. If the displacement between the highest and lowest points of a surface is no greater than 5 µm, 2 µm, 1 µm, or 0.5 µm, then the surface can be considered substantially flat.

[0176] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include multiple indicators.

[0177] As used herein, the terms “conductive,” “electrically conductive,” and “conductivity” refer to the ability to conduct electric current. Conductive materials typically indicate those that exhibit very little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Generally, conductive materials are those with a conductivity greater than approximately 10. 4 S / m (e.g., at least 10) 5 S / m or at least 10 6 A material with an electrical conductivity of (S / m). The electrical conductivity of the material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of the material is measured at room temperature.

[0178] Additionally, quantities, ratios, and other values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only values ​​explicitly specified as range limits, but also all individual values ​​or subranges covered within the range, as if each value and subrange were explicitly specified.

[0179] While this disclosure has been described and illustrated with reference to specific embodiments of the invention, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions for equivalents may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Artistic representations in this disclosure may differ from actual equipment due to manufacturing processes and tolerances. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it will be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of this disclosure.

Claims

1. A coreless substrate-free wiring structure, comprising: An upper conductive structure includes at least one upper dielectric layer, a plurality of circuit layers in contact with the upper dielectric layer, and a plurality of internal through-holes disposed between two adjacent circuit layers, wherein each internal through-hole gradually decreases in size upward in a direction from the bottom surface of the upper conductive structure toward the top surface. A lower conductive structure includes at least one lower dielectric layer and a plurality of circuit layers in contact with the lower dielectric layer, wherein the line spacing of the circuit layers of the lower conductive structure is greater than the line spacing of the circuit layers of the upper conductive structure. A lower encapsulation material surrounds the outer surface of the lower conductive structure; An intermediate layer, disposed between the upper conductive structure and the lower conductive structure, and bonding the upper and lower conductive structures together, wherein the upper conductive structure is electrically connected to the lower conductive structure, and wherein the peripheral surface of the intermediate layer is substantially coplanar with the peripheral surface of the lower encapsulation; and An upper through-hole extends through the upper conductive structure and the intermediate layer, and terminates on the topmost circuit layer of the lower conductive structure, wherein the width of the upper through-hole gradually decreases downward.

2. The wiring structure without a core substrate according to claim 1, wherein the peripheral surface of the upper conductive structure is recessed inward from the peripheral surface of the lower encapsulation, and a portion of the top surface of the intermediate layer is exposed to air.

3. The wiring structure without a core substrate according to claim 1, wherein a portion of the intermediate layer covers the top surface of the lower encapsulation.

4. The coreless substrate-free wiring structure according to claim 1, further comprising: A single via extending through the upper conductive structure and the intermediate layer, the upper through-hole being disposed in the single via, wherein the upper dielectric layer of the upper conductive structure has a via, the intermediate layer has a via, the via in the upper dielectric layer and the via in the intermediate layer together define the single via, and the cross-sectional view of one side of the inner surface of the via in the upper dielectric layer and the inner surface of the via in the intermediate layer is a substantially straight segment.

5. The wiring structure without a core substrate according to claim 1, wherein the bottommost circuit layer of the upper conductive structure and the topmost circuit layer of the lower conductive structure are embedded in the intermediate layer.

6. The wiring structure without a core substrate according to claim 1, wherein the material of the upper dielectric layer and the material of the intermediate layer are transparent.

7. The wiring structure without a core substrate according to claim 6, wherein the material of the upper dielectric layer has a transmittance of 60% to 80% for wavelengths in the visible range.

8. The wiring structure without a core substrate according to claim 1, wherein the upper conductive structure comprises a plurality of upper dielectric layers, the bonding force between two adjacent upper dielectric layers of the upper conductive structure is greater than the bonding force between the bottom upper dielectric layer of the upper conductive structure and the intermediate layer, and the surface roughness of the boundary between the two adjacent upper dielectric layers of the upper conductive structure is 1.1 times or greater than the surface roughness of the boundary between the bottom upper dielectric layer of the upper conductive structure and the intermediate layer.

9. The wiring structure without a core substrate according to claim 1, wherein the plurality of circuit layers of the upper conductive structure includes a first circuit layer and a second circuit layer, the first circuit layer is embedded in the upper conductive structure, the second circuit layer is disposed on and extends from the top surface of the upper conductive structure, the line spacing of the second circuit layer is greater than or equal to the line spacing of the first circuit layer, and the upper through-hole and the second circuit layer are integrally formed as a single block or single piece structure.

10. A method for manufacturing a wiring structure without a core substrate, comprising: (a) A lower substrate comprising at least one lower conductive structure, wherein the lower conductive structure comprises at least one dielectric layer and at least one circuit layer in contact with the dielectric layer; (a1) Test the electrical properties of the lower conductive structure of the lower substrate to confirm that the lower conductive structure is a known good lower conductive structure; (b) Providing a plurality of upper strips, wherein each of the upper strips includes at least one upper conductive structure, and the upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer, wherein (b) includes: (b1) Forming a conductive structure on the carrier; (b2) Cutting the conductive structure and the carrier to form a plurality of upper strips having a plurality of carrier strips; and (b3) Test the electrical properties of the upper conductive structure of the plurality of upper strips to confirm that the plurality of upper strips are known good upper strips with a yield greater than or equal to 80%; (c) A plurality of the upper strips are attached side-by-side to the lower substrate through an intermediate layer, wherein the relative positions of the plurality of upper strips are separated, wherein the position of the upper conductive structure of the upper strip corresponds to the position of the lower conductive structure of the lower substrate. (d) Forming at least one through-hole extending through at least a portion of the upper conductive structure and the intermediate layer by drilling, and forming at least one upper through-hole in the at least one through-hole to electrically connect the upper conductive structure of the upper strip to the lower conductive structure of the lower substrate through the at least one upper through-hole; and (e) Perform a single-part process to form multiple wiring structures.

11. The method according to claim 10, In (c), the upper strip and the carrier strip are attached to the lower substrate, wherein the upper strip faces the lower substrate; Following (c), the method further includes: (c1) Remove the carrier strip.

12. The method of claim 10, wherein in (c), the upper strip is attached to the lower substrate by an adhesive layer.

13. The method according to claim 10, wherein the width of the at least one through hole gradually decreases downwards, and the width of the at least one upper through hole gradually decreases downwards.

14. The method of claim 10, wherein in (b3), the manufacturing yield of the circuit layer of the upper conductive structure of the upper strip is different from the manufacturing yield of the circuit layer of the lower conductive structure of the lower substrate.

15. The method of claim 14, wherein in (b3), the manufacturing yield of the circuit layer of the upper conductive structure of the upper strip is lower than the manufacturing yield of the circuit layer of the lower conductive structure of the lower substrate.

16. A method for manufacturing a wiring structure without a core substrate, comprising: (a) A plurality of lower conductive structures are provided, wherein each of the lower conductive structures includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer; (b) Forming a lower encapsulation to encapsulate multiple known good lower conductive structures to form a lower module; (c) Providing a plurality of upper conductive structures, wherein each of the upper conductive structures comprises at least one dielectric layer and at least one circuit layer in contact with the dielectric layer of the upper conductive structure, wherein (c) includes: (c1) Forming a conductive structure on a carrier; and (c2) Cut the conductive structure and the carrier to form the plurality of upper conductive structures; (d) Attaching a plurality of the upper conductive structures side-by-side to the known good lower conductive structure of the lower module through an intermediate layer, wherein the relative positions of the plurality of upper conductive structures are separated; (e) Forming at least one through-hole extending through at least a portion of the upper conductive structure and the intermediate layer by drilling, and forming at least one upper through-hole in the at least one through-hole to electrically connect the upper conductive structure to the known good lower conductive structure of the lower module through the at least one upper through-hole; and (f) Perform a single-step process to form multiple wiring structures.

17. The method according to claim 16, In (d), the upper conductive structure and the carrier are attached to the lower module, wherein the upper conductive structure faces the lower module; Wherein, after (d), the method further includes: (d1) Remove the carrier.

18. The method of claim 16, wherein after (c), the method further comprises: (c1) An upper encapsulation is formed to encapsulate a plurality of known good upper conductive structures to form an upper module, wherein the peripheral side surface of the upper encapsulation is substantially coplanar with the peripheral side surface of the intermediate layer.

19. The method of claim 18, wherein (d) comprises: (d1) Attach the upper module to the lower module.

20. The method of claim 16, wherein in (d), the upper conductive structure is attached to the known good lower conductive structure of the lower module via an adhesive layer.

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