Display device

Abstract

A display device is disclosed. The display device may include the following elements: a substrate; a light shielding layer disposed on the substrate; a first insulating layer disposed on the light shielding layer; a transistor including a source electrode or a drain electrode, the source electrode or the drain electrode having an extension overlapping each of the first insulating layer and the light shielding layer; a second insulating layer disposed on the extension; and a pixel electrode disposed on the second insulating layer. The first insulating layer and the second insulating layer may include a contact hole, the contact hole exposing a portion of the light shielding layer and exposing a portion of the extension. The pixel electrode may directly contact each of the portion of the extension and the portion of the light shielding layer.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0060537 filed on May 23, 2019, in the Korean Intellectual Property Office; the entire contents of which are incorporated herein by reference. Technical Field

[0002] The technical field relates to a display device. Background Art

[0003] Modern display devices include, for example, liquid crystal display devices and organic light emitting diode display devices. A display device generally includes pixels for displaying an image, and each pixel includes a pixel electrode for receiving a data signal for displaying a predetermined brightness.

[0004] The pixel electrode may be electrically connected to the data line through a switching element such as a transistor. The pixel electrode and the switching element may be partially insulated by an insulating layer therebetween, and may be electrically connected through a contact hole formed through the insulating layer.

[0005] The above information disclosed in this Background section is for enhancement of understanding of the background of the application. This Background section may contain information that does not constitute the prior art that is already known in this country to a person of ordinary skill in the art. Summary of the invention

[0006] Embodiments relate to a display device that can prevent / minimize undesirable changes in charging voltage of pixels of the display device to prevent / minimize undesirable changes in brightness of the pixels. Advantageously, satisfactory display quality of the display device can be obtained.

[0007] In an embodiment, the display device can prevent connection failure of the pixel electrode. Advantageously, sufficient reliability of the display device can be obtained.

[0008] An embodiment may be directed to a display device, the display device comprising the following structure: a substrate; a light shielding layer disposed on the substrate; a first insulating layer disposed on the light shielding layer; an extension of a source electrode or a drain electrode disposed on the first insulating layer and overlapping the light shielding layer; a second insulating layer disposed on the extension; and a pixel electrode disposed on the second insulating layer and overlapping the light shielding layer and the extension. The first insulating layer and the second insulating layer may include a contact hole overlapping the light shielding layer and the extension, and the pixel electrode may contact an upper surface of the extension and an upper surface of the light shielding layer through the contact hole.

[0009] The contact hole may include a first region overlapping the light shielding layer and the extension and a second region overlapping the light shielding layer and not overlapping the extension.

[0010] The extension may be arranged within the light shielding layer in plan view.

[0011] The pixel electrode may include a portion disconnected in the contact hole.

[0012] The potential of the light shielding layer may be equal to the potential of the pixel electrode.

[0013] The display device may further include: a gate line disposed on the substrate and extending in the first direction; and a shielding electrode disposed on the second insulating layer. The shielding electrode may be a portion overlapping an edge of the gate line and extending along the edge of the gate line.

[0014] The display device may further include a gate line disposed on the substrate and extending in the first direction. The pixel electrode may include a first sub-pixel electrode disposed at one side of the gate line and a second sub-pixel electrode disposed at the other side of the gate line.

[0015] The first sub-pixel electrode or the second sub-pixel electrode may contact the extension and the light shielding layer through the contact hole.

[0016] The second insulating layer may include a first layer and a second layer, the first layer including an inorganic insulating material, and the second layer is disposed on the first layer and includes an organic insulating material.

[0017] The display device may further include a semiconductor layer overlapping the extension.

[0018] The display device may further include a liquid crystal layer disposed on the pixel electrode.

[0019] Embodiments may be directed to a display device including the following structure: a substrate; a gate line disposed on the substrate and extending in a first direction; a first insulating layer disposed on the gate line; a data line disposed on the first insulating layer and extending in a second direction intersecting the first direction; an extension of a source electrode or a drain electrode disposed on the first insulating layer; a second insulating layer disposed on the data line and the extension and including a contact hole overlapping the extension; and a pixel electrode connected to the extension through the contact hole. The contact hole has a polygonal shape including sides forming an angle in a range of about 15 degrees to about 75 degrees with the second direction.

[0020] The contact hole may have a polygonal shape including sides forming an angle of about 45 degrees with the second direction.

[0021] The contact hole may be formed in a rectangular shape.

[0022] A diagonal line of the rectangle may be parallel to the second direction.

[0023] The display device may further include a storage voltage line disposed on the substrate and extending in the first direction. The contact hole may overlap the storage voltage line.

[0024] The display device may further include: a reference voltage line disposed on the first insulating layer; an additional contact hole overlapping the reference voltage line and the storage voltage line; and a connecting member disposed on the second insulating layer and electrically connecting the reference voltage line and the storage voltage line through the additional contact hole.

[0025] The additional contact hole may be formed in a rectangular shape, wherein one diagonal line of the rectangle is parallel to the second direction.

[0026] The pixel electrode may include a first sub-pixel electrode disposed at one side of the gate line and a second sub-pixel electrode disposed at the other side of the gate line. The first sub-pixel electrode or the second sub-pixel electrode may be connected to the extension through a contact hole.

[0027] The display device may further include: a first shielding electrode disposed on the second insulating layer and overlapping the data line; and a second shielding electrode extending from the first shielding electrode in the first direction and overlapping the transistor including the extension.

[0028] The display device may further include a liquid crystal layer disposed on the pixel electrode.

[0029] Embodiments may relate to a display device. The display device may include the following structure: a substrate; a light shielding layer disposed on the substrate; a first insulating layer disposed on the light shielding layer; a transistor including a source electrode or a drain electrode, wherein the source electrode or the drain electrode includes an extension overlapping each of the first insulating layer and the light shielding layer; a second insulating layer disposed on the extension; and a pixel electrode disposed on the second insulating layer. The first insulating layer and the second insulating layer may include a contact hole that exposes a portion of the light shielding layer and exposes a portion of the extension. The pixel electrode may directly contact each of the portion of the extension and the portion of the light shielding layer.

[0030] The contact hole may include a first portion and a second portion. The first portion of the contact hole may expose the portion of the extension. The portion of the extension may partially overlap with the light shielding layer. The second portion of the contact hole may expose the portion of the light shielding layer. The portion of the light shielding layer may not overlap with the extension.

[0031] The extension may be provided within the light shielding layer in a plan view of the display device.

[0032] The extended surface may be exposed between two portions of the pixel electrode in the contact hole.

[0033] When the display device displays an image, the potential of the light shielding layer may be equal to the potential of the pixel electrode.

[0034] The display device may include the following elements: a gate line disposed on the substrate and extending in a first direction; and a shielding electrode disposed on the second insulating layer. A portion of the shielding electrode may overlap an edge of the gate line and may extend along the edge of the gate line.

[0035] The display device may include a gate line disposed on a substrate and extending in a first direction. The pixel electrode may include a first sub-pixel electrode and a second sub-pixel electrode. The gate line may be disposed between the first sub-pixel electrode and the second sub-pixel electrode. The first sub-pixel electrode or the second sub-pixel electrode may directly contact each of the extension and light shielding layers, and may be partially disposed inside the contact hole.

[0036] The second insulating layer may include a first layer and a second layer. The first layer may include an inorganic insulating material. The second layer may be disposed on the first layer and may include an organic insulating material.

[0037] The transistor may include a semiconductor layer overlapping the extension.

[0038] The display device may include a liquid crystal layer disposed on the pixel electrode and partially disposed inside the contact hole.

[0039] Embodiments may relate to a display device. The display device may include the following structure: a substrate; a gate line disposed on the substrate; a first insulating layer disposed on the gate line; a data line disposed on the first insulating layer, wherein an edge of the data line may be perpendicular to an edge of the gate line; a transistor including a source electrode or a drain electrode, wherein the source electrode or the drain electrode includes an extension overlapping the first insulating layer; a second insulating layer overlapping each of the data line and the extension and including a contact hole exposing a portion of the extension; and a pixel electrode directly contacting the portion of the extension. In a plan view of the display device, the contact hole may have a straight edge oriented at a certain angle relative to an edge of the data line. The angle may be in the range of 15 degrees to 75 degrees.

[0040] The angle may be in the range of 40 to 50 degrees.

[0041] The angle may be 45 degrees.

[0042] The contact hole may have a quadrilateral structure in a plan view of the display device.

[0043] A diagonal line of the quadrilateral structure may be parallel to an edge of the data line in a plan view of the display device.

[0044] The display device may include a storage voltage line disposed on the substrate and extending parallel to the gate line. The contact hole may expose the storage voltage line.

[0045] The display device may include the following structure: a reference voltage line, which is arranged on a first insulating layer; an additional contact hole, which exposes a portion of the reference voltage line and exposes a portion of the storage voltage line; and a connecting member, which is arranged on a second insulating layer and directly contacts each of the portion of the reference voltage line and the portion of the storage voltage line.

[0046] The additional contact hole may have a quadrilateral structure in a plan view of the display device, and a diagonal line of the quadrilateral structure may be parallel to an edge of the data line in a plan view of the display device.

[0047] The pixel electrode may include a first sub-pixel electrode and a second sub-pixel electrode. The gate line may be disposed between the first sub-pixel electrode and the second sub-pixel electrode. The first sub-pixel electrode or the second sub-pixel electrode may extend directly in contact and may be partially disposed inside the contact hole.

[0048] The display device may include the following elements: a first shielding electrode disposed on the second insulating layer and overlapping the data line; and a second shielding electrode extending from the first shielding electrode and overlapping the transistor.

[0049] The display device may include a liquid crystal layer disposed on the pixel electrode and partially disposed inside the contact hole.

[0050] According to an embodiment, parasitic capacitance in the connection area of ​​the pixel electrode can be prevented or minimized, and undesirable changes in the charging voltage of the pixel can be prevented or minimized, so that undesirable changes in the brightness of the pixel can be prevented or minimized.

[0051] According to the embodiment, even if an overlap shift occurs when forming a contact hole for connecting a pixel electrode, a connection failure of the pixel electrode can be prevented or minimized. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 A layout diagram of a display device according to an embodiment is shown.

[0053] Figure 2 An equivalent circuit diagram of one pixel of a display device according to an embodiment is shown.

[0054] Figure 3 A plan view showing one pixel of a display device according to an embodiment is shown.

[0055] Figure 4 A plan view of a region including a transistor and a contact hole according to an embodiment is shown.

[0056] Figure 5 According to an embodiment, Figure 4 A cross-sectional view taken along line AA'.

[0057] Figure 6 According to an embodiment, Figure 4 A cross-sectional view taken along line BB'.

[0058] Figure 7 A plan view showing one pixel of a display device according to an embodiment is shown.

[0059] Figure 8 A plan view of a region including a transistor and a contact hole according to an embodiment is shown.

[0060] Fig. 9 According to an embodiment, Figure 8 A cross-sectional view taken along line CC'.

[0061] Fig.10 is a plan view showing the positions of contact holes formed when an overlay shift occurs in a display device according to a comparative example.

[0062] Fig.11 is a plan view showing the positions of contact holes formed when an overlay shift occurs in a display device according to a comparative example.

[0063] Fig.12 is a plan view showing the positions of contact holes formed when an overlay shift occurs in the display device according to the embodiment.

[0064] Fig.13 is a plan view showing the positions of contact holes formed when an overlay shift occurs in the display device according to the embodiment.

[0065] Fig.14 The comparative example shows Fig.10 A cross-sectional view taken along line D-D'.

[0066] Fig.15 A plan view showing a region including a transistor and a contact hole in one pixel of a display device according to an embodiment is shown.

[0067] Fig.16 A plan view of a region including a transistor and a contact hole in one pixel of a display device according to an embodiment is shown. DETAILED DESCRIPTION

[0068] Example embodiments are described with reference to the accompanying drawings. The described embodiments may be modified in various ways, all without departing from the spirit or scope of the present disclosure.

[0069] Throughout the disclosure, like reference numerals may denote like elements.

[0070] In the drawings, the sizes of elements may be exaggerated for clarity.

[0071] Although the terms "first", "second", etc. can be used to describe various elements, these elements should not be limited by these terms. These terms can be used to distinguish an element from another element. Without departing from the teaching of one or more embodiments, the first element can be named as the second element. Describing an element as a "first" element may not require or imply the existence of a second element or other elements. The terms "first", "second", etc. can be used to distinguish between different classes or different groups of elements. For simplicity, the terms "first", "second", etc. can represent "first class (or first group)", "second class (or second group)", etc. respectively.

[0072] When a first element is referred to as being "on" a second element, the first element may be directly on the second element, or one or more intervening elements may be present between the first element and the second element. When a first element is referred to as being "directly on" a second element, there are no intended intervening elements between the first element and the second element (except for environmental elements such as air).

[0073] In this specification, unless explicitly described to the contrary, the word "include" and variations such as "comprising" may imply the inclusion of the stated elements, but may not require the exclusion of any other elements. In the drawings, as symbols for indicating directions, "x" is a first direction, "y" is a second direction perpendicular to the first direction, and "z" is a third direction perpendicular to the first direction and the second direction.

[0074] When a hole overlaps an element, the hole may expose the element, the position of the hole may coincide with the position of the element in a plan view showing both the hole and the element, and / or the edge of the hole may overlap the element. When an element extends in an indicated direction, the length direction of the element is equal to or parallel to the indicated direction. The term "connected" may mean "electrically connected". The term "insulated" may mean "electrically insulated".

[0075] Figure 1 A layout diagram of a display device according to an embodiment is shown.

[0076] Reference Figure 1 , the display device includes a display panel 10 , a gate driver 20 , a data driver 30 and a signal controller 40 .

[0077] The display panel 10 may include a plurality of gate lines GL1 to GLn, a plurality of data lines DL1 to DLm, and a plurality of pixels PX connected to the gate lines GL1 to GLn and the data lines DL1 to DLm and arranged substantially in a matrix (or a two-dimensional array). The gate lines GL1 to GLn may extend substantially in a row direction, and the data lines DL1 to DLm may extend substantially in a column direction. Each pixel PX may receive a gate signal. The gate signal may include a gate-on voltage for turning on a transistor of the pixel PX, and may include a gate-off voltage for turning off a transistor of the pixel PX. The gate signal may be transmitted through the gate lines GL1 to GLn. When the corresponding transistor is turned on, each pixel PX may receive a data voltage (corresponding to an image signal) through a corresponding data line among the data lines DL1 to DLm.

[0078] The signal controller 40 controls the gate driver 20 and the data driver 30. The signal controller 40 may receive an image signal and a control signal from an external device (such as a graphics processor), process the video signal to be suitable for the operating state of the display panel 10, and then generate and output image data, a gate control signal, a data control signal, etc. The gate driver 20 may receive a gate control signal from the signal controller 40, generate a gate signal, and output the gate signal to the gate lines GL1-GLn. The data driver 30 may receive a data control signal and image data from the signal controller 40, convert the image data into a data voltage (using a gray voltage generated by a gray voltage generator), and output the data voltage to the data lines DL1 to DLm.

[0079] Figure 2 An equivalent circuit diagram of one pixel of a display device according to an embodiment is shown.

[0080] Reference Figure 2 , the pixel PX includes two sub-pixels sPX1 and sPX2. The structure having sub-pixels may be beneficial to the side visibility of the display device.

[0081] The pixel PX is connected to the gate line GL, the data line DL and the reference voltage line RL. The pixel PX includes a first sub-pixel sPX1 and a second sub-pixel sPX2. The first sub-pixel sPX1 includes a first transistor T1, a first liquid crystal capacitor Clc1 and a first storage capacitor Cst1. The second sub-pixel sPX2 includes a second transistor T2, a third transistor T3, a second liquid crystal capacitor Clc2 and a second storage capacitor Cst2.

[0082] The first transistor T1 is connected to the gate line GL and the data line DL. The second transistor T2 is also connected to the gate line GL and the data line DL. The third transistor T3 is connected to the output terminal (source electrode or drain electrode) of the second transistor T2 and the reference voltage line RL. The gate line GL may extend substantially in the row direction, and the data line DL and the reference voltage line RL may extend substantially in the column direction.

[0083] In the operation of the pixel PX, when the gate-on voltage is applied to the gate line GL, the first transistor T1, the second transistor T2, and the third transistor T3 connected to the gate line GL are turned on. Therefore, the data signal applied to the data line DL is applied to the first liquid crystal capacitor Clc1 and the second liquid crystal capacitor Clc2 through the turned-on first transistor T1 and the second transistor T2, respectively, and the first liquid crystal capacitor Clc1 and the second liquid crystal capacitor Clc2 are charged with a voltage corresponding to the difference between the data voltage and the common voltage. In this case, although the same data voltage is transmitted to the first liquid crystal capacitor Clc1 and the second liquid crystal capacitor Clc2 through the first transistor T1 and the second transistor T2, respectively, the charging voltage of the second liquid crystal capacitor Clc2 is divided by the third transistor T3. Therefore, the charging voltage of the second liquid crystal capacitor Clc2 becomes smaller than the charging voltage of the first liquid crystal capacitor Clc1, so that the two sub-pixels sPX1 and sPX2 can have different brightness. By properly adjusting the voltage charged in the first liquid crystal capacitor Clc1 and the voltage charged in the second liquid crystal capacitor Clc2, an image viewed from a side surface may be maximally similar to an image viewed from a front surface, thereby improving the side visibility of the display device.

[0084] Figure 3 1 is a plan view showing one pixel of a display device according to an embodiment, Figure 4 shows a plan view of a region including a transistor and a contact hole according to an embodiment, Figure 5 According to an embodiment, Figure 4 A cross-sectional view taken along line A-A', Figure 6 According to an embodiment, Figure 4 A cross-sectional view taken along line BB'. Figures 3 to 6 The pixels shown in can have Figure 2 The electronic components and / or structures shown in .

[0085] The display device includes a first substrate SB1, a second substrate SB2, and a liquid crystal layer LC between the first substrate SB1 and the second substrate SB2. The first substrate SB1 and / or the second substrate SB2 may be made of a transparent insulating material such as glass.

[0086] A gate conductor including a gate line GL, a storage voltage line SL, and light shielding layers LB1 and LB2 (formed of the same material or the same materials in the same process) may be disposed on the first substrate SB1.

[0087] The gate line GL (for transmitting a gate voltage / signal) may extend substantially in the first direction x. Portions or protrusions of the gate line GL may form the gate electrode G1 of the first transistor T1, the gate electrode G2 of the second transistor T2, and the gate electrode G3 of the third transistor T3. The protrusions may protrude in the second direction y in a plan view of the display device.

[0088] The storage voltage line SL may transmit a constant voltage such as a common voltage. A portion or protrusion of the storage voltage line SL may form one or more electrodes of one or more storage capacitors Cst1 and Cst2. The storage voltage line SL may include a portion extending substantially in the first direction x and a portion extending substantially in the second direction y.

[0089] The light shielding layers LB1 and LB2 may include a first light shielding layer LB1 and a second light shielding layer LB2 separated from each other. The first light shielding layer LB1 and the second light shielding layer LB2 may be disposed at respective sides of the gate line GL and separated from the gate line GL. The light shielding layers LB1 and LB2 and the gate line GL prevent external light from reaching the semiconductor layers A1, A2, and A3. Therefore, changes in physical properties and electrical characteristics of the semiconductor layers A1, A2, and A3 caused by external light may be prevented. The voltage applied to the first sub-pixel electrode sPE1 and the second sub-pixel electrode sPE2 may be applied to the light shielding layers LB1 and LB2.

[0090] The gate conductor may include a metal such as molybdenum (Mo), copper (Cu), aluminum (Al), magnesium (Mg), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), tungsten (W), titanium (Ti), chromium (Cr), or tantalum (Ta). The gate conductor may be a single layer or a multi-layer structure.

[0091] A first insulating layer IL1, which may include an inorganic insulating material such as silicon oxide and silicon nitride, may be disposed on the gate conductor. The first insulating layer IL1 may be referred to as a gate insulating layer.

[0092] The semiconductor layers AL, A1, A2, and A3 may be disposed on the first insulating layer IL1. The semiconductor layers AL, A1, A2, and A3 may include a semiconductor layer AL overlapping the data line DL, a semiconductor layer A1 of the first transistor T1, a semiconductor layer A2 of the second transistor T2, and a semiconductor layer AL3 of the third transistor T3. The semiconductor layers AL, A1, A2, and A3 may include a semiconductor material such as amorphous silicon, polycrystalline silicon, or an oxide semiconductor.

[0093] Data conductors including a data line DL, a reference voltage line RL, source and drain electrodes S1 and D1 of the first transistor T1, S2 and D2 of the second transistor T2, and source and drain electrodes S3 and D3 of the third transistor T3 may be disposed on the semiconductor layers AL, A1, A2, and A3.

[0094] The data line DL (for transmitting a data voltage) may extend substantially in the second direction y. The source electrode S1 may be a protrusion or portion of the data line DL. The source electrode S2 may be connected to the source electrode S1, and the drain electrode D2 may be connected to the source electrode S3. The drain electrode D3 may be a protrusion or portion of the reference voltage line RL.

[0095] The drain electrode D1 includes an extension EX1 for connecting to the first sub-pixel electrode sPE1, and the drain electrode D2 includes an extension EX2 for connecting to the second sub-pixel electrode sPE2. The extensions EX1 and EX2 are wider than other portions of the drain electrodes D1 and D2, respectively. The extension EX1 overlaps with the light shielding layer LB1, and the extension EX2 overlaps with the light shielding layer LB2. The light shielding layer LB1 may be wider than the extension EX1, and the extension EX1 may be disposed within the region of the light shielding layer LB1 in a plan view of the display device. The light shielding layer LB2 may be wider than the extension EX2, and the extension EX2 may be disposed within the region of the light shielding layer LB2 in a plan view of the display device.

[0096] In transistors T1, T2, and T3, source electrodes S1, S2, and S3 and drain electrodes D1, D2, and D3 may be opposite to those shown in the figure. For example, the portion indicated by reference numeral S1 in the first transistor T1 may be a drain electrode, and the portion indicated by reference numeral D1 may be a source electrode. Therefore, extension EX1 may be an extension of the source electrode of the first transistor T1, and extension EX2 may be an extension of the source electrode of the second transistor T2.

[0097] Channels of transistors T1, T2, and T3 may be formed in semiconductor layers A1, A2, and A3 (respectively) between source electrodes S1, S2, and S3 (respectively) and drain electrodes D1, D2, and D3 (respectively). Ohmic contacts may be provided between the data conductor and each of the semiconductor layers A1, A2, and A3.

[0098] The data conductor may include a metal such as one or more of aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), and tantalum (Ta).

[0099] The data conductor and the semiconductor layers AL, A1, A2 and A3 may be formed in the same photolithography process using the same mask. The data conductor may be formed by wet etching, and the semiconductor layers AL, A1, A2 and A3 may be formed by dry etching. The semiconductor layers AL, A1, A2 and A3 may overlap with the data conductor in the region other than the channel portion of the semiconductor layers A1, A2 and A3. The edges of the semiconductor layers AL, A1, A2 and A3 may be substantially parallel to the edges of the data conductor. Each of the semiconductor layers AL, A1, A2 and A3 may be substantially wider than the corresponding portion of the data conductor in a plan view of the display device. Since the semiconductor layers A1 and A2 are substantially disposed below the extensions EX1 and EX2, light may be prevented from entering the semiconductor layers A1 and A2 by the light shielding layers LB1 and LB2.

[0100] The second insulating layer IL2 may be disposed on the data conductor. The second insulating layer IL2 may be a multi-layer structure and may include a first layer IL2a and a second layer IL2b. The first layer IL2a may include an inorganic insulating material such as silicon nitride and silicon oxide. The second layer IL2b may include an organic insulating material. The second layer IL2b may be a color filter or may include a color filter.

[0101] The pixel electrode PE and the shielding electrodes SE1 and SE2 may be disposed on the second insulating layer IL2. The pixel electrode PE may include a first sub-pixel electrode sPE1 and a second sub-pixel electrode sPE2 disposed at respective sides of the gate line GL. The first sub-pixel electrode sPE1 and the second sub-pixel electrode sPE2 may be physically separated. The first sub-pixel electrode sPE1 forms one electrode of a first liquid crystal capacitor Clc1 of a first sub-pixel sPX1, and the second sub-pixel electrode sPE2 forms one electrode of a second liquid crystal capacitor Clc2 of a second sub-pixel sPX2.

[0102] The first sub-pixel electrode sPE1 is connected to the extension EX1 of the drain electrode D1 (directly and electrically) through the contact hole H1 formed in the second insulating layer IL2 and the first insulating layer IL1. Therefore, the first sub-pixel electrode sPE1 can receive the data voltage from the drain electrode D1 of the first transistor T1. The first sub-pixel electrode sPE1 is also connected to the light shielding layer LB1 (directly and electrically) through the contact hole H1. That is, the first sub-pixel electrode sPE1 is connected to the extension EX1 and the light shielding layer LB1 through the same contact hole H1. Due to this connection, the light shielding layer LB1 can be equipotential with the first sub-pixel electrode sPE1 and the extension EX1.

[0103] If the light shielding layer LB1 is in an electrically floating state and if the first sub-pixel sPX1 is charged, an undesirable parasitic capacitance is generated between the first sub-pixel electrode sPE1 and the light shielding layer LB1 and between the extension EX1 and the light shielding layer LB1. The parasitic capacitance changes the potential of the first sub-pixel sPX1 by changing the potential of the first sub-pixel electrode sPE1, thereby changing the brightness of the pixel PX. Therefore, the parasitic capacitance may reduce the image quality. According to an embodiment, since the potential of the light shielding layer LB1 is equal to the potential of the first sub-pixel electrode sPE1 and the potential of the extension EX1, the parasitic capacitance is substantially not generated between the light shielding layer LB1 and the extension EX1 or between the light shielding layer LB1 and the first sub-pixel electrode sPE1. Therefore, satisfactory image quality can be maintained.

[0104] Since the extension EX1 and the light shielding layer LB1 are arranged on different layers, a side contact method can be used, in which conductors arranged in different layers are electrically connected through one contact hole H1. The contact hole H1 may include a first region H1a overlapping the extension EX1 and the light shielding layer LB1. The first region H1a may expose a portion of the extension EX1 that partially overlaps the light shielding layer LB1 and is exposed to directly contact the first sub-pixel electrode sPE1. The contact hole H1 may include a second region H1b overlapping the light shielding layer LB1 and not overlapping the extension EX1. The second region H1b may expose a portion of the light shielding layer LB1 that is not overlapped by the extension EX1 and is exposed to directly contact the first sub-pixel electrode sPE1. Before forming the first sub-pixel electrode sPE1, the first region H1a exposes the upper surface of the portion of the extension EX1, and the second region H1b exposes the upper surface of the portion of the light shielding layer LB1. Therefore, the first subpixel electrode sPE1 (formed on the second insulating layer IL2 after the contact hole H1 is formed) may directly contact each of the upper surface of the portion of the extension EX1 and the upper surface of the portion of the light shielding layer LB1 through the contact hole H1.

[0105] Due to the abrupt inclination of the side surface of the extension EX1 and due to the step between the extension EX1 and the light shielding layer LB1, the first sub-pixel electrode sPE1 may not be disposed on the side surface of the extension EX1, and as shown in FIG. Figure 5As shown in , the side surface of the extension EX1 may be exposed between the portion of the first sub-pixel electrode sPE1 connected to the extension EX1 and the portion of the first sub-pixel electrode sPE1 connected to the light shielding layer LB1, and the portion of the first sub-pixel electrode sPE1 connected to the extension EX1 and the portion of the first sub-pixel electrode sPE1 connected to the light shielding layer LB1 may be disconnected. The disconnection of the first sub-pixel electrode sPE1 may substantially correspond to the boundary between the first region H1a and the second region H1b. Since the portion of the sub-pixel electrode sPE1 is connected around the contact hole H1, the sub-pixel electrode sPE1 may still electrically connect the extension EX1 to the light shielding layer LB1.

[0106] Similar to the first sub-pixel electrode sPE1, the second sub-pixel electrode sPE2 is connected to the extension EX2 of the drain electrode D2 through the contact hole H2 formed in the second insulating layer IL2 and the first insulating layer IL1. Therefore, the second sub-pixel electrode sPE2 can receive the data voltage from the drain electrode D2 of the second transistor T2. The second sub-pixel electrode sPE2 is also connected to the light shielding layer LB2 through the contact hole H2. That is, the second sub-pixel electrode sPE2 is connected to the extension EX2 and the light shielding layer LB2 through the same contact hole H2. Due to this connection, the light shielding layer LB2 can be equipotential with the second sub-pixel electrode sPE2 and the extension EX2, and parasitic capacitance between the light shielding layer LB2 and the extension EX2 and between the light shielding layer LB2 and the second sub-pixel electrode sPE2 can be prevented.

[0107] The second sub-pixel electrode sPE2 may be connected to the extension EX2 and the light shielding layer LB2 in a side contact manner. The contact hole H2 may include a first region overlapping the extension EX2 and the light shielding layer LB2, and may include a second region overlapping the light shielding layer LB2 and not overlapping the extension EX2. The second sub-pixel electrode sPE2 may directly contact both the upper surface of the exposed portion of the extension EX2 and the upper surface of the exposed portion of the light shielding layer LB2 through the contact hole H2.

[0108] Slits 90 extending in different directions may be formed in the subpixel electrodes sPE1 and sPE2. Each of the subpixel electrodes sPE1 and sPE2 may be divided into a plurality of regions by the slits 90, and tilt directions of liquid crystal molecules LM of the liquid crystal layer LC in the plurality of regions are differently controlled to achieve a wide viewing angle.

[0109] The shielding electrodes SE1 and SE2 may include a shielding electrode SE1 overlapping the data line DL, and may include a shielding electrode SE2 overlapping the edge of the gate line GL. The shielding electrode SE2 may extend along the edge of the gate line GL. The shielding electrodes SE1 and SE2 may shield the electric field of the data line DL and the gate line GL so as not to affect the liquid crystal layer LC and the sub-pixel electrodes sPE1 and sPE2. A voltage equal to the voltage (common voltage) applied to the common electrode CE may be applied to the shielding electrodes SE1 and SE2. Because there is no potential difference between the shielding electrodes SE1 and SE2 and the common electrode CE, the liquid crystal molecules LM between the shielding electrodes SE1 and SE2 and the common electrode CE may not be oriented. In a normally black mode display device, the shielding electrodes SE1 and SE2 may be used as shielding members.

[0110] The first sub-pixel electrode sPE1, the second sub-pixel electrode sPE2 and the shielding electrodes SE1 and SE2 may be formed in the same process, wherein the process may include forming a conductive layer on the second insulating layer IL2 using a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), and then patterning the conductive layer through a photolithography process.

[0111] A light blocking member BM (or a black matrix) may be disposed on the second substrate SB2, and the second substrate SB2 may be made of a transparent insulating material such as glass. The light blocking member BM serves to prevent light leakage.

[0112] The common electrode CE may be disposed on the light blocking member BM. The common electrode CE may be made of a transparent conductive material such as ITO or IZO. The common electrode CE may overlap the plurality of pixels PX and / or may substantially overlap the second substrate SB2.

[0113] The liquid crystal layer LC (including liquid crystal molecules LM) may be disposed between the first substrate SB1 and the second substrate SB2. An alignment film may be disposed between the sub-pixel electrodes sPE1 and sPE2 and the liquid crystal layer LC and between the common electrode CE and the liquid crystal layer LC.

[0114] Figure 7 1 is a plan view showing one pixel of a display device according to an embodiment, Figure 8 shows a plan view of a region including a transistor and a contact hole according to an embodiment, Fig. 9 Shown along Figure 8 A cross-sectional view taken along the line C-C'. Figure 7 , Figure 8 and Fig. 9 Some elements and / or structures of the display device described may be the same as those in the above reference Figures 1 to 6 Some elements and / or structures described in one or more of the embodiments are similar or identical.

[0115] Reference Figure 7 , Figure 8 and Fig. 9 , one pixel PX includes a first sub-pixel sPX1 and a second sub-pixel sPX2, so as to improve the side visibility of the display device. The gate line GL, the data line DL and the reference voltage line RL are electrically connected to the pixel PX. The sub-pixel electrode sPE1 of the first sub-pixel sPX1 is connected to the gate line GL and the data line DL through the first transistor T1. The sub-pixel electrode sPE2 of the second sub-pixel sPX2 is connected to the gate line GL and the data line DL through the second transistor T2, and is connected to the gate line GL and the reference voltage line RL through the third transistor T3.

[0116] The drain electrode D1 of the first transistor T1 includes an extension EX1, and the first sub-pixel electrode sPE1 may be connected to the extension EX1 through a contact hole H1 formed in the second insulating layer IL2. The drain electrode D2 of the second transistor T2 includes an extension EX2, and the second sub-pixel electrode sPE2 may be connected to the extension EX2 through a contact hole H2 formed in the second insulating layer IL2. According to the connection, the first sub-pixel electrode sPE1 and the second sub-pixel electrode sPE2 may receive a data voltage transmitted through the data line DL through the first transistor T1 and the second transistor T2, respectively.

[0117] The contact holes H1 and H2 for connecting the first sub-pixel electrode sPE1 and the second sub-pixel electrode sPE2 to the extensions EX1 and EX2 of the drain electrodes D1 and D2 may be polygonal in a plan view of the display device, and as shown in the accompanying drawings, may be substantially quadrilateral, for example, substantially rectangular. The contact holes H1 and H2 may each have a polygonal shape in which one diagonal line is substantially parallel to the second direction y. Therefore, in a figure (e.g., a mask feature) defining one of the contact holes H1 and H2, one diagonal line may be substantially parallel to the extension direction of the data line DL, and may be substantially parallel to the longitudinal edge of the data line DL. This is equivalent to rotating a rectangle or square in which four sides are parallel to the first direction x or the second direction y by approximately 45 degrees, and the angle formed by one of the sides of the figure defining the contact holes H1 and H2 and the first direction x or the second direction y may be approximately 45 degrees.

[0118] When the contact holes H1 and H2 have such a planar shape, even if the mask is not accurately aligned during the photolithography process of forming the contact holes H1 and H2 in the second insulating layer IL2 (i.e., even if the mask overlay shift occurs), the contact holes H1 and H2 are not substantially deviated from the extensions EX1 and EX2. Even if they deviate, the deviation can be minimized. Therefore, the connection failure between the sub-pixel electrodes sPE1 and sPE2 and the extensions EX1 and EX2 can be prevented.

[0119] Reference Figures 10 to 13 Overlay shift margin increase according to an embodiment is described.

[0120] Fig.10 The position of the contact hole H11 ′ formed when the overlay shift occurs in the second direction y in the display device according to the comparative example is shown. Fig.11 The position of the contact hole H11 ′ formed when the overlay shift occurs in the first direction x in the display device according to the comparative example is shown. Fig.12 The positions of the contact holes H1 ′ and H2 ′ formed when an overlay shift occurs in the second direction y in the display device according to the embodiment are shown. Fig.13 1 and 2 show the positions of contact holes H1' and H2' formed when an overlay shift occurs in the first direction x in the display device according to the embodiment. The shifted contact holes are indicated by dotted lines.

[0121] Reference Fig.10 and Fig.11 As expected, the contact hole H11 overlapping the extension EX1 of the drain electrode D1 is substantially rectangular (eg, square), and each side of the contact hole H11 extends substantially in the first direction x or in the second direction y. Fig.10 as shown in the second direction y or as Fig.11 When shifted in the first direction x as shown in , the contact hole H11' may include a shifted region deviating from the extension EX1 (a region not overlapping with the extension EX1 / a region not exposing the extension EX1). Since the edge of the contact hole H11' and the edge of the extension EX1 are substantially parallel to each other in the shifted region, the size of the shifted region is substantially equal to the shift distance in the second direction y or in the first direction x (i.e., the distance between the edge of the contact hole H11' and the corresponding edge of the intended contact hole H11) multiplied by the length of the edge of the extension EX1.

[0122] Reference Fig.12 and Fig.13 , when the contact holes H1' and H2' are displaced in the second direction y or in the first direction x due to the overlay displacement, the contact holes H1' and H2' may include a displaced region deviating from the extensions EX1 and EX2. In the displaced region, the diagonal lines of the contact holes H1' and H2' are substantially perpendicular to the respective edges of the extensions EX1 and EX2. Therefore, the displaced region associated with the contact holes H1' and H2' is significantly smaller than that associated with the contact holes H1' and H2'. Fig.10 and Fig.111 and 1 '. According to the embodiment, even if the overlapping shift is as much as that of the comparative example, since the shift area is small, the sub-pixel electrodes sPE1 and sPE2 can still directly contact the extensions EX1 and EX2 with a sufficiently large area. Therefore, sufficient connection reliability of the sub-pixel electrodes sPE1 and sPE2 can be ensured, and the overlapping process margin can be optimized.

[0123] Fig.14 Shown along Fig.10 A cross-sectional view taken along the line D-D'. Fig.14 , when part of the contact hole H11' does not fully expose the extension EX1 due to the overlap displacement, a step coverage defect may occur in the area with a large step. When the step coverage defect area is large, a connection defect occurs between the first subpixel electrode sPE1 and the extension EX1, and the pixel PX may not operate normally (for example, it may not respond to the input signal or may have an unexpected low brightness). Even if the overlap displacement does not occur, the step coverage defect may also occur when the contact hole H11 is formed to be larger than the design size. On the contrary, according to the embodiment, even if the contact holes H1 and H2 are shifted or formed larger than the design size, the step coverage defect area can be minimized.

[0124] Return to reference Figure 7 , Figure 8 and Fig. 9 , a gate conductor including a gate line GL and storage voltage lines SL1 and SL2 may be disposed on the first substrate SB1. The gate line GL is disposed between the storage voltage line SL1 and the storage voltage line SL2. The storage voltage lines SL1 and SL2 may extend substantially in the first direction x. The storage voltage line SL1 may include a portion extending along an edge of the first subpixel electrode sPE1. The storage voltage lines SL1 and SL2 may include portions overlapping with extensions EX1 and EX2 of the drain electrodes D1 and D2, and they may serve as light shielding layers to prevent external light from reaching the semiconductor layers A1 and A2. The contact hole H1 may overlap with the storage voltage line SL1 / may expose the storage voltage line SL1, and the contact hole H2 may overlap with the storage voltage line SL2 / may expose the storage voltage line SL2.

[0125] The first and second subpixel electrodes sPE1 and sPE2 (disposed on the second insulating layer IL2) may be connected to extensions EX1 and EX2 of drain electrodes D1 and D2 through contact holes H1 and H2, respectively. The extension EX1 may be an extension of the source electrode of the first transistor T1, and the extension EX2 may be an extension of the source electrode of the second transistor T2.

[0126] The reference voltage line RL and the storage voltage line SL1 may be electrically connected to each other in a side contact manner through the contact hole H3. The contact hole H3 may include a first region overlapping the reference voltage line RL and the storage voltage line SL1. The first region may expose a portion of the reference voltage line RL that partially overlaps the storage voltage line SL1 and is exposed to directly contact the connection member CM. The contact hole H3 may include a second region overlapping the storage voltage line SL1 and not overlapping the reference voltage line RL. The second region may expose a portion of the storage voltage line SL1 that is not overlapped by the reference voltage line RL and is exposed to directly contact the connection member CM. The connection member CM may be disposed on the second insulating layer IL2. The connection member CM may directly contact each of the upper surface of the portion of the reference voltage line RL and the upper surface of the portion of the storage voltage line SL1 through the contact hole H3 to electrically connect the reference voltage line RL to the storage voltage line SL1. In this connection, the reference voltage line RL and the storage voltage line SL1 may transmit the same voltage and may be connected in a network structure throughout the display panel. Therefore, the resistance and voltage drop of the reference voltage line RL and the storage voltage line SL1 can be reduced, and sufficiently uniform reference voltage and storage voltage can be supplied to the relevant components of the display panel. Some structures related to the area of ​​the contact hole H3 can be similar to those related to the reference voltage line RL and the storage voltage line SL1. Figure 5 and Figure 6 Some structures related to the regions H1a and H1b of the contact hole H1 are described.

[0127] The shielding electrodes SE1 and SE2 may be disposed on the second insulating layer IL2, may include a first shielding electrode SE1 overlapping the data line DL, and may include a second shielding electrode SE2 overlapping the first transistor T1 and the second transistor T2. The first shielding electrode SE1 may extend in the second direction y, and the second shielding electrode SE2 may substantially protrude from the first shielding electrode SE1 in the first direction x.

[0128] The pixel electrode PE, the connection member CM and the shielding electrodes SE1 and SE2 may be formed in the same process. The process may include forming a conductive layer on the second insulating layer IL2 using a transparent conductive material such as ITO or IZO, and then patterning the conductive layer by a photolithography process.

[0129] Fig.15 A plan view of a region including a transistor and a contact hole in one pixel of a display device according to an embodiment is shown.

[0130] Reference Fig.15In the plan view of the display device, each of the contact hole H3 (for electrically connecting the reference voltage line RL and the storage voltage line SL1 in a side contact manner), the contact hole H1, and the contact hole H2 may have a quadrilateral structure (e.g., a rectangular, square, or diamond structure) in which one diagonal line extends substantially in the second direction y and substantially to the longitudinal edge of the data line DL. In an embodiment, one or more of the contact holes H1, H2, and H3 may have a polygonal structure other than a quadrilateral structure in the plan view of the display device.

[0131] Fig.16 A plan view of a region including a transistor and a contact hole in one pixel of a display device according to an embodiment is shown.

[0132] Fig.16 Possible orientations of each of the contact holes H1 and H2 are shown. In a plan view of the display device, the contact hole H1 has a rectangular structure (e.g., a square structure) having sides oriented at approximately 15 degrees or 75 degrees relative to the first direction x (or the longitudinal edge / direction of the gate line GL) or the second direction y (or the longitudinal edge / direction of the data line DL), and the contact hole H2 has a rectangular structure (e.g., a square structure) having sides oriented at approximately 75 or 15 degrees relative to the first direction x or the second direction y.

[0133] When the edges of the extensions EX1 and EX2 are substantially parallel to the first direction x or the second direction y, and when an angle formed by one of the edges of the contact holes H1 and H2 and the first direction x or the second direction y is approximately 45 degrees (eg, Fig.15 ), the step coverage defect can be minimized. However, the extensions EX1 and EX2 may include sides that are not completely parallel to the first direction x or the second direction y, and even if a step coverage defect occurs, when the area of ​​the step coverage defect is small, an inconspicuous connection defect may occur between the sub-pixel electrodes sPE1 and sPE2 and the extensions EX1 and EX2. In view of this, when the acute angle formed by one side of the pattern (e.g., mask feature) defining the contact holes H1 and H2 and the first direction x or the second direction y is in the range of about 15 degrees to about 75 degrees (specifically, in the range of 40 degrees to 50 degrees), the connection defect that may be caused by the step coverage defect can be prevented or the connection defect can be minimized.

[0134] Although example embodiments have been described, actual embodiments are not limited to the disclosed embodiments. Actual embodiments cover various modifications and equivalent arrangements within the scope of the claims.

Claims

1. A display device, comprising: substrate; A light shielding layer is disposed on the substrate; A first insulating layer, disposed on the light shielding layer; a transistor comprising a source electrode or a drain electrode, wherein the source electrode or the drain electrode comprises an extension overlapping each of the first insulating layer and the light shielding layer; A second insulating layer disposed on the extension; and A pixel electrode is disposed on the second insulating layer, The first insulating layer and the second insulating layer include contact holes, wherein the contact holes expose a portion of the light shielding layer and the extended portion. wherein the pixel electrode directly contacts each of the portion of the extension and the portion of the light shielding layer, and The extended side surface is exposed between two parts of the pixel electrode in the contact hole.

2. The display device according to claim 1, wherein: The contact hole includes a first portion and a second portion, wherein the first portion of the contact hole exposes the portion of the extension, wherein the portion of the extension partially overlaps with the light-shielding layer, wherein the second portion of the contact hole exposes the portion of the light-shielding layer, and wherein the portion of the light-shielding layer does not overlap with the extension.

3. The display device according to claim 1, wherein: The extension is disposed within the light shielding layer in a plan view of the display device.

4. The display device according to claim 1, wherein: When the display device displays an image, the potential of the light shielding layer is equal to the potential of the pixel electrode.

5. The display device according to claim 1, further comprising: A gate line, disposed on the substrate and extending in a first direction; as well as a shielding electrode, disposed on the second insulating layer, Part of the shielding electrode overlaps with an edge of the gate line and extends along the edge of the gate line.

6. The display device according to claim 1, further comprising: A gate line is disposed on the substrate and extends in a first direction, wherein the pixel electrode comprises a first sub-pixel electrode and a second sub-pixel electrode, wherein the gate line is arranged between the first sub-pixel electrode and the second sub-pixel electrode, and wherein the first sub-pixel electrode or the second sub-pixel electrode directly contacts each of the extension and the light-shielding layer and is partially arranged inside the contact hole.

7. The display device according to claim 1, wherein: The second insulating layer includes a first layer and a second layer, wherein the first layer includes an inorganic insulating material, and wherein the second layer is disposed on the first layer and includes an organic insulating material.

8. The display device according to claim 1, wherein: The transistor also includes a semiconductor layer overlapping the extension.

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