Single transistor multiplier and method thereof

Abstract

A multiplier has a MOSFET in a common source configuration. A MOSFET current source is coupled to the drain terminal of the MOSFET. An input terminal of an inverter is coupled to the drain terminal of the MOSFET. The output terminal of the inverter selects two currents, and the current magnitudes of the two currents are proportional. A first capacitor has a first terminal coupled to the first current of the two currents and the gate of the MOSFET and a second terminal connected to ground. A second capacitor has a first terminal coupled to the second current of the two currents and a second terminal coupled to the first current of the two currents. The multiplier is reset by first discharging the gate capacitance of the MOSFET, then recharging it to a Vt comparator threshold, and then removing the charge from the gate terminal of the MOSFET, thereby reducing the voltage on the gate terminal to below the Vt comparator threshold, so that the two currents are enabled until the Vt comparator threshold reaches the previous Vt comparator threshold and the inverter turns off the two currents. In the next reset phase, the second capacitor maintains the product value of the charge.

Description

[0001] Related Applications

[0002] This patent application is related to U.S. Provisional Application No. 62 / 637,507, filed on March 2, 2018 in the name of David Schie, entitled “Single Transistor Multiplier,” the entire contents of which are incorporated herein by reference. This patent application claims benefits under 35 U.S.C. §119(e). Technical Field

[0003] The present invention relates generally to a multiplier circuit, and more particularly to a multiplier circuit having a reduced number of transistors. Background Art

[0004] Machine learning relies heavily on multiplication. For example, neurons within a neural network 10 can be connected with a one-to-many architecture that relies on Figure 1 A multiplier within each of the large number of connections shown. In the neural network 10, the circle 12 is a neuron with input data. The line 14 is a multiplier that multiplies the input data by a weight (w). The result can be fed to a decision circuit or subsequent layer, and the output is fed to the next layer in turn. Because each neuron contains an adder for the weighted inputs and, in some cases, a decision circuit, each neuron may be connected to many neurons in subsequent layers, so the number of weights can be very large.

[0005] Machine learning often relies on digital multipliers that require a large number of transistors to perform multiply and accumulate functions. By necessity, each bit in the digital word to be multiplied requires at least two transistors, and the gates that perform the bitwise multiplication require at least four transistors each. Once the additional transistors associated with bit shifting are taken into account, the number of transistors can increase even if the input word for the bit calculation is reduced. In addition, performing load and multiply activities in digital systems often takes multiple cycles, which is a considerable amount of time.

[0006] To increase throughput, digital architectures utilize multiple parallel threads to allow multiple multiplications to be executed simultaneously, and employ architectures such as systolic architectures that minimize load overhead. However, more overhead is required to accommodate multithreading and systolic architectures and to break the problem into streams that can be executed in parallel.

[0007] Therefore, it is desirable to provide a system and method that overcomes the above problems. The system and method will provide a multiplication device that can be created using a smaller number of transistors. Summary of the invention

[0008] According to one embodiment, a multiplier is disclosed. The multiplier has a MOSFET in a common source configuration and is used as a comparator related to a Vt comparator threshold. A current source is coupled to the drain terminal of the MOSFET. An inverter has an input terminal coupled to the drain terminal of the MOSFET. The output terminal of the inverter selects two currents I1 and I2, and the current magnitudes of the two currents are proportional. A first capacitor has a first terminal coupled to the first current I1 of the two currents and the gate of the MOSFET and a second terminal grounded. A second capacitor has a first terminal coupled to the second current I2 of the two currents and a second terminal coupled to the first current I1 of the two currents and coupled to the gate of the MOSFET. The multiplier is first reset by using the MOSFETs in I1 and I2 to discharge the second capacitor. Thereafter, the MOSFET gate is pulled below the threshold (Vt) of the MOSFET, and only I1, which charges the gate capacitance, is turned on until the inverter turns off the current. Once the Vt comparator threshold is reached, the input charge is removed from the gate terminal of the MOSFET, thereby reducing the voltage on the gate terminal to below the Vt comparator threshold. Falling below the Vt comparator threshold causes two currents I1 and I2 to be enabled until the comparator reaches the Vt comparator threshold and the inverter turns both currents off. At this point, the second capacitor holds the product value of the charge, which is used to convert to a voltage of the magnitude of the second capacitor or to be used in a subsequent multiplier. Alternatively, both currents I1 and I2 can be used to find the Vt comparator threshold during reset, and then the second capacitor can be discharged to ground potential at the first terminal of the second capacitor through an additional switch, and the reset MOSFET can be discharged from the gate of the MOSFET to ground potential.

[0009] According to a second embodiment, a weighted adder is disclosed. In the first cycle, MNR causes the voltage on the gate of MN1 to be below the Vt comparator threshold, and then I1 charges the gate of MN1 up to the Vt comparator threshold, which causes the drain of MN1 to drop and the inverter turns off the current source. Thereafter, during the first cycle, one or more current sources programmed to be proportional to I2 to represent the weight value are gated by pulses proportional to the input charge to remove the charge from MN1 as a weighted sum of the inputs. In the second cycle, I2 charges the gate of MN1 back to its trigger voltage, thereby replacing the removed weighted charge. The time required to recharge the charge, represented by the pulse at the output of the inverter, can be used as an input pulse to gate the charge in a subsequent multiplier and represents a pulse proportional to the multiplied output charge. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present application is further described in detail with respect to the following drawings. These drawings are not intended to limit the scope of the present application, but to illustrate certain attributes thereof. The same reference numerals will be used throughout the drawings to refer to the same or similar components.

[0011] Figure 1 is a block diagram illustrating an exemplary embodiment of a neural network architecture according to one aspect of the present application, the neural network architecture relying on multipliers within each connection engine;

[0012] Figure 2 is a block diagram illustrating an exemplary embodiment of a multiplier according to one aspect of the present application;

[0013] Figure 3 A cross-sectional view of an exemplary embodiment of a depletion junction structure according to one aspect of the present application is shown, the depletion junction structure being optimized to reduce overlap capacitance;

[0014] Figure 4 is a block diagram illustrating an exemplary embodiment of a multiplier coupled to a transconductor according to one aspect of the present application; and

[0015] Figure 5 is a block diagram illustrating an exemplary embodiment of a weighted adder with pulse output according to one aspect of the present application. DETAILED DESCRIPTION

[0016] The description set forth below in conjunction with the accompanying drawings is intended as a description of the current preferred embodiments of the present disclosure, and is not intended to represent the only form in which the present disclosure can be constructed and / or utilized. The description sets forth the functions and step sequences for constructing and operating the present disclosure in conjunction with the illustrated embodiments. However, it should be understood that the same or equivalent functions and sequences may be implemented by different embodiments, which are also intended to be included in the spirit and scope of the present disclosure.

[0017] refer to Figure 2 , one embodiment of a multiplier 20 with a reduced number of transistors can be seen. According to one embodiment, the multiplier 20 may have a MOSFET MN1. The MOSFET MN1 may be arranged in a common source configuration. The current source I MN1 The inverter 22 may be coupled to the drain of the MOSFET MN1. The output of the inverter 22 may be used to select two current sources I1 and I2, and the current magnitudes of the two current sources may be proportional.

[0018] Capacitor C1 may have a terminal coupled to a first current source I1 and a gate of MOSFET MN1. A second terminal of capacitor C1 may be grounded. First current source I1 may be coupled to a second terminal of capacitor C2 and to the gate of MOSFET MN1. Second current source I2 may be coupled to a first terminal of second capacitor C2.

[0019] The reset switch may be coupled to the gate of the MOSFET MN1. According to one embodiment, the reset switch may be a reset transistor MOSFET MNR. In this embodiment, the MOSFET MNR may be configured as a common source configuration. The gate terminal of the MOSFET MNR may be coupled to a reset signal RESET.

[0020] The transmission gate TG can be coupled to the gate terminal of the MOSFET MN1, the first terminal of the capacitor C1, the second terminal of C2, and the current source I1. The multiplier 20 can operate in the following manner. First, the transmission gate TG is opened, and the current source MOSFETs that generate I1 and I2 discharge the capacitor C2 by pulling the capacitor C2 to the power rail or coupling an additional current source to the second terminal of the capacitor C2 and the MOSFET MNR remains at a low level. Once the capacitor C2 is discharged, the other transistors are turned off. The reset transistor MOSFETMNR pulls the gate below the trigger threshold (trip threshold) Vt and enables the current source I1 to start charging the MN1 gate node. At a certain point, the voltage on the gate of the MOSFET MN1 inverts the drain of the MOSFET MN1, and the output of the inverter 22 turns off the current source I1. The gate terminal of the MOSFET MN1 is now a voltage corresponding to the comparator threshold Vt. Alternatively, C2 can be reset twice and I1+I2 can be used to establish the Vt threshold to maintain a constant charging current and reduce the variation of the slope associated with the error.

[0021] from Figure 2 As can be seen in FIG. 1 , a charge packet can be introduced to the left side of the transmission gate TG. According to one embodiment, the charge packet is a negative charge packet. The current sources I1 and I2 can be programmed in proportion to each other to form a desired multiplicand. When the transmission gate TG is turned on, charge is removed in proportion to the charge in the negative charge packet. Therefore, when a negative charge packet is introduced at the transmission gate TG, the charge at the gate of the MOSFET MN1 is removed in proportion to the negative charge packet. This reduces the voltage on the gate of the MOSFET MN1 in proportion to the negative charge applied.

[0022] The charge packet may be a current source that discharges the gate capacitance of MN1. The charge packet may also be charge that is removed in concert with the charge stored in a pinned photodiode from an active pixel or in a charge reservoir from a floating diffusion of an active pixel or stored at the output of a CCD shift register. In some cases, such as when a current source is gated to discharge the gate capacitance of MN1, a transfer gate is not required.

[0023] After the transmission gate TG is turned on and the voltage on the gate of the MOSFETMN1 drops below the Vt comparator threshold in proportion to the input charge, the current sources I1 and I2 are turned on. The capacitor C1 is charged by I1+I2 until the Vt comparator threshold is reached, at which time the inverter 22 turns off the current sources I1 and I2. The time taken to charge the capacitor C1 to the Vt comparator threshold can be represented by the equation tcharge=Qin / (I1+I2). During this period, the capacitor C2 is charged only by the current source I2. It takes a period of time Qin / (I1+I2) to put the charge Qin*I2 / (I1+I2) into the capacitor C2. Therefore, the input charge has been multiplied by I2 / (I1+I2) and is stored on the capacitor C2.

[0024] C2 now contains the product charge. The charge magnitude can be used in subsequent addition or multiplication stages, can be read differentially as a voltage, or can be transferred to a known capacitance for reading. It is important to note that in cases where the information of interest is purely charge, the actual capacitance value may not matter and does not have to be large enough to accommodate the charge. This can be a very useful circuit in active pixel applications, for example, as the integrated charge can be used directly as the input to the multiplier 20.

[0025] It should be noted that capacitor C1 can be the parasitic capacitance of MOSFET MN1, the drain capacitor of MOSFET MNR, the drain capacitance of current source I1, and the overlap capacitance of transmission gate TG. Since this capacitor acts only as a charge sink, there is no need to control the value of this capacitor. Capacitor C2 can be a very small capacitor because it only integrates charge, which is no larger than the charge on capacitor C1. The cycle-by-cycle reset to the Vt trigger point acts as a correlated double sampling mechanism, eliminating flicker noise and trigger point variations due to process or temperature.

[0026] To reduce charge injection, the transmission gate TG, MOSFET MN1, MOSFETMNR, and current sources I1 and I2 can be created using a depletion junction structure that is further optimized to reduce overlap capacitance. An example of such a structure can be found in Figure 3 These structures can be used to enable capacitors in the femtofarad (fF) or fraction of a fF range, so they can be filled very quickly, requiring very little power. For example, by directly coupling the input charge from a pinned photodiode in an active pixel as a direct input from a photodetector, the conversion of charge to voltage or current can be saved, improving noise compared to conventional systems (as with digitization, each conversion adds noise, cost, power, and delay).

[0027] Current sources I1 and I2 in multiplier 20 may be difficult to program directly. Figure 4The circuit in can help overcome this problem. The four-quadrant transconductor can be coupled to Figure 2 A single transistor multiplier 20 is shown.

[0028] like Figure 4 As shown, a transconductor 40 can be seen. The transconductor 40 is coupled to the multiplier 20. A switch 44 may be used to couple the transconductor 40 to the multiplier 20. The two voltage inputs 48 to the multiplier 20 are very low leakage capacitors or NVM memories.

[0029] In order to achieve direct programming of the current source I1+I2 (the current in the multiplier 10) by voltage differential, the following operations can be performed. By turning on switch 49 and sampling and holding the result, the voltage drop across the transconductor resistor 46 is eliminated, and the difference between the currents in the transconductor 40 can be sampled. This current is then used as the I2 current in the multiplier 20. The same sampled current can then be used and removed by the MOSFET MNR in the second stage charging phase. Thereafter, the input 48 or ΔV is applied across resistor r46 as the differential voltage across the input of the transconductor 40. Therefore, the resulting multiplicand of the input charge is (I1-I2) / (ΔV / r), in which case I2-I1 is the difference in the transconductor bias current, not the current source in the multiplier 20.

[0030] During the calibration phase (I2-I1) can be adjusted for errors in r. Alternatively, I2-I1 can be adjusted by making r a variable resistor. The result is that we can set the charge multiplicand according to (I2-I1) / (ΔV / r). According to one embodiment, the transconductor resistor 46 can be a ferromagnetic memristor. The transconductor resistor 46 can also be a transistor biased in the triode region by a series of paired diode-connected devices, which are biased by a current 42 of the magnitude of I1. If I1 and I2 are also biased by a constant transconductance bias circuit, then (I2-I1) and r depend only on the geometry and separate the process and temperature dependencies.

[0031] The transconductor 40 may be shared among multiple multipliers. For example, in a broadcast systolic architecture, multiple copies of the transconductor current may be fanned out to generate multiple copies of the weight operand.

[0032] Instead of an input charge packet, a gated current source can also be used. In this case, a transmission gate is not required. The gating of the current source will remove the charge from the gate of MOSFET MN1, bringing the gate voltage below the Vt comparator threshold. After the current source is turned off, the circuit will operate as described before after the transmission gate is opened.

[0033] refer to Figure 5 , it may be considered to illustrate an embodiment of a weighted adder 20. Here, a single charge reservoir is shown, comprising the gate of a MOSFET MN1 also connected to a capacitor C1 (which may be a capacitor or a floating diffusion), the drain of a gate MOSFET 42, and a current source 40 also referred to as Iout. The charge mover 30, labeled w1, wn, and a bias b1, is programmed in accordance with the desired weight inputs and in proportion to the current source Iout 40. These weight inputs are gated by time inputs a1, an, and b, which are shown as buffers connected to the gate of the drive MOSFET 42. During reset, the gate of the MOSFET MN1 is pulled below its Vt comparator threshold, which causes the drain of the MOSFET MN1 to invert and allows the inverter 41 to turn on the current source 40 until the MOSFET MN1 gate reaches its switching threshold, after which it is turned off. In the first cycle, the timing of the multiple pulse inputs a1…an and b effectively allows the weights to flow for a given time, thereby removing the weighted charge from the charge reservoir at the gate of MN1. Once this current is removed, the drain of MN1 will flip again and cause inverter 41 to switch on current source Iout which will replace the charge removed by the weighted input. The time required to do this will represent the weighted sum output pulse at the analog output (aout).

[0034] While embodiments of the disclosure have been described in terms of various specific embodiments, those skilled in the art will recognize that the embodiments of the disclosure can be practiced with modification within the spirit and scope of the claims.

Claims

1. A multiplier, comprising: a MOSFET in a common source configuration for use as a comparator having a Vt comparator threshold; a current source coupled to a drain terminal of the MOSFET; An inverter, the inverter having an input terminal coupled to the drain terminal of the MOSFET, an output terminal of the inverter selecting two current paths, and the current magnitudes of the two current paths are proportional; a first capacitor having a first terminal coupled to the first of the two currents and the gate of the MOSFET and a second terminal connected to ground; a second capacitor having a first end coupled to the second of the two currents and a second end coupled to the first of the two currents and coupled to the gate of the MOSFET; wherein, firstly, the multiplier is reset, then the gate of the MOSFET is pulled below the threshold Vt of the MOSFET, and only the first current for charging the gate capacitance is conducted until the inverter turns off the current; once the Vt comparator threshold is reached, the input charge is removed from the gate of the MOSFET, so that the voltage on the gate of the MOSFET drops below the Vt comparator threshold, wherein dropping below the Vt comparator threshold enables the two currents until the comparator reaches the Vt comparator threshold and the inverter turns off the two currents; Thereafter, the second capacitor holds a product value of the input charge, and the product value is converted into a voltage of the magnitude of the second capacitor or used as a charge input in a subsequent stage.

2. The multiplier according to claim 1, comprising a first current source and a second current source; the first current source provides the first current of the two currents; the second current source provides the second current of the two currents.

3. The multiplier of claim 1, comprising a transconductor; the transconductor being coupled to the multiplier, the transconductor providing programming of the two currents.

4. The multiplier of claim 3, comprising a switch; the switch coupling the multiplier to the transconductor.

5. The multiplier according to claim 4, wherein: The transconductor includes a sample and hold circuit and two current sources, wherein the difference between the bias currents of the two current sources is used as the second current of the two currents in the multiplier; wherein the current is removed from the first current source using the sample and hold circuit, and the sample and hold circuit samples the difference in bias current during a phase in which the input of the transconductor is zero.

6. The multiplier according to claim 5, wherein: The transconductor includes a resistor, wherein the resistor is adjusted for errors in the two currents.

7. The multiplier according to claim 6, wherein: Resistors are analog memory devices.

8. The multiplier according to claim 6, wherein: The resistor is a MOSFET biased in the triode region biased from a bias source designed to maintain a constant transconductance.

9. The multiplier according to claim 6, wherein: The resulting multiplicand is equal to (I1-I2) / ΔV / r, where I1 and I2 are the bias currents of the two current sources in the transconductor, r is the resistance of the resistor, and ΔV is the differential voltage across the input of the transconductor.

10. The multiplier according to claim 1, comprising: a transmission gate coupled to the first capacitor; as well as A reset transistor is coupled to the gate of the MOSFET and to the first capacitor.

11. The multiplier according to claim 10, wherein: The charge packet on the transmission gate causes a release of charge from the input of the multiplier.

12. A multiplier comprising: MOSFET, the MOSFET being in a common source configuration; a MOSFET current source coupled to a drain terminal of the MOSFET; An inverter, the inverter having an input terminal coupled to the drain terminal of the MOSFET, an output terminal of the inverter selecting two current paths, and the current magnitudes of the two current paths are proportional; a first capacitor having a first terminal coupled to the first of the two currents and the gate of the MOSFET and a second terminal connected to ground; a second capacitor having a first end coupled to the second of the two currents and a second end coupled to the first of the two currents; The multiplier is first reset by discharging the gate capacitance of the MOSFET, and then the gate capacitance is recharged to the Vt comparator threshold, and then the charge is removed from the gate terminal of the MOSFET, thereby reducing the voltage on the gate terminal to below the Vt comparator threshold, so that the two currents are enabled until the Vt comparator threshold reaches the previous Vt comparator threshold and the inverter turns off the two currents. In the next reset phase, the second capacitor maintains the product value of the charge.

13. A weighted adder, comprising: MOSFET, the MOSFET being in a common source configuration; a current source coupled to a drain terminal of the MOSFET; an inverter having an input coupled to the drain terminal of the MOSFET, an output of the inverter gated current source; a current source coupled to a gate of the MOSFET; a first capacitor having a first terminal coupled to a second current source and the gate of the MOSFET and a second terminal coupled to ground; a second MOSFET having a drain terminal coupled to the gate of the MOSFET, the current source, and the capacitor, a source terminal coupled to ground, and a gate terminal coupled to a reset signal; one or more current sources, the one or more current sources having a magnitude proportional to the second current source programmed according to a weight, and each current source being enabled according to an input value to remove charge from the gate of the MOSFET during a first cycle; as well as Wherein the second current source replaces the charge during a second period, the time for replacing the charge is a pulse proportional to the weighted sum of the inputs.

Images