Chip packaging structure and chip packaging method

Abstract

The present invention provides a chip packaging structure and a chip packaging method, the chip packaging structure comprising: a chip, a positioning groove is provided on the back of the chip; a substrate, a positioning bump is provided on the upper surface of the substrate; the chip is bonded to the upper surface of the substrate, and the positioning bump is inserted in the positioning groove; a plastic encapsulation layer is located on the upper surface of the substrate and plastic encapsulates the chip; a rewiring layer is located on the upper surface of the plastic encapsulation layer and is electrically connected to the chip; a solder ball bump is located on the upper surface of the rewiring layer and is electrically connected to the rewiring layer. In the chip packaging structure of the present invention, a positioning groove is provided on the back of the chip and a positioning bump is provided on the upper surface of the substrate, the chip is bonded to the upper surface of the substrate, the positioning groove and the positioning bump can enhance the ability of the chip to bond to the upper surface of the substrate, prevent the chip from shifting on the upper surface of the substrate after bonding, thereby ensuring the performance of the chip packaging structure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a chip packaging structure and a chip packaging method. Background Art

[0002] With the continuous demand for higher functionality, better performance and higher energy efficiency, manufacturing smaller packaging structures at lower manufacturing costs has become the pursuit of existing technologies; Fan-Out Wafer Level Package (FOWLP) has become one of the existing technologies that can meet the above needs.

[0003] However, in the existing fan-out packaging structure, the chip is directly bonded to the surface of the substrate before the plastic layer is formed. During the formation of the plastic layer and subsequent processes, the chip will shift under the action of external force, thereby affecting the performance of the final packaging structure. Summary of the invention

[0004] In view of the shortcomings of the prior art described above, an object of the present invention is to provide a chip packaging structure and a chip packaging method, which are used to solve the problem in the prior art that the chip is easily shifted due to the direct bonding of the chip to the surface of the substrate, thereby affecting the performance of the final packaging structure.

[0005] To achieve the above objectives and other related objectives, the present invention provides a chip packaging structure, the chip packaging structure comprising:

[0006] A chip, wherein a positioning groove is provided on the back of the chip;

[0007] A base, wherein a positioning bump is provided on the upper surface of the base; the chip is bonded to the upper surface of the base, and the positioning bump is inserted into the positioning groove;

[0008] A plastic sealing layer, located on the upper surface of the substrate and plastic sealing the chip;

[0009] A rewiring layer is located on the upper surface of the plastic packaging layer and is electrically connected to the chip;

[0010] The solder ball bump is located on the upper surface of the rewiring layer and is electrically connected to the rewiring layer.

[0011] Optionally, a connection pad is formed on the front side of the chip, and the connection pad is electrically connected to a device structure inside the chip; the connection pad is electrically connected to the rewiring layer; and the positioning groove is located on the back side of the chip.

[0012] Optionally, the upper surface of the plastic packaging layer is flush with the front surface of the chip.

[0013] Optionally, the chip packaging structure includes a plurality of the chips, and the plurality of the chips are arranged at intervals on the upper surface of the substrate; a plurality of the positioning grooves are formed on the back side of each chip, and a plurality of the positioning bumps are provided on the upper surface of the substrate, and the positioning bumps are arranged one-to-one correspondingly to the positioning grooves.

[0014] Optionally, the depth of the positioning groove is greater than or equal to the height of the positioning protrusion.

[0015] Optionally, the positioning protrusion includes:

[0016] A plastic packaging material layer, located on the upper surface of the substrate;

[0017] The seed layer is located on the upper surface of the plastic packaging material layer.

[0018] Optionally, the rewiring layer at least includes:

[0019] a first dielectric layer;

[0020] A metal stacked structure located in the first dielectric layer, the metal stacked structure comprising multiple layers of spaced metal wire layers and metal plugs, the metal plugs being located between adjacent metal wire layers to electrically connect adjacent metal wire layers;

[0021] The chip is connected to the metal stacked structure, and the solder ball bump is connected to the metal stacked structure.

[0022] Optionally, the chip packaging structure further includes:

[0023] a sacrificial layer, located on the upper surface of the substrate;

[0024] A second dielectric layer, located on the upper surface of the sacrificial layer;

[0025] The positioning protrusion and the plastic sealing layer are both located on the upper surface of the second dielectric layer.

[0026] To achieve the above object and other related objects, the present invention further provides a chip packaging method, which comprises the following steps:

[0027] preparing a chip, and forming a positioning groove on the back side of the chip;

[0028] Providing a substrate, and forming a positioning bump on an upper surface of the substrate;

[0029] Bonding the chip to the upper surface of the substrate and ensuring that the positioning bump is inserted into the positioning groove;

[0030] Forming a plastic sealing layer on the upper surface of the substrate, wherein the plastic sealing layer seals the chip;

[0031] forming a rewiring layer on the upper surface of the plastic packaging layer, wherein the rewiring layer is electrically connected to the chip;

[0032] forming a solder ball bump on the upper surface of the rewiring layer, wherein the solder ball bump is electrically connected to the rewiring layer;

[0033] The substrate is removed.

[0034] Optionally, forming the positioning bump on the upper surface of the substrate comprises the following steps:

[0035] forming a plastic encapsulation material layer on the upper surface of the substrate;

[0036] forming a seed layer on the upper surface of the plastic packaging material layer;

[0037] The positioning bumps are obtained by patterning the plastic encapsulation material layer and the seed layer.

[0038] Optionally, forming the rewiring layer on the upper surface of the plastic encapsulation layer includes the following steps: forming a first dielectric layer and a metal stack structure on the upper surface of the plastic encapsulation layer, the metal stack structure is located in the first dielectric layer, the metal stack structure includes multiple layers of spaced-apart metal wire layers and metal plugs, the metal plugs are located between adjacent metal wire layers to electrically connect adjacent metal wire layers.

[0039] Optionally, before forming the positioning bump on the upper surface of the substrate, the following steps are also included:

[0040] forming a sacrificial layer on the upper surface of the substrate;

[0041] forming a second dielectric layer on the upper surface of the sacrificial layer;

[0042] The positioning protrusion and the plastic sealing layer are formed on the upper surface of the second dielectric layer.

[0043] Optionally, the sacrificial layer is removed while removing the substrate.

[0044] Optionally, after removing the sacrificial layer, the method further includes removing the second dielectric layer.

[0045] Optionally, a plurality of chips are prepared, and the plurality of chips are bonded to the upper surface of the substrate via different positioning grooves and positioning bumps respectively; after removing the substrate, the obtained structure is sliced ​​to obtain a plurality of packaging structures including a single chip.

[0046] As described above, the chip packaging structure and chip packaging method of the present invention have the following beneficial effects:

[0047] In the chip packaging structure of the present invention, a positioning groove is provided on the back of the chip and a positioning bump is provided on the upper surface of the substrate. The chip is bonded to the upper surface of the substrate. The positioning groove and the positioning bump can enhance the ability of the chip to be bonded to the upper surface of the substrate, and prevent the bonded chip from shifting on the upper surface of the substrate, thereby ensuring the performance of the chip packaging structure.

[0048] The chip packaging method of the present invention first forms a positioning groove on the back side of the chip and forms a positioning bump on the upper surface of the substrate, and then bonds the chip to the upper surface of the substrate. The positioning groove and the positioning bump can enhance the ability of the chip to be bonded to the upper surface of the substrate, and prevent the bonded chip from shifting on the upper surface of the substrate when forming structures such as a plastic encapsulation layer and a rewiring layer, thereby ensuring the performance of the chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 Shown is a schematic flow chart of a chip packaging method provided in Embodiment 1 of the present invention.

[0050] Figures 2 to 18 It is a schematic cross-sectional structure diagram of the structure presented in each step of the chip packaging method provided in the first embodiment of the present invention.

[0051] Fig.19 Shown is a schematic cross-sectional structure diagram of a chip packaging structure provided in the second embodiment of the present invention.

[0052] Component number description

[0053] 10 Wafer

[0054] 11 Chip

[0055] 111 Connection pad

[0056] 12. Protective film

[0057] 13 Positioning slot

[0058] 14 Base

[0059] 15 Positioning bump

[0060] 151 plastic material layer

[0061] 152 Seed Layer

[0062] 16 Plastic layer

[0063] 17 Rewiring Layer

[0064] 171 First dielectric layer

[0065] 1711 Opening

[0066] 172 Metal laminate structure

[0067] 18 solder ball bumps

[0068] 19 Sacrificial layer

[0069] 20 Second dielectric layer DETAILED DESCRIPTION

[0070] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0071] See also Figures 1 to 19 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0072] Embodiment 1

[0073] See also Figure 1 The present invention provides a chip packaging method, the chip packaging method comprising the following steps:

[0074] 1) preparing a chip, and forming a positioning groove on the back side of the chip;

[0075] 2) providing a substrate, and forming a positioning bump on an upper surface of the substrate;

[0076] 3) bonding the chip to the upper surface of the substrate and ensuring that the positioning bump is inserted into the positioning groove;

[0077] 4) forming a plastic sealing layer on the upper surface of the substrate, wherein the plastic sealing layer seals the chip;

[0078] 5) forming a rewiring layer on the upper surface of the plastic packaging layer, wherein the rewiring layer is electrically connected to the chip;

[0079] 6) forming a solder ball bump on the upper surface of the rewiring layer, wherein the solder ball bump is electrically connected to the rewiring layer;

[0080] 7) Removing the substrate.

[0081] In step 1), refer to Figure 1 The S1 step in Figures 2 to 6 , prepare a chip 11, and form a positioning groove 13 on the back side of the chip 11.

[0082] As an example, step 1) may include the following steps:

[0083] 1-1) providing a wafer 10, wherein the wafer 10 has a plurality of chips 11 formed therein, such as Figure 2 As shown; the number of chips 11 in the wafer 10 can be set according to actual needs, Figure 2 Only two chips 11 in the wafer 10 are schematically shown; a device structure (not shown) is formed in the chip 11, and a connection pad 111 is formed on the front side of the chip 11 (i.e., the front side of the wafer 10), and the connection pad 111 is electrically connected to the device structure;

[0084] 1-2) forming a protective film 12 on the front side of the wafer 10, wherein the protective film 12 covers the front side of the wafer 10, so as to ensure that the protective film 12 covers the connection pad 111, such as Figure 3 As shown;

[0085] 1-3) The positioning groove 13 is formed on the back side of the wafer 10 by using a photolithography process, and it is ensured that the positioning groove 13 is formed on the back side of each chip 11. Figure 4 As shown; the thickness of the positioning groove 13 is less than the thickness of the wafer 10;

[0086] 1-4) Slicing the wafer 10 to separate the chips 11, such as Figure 5 and Figure 6 As shown;

[0087] 1-5) removing the protective film 12, such as Figure 6 shown.

[0088] As an example, the wafer 10 may include a silicon wafer, a gallium nitride wafer, or the like.

[0089] As an example, the protective film 12 may include any film structure that can protect the front side of the chip 11 in the process after step 1-2), such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film or an organic material layer (such as a photoresist layer, etc.).

[0090] As an example, the wafer 10 may be sliced ​​using any existing slicing process. The specific method of slicing the wafer 10 to separate the chips 11 is known to those skilled in the art and will not be described again here.

[0091] As an example, the protection film 12 may be removed by an etching process or a grinding process.

[0092] As an example, the schematic diagram of the cross-sectional structure of the chip 11 obtained after step 1) is as follows: Figure 6 shown.

[0093] In step 2), refer to Figure 1 The S2 step in Figures 7 to 9 , providing a substrate 14 , and forming a positioning protrusion 15 on the upper surface of the substrate 14 .

[0094] As an example, the material of the substrate 14 can be one material selected from silicon, glass, silicon oxide, ceramic, polymer and metal, or a composite material of two or more thereof, and its shape can be circular, square or any other desired shape. Preferably, in this embodiment, the material of the substrate 14 is silicon.

[0095] As an example, before forming the positioning bump 15 on the upper surface of the substrate 14, the following steps are also included:

[0096] A sacrificial layer 19 is formed on the upper surface of the substrate 14. Figure 7 As shown;

[0097] A second dielectric layer 20 is formed on the upper surface of the sacrificial layer 19. Figure 7 shown.

[0098] As an example, the sacrificial layer 19 serves as a separation layer between the second dielectric layer 20 and the substrate 14 in the subsequent process. It is best to be made of an adhesive material with a smooth surface. It must have a certain bonding force with the second dielectric layer 20. In addition, it also has a strong bonding force with the substrate 14. Generally speaking, the bonding force between the sacrificial layer 19 and the substrate 14 needs to be greater than the bonding force between the sacrificial layer 19 and the second dielectric layer 20.

[0099] As an example, the sacrificial layer 19 may include a polymer layer or a tape-shaped adhesion layer; specifically, the material of the sacrificial layer 19 may be selected from a tape with sticky surfaces on both sides (e.g., a chip attachment film or a non-conductive film, etc.) or an adhesive made by a spin coating process, etc.; preferably, in this embodiment, the sacrificial layer 19 is preferably a UV tape, which can be easily torn off after being irradiated with UV light (ultraviolet light); of course, in other examples, the sacrificial layer 19 may also be made of other material layers formed by physical vapor deposition or chemical vapor deposition, such as epoxy resin (Epoxy), silicone rubber (Silicone rubber), polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), etc. When the substrate 14 is subsequently separated, the sacrificial layer 19 may be removed by wet etching, chemical mechanical grinding, etc.

[0100] As an example, the sacrificial layer 19 may also be formed by an automatic bonding process.

[0101] As an example, the material of the second dielectric layer 20 may include a low-k dielectric material. Specifically, the material of the second dielectric layer 20 may include one of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorus silicon glass and fluorine-containing glass; the second dielectric layer 20 may be formed by processes such as spin coating, CVD, plasma enhanced CVD, etc.

[0102] As an example, forming the positioning bump 15 on the upper surface of the substrate 14 includes the following steps:

[0103] 2-1) Forming a plastic encapsulation material layer 151 on the upper surface of the substrate 14, such as Figure 8 As shown;

[0104] 2-2) forming a seed layer 152 on the upper surface of the molding material layer 151, such as Figure 8 As shown;

[0105] 2-3) The molding material layer 151 and the seed layer 152 are patterned to obtain the positioning bump 15, such as Fig. 9 shown.

[0106] It should be noted that when the sacrificial layer 19 is formed on the upper surface of the substrate 14 and the second dielectric layer 20 is formed on the upper surface of the sacrificial layer 19 , the molding material layer 151 is formed on the upper surface of the second dielectric layer 20 .

[0107] As an example, the material of the molding material layer 151 may include but is not limited to polyimide, silicone or epoxy resin, etc.

[0108] As an example, the seed layer 152 may be formed by, but is not limited to, a sputtering process; the material of the seed layer 152 may include at least one of Ti (titanium) and Cu (copper); specifically, the seed layer 152 may be a titanium layer, a copper layer, a stacked structure of a titanium layer and a copper layer, or a titanium-copper alloy layer.

[0109] As an example, the number of the positioning protrusions 15 is the same as the number of the positioning grooves 13 .

[0110] As an example, the height of the positioning protrusion 15 is less than or equal to the depth of the positioning groove 13 .

[0111] In step 3), refer to Figure 1 The S3 steps in Fig.10 , bond the chip 11 to the upper surface of the substrate 14 , and ensure that the positioning bump 15 is inserted into the positioning groove 13 .

[0112] As an example, the chip 11 may be bonded to the upper surface of the substrate 14 through a bonding material layer. Specifically, when the sacrificial layer 19 is formed on the upper surface of the substrate 14 and the second dielectric layer 20 is formed on the upper surface of the sacrificial layer 19, the chip 11 may be bonded to the upper surface of the second dielectric layer 20 through a bonding material layer. Of course, the chip 11 may also be in direct contact with the upper surface of the second dielectric layer 20.

[0113] As an example, after the chip 11 is bonded to the upper surface of the chip 14 , the positioning bumps 15 are arranged in a one-to-one correspondence with the positioning grooves 13 , that is, the positioning bumps 15 are inserted into the positioning grooves 13 in a one-to-one correspondence with the positioning grooves 13 .

[0114] As an example, the number of the chips 11 bonded to the upper surface of the substrate 14 can be set according to actual needs. For example, the number of the chips 11 bonded to the upper surface of the substrate 14 can be one, two, three or even more.

[0115] In step 4), refer to Figure 1 Step S4 in Figure 11 to Figure 12 A plastic encapsulation layer 16 is formed on the upper surface of the substrate 14 , and the plastic encapsulation layer 16 encapsulates the chip 11 .

[0116] It should be noted that when the sacrificial layer 19 is formed on the upper surface of the substrate 14 and the second dielectric layer 20 is formed on the upper surface of the sacrificial layer 19 , the plastic encapsulation layer 16 is formed on the upper surface of the second dielectric layer 20 .

[0117] As an example, the molding bottom filling process, imprint molding process, transfer molding process, liquid sealing molding process, vacuum lamination process or spin coating process can be used to form the molding layer 16 on the upper surface of the substrate 14, but it is not limited to it. Preferably, in this embodiment, the molding bottom filling process is used to form the molding layer 16 on the upper surface of the substrate 14. The molding bottom filling process is used to form the molding layer 16, and the molding layer 16 can smoothly and quickly fill the gap between the chips 11, which can effectively avoid interface stratification. Moreover, the molding bottom filling process is not limited like the capillary bottom filling process in the prior art, which greatly reduces the process difficulty, can be used for smaller connection gaps, and is more suitable for stacking structures.

[0118] As an example, the material of the plastic packaging layer 16 may include but is not limited to polymer-based materials, resin-based materials, polyimide, silicone or epoxy resin, etc.

[0119] As an example, the upper surface of the initially formed plastic encapsulation layer 16 may be higher than the front surface of the chip 11. Fig.11 As shown, at this time, after the plastic encapsulation layer 16 is formed, a process of thinning the plastic encapsulation layer 16 is required. Specifically, the plastic encapsulation layer 16 can be thinned by, but not limited to, a chemical mechanical polishing process, so that the upper surface of the retained plastic encapsulation layer 16 is flush with the upper surface of the chip 11, as shown in FIG. Fig.12 Of course, in other examples, the upper surface of the initially formed plastic encapsulation material layer 16 is flush with the upper surface of the chip 11, such as Fig.12 As shown, at this time, the process of thinning the plastic sealing layer 16 can be saved.

[0120] In step 5), refer to Figure 1 Step S5 in Figure 13 to Figure 14 A rewiring layer 17 is formed on the upper surface of the plastic packaging layer 16 , and the rewiring layer 17 is electrically connected to the chip 11 .

[0121] As an example, forming the rewiring layer 17 on the upper surface of the plastic encapsulation layer 16 includes the following steps: forming a first dielectric layer 171 and a metal stack structure 172 on the upper surface of the plastic encapsulation layer 16, the metal stack structure 172 is located in the first dielectric layer 171, the metal stack structure 172 includes multiple layers of spaced-apart metal wire layers (not shown) and metal plugs (not shown), the metal plugs are located between adjacent metal wire layers to electrically connect the adjacent metal wire layers.

[0122] Specifically, forming the rewiring layer 17 on the upper surface of the plastic packaging layer 16 may include the following steps:

[0123] 5-1) forming a first dielectric layer 171 on the upper surface of the plastic encapsulation layer 16, and forming an opening 1711 in the first dielectric layer 171, wherein the opening exposes the connection pad 111, as shown in FIG. Fig.13 ;

[0124] 5-2) forming the metal stack structure 172 and other layers of the first dielectric layer 171 on the first dielectric layer 171 formed in step 5-1); the first dielectric layer 171 exposes the metal wire layer located at the top layer of the metal stack structure 172, such as Fig.14 shown.

[0125] As an example, the material of the first dielectric layer 171 may include a low-k dielectric material. As an example, the first dielectric layer 171 may be made of one of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass, and may be formed by processes such as spin coating, CVD, plasma enhanced CVD, etc.

[0126] As an example, the metal line layer may include a single metal layer, or may include two or more metal layers. As an example, the material of the metal line layer and the material of the metal plug may include one of copper, aluminum, nickel, gold, silver, and titanium, or a combination of two or more materials.

[0127] In step 6), refer to Figure 1 Step S6 in Fig.15 A solder ball bump 18 is formed on the upper surface of the rewiring layer 17 , and the solder ball bump 18 is electrically connected to the rewiring layer 17 .

[0128] As an example, the material of the solder bump 18 may include at least one of copper and tin.

[0129] Specifically, the solder ball bump 18 is electrically connected to the metal wire layer in the rewiring layer 17. The specific process of forming the solder ball bump 18 is known to those skilled in the art and will not be described here.

[0130] In step 7), refer to Figure 1 S7 steps in Fig.16 , removing the substrate 14.

[0131] As an example, the sacrificial layer 19 may be removed simultaneously with the removal of the substrate 14 .

[0132] As an example, the sacrificial layer 19 and the substrate 14 may be removed by a grinding process, a thinning process or a tearing process; preferably, in this embodiment, the substrate 14 is removed by tearing off the sacrificial layer 19 .

[0133] As an example, after removing the sacrificial layer 19, the second dielectric layer 20 may be removed. Specifically, the second dielectric layer 20 may be removed by a grinding process or an etching process. Of course, in other examples, the second dielectric layer 20 may also be retained instead of being removed.

[0134] As an example, a plurality of the chips 11 are bonded to the upper surface of the substrate 14, and after removing the substrate 14, a step of slicing the obtained structure is further included to obtain a plurality of package structures including a single chip 11, such as Fig.17 and Fig.18 shown.

[0135] Embodiment 2

[0136] Please combine Figures 2 to 18 See also Fig.19The present invention also provides a chip packaging structure, which includes: a chip 11, a positioning groove 13 is provided on the back of the chip 11; a substrate 14, a positioning bump 15 is provided on the upper surface of the substrate 14; the chip 11 is bonded to the upper surface of the substrate 14, and the positioning bump 15 is inserted into the positioning groove 13; a plastic encapsulation layer 16, the plastic encapsulation layer 16 is located on the upper surface of the substrate 14, and the chip 11 is plastic encapsulated; a rewiring layer 17, the rewiring layer 17 is located on the upper surface of the plastic encapsulation layer 16, and the rewiring layer 17 is electrically connected to the chip 11; a solder ball bump 18, the solder ball bump 18 is located on the upper surface of the rewiring layer 17, and the solder ball bump 18 is electrically connected to the rewiring layer 17.

[0137] As an example, the chip 11 may include a silicon chip, a gallium nitride chip, or the like.

[0138] As an example, a device structure (not shown) is formed in the chip 11 , and a connection pad 111 is formed on the front side of the chip 11 , and the connection pad 111 is electrically connected to the device structure.

[0139] As an example, the material of the substrate 14 can be one material selected from silicon, glass, silicon oxide, ceramic, polymer and metal, or a composite material of two or more thereof, and its shape can be circular, square or any other desired shape. Preferably, in this embodiment, the material of the substrate 14 is silicon.

[0140] As an example, the chip packaging structure may include a plurality of the chips 11, a plurality of the positioning grooves 13 and a plurality of the positioning bumps 15; the plurality of the chips 11 are arranged at intervals on the upper surface of the substrate 14. Of course, in other examples, the chip packaging structure may also include one chip 11.

[0141] As an example, the positioning bump 15 may include: a molding material layer 151 , wherein the molding material layer 151 is located on the upper surface of the substrate 14 ; and a seed layer 152 , wherein the seed layer 152 is located on the upper surface of the molding material layer 151 .

[0142] As an example, the material of the molding material layer 151 may include but is not limited to polymer-based materials, resin-based materials, polyimide, silicone or epoxy resin, etc.

[0143] As an example, the seed layer 152 may be formed by, but is not limited to, a sputtering process; the material of the seed layer 152 may include at least one of Ti (titanium) and Cu (copper); specifically, the seed layer 152 may be a titanium layer, a copper layer, a stacked structure of a titanium layer and a copper layer, or a titanium-copper alloy layer.

[0144] As an example, the height of the positioning protrusion 15 is less than or equal to the depth of the positioning groove 13 .

[0145] As an example, the number of the positioning protrusions 15 is the same as the number of the positioning grooves 13 .

[0146] As an example, the material of the plastic packaging layer 16 may include but is not limited to polyimide, silicone or epoxy resin, etc.

[0147] As an example, the upper surface of the plastic encapsulation layer 16 may be flush with the front surface of the chip 11 .

[0148] As an example, the rewiring layer 17 includes at least: a first dielectric layer 171; a metal stack structure 172, wherein the metal stack structure 172 is located in the first dielectric layer 171, and the metal stack structure 172 includes multiple layers of spaced metal wire layers (not shown) and metal plugs (not shown), wherein the metal plugs are located between adjacent metal wire layers to electrically connect adjacent metal wire layers; the chip 11 is electrically connected to the metal stack structure 172.

[0149] As an example, the material of the first dielectric layer 171 may include a low-k dielectric material. As an example, the first dielectric layer 171 may be made of one of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass, and may be formed by processes such as spin coating, CVD, plasma enhanced CVD, etc.

[0150] As an example, the metal line layer may include a single metal layer, or may include two or more metal layers. As an example, the material of the metal line layer and the material of the metal plug may include one of copper, aluminum, nickel, gold, silver, and titanium, or a combination of two or more materials.

[0151] As an example, the material of the solder bump 18 may include at least one of copper and tin. The solder bump 18 is electrically connected to the metal wire layer in the rewiring layer 17 .

[0152] As an example, the chip packaging structure also includes: a sacrificial layer 19, which is located on the upper surface of the substrate 14; a second dielectric layer 20, which is located on the upper surface of the sacrificial layer 19; the positioning bump 15 and the plastic encapsulation layer 16 are both located on the upper surface of the second dielectric layer 20.

[0153] As an example, the sacrificial layer 19 serves as a separation layer between the second dielectric layer 20 and the substrate 14 in the subsequent process. It is best to be made of an adhesive material with a smooth surface. It must have a certain bonding force with the second dielectric layer 20. In addition, it also has a strong bonding force with the substrate 14. Generally speaking, the bonding force between the sacrificial layer 19 and the substrate 14 needs to be greater than the bonding force between the sacrificial layer 19 and the second dielectric layer 20.

[0154] As an example, the sacrificial layer 19 may include a polymer layer or a tape-shaped adhesive layer; specifically, the material of the sacrificial layer 19 may be selected from a tape with sticky surfaces on both sides (e.g., a chip attachment film or a non-conductive film, etc.) or an adhesive made by a spin coating process, etc.; preferably, in this embodiment, the sacrificial layer 19 is preferably a UV tape, which can be easily torn off after being irradiated with UV light (ultraviolet light); of course, in other examples, the sacrificial layer 19 may also be made of other material layers formed by physical vapor deposition or chemical vapor deposition, such as epoxy resin (Epoxy), silicone rubber (Silicone rubber), polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), etc. When the substrate 14 is subsequently separated, the sacrificial layer 19 may be removed by wet etching, chemical mechanical grinding, etc.

[0155] As an example, the material of the second dielectric layer 20 may include a low-k dielectric material. Specifically, the material of the second dielectric layer 20 may include one of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorus silicon glass and fluorine-containing glass; the second dielectric layer 20 may be formed by processes such as spin coating, CVD, plasma enhanced CVD, etc.

[0156] In summary, the present invention provides a chip packaging structure and a chip packaging method, the chip packaging structure comprising: a chip, a positioning groove is provided on the back side of the chip; a substrate, a positioning bump is provided on the upper surface of the substrate; the chip is bonded to the upper surface of the substrate, and the positioning bump is inserted in the positioning groove; a plastic encapsulation layer is located on the upper surface of the substrate and plastic encapsulates the chip; a rewiring layer is located on the upper surface of the plastic encapsulation layer and is electrically connected to the chip; a solder ball bump is located on the upper surface of the rewiring layer and is electrically connected to the rewiring layer. In the chip packaging structure of the present invention, a positioning groove is provided on the back side of the chip and a positioning bump is provided on the upper surface of the substrate. The chip is bonded to the upper surface of the substrate. The positioning groove and the positioning bump can enhance the ability of the chip to be bonded to the upper surface of the substrate, and prevent the chip from shifting on the upper surface of the substrate after bonding, thereby ensuring the performance of the chip packaging structure; the chip packaging method of the present invention first forms a positioning groove on the back side of the chip and forms a positioning bump on the upper surface of the substrate, and then bonds the chip to the upper surface of the substrate. The positioning groove and the positioning bump can enhance the ability of the chip to be bonded to the upper surface of the substrate, and prevent the chip from shifting on the upper surface of the substrate when forming structures such as a plastic encapsulation layer and a rewiring layer, thereby ensuring the performance of the chip packaging structure.

[0157] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A chip packaging structure, characterized in that: include: A chip, wherein a positioning groove is provided on the back of the chip; A substrate, wherein a positioning bump is provided on the upper surface of the substrate; the chip is bonded to the upper surface of the substrate, and the positioning bump is inserted into the positioning groove, and the material of the substrate includes at least one of silicon, glass, silicon oxide, ceramic, polymer and metal; A plastic sealing layer, located on the upper surface of the substrate and plastic sealing the chip; A rewiring layer is located on the upper surface of the plastic packaging layer and is electrically connected to the chip; The solder ball bump is located on the upper surface of the rewiring layer and is electrically connected to the rewiring layer.

2. The chip packaging structure according to claim 1, characterized in that: A connection pad is formed on the front side of the chip, and the connection pad is electrically connected to the device structure inside the chip; the connection pad is electrically connected to the rewiring layer; The positioning groove is located on the back side of the chip.

3. The chip packaging structure according to claim 1, characterized in that: The upper surface of the plastic packaging layer is flush with the front surface of the chip.

4. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure includes a plurality of the chips, which are arranged at intervals on the upper surface of the substrate; a plurality of positioning grooves are formed on the back of each chip, and a plurality of positioning bumps are provided on the upper surface of the substrate, and the positioning bumps are arranged in a one-to-one correspondence with the positioning grooves.

5. The chip packaging structure according to claim 1, characterized in that: The depth of the positioning groove is greater than or equal to the height of the positioning protrusion.

6. The chip packaging structure according to claim 1, characterized in that: The positioning protrusion comprises: A plastic packaging material layer, located on the upper surface of the substrate; The seed layer is located on the upper surface of the plastic packaging material layer.

7. The chip packaging structure according to any one of claims 1 to 6, characterized in that: The rewiring layer comprises at least: a first dielectric layer; A metal stacked structure located in the first dielectric layer, the metal stacked structure comprising multiple layers of spaced metal wire layers and metal plugs, the metal plugs being located between adjacent metal wire layers to electrically connect adjacent metal wire layers; The chip is connected to the metal stacked structure, and the solder ball bump is connected to the metal stacked structure.

8. The chip packaging structure according to claim 7, characterized in that: The chip packaging structure further includes: a sacrificial layer, located on the upper surface of the substrate; A second dielectric layer, located on the upper surface of the sacrificial layer; The positioning protrusion and the plastic sealing layer are both located on the upper surface of the second dielectric layer.

9. A chip packaging method, characterized in that: The steps include: preparing a chip, and forming a positioning groove on the back side of the chip; Providing a substrate, and forming a positioning bump on an upper surface of the substrate; Bonding the chip to the upper surface of the substrate and ensuring that the positioning bump is inserted into the positioning groove; Forming a plastic sealing layer on the upper surface of the substrate, wherein the plastic sealing layer seals the chip; forming a rewiring layer on the upper surface of the plastic packaging layer, wherein the rewiring layer is electrically connected to the chip; forming a solder ball bump on the upper surface of the rewiring layer, wherein the solder ball bump is electrically connected to the rewiring layer; The substrate is removed.

10. The chip packaging method according to claim 9, characterized in that: Forming the positioning bump on the upper surface of the substrate comprises the following steps: forming a plastic encapsulation material layer on the upper surface of the substrate; forming a seed layer on the upper surface of the plastic packaging material layer; The positioning bumps are obtained by patterning the plastic encapsulation material layer and the seed layer.

11. The chip packaging method according to claim 9, characterized in that: Forming the rewiring layer on the upper surface of the plastic encapsulation layer includes the following steps: forming a first dielectric layer and a metal stack structure on the upper surface of the plastic encapsulation layer, the metal stack structure is located in the first dielectric layer, the metal stack structure includes multiple layers of spaced metal wire layers and metal plugs, the metal plugs are located between adjacent metal wire layers to electrically connect adjacent metal wire layers.

12. The chip packaging method according to claim 11, characterized in that: Before forming the positioning bump on the upper surface of the substrate, the method further includes the following steps: forming a sacrificial layer on the upper surface of the substrate; forming a second dielectric layer on the upper surface of the sacrificial layer; The positioning protrusion and the plastic sealing layer are formed on the upper surface of the second dielectric layer.

13. The chip packaging method according to claim 12, characterized in that: The sacrificial layer is removed simultaneously with the removal of the substrate.

14. The chip packaging method according to claim 13, characterized in that: After removing the sacrificial layer, the method further includes removing the second dielectric layer.

15. The chip packaging method according to any one of claims 9 to 14, characterized in that: The number of prepared chips is multiple, and the multiple chips are bonded to the upper surface of the substrate via different positioning grooves and positioning bumps respectively; After removing the substrate, the obtained structure is sliced ​​to obtain a plurality of package structures including a single chip.

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