Transistor structure

Abstract

Embodiments of the present disclosure generally relate to transistor structures. A transistor is disclosed. In one embodiment, the transistor includes a first semiconductor region of a substrate, a first channel separating the first semiconductor region on a first side, a first conductive element located in the first channel, a channel region in contact with the first semiconductor region, and a first region in contact with the first semiconductor region, wherein the channel region and the first contact region are located on a same surface side of the substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from French patent application No. 1905661, filed on May 28, 2019, which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to electronic devices and, more particularly, to transistors. Background Art

[0004] In certain electronic devices, field-effect transistors, for example of the MOS type, are used to block high voltages in a non-conducting state, which are typically greater than 10 V, for example, approximately 40 V, or even greater than 100 V. The smaller the transistor is and / or the greater the voltage it blocks in the non-conducting state, the greater the on-state resistance of the transistor. Summary of the Invention

[0005] There is a need to improve the balance between transistor on-resistance, size, and blocking off-state voltage.

[0006] One embodiment overcomes all or some of the disadvantages of known transistors.

[0007] An embodiment can reduce on-state resistance and / or reduce occupied surface area and / or increase blocking voltage.

[0008] Therefore, one embodiment provides a transistor comprising: a first semiconductor region of a substrate, the semiconductor region being delimited by a channel; a conductive element located in the channel; a channel region in contact with the semiconductor region; and a contact region in contact with the region, the channel region and the contact region being on the same surface side of the substrate.

[0009] According to one embodiment, a portion of the semiconductor region is located between the channel region and the contact region.

[0010] According to one embodiment, the semiconductor region is delimited by an additional trench on a side opposite to the channel, and the additional conductive element is located in the additional trench.

[0011] According to one embodiment, a portion of the additional element is located opposite the channel area.

[0012] According to one embodiment, a transistor includes a gate located in a channel.

[0013] According to one embodiment, the channel reaches the buried well.

[0014] According to one embodiment, a portion of the semiconductor region is located between the channel region and the buried well.

[0015] According to one embodiment, a portion of the electrically conductive element is located opposite to the portion of the semiconductor region.

[0016] According to one embodiment, the channel region reaches the buried well.

[0017] According to one embodiment, the transistor includes an additional semiconductor region in contact with the channel region on a side of the channel region opposite to the semiconductor region, and an additional contact region in contact with the additional semiconductor region.

[0018] According to one embodiment, the transistor comprises a further conductive element located in the channel opposite the additional semiconductor region.

[0019] According to one embodiment, the semiconductor region has a doping level which is reduced by a region in contact with said region.

[0020] According to an embodiment, the transistor comprises a doped region covering a portion of the channel region, said doped region preferably being electrically coupled to the conductive element.

[0021] According to one embodiment, the doped region comprises a branch extending between the conductive element and a contact region in contact with the channel region.

[0022] One embodiment provides an electronic device comprising one or more transistors as described. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in conjunction with the accompanying drawings, in which:

[0024] Figures 1A to 1D A top view of an embodiment of a device including a transistor is partially and schematically shown. Figure 1A and cross-section Figure 1B 、 1C and 1D;

[0025] Figure 2 Partially and schematically shown Figures 1A to 1D a perspective view of a device;

[0026] Figures 3A to 3D Partially and schematically illustrates the fabrication Figures 1A to 1D Top view of an example step of the method of the device Figure 3A and cross-section Figure 3B 、 3C and 3D;

[0027] Figures 4A to 4D A top view partially and schematically showing another step of the method Figure 4A and cross-section Figure 4B 、 4C and 4D;

[0028] Figure 5 a top view partially and schematically illustrating another embodiment of a device including a transistor; and

[0029] Figure 6 Partially and schematically shown Figure 5 A perspective view of the device. DETAILED DESCRIPTION

[0030] The same elements are denoted by the same reference numerals in different figures. In particular, structural and / or functional elements common to different embodiments may be designated by the same reference numerals and may have the same structure, dimensions and material properties.

[0031] For the sake of clarity, only those steps and elements that are helpful for understanding the described embodiments are shown and described in detail. In particular, mask making steps, doping steps and steps for making terminals in doped areas are not described in detail, the described embodiments being compatible with such common steps.

[0032] Throughout this disclosure, the term “connect” is used to designate a direct electrical connection between circuit elements, while the term “coupled” is used to designate an electrical connection between circuit elements, which may be direct or via one or more intermediate elements.

[0033] In the following description, when reference is made to terms that define absolute positions (such as terms "top", "bottom", "left", "right", etc.) or terms that define relative positions (such as terms "above", "below", "high", "low", etc.) or when reference is made to terms that define directions (such as terms "horizontal", "vertical", etc.), this refers to the direction of the cross-sectional view.

[0034] As used herein, the terms "about," "substantially," and "approximately" are intended to designate an error of plus or minus 10%, preferably plus or minus 5%, of the stated value.

[0035] Figures 1A to 1D A top view of an embodiment of a device 100 including a transistor is partially and schematically shown. Figure 1A and cross-section Figure 1B 、 1C and 1D. Cross-sectional view Figure 1B 、 1C and 1D have corresponding cross-sectional planes BB, CC, DD. Figure 2 A simplified perspective view of a portion of the device 100 is shown. In particular, Figure 2 Electrical insulators, doped regions and buried wells are not shown.

[0036] The device 100 is generally an electronic integrated circuit chip defined by a semiconductor substrate 102 and elements (such as electronic components) located within and on top of the substrate 102 .

[0037] In one example, substrate 102 is formed of a semiconductor wafer (eg, a silicon wafer). In another example, substrate 102 is formed of a layer located on the surface of a semiconductor wafer, such as an epitaxial layer on a semiconductor wafer. Preferably, substrate 102 is a single crystal substrate.

[0038] In an electronic component, device 100 includes one or more transistors. In particular, device 100 includes a field-effect transistor T110 or a plurality of transistors T110 electrically connected in parallel. Transistor T110 specifically includes: a gate 120 connected to a control terminal 122 of the transistor; a channel region 130 separated from gate 120 by a gate insulator 124. Channel region 130 is preferably connected to terminal 132, referred to as the body terminal of the transistor, via a contact region 134; and doped drain / source regions 140 and 150 located on either side of channel region 130 and in contact with respective conductive terminals 142 and 152. According to one embodiment, doped region 140 covers a portion of channel region 130.

[0039] The transistor T110 is located on the side of the front surface (upper surface) of the substrate 102. In particular, elements such as the gate 120, the channel region 130, and the doped regions 140 and 150 are located on the front side of the substrate, i.e., each of them has a surface on the front surface side that is not covered by a portion of the substrate 102. Therefore, the terminals 132, 142, and 152 can be defined by conductors located on these elements, for example, vias passing through an insulating layer covering the device. Compared to if the doped region 150 were located on the back surface side, it is easier to form connections that can electrically couple the transistor T110 to other components of the device or external devices.

[0040] Preferably, conductive terminal 142 and body terminal 132 are electrically coupled to each other, preferably electrically connected to each other. Terminal 142 then corresponds to the source terminal of transistor T110, and terminal 152 corresponds to the drain terminal of transistor T110. Doped regions 140 and 150 then define respective drain and source regions. This is not a limitation, and, for example, terminals 132 and 142 may not be coupled to or connected to each other.

[0041] Gate 120 includes at least one electrical conductor, such as metal and / or doped polysilicon. Gate insulator 124 contacts channel region 130 and the electrical conductor of gate 120. Gate insulator 124 is typically formed from one or more dielectric layers, such as a silicon oxide layer. The thickness of the gate insulator is typically less than 15 nm, preferably in the range of 3 nm to 10 nm.

[0042] For example, transistor T110 is of N-channel type. Therefore, doped regions 140 and 150 are N-type doped. Channel region 130 is P-type doped. However, in the described embodiment, the N and P conductivity types or doping types can be swapped. Then, by swapping the signs of the voltages in the device, similar operation to that described can be achieved. Preferably, the doping level of regions 140 and 150 is high, i.e., greater than 5*10 18 atoms / cm 3 And preferably greater than 10 19 atoms / cm 3 The contact region 134 that contacts the channel region 130 is a doped region that also has this high doping level. The doping level of the channel region 130 is preferably less than 10 18 atoms / cm 3 , more preferably less than 5*10 17 atoms / cm3.

[0043] The transistor T110 further includes a semiconductor region 160 ( Figure 2 The semiconductor region 160 is insulated from the doped region 140 by the channel region 130. The semiconductor region 160 includes at least a portion 162 (not shown) located between the channel region 130 and the doped region 150. Figure 1D ). The distance separating the channel region 130 from the doped region 150 is, for example, in the range of 1 μm to 5 μm, preferably in the range of 2 μm to 4 μm. The N-type doping level of the semiconductor region 160 is lower than that of the N-type doped region 150. Preferably, the semiconductor region 160 has a low doping level, i.e., less than 2*10 17 atoms / cm 3 The doping level is preferably greater than 5*10 16 atoms / cm 3 Since its doping level is greater than that of the semiconductor region 160 , the doped region 150 forms an electrical contact region that is in electrical contact with the semiconductor region 160 .

[0044] In the non-conductive state of the transistor, the drift region 160, due to its low doping level, blocks the high voltage between the channel region 130 and the contact region 150 as previously described. In the conductive state of the transistor, the current flowing through the transistor flows through the drift region 160, from the contact region 150 to the channel region 130.

[0045] The semiconductor region 160 is delimited by a channel 170. More specifically, the channel 170 extends in the substrate 102 from the front surface of the substrate 102, and the well of the channel 170 forms the side surface of the semiconductor region 160. Preferably, the well of the channel 170 also forms the surface of the channel region 130. For example, the width of the channel is between 100 nm and 500 nm.

[0046] Transistor T110 further includes a conductive element 180 located in channel 170. Conductive element 180 is connected to terminal 182. Terminal 182 is preferably connected to body terminal 132. Conductive element 180 is located opposite at least a portion of semiconductor region 160, that is, conductive element 180 is located on an insulator 184 that covers the sides of at least a portion of semiconductor region 160. In particular, conductive element 180 is located opposite portion 162 located between channel region 130 and doped region 140. Preferably, conductive element 180 is located opposite the entire semiconductor region 160, or substantially the entire semiconductor region 160. An insulating layer 184 separates conductive element 180 from semiconductor region 160. Corresponding to the thickness of insulating layer 184, the distance between conductive element 180 and semiconductor region 160 is, for example, in the range of 100 nm to 200 nm, preferably in the range of 120 nm to 180 nm. Insulating layer 184 preferably has a thickness greater than that of gate insulator 124. For example, the insulating layer 184 is made of silicon oxide or silicon nitride.

[0047] At the bottom of the channel 170, an insulating portion (preferably a portion of layer 184) is located below the conductive element 180. This portion electrically insulates the conductive element 180 from the portion of the substrate located below the conductive element 180. In addition, an insulating portion 186, preferably having the same thickness and the same material(s) as the gate insulator 124, electrically insulates the conductive element 180 from the gate 120.

[0048] Preferably, conductive element 180 is formed by a conductive well located in the center of channel 170. The well extends in the same direction as the channel. The well extends perpendicularly in substrate 102 toward the front surface of the substrate. For example, the well is preferably made of a metal material or preferably doped polysilicon. The width of the conductive well, in the direction of the width of the channel, is, for example, in the range of 30 nm to 200 nm.

[0049] In the non-conductive state of the transistor, the conductive element 180 shields a portion of the electric field due to the voltage between the channel region 130 and the contact region 150. The electric field at the level of the PN junction between the channel region 130 and the semiconductor region 160 is lower than if the conductive element 180 were not provided. This increases the maximum voltage that the transistor can block.

[0050] In the absence of the conductive element 180, in order to increase the maximum voltage that the transistor can block, it can be designed to reduce the doping level of the drift region 160 or increase the distance between the channel region 130 and the drain contact region 150. However, this will increase the resistance of the drift region 160, thereby increasing the on-state resistance of the transistor. Therefore, the conductive element 180 can increase the maximum voltage blocked by the transistor without increasing the on-state resistance of the transistor. In addition, the conductive element 180 can increase the doping level of the drift region 160 and / or reduce the distance between the channel region 130 and the drain contact region 150, thereby reducing the on-state resistance of the transistor, while maintaining the maximum blocking voltage at least equal to the maximum blocking voltage of the transistor without the conductive element 180.

[0051] Preferably, semiconductor region 160 is delimited by an additional trench 170A on its side opposite channel 170. Semiconductor region 160 is then located between channels 170 and 170A. Additional trench 170A is parallel to channel 170, i.e., channels 170 and 170A extend in the same direction. More preferably, additional trench 170A comprises the same elements as channel 170 and is arranged symmetrically relative to semiconductor region 160, i.e., additional conductive element 180A is symmetrical to conductive element 180 and is located opposite at least a portion of semiconductor region 160. Conductive element 180A is in contact with terminal 182A, preferably connected to terminal 182 of conductive element 180.

[0052] The additional conductive element 180A can improve the shielding allowed by the conductive element 180. This results in an additional improvement in the maximum voltage blocked by the transistor and / or in the on-resistance of the transistor.

[0053] Preferably, the channel region 130 is delimited by the channel 170. More particularly, the channel region then has side surfaces formed by the well of the channel 170. More preferably, the gate 120 is then located in the channel 170 opposite the channel region 130. The gate insulator 124 covers the corresponding portion of the well of the channel 170.

[0054] Due to the fact that the gate is in the channel, a conductive channel is formed relative to the side surface of the channel region 130 when the channel region 130 is in a conductive state. Compared to a variant in which the gate 120 is arranged on the channel region 130, this avoids the conductive channel having a width that is the same as the distance between the channels 170 and 170A. Therefore, the fact that the gate 120 is provided in the channel 170 makes the shape of the conductive channel independent of the distance that the channel region 130 extends from the channel 170. Therefore, this distance can be reduced, for example, the channels can be brought closer to each other without modifying the shape of the conductive channel, for example, without reducing its width, thereby reducing the current flowing through the transistor, and without increasing the on-state resistance of the transistor. Therefore, for the same current and the same on-state resistance, the surface area occupied by the transistor T110 is smaller than the surface area of ​​a transistor whose gate is located in the channel region. For example, the width of the semiconductor region 160 in the channel width direction is in the range of 300nm to 1μm.

[0055] The conductive element 180 and the gate 120 located in the channel result in a current in the transistor T110 in the conductive state flowing through a portion of the drift region 160 that is larger than when the conductive element 180 and / or the gate 120 are not located in the channel. In particular, the current flows through a portion of the drift region 160 that is further from the side of the drift region 160 than when the conductive element is not located. The current also flows through a portion of the drift region 160 that is further from the upper surface of the drift region 160 than when the gate is located in the channel region. This makes it possible to reduce the on-state resistance of the transistor, in particular by reducing various effects of the presence of the surface of the drift region 160 on the charge carrier mobility.

[0056] In a preferred example, the semiconductor region 160 has a reduced doping level from the contact region 150. In the example shown, the semiconductor region 160 includes two sub-regions 166-1 and 166-2.

[0057] Subregion 166-2 separates subregion 166-1 from contact region 150. Subregion 166-2 extends from the contact region to channel region 130 by a distance that is, for example, in the range of one-third to two-thirds of the distance between contact region 150 and channel region 130, preferably substantially half. Subregion 166-2 extends from the contact region to channel region 130 by a distance that is, for example, in the range of 0.5 μm to 1.5 μm, preferably approximately 1 μm. The doping level of subregion 166-2 is within the range from region 166-1 to contact region 150. The doping level of subregion 166-2 is within the range of 10 μm to 1.5 μm. 17 atoms / cm 3 to 10 18 atoms / cm 3 within the range.

[0058] This preferred example is not restrictive, and the semiconductor region 160 may include or be formed of a number N of semiconductor sub-regions 166-i, with the index i ranging from 1 to N. The sub-regions 166-N extend from the contact region 150. The sub-regions are arranged in order of decreasing index i from the contact region 150, and the doping level of the sub-region 166-i is an increasing function of the index i. As a variant, the semiconductor region 160 may have a doping level gradient from the contact region 150.

[0059] Subregion 166-i, for i different from 1, or for a subregion with a doping level gradient, forms a region having a doping level intermediate between subregion 166-1 and contact region 150. For a given on-state resistance, such a region allows achieving the maximum voltage level required for transistor blocking. The fact that the doping level of semiconductor region 160 is reduced from that of contact region 150 allows the on-resistance of the transistor to be increased for the same maximum voltage at which the transistor blocks in the non-conducting state.

[0060] According to one embodiment, channel region 130 is located on semiconductor region 160, more particularly, portion 168 of semiconductor region 160 is located below channel region 130. In other words, channel region 130 is on the front surface side compared to portion 168. Portion 188 of conductive element 180 is then preferably located below gate 120. Portion 188 of conductive element is then located opposite portion 168 of semiconductor region 160.

[0061] An advantage of providing portion 168 of semiconductor region 160 is that, in the conductive state, the conductive channel of the transistor includes horizontal portion 138 in contact with portion 168, and current originating from contact region 150 can pass through portion 168 of semiconductor region 160 to access portion 138 of the channel. This results in a lower on-state resistance.

[0062] According to another advantage, in the device 100, a transistor (not shown) can also be provided, which differs from the transistor T110 including the portion 168 of the semiconductor region 160 in that the contact region 150 is omitted and replaced by a drain contact region on the rear surface of the substrate. In this transistor, referred to as a vertical transistor, in the conductive state, current flows vertically between the channel region and the drain contact region. In order to manufacture the transistor T110 including the portion 168 of the region 160 and the vertical transistor in the same device, the steps of manufacturing the transistor T110 and the vertical transistor can be implemented simultaneously. Then, the device including the vertical transistor and the transistor T110 is particularly easy to manufacture.

[0063] Preferably, the doped region 140 has a branch 144 extending between the contact region 134 in contact with the channel region and the conductive element 180. This allows the length of the conductive channel between the doped region 140 and the semiconductor region 160 to be reduced for a given size of the contact region 134, thereby reducing the on-state resistance.

[0064] Preferably, channels 170 and 170A reach a buried well 190, i.e., a region having a conductivity type (here, P-type) opposite to that of substrate 102 (here, N-type) covers a portion of the substrate and is covered by a region having the same conductivity type as the substrate. In other words, the channel extends from the front surface of substrate 102 to buried well 190. Thus, a possible portion 168 of semiconductor region 160 is located between channel region 130 and buried well 190. Buried well 190 can be biased to a potential lower than that of semiconductor region 160. To this end, buried well 190 is coupled to ground (not shown), for example. Thus, the buried well can electrically insulate semiconductor region 160 from the rest of substrate 102. Consequently, transistor T110 can be insulated from other components of the device (e.g., other transistors).

[0065] Preferably, the device 100 comprises a plurality of transistors T110, more preferably repeated in an array. Thus, in the example shown, the transistors are repeated in a first direction parallel to the front surface (e.g., the column direction of the array), which in this example is orthogonal to the direction in which the channels 170 and 170A extend.

[0066] Preferably, device 100 includes transistors T112 inserted between adjacent transistors T110 repeated in a first direction, i.e., a column includes alternately repeated transistors T110 and T112. Transistor T112 is symmetrical with respect to a plane orthogonal to the first direction. In the example shown, each channel 170 is shared by one transistor T110 and one transistor T112 symmetrically arranged on either side of the channel, and gate 120 and conductive element 180 are shared by both transistors. In this example, semiconductor region 160, channel region 130, and doped regions 140 and 150 are shared by one transistor T110 and one transistor T112 symmetrically arranged on either side of semiconductor region 160, and for each of the two transistors, the channel 170 of one of the two transistors corresponds to the additional channel 170A of the other of the two transistors.

[0067] The transistors T110 and preferably the transistors T112 are also repeated in a second direction parallel to the front surface and orthogonal to the first direction, for example the row direction of the array (repetition not shown). Figure 1A 、 1C and the left and right directions of 1D. Preferably, the columns close to the array are symmetrical with respect to the plane of the row direction. The semiconductor region 160 can be selectively demarcated by channels (channel walls 195) extending along the column direction. As a variant, the transistors are repeated only in the first direction or only in the second direction. This is not restrictive, and the device can include a plurality of transistors in different arrangements, or one or more pairs of transistors T110 and T112 between the two channels 170, 170A.

[0068] In a preferred example, terminals 132, 142, 152, and 182 are common to transistors T110 and / or T112. Thus, transistors T110 and / or T112 are electrically connected in parallel and controlled in parallel, which enables the conduction of high currents, i.e., currents greater than 1 A, for example, currents greater than 5 A, or even currents greater than 50 A, by the series connection of parallel transistors. This connection corresponds to the transistor formed by the basic transistors T110 and / or T112. A possible buried well 190 is preferably common to transistors T110 and / or T112.

[0069] Thus, as described above, the transistor formed from the basic transistors T110 and / or T112 enables high current flow and improves the balance between maximum blocking voltage and on-resistance. This is achieved for a relatively small substrate surface area occupied by the formed transistor. For example, for a maximum blocking voltage of approximately 44 V, the on-resistance of the formed transistor can be less than 17 mΩ / mm. 2 .

[0070] Figures 3A to 3D and Figures 4A to 4D Partially and schematically illustrates the fabrication Figures 1A to 1D The exemplary steps of the method of the device 100 are as follows. More particularly, Figures 3A to 3D Shows the top view of the same step Figure 3A and cross-section Figure 3B 、 3C and 3D, and Figures 4A to 4D Shows a top view of another step Figure 4A and cross-section Figure 4B 、 4C and 4D. The cross-sectional planes are respectively Figures 1A to 1D The same as in .

[0071] exist Figures 3A to 3D In step 102, a substrate 102 is provided. Optionally, a buried well 190 is formed. The buried well 190 may be formed in this step or in a subsequent step of the method.

[0072] Then, trenches 170, 170A are etched into the substrate, preferably down to the level of the buried well. An electrically insulating layer 384 is then formed at the well and bottom of the trench, comprising a portion of the future insulating layer 184 that will form the transistor. This layer is obtained, for example, by conformal deposition covering the structure resulting from the etching of the trench. The insulating layer 384 is preferably made of silicon oxide. The thickness of the insulating layer 384 is less than half the width of the trench, so as to leave an unfilled space in the central portion of the trench.

[0073] The remaining space in the trench is then filled, preferably with doped polysilicon. This forms the conductive elements 180, 180A. For example, the entire structure formed by deposition of an insulating layer is covered with polysilicon, and the polysilicon above a given level is removed by etching. This given level is preferably the level of the front surface of the substrate, or a height less than 10 nm above the front surface of the substrate. This results in the conductive walls 180, 180A being located in the trench.

[0074] exist Figures 4A to 4D In a step 420, portions of the insulating layer 384 and portions of the conductive material of the element 180 are removed at the locations 420 of the gate 120 and the gate insulator 124. Preferably, a mask 460 (shown in dashed lines) has previously been formed for this purpose, which allows access to portions 464 of the upper surface of the structure. Portions 464 are strip-shaped in top view with a main direction or extension direction orthogonal to the direction of extension of the channel. The portions of the conductive material of the element 180 located in the strips 464 are selectively etched on the insulating layer 384 to the upper layer of the portion 188 of the conductive element 180. The insulating layer 384 protects the substrate during the etching of the conductive material. The portions of the insulating layer 384 that were made accessible by the etching of the conductive material are then selectively etched on the substrate 102.

[0075] In a subsequent step (not shown), a gate insulator is formed over the well of the accessible channel 170 in the strip 464. An insulating portion 186, which insulates the conductive element 180 from the future gate 120, is preferably formed simultaneously with the gate insulator. This can be achieved by thermal oxidation. Gate 120 is then formed. Before or after the aforementioned steps, channel region 130, doped regions 134, 140, 150, and subregion 166-i can be formed by doping substrate 102. Subsequently, terminals 122, 132, 142, 152, and 182 are formed.

[0076] Figure 5 and Figure 6 1 and 2 are a cross-sectional view and a partial perspective view, respectively, schematically illustrating an embodiment of a device 500 including one or more transistors, in particular a transistor T510. The device 500 includes Figures 1A to 1D and Figure 2The same or similar elements of the device 100 are arranged the same or similarly. Therefore, these elements will not be described in detail, and only the differences will be highlighted here.

[0077] Transistor T510 and Figures 1A to 1D and Figure 2 The transistor T110 of device 100 differs in that the channel region 130 extends from the front surface of substrate 102 toward buried well 190, i.e., reaches the buried well. Consequently, semiconductor region 160 is stripped of a portion 168 located beneath the channel region. Device 500 includes a semiconductor region 560 in contact with channel region 130 and located on the side of channel region 130 opposite semiconductor region 160. Due to the fact that the channel region reaches the buried well, semiconductor regions 160 and 560 are electrically insulated from one another in the blocked state. Furthermore, N-type doped region 140 is replaced by an N-type doped region 540 having a high doping level, such that doped region 540 forms a region in electrical contact with region 560. Contact region 540 is connected to terminal 542, preferably to the body terminal 132 of the transistor.

[0078] Preferably, the conductive element 180 does not include the portion 188 located below the gate 120. More preferably, the transistor T510 then includes a conductive element 580 arranged in the channel 170 on the side of the gate 120 opposite the conductive element 180. The conductive element 580 is located opposite at least a portion of the semiconductor region 560, i.e., in the insulating layer 584 located in the semiconductor region 560. The conductive element 580 is connected to a terminal 582, preferably to the terminal 182 of the conductive element 180. As a variant, the conductive element 180 may include the portion 188 located below the gate 120 and continue with the portion 580 located in the channel 170 opposite the semiconductor region 560.

[0079] Preferably, transistor T510 has a symmetry plane orthogonal to the extension direction of the channel and passing through gate 120 and channel region 130. In particular, conductive element 580, region 560, and contact region 540 are symmetrical with conductive element 180, semiconductor region 160, and doped region 150, respectively, relative to the symmetry plane.

[0080] In the preferred case where transistor T510 includes channel 170A and conductive element 180A located in channel 170A, conductive element 180A extends in channel 170A, more preferably opposite semiconductor region 160, channel region 130, and semiconductor region 560. In other words, channel 170 does not include a gate of another transistor.

[0081] In one example, the doping level is substantially uniform in each of the semiconductor regions 160 and 560, e.g., the doping levels of these regions are equal. In another example, the doping of the semiconductor regions 160 and 560 is reduced from the corresponding contact regions 150 and 540. Then, the semiconductor regions 160 and 560 can include, for example, corresponding sub-regions 166-2 and 566-2 located in the corresponding contact regions 150 and 540, respectively, with these sub-regions having a doping level intermediate between the rest of the regions 160, 560 and the contact regions 150 and 540.

[0082] As described in the case of the transistor T110 , the structure of the transistor T510 makes it possible to optimize the balance between the maximum off-state voltage, the on-state resistance and the substrate surface area occupied by the transistor (top view).

[0083] Preferably, the device 500 further includes a transistor T512 symmetrical to the transistor T510 with respect to the channel 170 , the channel 170 , a gate 600 , and conductive elements 180 and 580 shared by the transistors T510 and T512 .

[0084] Preferably, transistors T510 and T512 are connected in parallel, and their control terminals 122 are coupled together, preferably connected together.

[0085] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these different embodiments and variations may be combined, and that other variations will occur to those skilled in the art.

[0086] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

Claims

1. A transistor comprising: a first drift region of the substrate; a first source / drain region, disposed in the first drift region; a second source / drain region disposed in the first drift region and separated from the first source / drain region; a first channel extending from the first source / drain region to the second source / drain region along a first side of the first drift region; a first conductive element located in the first channel; a gate electrode located in the first channel and adjacent to the first conductive element; a channel region adjacent to the gate electrode and the first source / drain region and in contact with the first drift region; and wherein the channel region and the second source / drain region are on the same surface side of the substrate; The transistor further includes a buried well separated from the surface side of the substrate by the first drift region, wherein the first channel reaches the buried well; wherein a second portion of the first drift region is located between the channel region and the buried well.

2. The transistor according to claim 1 , further comprising: a second channel extending along a second side of the first drift region, the second side being opposite to the first side; as well as The second conductive element is located in the second channel. The transistor according to claim 2 , wherein a portion of the second conductive element is opposite to the channel region. 4 . The transistor of claim 1 , wherein a portion of the first conductive element is opposite to the second portion of the first drift region. The transistor of claim 1 , wherein the first source / drain region covers a portion of the channel region. 6 . The transistor of claim 5 , wherein the first source / drain region includes a branch extending between the first channel and a channel contact region of the channel region.

7. An electronic device comprising: A plurality of transistors according to claim 1.

8. A transistor comprising: a first drift region of the substrate; a first source / drain region, disposed in the first drift region; a second source / drain region disposed in the first drift region and laterally separated from the first source / drain region; a first channel extending from the first source / drain region to the second source / drain region along a first side of the first drift region; a first conductive element located in the first channel; a first gate located in the first channel; a second channel extending from the first source / drain region to the second source / drain region along a second side of the first drift region, the second side being opposite to the first side; a second conductive element located in the second channel; a second gate located in the second channel; a channel region, contacting the first drift region and located between the first channel and the second channel; a channel contact region contacting the channel region; wherein the first source / drain region includes a branch between the first channel and the second channel located on the front surface side of the substrate, the branch partially surrounding the channel contact region and located above the channel region; as well as wherein the second source / drain region is located on the same front surface side of the substrate as the first source / drain region; wherein the first channel and the second channel reach a buried well located at a rear surface side of the substrate; and wherein a second portion of the first drift region is located between the channel region and the buried well.

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