Vertical memory device

Abstract

A vertical memory device includes a substrate including a first region and a second region; gate electrodes spaced apart from each other in a first direction, each of the gate electrodes extending over the first region and the second region in a second direction, and the gate electrodes stacked over the second region; a channel extending over the first region in the first direction, the channel extending through the gate electrodes; a first conductive structure on an end of a first gate electrode, the end being over the second region, the first gate electrode disposed at a lowermost level; and a second conductive structure spaced apart from the first conductive structure in the second direction over the second region, the second conductive structure not overlapping the first gate electrode in the first direction and disposed at a different level than the first conductive structure.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0066135, filed on June 4, 2019 with the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a vertical memory device. Background Technology

[0004] When manufacturing VNAND flash memory devices, insulating pads can be disposed at the ends of the sacrificial layer to form pads for contacting the contact plugs at the ends of the gate electrodes. During the gate replacement process, the insulating pads can be replaced with metal. Metal gates can cause electrical short circuits and are therefore eventually removed. However, removing the insulating pads is time-consuming and difficult, thus increasing the cost of VNAND flash memory devices. Summary of the Invention

[0005] According to an exemplary embodiment of the present invention, a vertical memory device is provided. The vertical memory device may include: a substrate including a first region and a second region at least partially surrounding the first region; gate electrodes at a plurality of horizontal levels, the gate electrodes being spaced apart from each other in a first direction substantially perpendicular to an upper surface of the substrate, each of the gate electrodes extending in a second direction substantially parallel to the upper surface in the first and second regions, and the gate electrodes being stacked in a stepped shape in the second region; a channel extending in the first direction in the first region, the channel extending through the gate electrodes; a first conductive structure at an end of a first gate electrode among the gate electrodes, the end being in the second region, the first gate electrode being disposed at the lowest of the plurality of horizontal levels; and a second conductive structure spaced apart from the first conductive structure in the second direction in the second region, the second conductive structure not overlapping the first gate electrode in the first direction and being disposed at a height different from the height of the first conductive structure.

[0006] According to an exemplary embodiment of the present invention, a vertical memory device is provided. The vertical memory device may include: a substrate including a cell array region, an extension region at least partially surrounding the cell array region, and a circuit region at least partially surrounding the extension region; gate electrodes at a plurality of horizontal levels, the gate electrodes being spaced apart from each other in a first direction substantially perpendicular to an upper surface of the substrate, each of the gate electrodes extending in a second direction substantially parallel to the upper surface of the substrate in both the cell array region and the extension region, and the gate electrodes being stacked in a stepped shape in the extension region of the substrate; a channel extending in the first direction in the cell array region of the substrate, the channel extending through the gate electrodes; a first insulating pad spaced apart in a portion of the circuit region of the substrate from an end of a first gate electrode in the second direction, the first gate electrode being disposed at the lowest of the plurality of horizontal levels, and the first insulating pad being higher than the first gate electrode relative to the upper surface of the substrate; and a second insulating pad spaced apart in the second direction from the first insulating pad in the circuit region of the substrate, the second insulating pad being at a height different from the height of the first insulating pad, wherein the first insulating pad and the second insulating pad comprise substantially the same material.

[0007] According to an exemplary embodiment of the present invention, a vertical memory device is provided. The vertical memory device may include: a substrate including a cell array region, an extension region at least partially surrounding the cell array region, and a circuit region at least partially surrounding the extension region; a plurality of horizontal gate electrodes spaced apart from each other in a first direction substantially perpendicular to an upper surface of the substrate, each of the gate electrodes extending in a second direction substantially parallel to the upper surface of the substrate in both the cell array region and the extension region, and the gate electrodes being stacked in a stepped shape in the extension region of the substrate; a channel extending in the first direction in the cell array region of the substrate, the channel extending through the gate electrodes; a conductive structure higher than a first gate electrode and lower than a second gate electrode, the conductive structure overlapping an end of a first gate electrode in the first direction, the first gate electrode being adjacent to the upper surface of the substrate; and a cut pattern extending in the first direction in the circuit region of the substrate, the cut pattern contacting the conductive structure.

[0008] According to an exemplary embodiment of the present invention, a vertical memory device is provided. The vertical memory device may include: a substrate including a cell array region and an extension region at least partially surrounding the cell array region; gate electrodes at a plurality of horizontal levels, the gate electrodes being spaced apart from each other in a first direction substantially perpendicular to an upper surface of the substrate, each of the gate electrodes extending in a second direction substantially parallel to the upper surface of the substrate in both the cell array region and the extension region of the substrate, and the gate electrodes having a stepped shape in the extension region of the substrate; a channel extending in the first direction in the cell array region of the substrate, the channel extending through the gate electrodes; a conductive structure on an end of a first gate electrode in the extension region of the substrate, the first gate electrode being disposed at the lowest of the plurality of horizontal levels; and conductive pads formed at the ends of the gate electrodes, each of the conductive pads being thicker than other portions of the gate electrode on which the conductive pads are formed, wherein each of the conductive pads protrudes upward from its respective gate electrode in a third direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction.

[0009] According to an exemplary embodiment of the present invention, a vertical memory device is provided. The vertical memory device may include: a circuit pattern on a substrate; gate electrodes spaced apart from each other on the circuit pattern in a first direction substantially perpendicular to the upper surface of the substrate, each of the gate electrodes extending in a second direction substantially parallel to the upper surface of the substrate, and the gate electrodes being stacked in a stepped shape; a channel extending through the gate electrodes in the first direction; and a first contact plug extending through at least one of the gate electrodes in the first direction to be electrically connected to the circuit pattern, wherein conductive pads are respectively formed at the ends of the gate electrodes in the second direction, each of the conductive pads having a thickness greater than the thickness of the gate electrode on which the conductive pads are formed, and each of the conductive pads protruding upward from the gate electrode on which the conductive pads are formed in a third direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction, and wherein the first contact plug extends through the conductive pad of at least one of the gate electrodes.

[0010] According to an exemplary embodiment of the present invention, a vertical memory device is provided. The vertical memory device may include: a substrate including a cell array region and an extension region at least partially surrounding the cell array region; gate electrodes at a plurality of horizontal locations, the gate electrodes being spaced apart from each other in a first direction substantially perpendicular to an upper surface of the substrate, each of the gate electrodes extending in a second direction substantially parallel to the upper surface of the substrate over the cell array region and the extension region of the substrate, and the gate electrodes having a stepped shape over the extension region of the substrate; and a channel extending in the first direction over the cell array region of the substrate, the channel extending through the gate electrodes, wherein the ends of the gate electrodes in the second direction form a stepped structure, the stepped structure including a third upward step disposed substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction, and wherein a sacrificial pattern and an insulating layer are formed between a portion of a gate electrode at a level directly below the uppermost level of the stepped structure and the step at the second level, the sacrificial pattern and the insulating layer comprising materials different from each other. Attached Figure Description

[0011] FIG. 1 , FIG. 2 , FIG. 3 , FIG. 4 and FIG. 5 These are plan and cross-sectional views illustrating an exemplary embodiment of a vertical memory device according to the present invention.

[0012] FIG. 6 , FIG. 7 , FIG. 8 , FIG. 9 , FIG. 10 , FIG. 11 , FIG. 12 , FIG. 13 , FIG. 14 , FIG. 15 , FIG. 16 , FIG. 17 , FIG. 18 , FIG. 19 , FIG. 20 , FIG. 21 and FIG. 22 These are plan and cross-sectional views illustrating a method for manufacturing a vertical memory device according to an exemplary embodiment of the present invention.

[0013] FIG. 23 , FIG. 24 , FIG. 25 , FIG. 26 , FIG. 27 and FIG. 28 These are plan and cross-sectional views illustrating a manufacturing method of a vertical memory device according to a comparative example.

[0014] FIG. 29 ,FIG. 30 and FIG. 31 These are plan and cross-sectional views illustrating an exemplary embodiment of a vertical memory device according to the present invention.

[0015] FIG. 32 , FIG. 33 , FIG. 34 and FIG. 35 These are plan and cross-sectional views illustrating a method for manufacturing a vertical memory device according to an exemplary embodiment of the present invention.

[0016] FIG. 36 and FIG. 37 This is a cross-sectional view illustrating an exemplary embodiment of a vertical memory device according to the present invention.

[0017] FIG. 38 This is a plan view illustrating an exemplary embodiment of a vertical memory device according to a concept conceived in the present invention.

[0018] FIG. 39 and FIG. 40 These are plan and cross-sectional views illustrating a method for manufacturing a vertical memory device according to an exemplary embodiment of the present invention.

[0019] FIG. 41 and FIG. 42 These are plan and cross-sectional views illustrating an exemplary embodiment of a vertical memory device according to the present invention.

[0020] FIG. 43 This is a plan view illustrating an exemplary embodiment of a vertical memory device according to a concept conceived in the present invention.

[0021] FIG. 44 , FIG. 45 , FIG. 46 and 47 These are plan and cross-sectional views illustrating an exemplary embodiment of a vertical memory device according to the present invention.

[0022] FIG. 48 , FIG. 49 , FIG. 50 , FIG. 51 , FIG. 52 , FIG. 53 , FIG. 54 and FIG. 55 These are plan and cross-sectional views illustrating a method for manufacturing a vertical memory device according to an exemplary embodiment of the present invention.

[0023] FIG. 56 , FIG. 57 , FIG. 58 and FIG. 59 These are plan and cross-sectional views illustrating an exemplary embodiment of a vertical memory device according to the present invention.

[0024] FIG. 60 , FIG. 61 and FIG. 62 These are plan and cross-sectional views illustrating an exemplary embodiment of a vertical memory device according to the present invention.

[0025] FIG. 63 , FIG. 64 , FIG. 65 , FIG. 66 , FIG. 67 , FIG. 68 , FIG. 69 , FIG. 70 , FIG. 71 , FIG. 72 , FIG. 73 , FIG. 74 , FIG. 75 , FIG. 76 , FIG. 77 , FIG. 78 , FIG. 79 , FIG. 80 , FIG. 81 and FIG. 82 These are plan views, cross-sectional views, and perspective views illustrating a method for manufacturing a vertical memory device according to an exemplary embodiment of the present invention. Detailed Implementation

[0026] The above and other features of the present invention will become readily understood by referring to the accompanying drawings and describing exemplary embodiments thereof in detail.

[0027] Hereinafter, the two directions that are substantially parallel to the upper surface of the substrate 100 and intersect each other may be referred to as the first direction and the second direction, respectively. Additionally, the direction that is substantially perpendicular to the upper surface of the substrate 100 may be referred to as the third direction. In an exemplary embodiment of the present invention, the first direction and the second direction may be substantially perpendicular to each other.

[0028] FIGS. 1-5 These are plan views and cross-sectional views illustrating an exemplary embodiment of a vertical memory device according to the present invention. Specifically, FIG. 1 and FIG. 2 It's a floor plan. FIG. 3 It is along FIG. 2 A cross-sectional view taken from line B-B'. FIG. 4 It is along FIG. 1 A cross-sectional view taken from line C-C'. FIG. 5 It is along FIG. 1 The cross-sectional view taken by line D-D'. FIGS. 2-5 yes FIG. 1 The graph of region X.

[0029] Reference FIGS. 1-5The vertical memory device may include a gate electrode structure comprising gate electrodes 432, 434, and 436 disposed horizontally in a first direction, each of which extends in a second direction and is stacked in a stepped shape on a first region I and a second region II of the substrate 100. The substrate 100 may include a first region I, a second region II, and a third region III. The vertical memory device may also include a channel 340 extending in the first region I of the substrate 100 at least partially through the gate electrode structure, the first conductive structure 440, the second conductive structure 450, and the third insulating pad 246 and the fourth insulating pad 248 in a first direction.

[0030] The vertical memory device may further include a first impurity region 105, a first insulating pattern 162, a second insulating pattern 164 and a third insulating pattern 225, a first gate structure 140, a first gate spacer 150, a first etch stop pattern 174, a semiconductor pattern 290, a charge storage structure 330, a fill pattern 350, a capping pattern 360, a second barrier layer 420, a first dividing pattern 180 and a second dividing pattern 370, a first common source line (CSL) 470 and a second CSL 475, a second spacer 460, a first contact plug 492, a second contact plug 494, a third contact plug 496 and a fourth contact plug 500, and a first insulating intermediate layer 190, a second insulating intermediate layer 270, a third insulating intermediate layer 280, a fourth insulating intermediate layer 380 and a fifth insulating intermediate layer 480.

[0031] Vertical memory devices may also include bit lines, vias, top wiring, etc. Bit lines may extend upward in a third direction, and multiple bit lines may be spaced apart from each other in a second direction.

[0032] The substrate 100 may include silicon, germanium, silicon-germanium, or III-V compounds such as GaP, GaAs, and GaSb. In some embodiments of the present invention, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0033] The substrate 100 may include a first region I on which memory cells are formed, a second region II at least partially surrounding the first region I, and a third region III at least partially surrounding the second region II. Contact plugs 492, 494, 496, and 500 for transferring electrical signals to the memory cells may be formed in the second region II, and circuit patterns for applying electrical signals to the memory cells through the contact plugs 492, 494, 496, and 500 may be formed in the third region III. The first region I, the second region II, and the third region III may be referred to as a cell region, an extension (e.g., a connection) region, and a peripheral circuit region, respectively.

[0034] The gate electrode structure may include at least one first gate electrode 432, a plurality of second gate electrodes 434, and at least one third gate electrode 436 that can be sequentially stacked in a first direction. The plurality of gate electrode structures may be spaced apart from each other in a third direction by a first CSL 470 and a second CSL 475 and a second spacer 460, the first CSL 470 and the second CSL 475 extending in a second direction, and the second spacer 460 covering the respective opposite sidewalls of the first CSL 470 and the second CSL 475 in the third direction.

[0035] A first insulating pattern 162 may be formed between the substrate 100 and the first gate electrode 432, a first insulating intermediate layer 190 may be formed between the first gate electrode 432 and the second gate electrode 434, and a third insulating pattern 225 may be formed between the second gate electrode 434, between the second gate electrode 434 and the third gate electrode 436, and between the third gate electrode 436. The first insulating pattern 162 and the third insulating pattern 225 may include oxides (e.g., silicon oxide).

[0036] In an exemplary embodiment of the present invention, the gate electrode structure may have a stepped shape, the length of which on the second region II of the substrate 100 in the second direction may gradually decrease from its lowest level to its highest level in the first direction; therefore, the gate electrode structure may be referred to as a stepped structure. Hereinafter, each level constituting the stepped structure may be referred to as a “step layer,” and the exposed end of a step layer that does not overlap with the upper step layer may be referred to as a “step.”

[0037] In an exemplary embodiment of the inventive concept, one of the second gate electrode 434 and the third gate electrode 436, other than the uppermost third gate electrode 436, may have a higher top surface and a thicker thickness at its end in a second direction than its other portions. Such an end may be referred to as a “conductive pad” of the gate electrode. However, the first gate electrode 432 and the uppermost third gate electrode 436 may not include a conductive pad. The conductive pad may extend a given length in a third direction.

[0038] Each of the first to third gate electrodes 432, 434, and 436 may include a gate conductive pattern and a gate barrier pattern covering at least a portion of the surface of the gate conductive pattern. The gate conductive pattern may include a metal with low resistance (e.g., tungsten, titanium, tantalum, platinum, etc.), and the gate barrier pattern may include a metal nitride (e.g., titanium nitride, tantalum nitride, etc.).

[0039] The second barrier layer 420 may cover the upper and lower surfaces and sidewalls of each of the first to third gate electrodes 432, 434 and 436, and may be further formed on the sidewalls of the second segmentation pattern 370, the outer sidewalls of the first barrier pattern 300, the sidewalls of the semiconductor pattern 290, the surface of the third insulating pattern 225, and the upper surface of the substrate 100. The second barrier layer 420 may include a metal oxide (e.g., aluminum oxide).

[0040] The first CSL 470 may extend continuously in a second direction over a first region I and a second region II of the substrate 100; however, the second CSL 475 may extend in the second direction over the first region I and the second region II and be partially cut in the second region II. In an exemplary embodiment of the inventive concept, the cut portion of the second CSL 475 may overlap with the first segmentation pattern 180 in the first direction, and a gate electrode corresponding to the cut portion of the second CSL 475 may not be segmented. Each of the first CSL 470 and the second CSL 475 may include a metal (e.g., tungsten, copper, aluminum, etc.).

[0041] A first impurity region 105 may be formed on the upper portion of the substrate 100 that is in contact with the bottom of each of the first CSL 470 and the second CSL 475. The first impurity region 105 may comprise, for example, single-crystal silicon doped with n-type impurities. Due to the formation of the first impurity region 105, the contact resistance between the substrate 100 and each of the first CSL 470 and the second CSL 475 may be reduced.

[0042] The first dividing pattern 180 may extend through the first gate electrode 432 on the second region II of the substrate 100 to divide the first gate electrode 432 in a third direction, and a plurality of first dividing patterns 180 may be formed in a third direction. The first dividing pattern 180 may include an oxide (e.g., silicon oxide).

[0043] A semiconductor pattern 290 may be formed through a first gate electrode 432 on a first region I of the substrate 100, and a channel 340 may be formed on the semiconductor pattern 290 to extend through a second gate electrode 434 and a third gate electrode 436. The channel 340 may have, for example, a cup shape, and the outer walls of the channel 340 may be covered by a charge storage structure 330, and the internal space formed by the channel 340 may be filled by a fill pattern 350. The channel 340 may comprise, for example, undoped polysilicon, and the fill pattern 350 may comprise an oxide (e.g., silicon oxide).

[0044] Multiple channels 340 may be formed in each of the second direction and the third direction. In an exemplary embodiment of the present invention, multiple channels 340 disposed in the second direction may form a channel column, multiple channels disposed in the third direction may form a channel group, and two channel groups spaced apart from each other in the third direction on opposite sides of the second CSL 475 and adjacent to the first CSL 470 may form a channel block.

[0045] The charge storage structure 330 may include a tunnel insulating pattern 320, a charge storage pattern 310, and a first barrier pattern 300 sequentially stacked from the outer wall of the channel 340 in a horizontal direction substantially parallel to the upper surface of the substrate 100. For example, the tunnel insulating pattern 320, the charge storage pattern 310, and the first barrier pattern 300 may respectively include oxides such as silicon oxide, nitrides such as silicon nitride, and oxides such as silicon oxide.

[0046] Capping pattern 360 may be formed on channel 340, charge storage structure 330 and fill pattern 350, and thus may be connected to channel 340. Capping pattern 360 may include, for example, doped polysilicon.

[0047] In an exemplary embodiment of the present invention, the second dividing pattern 370 may extend in a second direction at the central portion of a channel group in a third direction. Therefore, the second dividing pattern 370 may extend at the central portion of a channel group through the upper portion of a channel 340 included in one of the channel columns.

[0048] In an exemplary embodiment of the present invention, each of the third gate electrodes 436 may be divided in a third direction by a second dividing pattern 370.

[0049] The first gate structure 140 may include a first gate insulating pattern 110, a first gate electrode pattern 120, and a first gate mask 130 sequentially stacked on a third region III of the substrate 100. A first gate spacer 150 may be formed on a sidewall of the first gate structure 140.

[0050] A second insulating pattern 164 may be formed on a third region III of the substrate 100 to cover the first gate structure 140 and the first gate spacer 150, and a first etch stop pattern 174 may be formed on the second insulating pattern 164. The second insulating pattern 164 and the first etch stop pattern 174 may respectively comprise oxides and nitrides.

[0051] The first insulating intermediate layer 190 may cover the first gate electrode 432 on the first region I and the second region II of the substrate 100, and may cover the first etch stop pattern 174 on the third region III of the substrate 100.

[0052] In an exemplary embodiment of the present invention, a step connected to the next-most second gate electrode 434 may be formed on the upper surface of the first insulating intermediate layer 190 at the end of the first gate electrode 432 in the second direction, and a recess 200 lower than the step may be formed at the portion adjacent to the step at the boundary between the second region II and the third region III.

[0053] The first conductive structure 440 may be formed on a step on the upper surface of the first insulating intermediate layer 190 on the second region II of the substrate 100, and may have a linear shape extending upward in a third direction. The second conductive structure 450 may be formed on a recess 200 at the portion of the boundary between the second region II and the third region III of the substrate 100 to be spaced apart from the first conductive structure 440 in a second direction, and may extend upward in a third direction. Therefore, the second conductive structure 450 may not overlap with the first gate electrode 432 in the first direction, and may be formed at a height different from the height of the first conductive structure 440 (e.g., at a lower height).

[0054] However, a portion of the second conductive structure 450 may be narrower in the second direction than the other portions and may contact the third insulating pad 246 on the recess 200.

[0055] Each of the first conductive structure 440 and the second conductive structure 450 may have a structure and material substantially the same as each of the first to third gate electrodes 432, 434 and 436, and the upper and lower surfaces and sidewalls of each of the first conductive structure 440 and the second conductive structure 450 may be covered by the second barrier layer 420.

[0056] The third insulating pad 246 may be spaced apart from the end of the first gate electrode 432 in a second direction. The fourth insulating pad 248 may be formed on the third region III of the substrate 100 and has a linear shape extending upward in the third region. In an exemplary embodiment of the inventive concept, the fourth insulating pad 248 may be formed at a height different from that of the third insulating pad 246 (e.g., at a higher height). Each of the third insulating pad 246 and the fourth insulating pad 248 may include a nitride (e.g., silicon nitride).

[0057] The fourth insulating layer 260 may be formed on the third insulating pattern 225, the first conductive structure 440 and the second conductive structure 450, as well as the third insulating pad 246 and the fourth insulating pad 248. The fourth insulating layer 260 may include an oxide (e.g., silicon oxide).

[0058] The second to fifth insulating intermediate layers 270, 280, 380 and 480 may be sequentially stacked on the fourth insulating layer 260 and may include oxides (e.g., silicon oxide).

[0059] The first to third contact plugs 492, 494 and 496 can extend on the second region II of the substrate 100 through the first to fifth insulating intermediate layers 190, 270, 280, 380 and 480, the third insulating pattern 225, the fourth insulating layer 260 and the second barrier layer 420 to contact the first to third gate electrodes 432, 434 and 436 respectively, and the fourth contact plug 500 can extend on the third region III of the substrate 100 through the first to fifth insulating intermediate layers 190, 270, 280, 380 and 480, the fourth insulating layer 260, the fourth insulating pad 248, the first etch stop pattern 274, the second insulating pattern 164 and the first gate mask 130 to contact the first gate electrode pattern 120.

[0060] The second contact plug 494 can contact the conductive pads of each of the second gate electrodes 434, and the third contact plug 496 can contact each of the third gate electrodes 436 (specifically, the conductive pads of each of the third gate electrodes 436) except for the uppermost third gate electrode 436.

[0061] In an exemplary embodiment of the present invention, a first contact plug 492 may extend through a first conductive structure 440 to contact a first gate electrode 432. The first conductive structure 440 and the second conductive structure 450 may be formed at different heights and spaced apart from each other to provide electrical insulation. Therefore, the first contact plug 492 located on opposite sides of one of the first CSL 470 and the second CSL 475 in a third-party orientation will not be electrically short-circuited through the first conductive structure 440 and the second conductive structure 450.

[0062] So far, word lines extending in a second direction and bit lines extending upward in a third direction have been described; however, the inventive concept is not limited thereto. For example, the extension directions of word lines and bit lines can be interchanged. In other words, the description given for word lines can be applied to bit lines.

[0063] FIGS. 6-22 These are plan views and cross-sectional views illustrating a method for manufacturing a vertical memory device according to an exemplary embodiment of the present invention. Specifically, FIG. 6 , FIG. 8 , FIG. 11 , FIG. 14 , FIG. 16 and FIG. 19 yes FIG. 1 A planar diagram of region X, and FIG. 7 , FIGS. 9-10 , FIGS. 12-13 , FIG. 15 , FIGS. 17-18 and FIGS. 20-22 yes FIG. 1 A cross-sectional view of region X.

[0064] FIG. 7 , FIGS. 9-10 and FIGS. 12-13 These are cross-sectional views taken along line A-A' of the corresponding plan view. FIG. 15 , FIG. 17 and FIG. 20 These are cross-sectional views taken along line B-B' of the corresponding plan view, and FIG. 18 and FIGS. 21-22 These are cross-sectional views taken along line C-C' of the corresponding plan view.

[0065] Reference FIG. 6 and FIG. 7 A first gate structure 140 can be formed on a substrate 100 including a first region I, a second region II and a third region III.

[0066] The first gate structure 140 may include a first gate insulating pattern 110, a first gate electrode pattern 120, and a first gate mask 130 sequentially stacked on the substrate 100. A first gate spacer 150 may be formed on the sidewall of the first gate structure 140.

[0067] A first insulating layer and a first etch stop layer may be formed on substrate 100 to cover the first gate structure 140 and the first gate spacer 150, and may be patterned to form a first insulating pattern 162 and a first sacrificial pattern 172 sequentially stacked on a first region I and a second region II of substrate 100, and a second insulating pattern 164 and a first etch stop pattern 174 formed on a third region III of substrate 100.

[0068] In an exemplary embodiment of the present invention, in a plan view, the first insulating pattern 162 and the first sacrificial pattern 172 may have rectangular shapes on the first region I and the second region II, and the second insulating pattern 164 and the first etch stop pattern 174 may cover the first gate structure 140 and the first gate spacer 150 on the third region III of the substrate 100.

[0069] The first etch stop layer may include a nitride (e.g., silicon nitride).

[0070] The first sacrificial pattern 172 on the second region II of the substrate 100 may be partially removed to form a first opening that exposes the first insulating pattern 162, and a first dividing pattern 180 may be formed to fill the first opening.

[0071] A first insulating intermediate layer 190 may be formed on a substrate 100 to cover a first insulating pattern 162 and a second insulating pattern 164, a first sacrificial pattern 172 and a first etch stop pattern 174.

[0072] Reference FIG. 8 and FIG. 9The sacrificial layer 210 and the third insulating layer 220 can be stacked alternately and repeatedly on the first insulating intermediate layer 190. Therefore, multiple sacrificial layers 210 and multiple third insulating layers 220 can be stacked alternately in the first direction. The second etch stop layer 230 can be formed on the uppermost third insulating layer 220.

[0073] The sacrificial layer 210 may include a material (e.g., silicon nitride) that has etch selectivity relative to the third insulating layer 220, and the second etch stop layer 230 may include a material substantially the same as that of the sacrificial layer 210.

[0074] A photoresist pattern partially covering the second etch stop layer 230 can be formed on the second etch stop layer 230. Therefore, the photoresist pattern can be used as an etching mask to etch the second etch stop layer 230, the uppermost third insulating layer 220, and the uppermost sacrificial layer 210. Thus, a portion of one of the third insulating layers 220 below the uppermost sacrificial layer 210 can be partially exposed. The area of ​​the photoresist pattern can be reduced by a trimming process, and the reduced photoresist pattern can be used as an etching mask to etch the second etch stop layer 230, the uppermost third insulating layer 220, the uppermost sacrificial layer 210, an exposed third insulating layer 220, and an exposed sacrificial layer 210 below it. The trimming and etching processes can be repeated to form a molded part with a stepped shape on the first region I and the second region II of the substrate 100. The stepped shape includes multiple step layers, each of which may consist of sequentially stacked sacrificial layers 210 and third insulating layers 220. The second etch stop layer 230 may remain on the molded part. The upper surface of the first insulating intermediate layer 190 may be exposed on the second region II of the substrate 100 adjacent to the third region III of the substrate 100. Hereinafter, each layer included in the stepped structure may be referred to as a “step layer”, and the end of each layer that is not covered by the upper step layer and is exposed may be referred to as a “step”.

[0075] In an exemplary embodiment of the present invention, the area of ​​the stepped layers of the molded part can gradually decrease from the lowest level to the highest level. In a plan view, the area of ​​the lowest stepped layer of the molded part can be smaller than the area of ​​the stepped layer composed of the first insulating pattern 162 and the first sacrificial pattern 172. Therefore, the upper surface of the first insulating intermediate layer 190 can be exposed on the stepped layer composed of the first insulating pattern 162 and the first sacrificial pattern 172.

[0076] A portion of the first insulating interlayer 190 at the boundary between the second region II and the third region III of the substrate 100 may be partially removed to form a recess 200. The recess 200 can be formed by partially removing a portion of the first insulating interlayer 190 that does not overlap with the end of the first sacrificial pattern 172 in the first direction on each of the second and third regions II and III of the substrate 100. Therefore, in a plan view, the recess 200 may have a rectangular ring shape, and in a cross-sectional view, the recess 200 may extend in each of the second and third directions. FIG. 8 and FIG. 9 These are the plan view and cross-sectional view of region X, respectively, so the recess 200 is shown as extending upwards in the third direction. The shape of the element will be shown below with respect to region X.

[0077] Reference FIG. 10 A portion of the third insulating layer 220 in each step of each step layer, which consists of sequentially stacked sacrificial layers 210 and third insulating layers 220, can be removed to expose the sacrificial layer 210.

[0078] A portion of the third insulating layer 220 can be removed by, for example, a wet etching process, and the sidewall of the remaining portion of the third insulating layer 220 of the first step layer can be closer to the first region I of the substrate 100 than the sidewall of the end of the sacrificial layer 210 of the second step layer directly on the first step layer.

[0079] During the etching process, the exposed upper portion of the first insulating intermediate layer 190 on the stepped layer composed of the first insulating pattern 162 and the first sacrificial pattern 172, the recess 200 at the boundary between the second region II and the third region III of the substrate 100, and the upper portion of the first insulating intermediate layer 190 on the third region III of the substrate 100 can also be removed by a given thickness. Therefore, the step of the first insulating intermediate layer 190 on the end of the first sacrificial pattern 172 and the step of the first insulating intermediate layer 190 in the recess 200 at the boundary between the second region II and the third region III of the substrate 100 can also be formed below the lowest step of the molded part.

[0080] Reference FIG. 11 and FIG. 12 An insulating pad layer may be formed on a first region I, a second region II, and a third region III of a substrate 100 having a molding and a first insulating intermediate layer 190 thereon, and may be partially removed to form a first insulating pad 242, a second insulating pad 244, a third insulating pad 246, a fourth insulating pad 248, and a fifth insulating pad 250.

[0081] In exemplary embodiments of the present invention, the insulating pad layer may comprise a material substantially the same as that of the sacrificial layer 210; however, the etch rate of the insulating pad layer may differ from that of the sacrificial layer 210. For example, the insulating pad layer can be formed by depositing a nitride (e.g., silicon nitride) and performing an ion implantation or plasma treatment process thereon to alter its etch rate. Alternatively, the deposition rate and / or process gas may be adjusted during the deposition process such that the insulating pad layer comprising a material substantially the same as that of the sacrificial layer 210 may have an etch rate different from that of the sacrificial layer 210. In exemplary embodiments of the present invention, the etch rate of the insulating pad layer may be greater than that of the sacrificial layer 210.

[0082] After the insulating pad layer is formed, the portion of the insulating pad layer adjacent to the sidewalls of the molded part and the steps of the first insulating intermediate layer 190 can be removed, such that the first to fifth insulating pads 242, 244, 246, 248, and 250 can be formed spaced apart from the sidewalls of the molded part and the steps of the first insulating intermediate layer 190. The first insulating pad 242 can be formed on a portion of the sacrificial layer 210 of each step of the molded part, the second insulating pad 244 can be formed on the step of the first insulating intermediate layer 190 at the end of the first sacrificial pattern 172, the third insulating pad 246 can be formed on the recess 200, the fourth insulating pad 248 can be formed on the third region III of the substrate 100, and the fifth insulating pad 250 can be formed on the second etch stop layer 230. In an exemplary embodiment of the inventive concept, each of the first to fifth insulating pads 242, 244, 246, 248, and 250 can have a linear shape extending upward in a third direction.

[0083] Reference FIG. 13 A fourth insulating layer 260 can be formed on the substrate 100 in first region I, second region II, and third region III, which have a molding element, a second etch stop layer 230, a first insulating intermediate layer 190, and first to fifth insulating pads 242, 244, 246, 248, and 250. A second insulating intermediate layer 270 can be formed on the fourth insulating layer 260, and the upper part of the second insulating intermediate layer 270 can be planarized until the uppermost third insulating layer 220 is exposed. Therefore, the second etch stop layer 230 and the fifth insulating pad 250 can be removed.

[0084] The fourth insulating layer 260 can be formed, for example, by an atomic layer deposition (ALD) process.

[0085] Reference FIG. 14 and FIG. 15A third insulating intermediate layer 280 can be formed on the second insulating intermediate layer 270, and the third insulating intermediate layer 280, the third insulating layer 220 and the sacrificial layer 210 can be etched by an etching process to form a channel hole through which the upper surface of the substrate 100 can be exposed, and a pillar structure filling the channel hole can be formed as follows.

[0086] The upper surface of the substrate 100 exposed through the channel via can be used as a seed to perform a selective epitaxial growth (SEG) process to form a semiconductor pattern 290 that partially fills the channel via. The upper surface of the semiconductor pattern 290 may have a height between the height of the upper surface and the height of the lower surface of the first insulating intermediate layer 190, respectively. In some cases, the formation of the semiconductor pattern 290 may be skipped.

[0087] A first barrier layer, a charge storage layer, a tunnel insulating layer, and a first spacer layer may be sequentially formed on the sidewalls of the channel via, the upper surface of the semiconductor pattern 290, and the upper surface of the third insulating intermediate layer 280. The first spacer layer may be anisotropically etched to form first spacers on each sidewall of the channel via, and the first spacer may be used as an etching mask to etch the tunnel insulating layer, the charge storage layer, and the first barrier layer to form a cup-shaped tunnel insulating pattern 320, a charge storage pattern 310, and a first barrier pattern 300, respectively. The bottom of the cup-shaped pattern is open on the upper surface of the semiconductor pattern 290 and on each sidewall of the channel via. The upper part of the semiconductor pattern 290 may also be partially removed. The tunnel insulating pattern 320, the charge storage pattern 310, and the first barrier pattern 300 may form a charge storage structure 330.

[0088] The first spacer layer may include a nitride (e.g., silicon nitride).

[0089] After removing the first spacer, a channel layer can be formed on the exposed semiconductor pattern 290, tunnel insulating pattern 320, and third insulating intermediate layer 280, and a fill layer can be formed on the channel layer to fill the remaining portion of the channel via. The fill layer and channel layer can be planarized until the upper surface of the third insulating intermediate layer 280 is exposed, so that a fill pattern 350 can be formed in each channel via, and the channel layer can be transformed into a channel 340.

[0090] In an exemplary embodiment of the present invention, a plurality of channels 340 disposed in a second direction may form a channel column, a plurality of channel columns disposed in a third direction may form a channel group, and a plurality of channel groups disposed in a third direction (e.g., two channel groups) may form a channel block.

[0091] The upper part of the structure, including the filling pattern 350, the channel 340 and the charge storage structure 330, can be removed to form a groove, and a capping pattern 360 can be formed in the groove to form a column structure.

[0092] A second segmentation pattern 370 may be formed on a portion of the second region II and the first region I of the substrate 100 through one of the sacrificial layers 210 and one of the third insulating layers 220.

[0093] The second segmentation pattern 370 can be formed by partially etching one of the third insulating intermediate layer 280, the third insulating layer 220 and the sacrificial layer 210 to form a second opening therethrough, and by filling the second opening with an insulating material.

[0094] In an exemplary embodiment of the present invention, the second dividing pattern 370 may extend in a second direction at the central portion of a channel group in a third direction. Therefore, the second dividing pattern 370 may extend through the upper portion of the channel 340 of the channel column disposed at the central portion of each channel group.

[0095] In an exemplary embodiment of the present invention, the second dividing pattern 370 may extend not only through the upper portion of the channel 340, but also through one of the sacrificial layers 210 at the two upper horizontal levels and one of the third insulating layers 220 at the two upper horizontal levels, and also partially through one of the third insulating layers 220 at the level below the two upper horizontal levels. The second dividing pattern 370 may extend in a second direction on a first region I of the substrate 100, and may also extend in a second direction on a second region II of the substrate 100 through the two upper stepped layers of the molded part. Therefore, each of the sacrificial layers 210 at the two upper horizontal levels may be divided in a third direction by the second dividing pattern 370.

[0096] Reference FIGS. 16-18 A fourth insulating intermediate layer 380 may be formed on the third insulating intermediate layer 280 and the capping pattern 360, and a third opening 390 and a fourth opening 400 may be formed through the first to fourth insulating intermediate layers 190, 270, 280 and 380, the third insulating layer 220, the sacrificial layer 210, the first insulating pattern 162 and the first sacrificial pattern 172 to expose the upper surface of the substrate 100.

[0097] In an exemplary embodiment of the present invention, each of the third opening 390 and the fourth opening 400 may extend in a second direction between adjacent channel groups on the first region I and the second region II of the substrate 100, and the third opening 390 and the fourth opening 400 may be formed alternately and repeatedly in a third direction. In other words, a channel group may be formed between the third opening 390 and the fourth opening 400, and two channel groups at opposite sides of the fourth opening 400 may form a channel block. A second dividing pattern 370 may be disposed between a portion of the second region II and the third opening 390 and the fourth opening 400 in the first region I.

[0098] When the third opening 390 and the fourth opening 400 are formed, the sacrificial layer 210 can be divided into second sacrificial patterns that can extend in the second direction, and the third insulating layer 220 can be divided into third insulating patterns 225 that can extend in the second direction.

[0099] In an exemplary embodiment of the present invention, the third opening 390 may extend continuously in a second direction on the first region I and the second region II of the substrate 100, while the fourth opening 400 may be partially cut in the second region II of the substrate 100. Therefore, the second sacrificial patterns, each extending in the second direction, at opposite sides of the fourth opening 400, may be partially connected to each other on the second region II of the substrate 100. In an exemplary embodiment of the present invention, the cut portion of the fourth opening 400 (in other words, the connecting portion for connecting the second sacrificial patterns to each other) may overlap with the first dividing pattern 180 in the first direction. In other words, the first dividing pattern 180 may be disposed between the ends of the fourth opening 400 at the cut portion of the fourth opening 400.

[0100] The second sacrificial patterns exposed through the third opening 390 and the fourth opening 400 can be removed, for example, by a wet etching process, to form a first gap 410 between the third insulating patterns 225 at each level and between the first insulating pattern 162 and the first insulating interlayer 190, and the first insulating pad 242 at the end of each second sacrificial pattern can also be removed. A portion of the sidewall of the second dividing pattern 370, a portion of the outer sidewall of the first blocking pattern 300, and a portion of the sidewall of the semiconductor pattern 290 can be exposed through the first gap 410.

[0101] The second insulating pad 244 and the third insulating pad 246 may also be removed to form the second gap 412 and the third gap 414, respectively. In an exemplary embodiment of the inventive concept, the second gap 412 may have a linear shape extending upward in a third direction, and the third gap 414 may be spaced apart from the second gap 412 in a second direction and extend upward in a third direction. A portion of the third gap 414 may have a width in the second direction that is smaller than the width of other portions of it in the second direction. For example, the portion of the third insulating pad 246 furthest from the end of the lowermost gate electrode 432 in the second direction may not be removed, and thus this portion is retained when the third insulating pad 246 is removed by a wet etching process with isotropic etching characteristics.

[0102] Reference FIGS. 19-21A second barrier layer 420 may be formed on the exposed sidewalls of the second segmentation pattern 370, the outer sidewalls of the first barrier pattern 300, the sidewalls of the semiconductor pattern 290, the inner walls of the first to third gaps 410, 412 and 414, the surface of the third insulating pattern 225, the upper surface of the substrate 100 and the upper surface of the fourth insulating intermediate layer 380. A gate conductive layer may be formed on the second barrier layer 420 to fill the first to third gaps 410, 412 and 414. A gate barrier layer may also be formed between the second barrier layer 420 and the gate conductive layer.

[0103] The gate conductive layer can be partially removed to form a gate conductive pattern in the first gap 410, and if a gate barrier layer has been formed, it can also be partially removed to form a gate barrier pattern. The gate conductive pattern and the gate barrier pattern can form a gate electrode. A first conductive structure 440 and a second conductive structure 450 can be formed in the second gap 412 and the third gap 414, respectively. The first conductive structure 440 and the second conductive structure 450 can extend longitudinally in a second direction.

[0104] In an exemplary embodiment of the present invention, the gate electrodes may extend in a second direction, and a plurality of gate electrodes may be formed to be spaced apart from each other in a first direction. Additionally, the plurality of gate electrodes may be formed to be spaced apart from each other in a third direction. In other words, the plurality of gate electrodes may be spaced apart from each other in a third direction through a third opening 390. Furthermore, the plurality of gate electrodes may be spaced apart from each other in a third direction through a fourth opening 400; however, adjacent gate electrodes among the plurality of gate electrodes on opposite sides of the fourth opening 400 in the third direction may be connected to each other on a second region II of the substrate 100 through a connection portion overlapping with the first dividing pattern 180. The top two gate electrodes among the gate electrodes extending in the second direction on the second region II of the substrate 100 may be further divided in a third direction by a second dividing pattern 370.

[0105] The gate electrode may include a first gate electrode 432, a second gate electrode 434, and a third gate electrode 436 sequentially stacked in a first direction. In an exemplary embodiment of the inventive concept, the first gate electrode 432 may be formed at the lowest level, the third gate electrode 436 may be formed at the two upper levels, and the second gate electrode 434 may be formed at multiple levels between the first gate electrode 432 and the third gate electrode 436.

[0106] The gate electrode can be formed by replacing the second sacrificial pattern stacked in a stepped shape, thus the gate electrodes can also be stacked to form a stepped structure. The end of each of the gate electrodes, except for the first gate electrode 432 and the uppermost third gate electrode 436, can be formed by replacing both the second sacrificial pattern and the first insulating pad 242, thus the end can have a higher upper surface and a greater thickness than the other portions of the gate electrode. Hereinafter, the end of each of the gate electrodes with a thickness greater than the other portions of the gate electrode can be referred to as a conductive pad.

[0107] In an exemplary embodiment of the present invention, the first conductive structure 440 and the second conductive structure 450 may be formed at different heights and spaced apart from each other in a second direction. In this case, the first conductive structure 440 and the second conductive structure 450 are electrically insulated from each other.

[0108] Reference FIG. 22 Impurities can be injected into the upper portion of each exposed substrate 100 through the third opening 390 and the fourth opening 400 to form a first impurity region 105.

[0109] The second spacer layer may be formed on the upper surface of the substrate 100 exposed through the third opening 390 and the fourth opening 400, the sidewalls of the third opening 390 and the fourth opening 400, and the upper surface of the fourth insulating intermediate layer 380, and may be anisotropically etched to form a second spacer 460 on the sidewalls of each of the third opening 390 and the fourth opening 400.

[0110] A first common source line (CSL) 470 and a second CSL 475 can be formed on the first impurity region 105 (refer to...). FIG. 2 The third opening 390 and the fourth opening 400 are respectively filled. A portion of the second barrier layer 420 on the upper surface of the fourth insulating intermediate layer 380 can be removed, and each of the first CSL 470 and the second CSL 475 can access the upper surface of the first impurity region 105.

[0111] Refer again FIGS. 1-5A fifth insulating intermediate layer 480 can be formed on the fourth insulating intermediate layer 380, the first CSL 470 and the second CSL 475, the second spacer 460 and the second barrier layer 420. First to third contact plugs 492, 494 and 496 can be formed on the second region II of the substrate 100 through the first to fifth insulating intermediate layers 190, 270, 280, 380 and 480, the third insulating pattern 225, the fourth insulating layer 260 and the second barrier layer 420 to contact the upper surfaces of the first to third gate electrodes 432, 434 and 436, respectively. Additionally, a fourth contact plug 500 can be formed on the third region III of the substrate 100 through the first to fifth insulating intermediate layers 190, 270, 280, 380 and 480, the fourth insulating layer 260, the fourth insulating pad 248, the first etch stop pattern 174, the second insulating pattern 164 and the first gate mask 130 to contact the first gate electrode pattern 120.

[0112] The second contact plug 494 can contact the conductive pads of each of the second gate electrodes 434, and the third contact plug 496 can contact the conductive pads of each of the third gate electrodes 436 except for the uppermost third gate electrode 436. In an exemplary embodiment of the inventive concept, the first contact plug 492 can extend through the first conductive structure 440 to contact the first gate electrode 432. The first conductive structure 440 and the second conductive structure 450 are electrically insulated from each other, so that the first contact plugs 492 on the opposite sides of the first CSL 470 and the second CSL 475 will not be electrically short-circuited to each other through the first conductive structure 440 and the second conductive structure 450.

[0113] The vertical memory device can be manufactured using the above process. As described above, the second to fourth insulating pads 244, 246, and 248 do not need to be removed, thus avoiding the cost and time required for their removal. Furthermore, even if the second insulating pad 244 and the third insulating pad 246 are replaced by the first conductive structure 440 and the second conductive structure 450, the first conductive structure 440 and the second conductive structure 450 can still be electrically insulated from each other, so that the separated first CSL 470 and second CSL 475 will not be electrically short-circuited to each other due to the first contact plug 492.

[0114] FIGS. 23-28 These are plan and cross-sectional views illustrating a method for manufacturing a vertical memory device according to a comparative example. Specifically, FIG. 25 and FIG. 27 It's a floor plan. FIG. 23 and FIG. 24 These are cross-sectional views taken along line A-A' of the corresponding plan view, and FIG. 26 and FIG. 28 These are cross-sectional views taken along line B-B' of the corresponding plan view. This method may include references. FIGS. 6-22and FIGS. 1-5 The processes shown are substantially the same or similar, so their repeated descriptions are omitted in this document.

[0115] Reference FIG. 23 Executable and reference FIGS. 6-9 The processes shown are substantially the same or similar. However, the recess 200 may not be formed on the first insulating intermediate layer 190.

[0116] Reference FIG. 24 Executable and reference FIGS. 10-12 The processes shown are substantially the same or similar. However, the second to fourth insulating pads 244, 246 and 248 are not separated, but connected to each other, so that a sixth insulating pad 249 can be formed on the second region II and the third region III of the substrate 100.

[0117] Reference FIG. 25 and FIG. 26 Executable and reference FIGS. 13-17 The processes shown are substantially the same or similar. However, instead of forming the second gap 412 and the third gap 414 which can be formed at different heights to be separate from each other, only the fourth gap 415 can be formed at a given height.

[0118] Reference FIG. 27 and FIG. 28 Executable and reference FIGS. 18-22 and FIGS. 1-5 The processes shown are substantially the same or similar. However, instead of forming the first conductive structure 440 and the second conductive structure 450, which can be formed at different heights to be separate from each other, a third conductive structure 445 can be formed at a given height.

[0119] Therefore, the first contact plug 492, which extends through the third conductive structure 445 at the opposite side of the first CSL 470 or the second CSL 475 to contact the first gate electrode 432 that is separated from each other, can be electrically short-circuited because the first contact plug 492 commonly contacts the third conductive structure 445.

[0120] However, in FIGS. 1-5 In the vertical memory device, the first conductive structure 440 and the second conductive structure 450 can be separated from each other, and the first conductive structure 440 through which the first contact plug 492 extends can be separated at the opposite side of the first CSL 470 or the second CSL 475 so that no electrical short circuit occurs.

[0121] FIGS. 29-31 These are plan views and cross-sectional views illustrating an exemplary embodiment of a vertical memory device according to the present invention. Specifically, FIG. 29 It's a floor plan. FIG. 30It is along FIG. 29 The cross-sectional view taken by line B-B', and FIG. 31 It is along FIG. 29 A cross-sectional view taken along line D-D'. Aside from some components, this vertical memory device can be compared with a reference. FIGS. 1-5 The vertical memory devices shown are substantially the same or similar, therefore repeated descriptions of the same or similar elements are omitted in this document.

[0122] Reference FIGS. 29-31 A protrusion 205 may be formed on the upper surface of the first insulating intermediate layer 190 at the boundary between the second region II and the third region III of the substrate 100, and a fourth conductive structure 452 having a linear shape extending upward in the third region may be formed on the protrusion 205 to be spaced apart from the first conductive structure 440 in the second direction. However, a portion of the fourth conductive structure 452 may be narrower in the second direction than the width of its other portions in the second direction, and may contact the seventh insulating pad 247 on the protrusion 205.

[0123] In an exemplary embodiment of the present invention, the first contact plug 492 may extend through the first conductive structure 440 to contact the first gate electrode 432. The first conductive structure 440 and the fourth conductive structure 452 may be formed at different heights and spaced apart from each other to be electrically insulated from each other, so that the first contact plug 492 at the opposite sides of the first CSL 470 and the second CSL 475 in the third direction will not be electrically short-circuited through the first conductive structure 440 and the fourth conductive structure 452.

[0124] FIGS. 32-35 These are plan views and cross-sectional views illustrating a method for manufacturing a vertical memory device according to an exemplary embodiment of the present invention. Specifically, FIG. 34 It's a floor plan. FIG. 32 and FIG. 33 These are cross-sectional views taken along line A-A' of the corresponding plan view, and FIG. 35 This is a cross-sectional view taken along line B-B' of the corresponding plan view. This method may include references FIGS. 6-22 and FIGS. 1-5 The processes shown are substantially the same or similar, so their repeated descriptions are omitted in this document.

[0125] Reference FIG. 32 Executable and FIGS. 6-9 The processes are substantially the same or similar. However, a protrusion 205 may be formed at the boundary between the second region II and the third region III of the substrate 100 instead of a recess 200. The protrusion 205 may extend longitudinally in the third direction.

[0126] Reference FIG. 33 Executable and FIGS. 10-12The process is substantially the same or similar. However, a seventh insulating pad 247 may be formed on the protrusion 205 instead of the third insulating pad 246 on the recess 200. The seventh insulating pad 247 may be formed at a height different from (e.g., higher) than the second insulating pad 244, and may be spaced apart from the second insulating pad 244 in a second direction.

[0127] Reference FIG. 34 and FIG. 35 Executable and FIGS. 13-18 The process is substantially the same or similar. However, a fifth gap 416 may be formed on the protrusion 205 instead of a third gap 414 on the recess 200. The fifth gap 416 may be spaced apart from the second gap 412 in a second direction and may extend upward in a third direction. A portion of the fifth gap 416 may be narrower in the second direction than the other portions thereof, and a seventh insulating pad 247 may remain adjacent to this portion of the fifth gap 416.

[0128] Reference FIGS. 29-31 Executable and FIGS. 19-22 and FIGS. 1-5 The processes are substantially the same or similar. However, instead of filling the second gap 412, the fourth conductive structure 452 can be formed to fill the fifth gap 416.

[0129] FIG. 36 and FIG. 37 This is a cross-sectional view illustrating an exemplary embodiment of a vertical memory device according to a concept conceived in accordance with the present invention. Specifically, FIG. 36 It is a cross-sectional view taken along line B-B' of the corresponding plan view, and FIG. 37 This is a cross-sectional view taken along line D-D' of the corresponding plan view. Apart from some components, this vertical memory device can be compared with a reference... FIGS. 1-5 The vertical memory devices shown are substantially the same or similar. Therefore, the same reference numerals may refer to the same elements, and repeated descriptions thereof are omitted herein.

[0130] Reference FIG. 36 and FIG. 37 A recess 200 and a protrusion 205 may be formed adjacent to each other at the boundary between the second region II and the third region III of the substrate 100, and a second conductive structure 450 and a fourth conductive structure 452 may be formed on the recess 200 and the protrusion 205, respectively. A portion of the fourth conductive structure 452 may have a width in the second direction that is smaller than the width of its other portions in the second direction, and may contact the seventh insulating pad 247 on the protrusion 205.

[0131] exist FIG. 36 and FIG. 37In this invention, recesses 200 and protrusions 205 are formed on the second region II and the third region III of the substrate 100; however, the invention is not limited thereto. For example, recesses 200 and protrusions 205 may be formed on the third region III and the second region II, respectively. Alternatively, one of the recesses 200 and protrusions 205 may be formed at the boundary between the second region II and the third region III of the substrate 100, and the other of the recesses 200 and protrusions 205 may be formed on either the second region II or the third region III of the substrate 100. For example, a recess 200 may be located in both the second region II and the third region III, and a protrusion 205 may be located in the third region III.

[0132] In an exemplary embodiment of the present invention, the first contact plug 492 may extend through the first conductive structure 440 to contact the first gate electrode 432. The first conductive structure 440 and the second conductive structure 450 are formed at different heights and spaced apart from each other, so that the first contact plug 492 at the opposite sides of the first CSL 470 and the second CSL 475 in the third direction will not be electrically short-circuited via the first conductive structure 440 and the second conductive structure 450.

[0133] FIG. 38 This is a plan view illustrating an exemplary vertical memory device according to a concept of the present invention. Apart from some components, this vertical memory device is comparable to a reference numeral. FIG. 27 and FIG. 28 The vertical memory devices shown are substantially the same or similar. Therefore, the same reference numerals may refer to the same elements, and repeated descriptions thereof are omitted herein.

[0134] Reference FIG. 38 The third conductive structure 445 extending in the third direction on the second region II and the third region III of the substrate 100 can be divided in the third direction on the second region II of the substrate 100 by the first CSL 470 and the second CSL 475 in the third opening 390 and the fourth opening 400 respectively, and by the second spacer 460 on its sidewall, and can be divided in the third direction on the third region III of the substrate 100 by the first cutting pattern 510. Therefore, the third conductive structure 445 at the opposite side of the first CSL 470 or the second CSL 475 can be separated from each other, so the first contact plugs 492 extending through the separated third conductive structures 445 will not short-circuit with each other.

[0135] In an exemplary embodiment of the present invention, the first cut pattern 510 may contact the ends of each of the first CSL 470 and the second CSL 475 in the second direction on the third region III of the substrate 100, and may extend a given length in the second direction. Therefore, a plurality of first cut patterns 510 may be formed to be spaced apart from each other in the second direction. The first cut pattern 510 may include an oxide (e.g., silicon oxide).

[0136] FIG. 39 and FIG. 40 These are plan views and cross-sectional views illustrating a method for manufacturing a vertical memory device according to an exemplary embodiment of the present invention. Specifically, FIG. 39 It is a floor plan, and FIG. 40 It is along FIG. 39 A cross-sectional view taken from line A-A'. This method may include references FIGS. 23-28 The processes shown are substantially the same or similar, therefore their repeated descriptions are omitted in this article.

[0137] Reference FIG. 39 and FIG. 40 Executable and FIG. 23 and FIG. 24 The processes are substantially the same or similar, and can be performed with... FIGS. 13-15 The processes are substantially the same or similar.

[0138] A first cutting pattern 510 may be formed on the third region III of the substrate 100 adjacent to the second region II of the substrate 100, through the first to third insulating intermediate layers 190, 270 and 280, the fourth insulating layer 260 and the sixth insulating pad 249 to contact the upper surface of the substrate 100.

[0139] In an exemplary embodiment of the inventive concept, a first cutting pattern 510 may be formed at a location that at least partially overlaps with the ends of each of the subsequently formed third opening 390 and fourth opening 400 in a second direction. Thus, a plurality of first cutting patterns 510 may be formed to be spaced apart from each other in a third direction, and each first cutting pattern 510 may extend a given length in the second direction.

[0140] A portion of the sixth insulating pad 249, which may extend upward on the second region II and the third region III of the substrate 100, on the third region III of the substrate may be removed by the first cutting pattern 510. Therefore, the sixth insulating pad 249 may include an opening.

[0141] Refer again FIG. 38 Executable and FIGS. 25-28The manufacturing processes are substantially the same or similar to those used to complete the vertical memory device. However, the sixth insulating pad 249 extending in the third direction on the second region II and the third region III of the substrate 100 can be divided in the third direction by the third opening 390 and the fourth opening 400 and the first cutting pattern 510.

[0142] FIG. 41 and FIG. 42 These are plan views and cross-sectional views illustrating an exemplary embodiment of a vertical memory device according to the present invention. Specifically, FIG. 41 It is a floor plan, and FIG. 42 It is along FIG. 41 A cross-sectional view taken along line B-B'. Aside from some components, this vertical memory device can be compared with a reference... FIG. 38 The vertical memory devices shown are substantially the same or similar. Therefore, the same reference numerals may refer to the same elements, and repeated descriptions thereof are omitted herein.

[0143] Reference FIG. 41 and FIG. 42 A fifth conductive structure 447 may be formed at the boundary between the second region II and the third region III of the substrate, rather than the third conductive structure 445 on the second region II of the substrate 100.

[0144] The fifth conductive structure 447 can be divided in the third direction by the first CSL 470 and the second CSL 475 and the second spacer 460 in the third opening 390 and the fourth opening 400, respectively, and the fifth conductive structure 447 may not be formed on the third region III of the substrate 100 due to the second cut pattern 520 on the third region III of the substrate 100. Therefore, the fifth conductive structures 447 on the opposite sides of the first CSL 470 or the second CSL 475 can be separated from each other. Therefore, the first contact plug 492 extending through the separated fifth conductive structures 447 to contact the first gate electrode 432 will not be electrically short-circuited.

[0145] In an exemplary embodiment of the present invention, the second cut pattern 520 may extend upward in a third direction on a third region III of the substrate 100 and may jointly contact the ends of the first CSL 470 and the second CSL 475 in the second direction and the sidewall of the fifth conductive structure 447 in the second direction.

[0146] FIG. 43 This is a plan view illustrating an exemplary embodiment of a vertical memory device according to a concept of the present invention. This vertical memory device may include... FIG. 38 The first cut pattern 510 shown and FIG. 41 and FIG. 42The second cut pattern 520 shown is both. Therefore, the fifth conductive structure 447 can be formed on the second region II of the substrate 100.

[0147] FIGS. 44-47 These are plan views and cross-sectional views illustrating an exemplary embodiment of a vertical memory device according to the present invention. Specifically, FIG. 44 It's a floor plan. FIG. 45 It is along FIG. 44 A cross-sectional view taken from line B-B'. FIG. 46 It is along FIG. 44 The cross-sectional view taken by line E-E', and FIG. 47 It is along FIG. 44 A cross-sectional view taken along line F-F'. Aside from some components, this vertical memory device can be compared with a reference. FIGS. 1-5 The vertical memory devices shown are substantially the same or similar. Therefore, the same reference numerals may refer to the same elements, and repeated descriptions thereof are omitted herein.

[0148] Reference FIGS. 44-47 The second CSL 475 may extend on a portion of the second region II and the first region I of the substrate 100, and the end of the second CSL 475 in the second direction may overlap with the first segmentation pattern 180 in the first direction.

[0149] Therefore, in the wet etching process used to remove the first sacrificial pattern 172 and the second sacrificial pattern 215, which will be described later, a portion of the second sacrificial pattern 215 located between the adjacent first CSL 470 in the third-direction direction in the area where the second CSL 475 is not formed, along with the first to third insulating pads 242, 244 and 246 thereon, may not be removed, but rather retained.

[0150] The thickness of each of the conductive pads in the second gate electrode 434 and the third gate electrode 436 (excluding the uppermost third gate electrode) may be greater than the thickness of the others, and may protrude relative to the others in a third-order direction. Therefore, the first sacrificial pattern 172 and the second sacrificial pattern 215 may be placed below the conductive pads of the respective gate electrodes.

[0151] In an exemplary embodiment of the present invention, each of the second contact plugs 494 may extend through the conductive pad of the second gate electrode 434 to reach the upper surface of the substrate 100. For example, in FIG. 45 and FIG. 47In this context, each of the second contact plugs 494 also extends through the alternately stacked third insulating pattern 225 and second sacrificial pattern 215 and first sacrificial pattern 172. However, the inventive concept is not limited thereto, and each of the second contact plugs 494 may extend through the conductive pad corresponding to the second gate electrode 434 to a given height relative to the upper surface of the substrate 100.

[0152] FIGS. 48-55 These are plan views and cross-sectional views illustrating a method for manufacturing a vertical memory device according to an exemplary embodiment of the present invention. Specifically, FIG. 48 and FIG. 52 It is a floor plan, and FIGS. 49-51 and FIGS. 53-55 It is a cross-sectional view. FIG. 49 and FIG. 53 It is a cross-sectional view taken along line B-B' of the corresponding plan view. FIG. 50 and FIG. 54 It is a cross-sectional view taken along line E-E' of the corresponding plan view, and FIG. 51 and FIG. 55 This is a cross-sectional view taken along line F-F' of the corresponding plan view. This method may include references FIGS. 6-22 and FIGS. 1-5 The processes shown are substantially the same or similar, therefore their repeated descriptions are omitted in this article.

[0153] Reference FIGS. 48-51 Executable and FIGS. 6-18 The processes are substantially the same or similar. However, the fourth opening 400 may extend over a portion of the second region II and the first region I of the substrate 100, and the end of the fourth opening 400 in the second direction may overlap with the first dividing pattern 180 in the first direction. For example, the first dividing pattern 180 may overlap with the end of the fourth opening 400 and the first insulating pad 242.

[0154] Therefore, for example, when performing a wet etching process for removing the second sacrificial pattern 215 and the first sacrificial pattern 172 formed by dividing the sacrificial layer 210 via the third opening 390 and the fourth opening 400, portions of the first sacrificial pattern 172 and the second sacrificial pattern 215 located between the adjacent third openings 390 in the third-direction upward direction in the area where the fourth opening 400 is not formed, and where the first to third insulating pads 242, 244, and 246 are disposed, may not be completely removed, but may be partially retained. However, the first insulating pad 242, having a different etching rate (e.g., a relatively high etching rate compared to its other portions), may be formed on the ends of the second sacrificial pattern 215 in the second direction at various horizontal levels, and thus can be etched at a relatively fast rate so that the first gap 410 may protrude in the third-direction upward direction, as... FIG. 49 As shown.

[0155] Reference FIGS. 52-55 Executable and FIGS. 19-21 The processes are substantially the same or similar. However, the thickness of the conductive pad of each of the second gate electrode 434 and the third gate electrode 436 (excluding the uppermost third gate electrode) may be greater than the thickness of its other portions, and may protrude relative to its other portions in a third-order direction. Therefore, the first sacrificial pattern 172 and the second sacrificial pattern 215 may be located below the conductive pad of each gate electrode.

[0156] Refer again FIGS. 44-47 Executable and FIG. 22 and FIGS. 1-5 The processes are substantially the same or similar to those used to manufacture vertical memory devices.

[0157] The first contact plug 492 can extend through the first conductive structure 440, which includes metal, to contact the first gate electrode 432, thus allowing for a longer process time to form the first contact plug 492. Additionally, when the first contact plug 492 is formed together with second contact plugs 494 at different levels, some of the second contact plugs 494 can extend through a corresponding one of the second gate electrodes 434 to reach one of the lower second gate electrodes 434.

[0158] However, in an exemplary embodiment of the present invention, the third insulating pattern 225 and the second sacrificial pattern 215 are stacked alternately under the conductive pad of each second gate electrode 434, so that some of the second contact plugs 494 can extend through the corresponding second gate electrode 434 to reach the area below.

[0159] FIGS. 56-59 These are plan views and cross-sectional views illustrating an exemplary embodiment of a vertical memory device according to the present invention. Specifically, FIG. 56 It's a floor plan. FIG. 57 It is along FIG. 56 A cross-sectional view taken from line B-B'. FIG. 58 It is along FIG. 56 The cross-sectional view taken by line E-E', and FIG. 59 It is along FIG. 56 A cross-sectional view taken along line F-F'. Aside from some components, this vertical memory device can be used with... FIGS. 44-47 The vertical memory devices shown are substantially the same or similar. Therefore, the same reference numerals may refer to the same elements, and their repeated descriptions are omitted herein.

[0160] This vertical memory device can have a peripheral upper cell (COP) structure. In other words, the circuit pattern for driving the memory cell can be formed not only on the peripheral circuit region but also below the memory cell. Therefore, the region where the lower circuit pattern can be formed can be called the lower circuit region.

[0161] Reference FIGS. 56-59 A lower circuit pattern can be formed on the lower substrate 600, and a first lower insulating intermediate layer 670 and a second lower insulating intermediate layer 730 can be formed on the lower substrate 600 to cover the lower circuit pattern.

[0162] The lower substrate 600 may include a field region and an active region having an isolation pattern 610 formed thereon. The lower circuit pattern may include, for example, a transistor, a lower contact plug, a lower wiring, a lower via, etc. For example, the transistor may include a second gate structure 650 on the lower substrate 600 and a second impurity region 605 above the active region adjacent to the second gate structure 650. The second gate structure 650 may include a second gate insulating pattern 620, a second gate electrode pattern 630, and a second gate mask 640 sequentially stacked on the lower substrate 600.

[0163] A first lower insulating interlayer 670 may be formed on a lower substrate 600 to cover the transistor, and a lower contact plug 660 may extend through the first lower insulating interlayer 670 to contact the second impurity region 605 or the second gate electrode pattern 630. A first lower wiring 680 may be formed on the first lower insulating interlayer 670 to contact the upper surface of the lower contact plug 660. A first lower via 690, a second lower wiring 700, a second lower via 710, and a third lower wiring 720 may be sequentially stacked on the first lower wiring 680. In an exemplary embodiment of the inventive concept, a plurality of third lower wirings 720 may be formed in a third direction. The plurality of third lower wirings 720 may be spaced apart from each other along the third direction. A second lower insulating interlayer 730 may be formed on the first lower insulating interlayer 670 to cover the first to third lower wirings 680, 700, and 720, as well as the first lower via 690 and the second lower via 710.

[0164] In an exemplary embodiment of the present invention, each of the first contact plug 492 and the second contact plug 494 may extend from above to contact a respective third lower wiring 720, and thus be electrically connected to the lower circuit pattern.

[0165] The vertical memory device may further include a fifth contact plug 499 extending through the first to fifth insulating intermediate layers 190, 270, 280, 380, and 480, the fourth insulating layer 260, the first insulating pad 242, the first sacrificial pattern 172 and the second sacrificial pattern 215, the first insulating pattern 162 and the third insulating pattern 225, and the substrate 100 to contact the third lower wiring 720. In an exemplary embodiment of the inventive concept, the fifth contact plug 499 may be formed in the region where the second sacrificial pattern 215 is retained in the third-direction adjacent first CSL 470. The fifth contact plug 499 may be disposed between a pair of second contact plugs 494 along the third direction.

[0166] FIGS. 60-62 These are plan views and cross-sectional views illustrating an exemplary embodiment of a vertical memory device according to the present invention. Specifically, FIG. 60 It's a floor plan. FIG. 61 It is along FIG. 60 The cross-sectional view taken by line B-B', and FIG. 62 It is along FIG. 60 The cross-sectional view taken from line E-E'.

[0167] Reference FIGS. 60-62 The circuit pattern used to drive the memory cell may not be formed on the peripheral circuit area, but only below the memory cell.

[0168] Unlike the lower substrate 600, the substrate 100 may be formed only on the first region I, and the fifth insulating layer 740 may replace the substrate 100 on the second region II and the third region IIII.

[0169] FIGS. 63-82 These are plan views, cross-sectional views, and perspective views illustrating a method for manufacturing a vertical memory device according to an exemplary embodiment of the present invention. Specifically, FIG. 79 It's a floor plan. FIGS. 72-78 and FIGS. 80-82 It is a cross-sectional view, and FIGS. 63-71 These are perspective views. Each of these figures corresponds to... FIG. 1 The third region of region Y is not shown in the perspective view. FIG. 72 , Figure 74 , Figure 76 and Figure 80 It is along Figure 1 A cross-sectional view taken from line B-B'. Figure 77 and Figure 81 It is along Figure 1 The cross-sectional view taken by line E-E', and Figure 73 , Figure 75 , Figure 78 and Figure 82 It is along Figure 1 A cross-sectional view taken from line G-G'.

[0170] The perspective view does not show the insulating layer and the second etch stop layer 230, and only the sacrificial layer 210 and the first insulating intermediate layer 190 are shown. An etching process, which will be shown later, can be performed on each of the pair of sacrificial layers 210 and on a third insulating layer 220 directly on each of the sacrificial layers 210. For ease of illustration, the third insulating layer 220 is not shown when the etching process is shown with reference to the perspective view.

[0171] This method may include... Figures 48 to 55 and Figures 44 to 47The processes are substantially the same or similar, therefore repeated descriptions are omitted in this article.

[0172] Reference Figure 63 Executable and Figure 6 and Figure 7 The processes are substantially the same or similar, and the sacrificial layer 210 and the third insulating layer 220 can be alternately and repeatedly stacked on the first insulating intermediate layer 190. Therefore, multiple sacrificial layers 210 and multiple third insulating layers 220 can be alternately stacked in the first direction. Second etch stop layer 230 (see reference) Figure 72 It can be further formed on the uppermost one of the third insulating layer 220.

[0173] Reference Figure 64 A first photoresist pattern covering the edge portions of the first region I and the adjacent second region II can be formed on the second etch stop layer 230. Here, the first photoresist pattern can be used as an etch mask to etch the second etch stop layer 230 and the uppermost sacrificial layer 210 to form a third sacrificial pattern 822 having a rectangular ring shape surrounding a portion of the uppermost sacrificial layer 210 on the first region I of the substrate 100.

[0174] However, Figure 64 Only a portion of the second region II of the substrate 100 (in other words, a portion of region Y) is shown, thus revealing a portion of the rectangular ring shape (in other words, a strip shape) of the third sacrificial pattern 822. Hereinafter, instead of showing the entire shape of the various sacrificial patterns that can be formed by etching the sacrificial layer 210 on the second region II, only the shape of the sacrificial pattern in region Y will be shown. Furthermore, when performing the process of forming a molded part as shown in the perspective view, the portion of the sacrificial layer 210 on the first region I of the substrate 100 may always be covered by a photoresist pattern; therefore, no further explanation regarding the sacrificial pattern on the first region I of the substrate 100 will be provided.

[0175] After the third sacrificial pattern 822 is formed, the first photoresist pattern can be removed by, for example, an ashing process and / or a stripping process.

[0176] A sacrificial layer 210 at a second level from the top level (hereinafter, the nth level from the top level will be referred to as the nth level) can be partially removed to form a fifth opening 840 exposing a sacrificial layer 210 at a third level. In an exemplary embodiment of the inventive concept, the fifth opening 840 may extend in a second direction on a second region II of the substrate 100, and a plurality of fifth openings 840 may be formed to be spaced apart from each other in a third direction. Additionally, a plurality of fifth openings 840 may also be formed to be spaced apart from each other in the second direction.

[0177] Reference Figure 65A second photoresist pattern 852 and a third photoresist pattern 854 spaced apart from the second photoresist pattern 852 in a second direction can be formed on a sacrificial layer 210 at the second etch stop layer 230 and the second level. The second photoresist pattern 852 covers the third sacrificial pattern 822 and has a length greater than the length of the third sacrificial pattern 822 in the second direction. The third photoresist pattern 854 covers a portion of the sacrificial layer 210 in the region Y and has a rectangular shape in the plan view.

[0178] In an exemplary embodiment of the present invention, a third photoresist pattern 854 may partially cover the respective fifth openings 840 spaced apart from each other in a third direction. Thus, for example, each end of the third photoresist pattern 854 in the third direction may overlap with the central portion of each fifth opening 840 in the third direction, and each end of the third photoresist pattern 854 in the second direction may overlap with each end of the fifth opening 840 in the second direction.

[0179] When multiple fifth openings 840 are formed in the second direction, multiple third photoresist patterns 854 can be formed to be spaced apart from each other in the second direction.

[0180] Reference Figure 66 A second photoresist pattern 852 and a third photoresist pattern 854 can be used as etching masks to etch a sacrificial layer 210 at the second level.

[0181] Therefore, a third sacrificial pattern 822 may be further formed below the third sacrificial pattern 822 at the first level (in other words, at the second level) to have a length greater than that of the third sacrificial pattern 822 at the first level, and a fourth sacrificial pattern 824 that may have a rectangular shape in the plan view may be formed at the second level.

[0182] A portion of the fifth opening 840 at the second level (in other words, the portion of the fifth opening 840 not covered by the third photoresist pattern 854) can be transferred to the third level to form the sixth opening 842. Therefore, the fourth sacrificial pattern 824 at the second level and the sixth opening 842 at the third level can be spaced apart from each other in a third-level direction.

[0183] Reference Figure 67 After removing the second photoresist pattern 852 and the third photoresist pattern 854, a fourth photoresist pattern 860 covering a portion of the fourth sacrificial pattern 824 can be formed on a sacrificial layer at the second etch stop layer 230 and the third level.

[0184] In an exemplary embodiment of the present invention, in a plan view, the fourth photoresist pattern 860 may have a strip shape extending upward in a third direction and may expose the end of the fourth sacrificial pattern 824 in a second direction.

[0185] Reference Figure 68 The fourth photoresist pattern 860 can be used as an etching mask to etch the fourth sacrificial pattern 824 and the sacrificial layer 210 at the third and fourth levels.

[0186] Therefore, a fifth sacrificial pattern 826, whose length in the second direction is greater than that of the third sacrificial pattern 822 in the second direction, can be formed at the third and fourth levels respectively. The portion of the fourth sacrificial pattern 824 not covered by the fourth photoresist pattern 860 can be moved from the second level to the fourth level, and the sixth opening 842 at the third level can be moved to the fifth level. The portion of the fourth sacrificial pattern 824 covered by the unremoved fourth photoresist pattern 860 can be transformed into a sixth sacrificial pattern 828, and can be retained on a fifth sacrificial pattern 826 at the third level.

[0187] The sacrificial layer 210 at the corresponding two levels has been etched using the fourth photoresist pattern 860 as an etching mask through an etching process. However, the inventive concept is not limited thereto, and the sacrificial layer 210 at more than two levels can be etched.

[0188] Reference Figure 69 A trimming process can be performed to reduce the area of ​​the fourth photoresist pattern 860 to partially expose the fifth sacrificial pattern 826 and the sixth sacrificial pattern 828, and the reduced fourth photoresist pattern 860 can be used as an etching mask to etch the fourth to sixth sacrificial patterns 824, 826 and 828 and the sacrificial layer 120 at the fifth and sixth levels, respectively.

[0189] Therefore, the lengths of the fifth sacrificial patterns 826 at the third and fourth levels in the second direction can be reduced to be the same as each other, and fifth sacrificial patterns 826 with lengths greater than those at the third and fourth levels can also be formed at the fifth and sixth levels, respectively. The exposed portion of the sixth sacrificial pattern 828 can be moved from the first level to the third level, and is hereinafter referred to as the seventh sacrificial pattern 830. The portion of the fourth sacrificial pattern 824 not covered by the fourth photoresist pattern 860 can be moved from the third level to the fifth level, and the sixth opening 842 at the fifth level can be moved to the seventh level.

[0190] Reference Figure 70 Repeatable execution with Figure 68 and Figure 69The substantially identical or similar process is used to form a molded part with a stepped shape on the second region II of the substrate 100.

[0191] The molded part may have a step disposed in the second direction. In addition, in the molded part, the fourth sacrificial pattern 824, the fifth sacrificial pattern 826 and the seventh sacrificial pattern 830 at the ends of each level may be disposed in the third direction to form a step.

[0192] In some exemplary embodiments of the present invention, after removing the fourth photoresist pattern 860, a photoresist pattern can be further formed, and a trimming process and an etching process can be further performed to form a molded part with more steps.

[0193] Reference Figures 71 to 73 A recess 200 may be formed on the first insulating intermediate layer 190 at the boundary between the second region II and the third region III of the substrate 100.

[0194] Reference Figure 74 and Figure 75 Executable and Figures 10 to 12 The processes are substantially the same or similar. Some sacrificial patterns (e.g., such as) exposed through the sixth opening 842 can be used. Figure 75 The first insulating pad 242 is formed on the fifth sacrificial pattern 826 shown.

[0195] Reference Figures 76 to 78 Executable and Figures 48 to 55 and Figure 22 The processes are substantially the same or similar.

[0196] Therefore, a gate electrode structure can be formed, which includes a step disposed in a second direction and also includes a step disposed in a third direction at its end in the second direction. The gate electrode structure may have the following characteristics, which can be derived from... Figure 78 The first step structure S1 is shown.

[0197] The first stepped structure S1 may include: an upper stepped layer comprising a first conductive pad P1; and a lower stepped layer comprising a second conductive pad P2, a fifth sacrificial pattern 826, and a second electrode E2. In other words, the second electrode E2 may be a portion of the second gate electrode 434 without the conductive pad, and the first conductive pad P1 and the second conductive pad P2 may be conductive pads of the second gate electrode 434 at a higher level and a lower level, respectively.

[0198] In an exemplary embodiment of the present invention, in the lower step layer, a sixth opening 842 may be formed between the second conductive pad P2 and the fifth sacrificial pattern 826, and the sixth opening 842 may be located between the third-direction end of the first conductive pad P1 and the third-direction end of the second conductive pad P2. Therefore, the first conductive pad P1 and the second conductive pad P2 do not overlap in the first direction. This is because when the first to seventh sacrificial patterns 172, 215, 822, 824, 826, 828, and 830 are removed through the third opening 390 and the fourth opening 400 to form the first gap 410 to form the first to third gate electrodes 432, 434, and 436, the ends of the sacrificial patterns 172, 215, 822, 824, 826, 828, and 830 that can be removed from the third opening 390 adjacent in the third-direction direction are limited by the sixth opening 842. Therefore, even if the first to third insulating pads 242, 244 and 246 have relatively high etching rates to be etched at high speed, in the first stepped structure S1, the end of the first gap 410 at the lower level in the third direction may not overlap with the end of the first gap 410 at the higher level in the third direction.

[0199] Reference Figures 79 to 82 Executable and Figures 44 to 47 The processes used are substantially the same or similar to those used to manufacture vertical memory devices.

[0200] For example, in the first stepped structure S1, the third insulating pattern 225 and the fifth sacrificial pattern 826 may be alternately and repeatedly stacked below the third-direction end of the first conductive pad P1, instead of the second electrode E2. Therefore, the second contact plug 494 for applying an electrical signal to the first conductive pad P1 can extend through the first conductive pad P1 to reach the area below. This occurs because in the first stepped structure S1, the second conductive pad P2 at a lower level may not overlap with the first conductive pad P1 at a higher level in the first direction.

[0201] In a method for manufacturing a vertical memory device according to an exemplary embodiment of the present invention, the insulating pad may not need to be removed separately, thereby saving time and cost associated with removing the insulating pad. For example, even if the insulating pad is replaced by a conductive structure, the CSL will not be electrically short-circuited due to the contact plugs extending through the conductive structure.

[0202] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

Claims

1. A vertical memory device, comprising: A substrate comprising a first region and a second region at least partially surrounding the first region; Gate electrodes at multiple horizontal locations, the gate electrodes being spaced apart from each other in a first direction substantially perpendicular to the upper surface of the substrate, each of the gate electrodes extending in a second direction substantially parallel to the upper surface in both the first and second regions, and the gate electrodes being stacked in a stepped shape in the second region; A channel extending in the first direction over the first region, the channel extending through the gate electrode; A first conductive structure is located at the end of a first gate electrode in the gate electrode, the end being in the second region, the first gate electrode being disposed at the lowest level of the plurality of levels; A second conductive structure is spaced apart from the first conductive structure in the second region in the second direction, and the second conductive structure does not overlap with the first gate electrode in the first direction and is disposed at a height different from that of the first conductive structure. as well as A barrier pattern comprising a metal oxide, the barrier pattern covering the upper and lower surfaces and sidewalls of each of the first and second conductive structures.

2. The vertical memory device according to claim 1, wherein, The second conductive structure is lower than the first conductive structure.

3. The vertical memory device according to claim 1, wherein, The second conductive structure is higher than the first conductive structure.

4. The vertical memory device of claim 1, further comprising a third conductive structure spaced apart from the first conductive structure and the second conductive structure in the second direction, the third conductive structure not overlapping the first gate electrode in the first direction and disposed at a height different from that of the second conductive structure.

5. The vertical memory device according to claim 4, wherein, The third conductive structure is positioned at a different height than the first conductive structure.

6. The vertical memory device according to claim 1, wherein, The first conductive structure is higher than the first gate electrode and lower than the gate electrode that is closest to the first gate electrode in the first direction.

7. The vertical memory device according to claim 1, wherein, The first conductive structure and the second conductive structure comprise materials substantially the same as those used for the gate electrode.

8. The vertical memory device according to claim 1, wherein, The blocking pattern covers the upper and lower surfaces and sidewalls of each of the gate electrodes.

9. The vertical memory device of claim 1, further comprising a first insulating pad spaced apart from the first conductive structure in the second direction on the second region, the first insulating pad not overlapping the first gate electrode in the first direction and disposed at a height substantially the same as the height of the second conductive structure.

10. The vertical memory device according to claim 9, wherein, The first insulating pad is spaced apart from the end of the first gate electrode in the second direction.

11. The vertical memory device according to claim 9, wherein, The first insulating pad comprises silicon nitride.

12. The vertical memory device according to claim 9, wherein, The substrate further includes a third region that at least partially surrounds the second region, and The vertical memory device further includes a second insulating pad on the third region at a height different from that of the second conductive structure.

13. The vertical memory device according to claim 12, wherein, The second insulating liner comprises a material substantially the same as that of the first insulating liner.

14. The vertical memory device according to claim 1, wherein, The second conductive structure is disposed on the second region and a portion of a third region adjacent to the second region.

15. The vertical memory device according to claim 1, wherein, A plurality of first gate electrodes are spaced apart from each other in a third direction, said third direction being substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction. In this configuration, multiple first conductive structures are spaced apart from each other on the multiple first gate electrodes in the third direction.

16. The vertical memory device according to claim 15, wherein, The second conductive structure extends upward on the third party and is spaced apart from the plurality of first conductive structures extending upward on the third party.

17. The vertical memory device according to claim 1, wherein, A conductive pad is formed at the end of the gate electrode in the second direction, and the thickness of each conductive pad is greater than the thickness of the other portions of the gate electrode on which the conductive pad is formed.

18. The vertical memory device according to claim 17, wherein, Each of the conductive pads protrudes from a corresponding gate electrode in a third direction, which is substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction.

19. A vertical memory device, comprising: A substrate comprising a cell array region, an extension region at least partially surrounding the cell array region, and a circuit region at least partially surrounding the extension region; The gate electrodes are spaced apart from each other in a first direction substantially perpendicular to the upper surface of the substrate, each of the gate electrodes extends in a second direction substantially parallel to the upper surface of the substrate in the cell array region and the extension region of the substrate, and the gate electrodes are stacked in a stepped shape in the extension region of the substrate. A channel extending in the first direction over the cell array region of the substrate, the channel extending through the gate electrode; A first insulating pad is spaced apart from the end of a first gate electrode in the second direction on a portion of the circuit region of the substrate, the first gate electrode being disposed at the lowest of the plurality of levels, and the first insulating pad being higher than the first gate electrode relative to the upper surface of the substrate. as well as A second insulating pad, spaced apart from the first insulating pad in the second direction on the circuit region of the substrate, is located at a height different from that of the first insulating pad. The first insulating pad and the second insulating pad comprise substantially the same material.

20. The vertical memory device according to claim 19, wherein, The first insulating pad and the second insulating pad comprise nitrides.

21. A vertical memory device, comprising: A substrate comprising a cell array region, an extension region at least partially surrounding the cell array region, and a circuit region at least partially surrounding the extension region; The gate electrodes are spaced apart from each other in a first direction substantially perpendicular to the upper surface of the substrate, each of the gate electrodes extends in a second direction substantially parallel to the upper surface of the substrate in the cell array region and the extension region of the substrate, and the gate electrodes are stacked in a stepped shape in the extension region of the substrate. A channel extending in the first direction over the cell array region of the substrate, the channel extending through the gate electrode; A conductive structure is higher than a first gate electrode and lower than a second gate electrode in the gate electrodes, the conductive structure overlapping an end of the first gate electrode in the first direction, the first gate electrode being adjacent to the upper surface of the substrate; as well as A cut pattern extends in the first direction over the circuit region of the substrate, the cut pattern contacting the conductive structure.

22. The vertical memory device according to claim 21, wherein, A plurality of first gate electrodes are spaced apart from each other in a third direction, said third direction being substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction. The conductive structure overlaps with the end of each of the plurality of first gate electrodes in the first direction.

23. The vertical memory device according to claim 22, wherein, The cut pattern contacts each of the conductive structure at each of the opposite ends in the third direction.

24. The vertical memory device of claim 23, further comprising an insulating pad on the circuit region of the substrate, at least a portion of the insulating pad having a height substantially the same as the height of the conductive structure and contacting the conductive structure.

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