Clock generator, semiconductor device and system on chip

Abstract

A clock generator, a semiconductor device, and a system on chip are provided. The clock generator includes: a phase detector, a voltage generator, a voltage-current converter, and an oscillation circuit. The voltage generator generates a control voltage. The voltage-current converter converts the control voltage into an internal current having a level based on a resistance value of a resistor circuit, the resistance value being set based on first control information. The oscillation circuit generates an output clock having a frequency based on the level of the internal current and a capacitance value of a capacitor circuit, the capacitance value being set based on second control information. The clock generator maintains a frequency value of the output clock and changes a jitter characteristic of the output clock in response to the first control information and the second control information.

Description

[0001] This application claims the priority benefit of Korean Patent Application No. 10-2019-0072420 filed on June 18, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a clock generator and a semiconductor device including the clock generator, and more particularly, to a clock generator for adjusting jitter characteristics and operating power, a semiconductor device including the clock generator, and an operating method of the clock generator. Background Art

[0003] The operation of a digital block for processing a digital signal may be synchronized with a clock signal. For example, an integrated circuit requires a clock signal with various dynamic frequencies for processing (such as timing of a data converter and a digital block), and for this purpose, a plurality of clock generators may be provided in the integrated circuit. Since a plurality of clock generators are provided in the integrated circuit, the area of ​​the integrated circuit increases, and power consumption increases.

[0004] A single clock generator may be provided in an integrated circuit, and clock signals having various frequencies may be generated by using the single clock generator. This can reduce area and power consumption. However, there is a problem that the jitter and power consumption of the clock generator must be designed for the most stringent jitter specification, and there is a limit to reducing undesirable power consumption. Summary of the invention

[0005] One aspect provides a clock generator for providing clock signals having various frequencies and adjusting jitter characteristics and operating power, a semiconductor device including the clock generator, and an operating method of the clock generator.

[0006] According to one aspect of an example embodiment, a clock generator is provided, the clock generator comprising: a phase detector configured to detect a phase difference between an input clock and a signal obtained by dividing an output clock; a voltage generator configured to generate a control voltage having a level based on the phase difference; a voltage-to-current converter comprising a resistor circuit including a plurality of resistors, the voltage-to-current conversion converting the control voltage into an internal current having a level based on a resistance value of the resistor circuit, the resistance value being set based on first control information; and an oscillation circuit comprising a capacitor circuit including a plurality of capacitors, the oscillation circuit generating an output clock having a frequency based on the level of the internal current and a capacitance value of the capacitor circuit, the capacitance value being set based on second control information, wherein the clock generator is configured to maintain a frequency value of the output clock and change a jitter characteristic of the output clock in response to the first control information and the second control information.

[0007] According to another aspect of an example embodiment, a semiconductor circuit is provided, the semiconductor circuit comprising: a clock generator configured to receive an input clock to generate an output clock having a target frequency; and control logic configured to output control information for controlling a jitter characteristic of the output clock of the clock generator, wherein the clock generator comprises: a voltage-controlled oscillator configured to generate an output clock having a frequency based on a control voltage, the control voltage being generated based on a phase difference between the input clock and a signal obtained by dividing the output clock, and when receiving control information having a first value, the voltage-controlled oscillator is configured to reduce the jitter of the output clock having the target frequency, and when receiving control information having a second value, the voltage-controlled oscillator is configured to increase the jitter of the output clock having the target frequency.

[0008] According to another aspect of an example embodiment, there is provided an operating method of a clock generator, the operating method comprising: in response to receiving control information having a first value, reducing a level of an internal current provided to an oscillation circuit; in response to receiving the control information having the first value, reducing a capacitance value of a capacitor circuit of the oscillation circuit to output an output clock having a first frequency; in response to receiving the control information having a second value, increasing the level of the internal current provided to the oscillation circuit; and in response to receiving the control information having the second value, increasing the capacitance value to maintain the frequency of the output clock to the first frequency, wherein a jitter of the output clock when the control information has the first value is greater than a jitter of the output clock when the control information has the second value.

[0009] According to another aspect of an example embodiment, a clock generator is provided, the clock generator comprising: a voltage generator configured to generate a control voltage having a level based on a phase difference between an input clock and a signal obtained by dividing an output clock; and a voltage-controlled oscillator comprising a voltage-to-current converter and an oscillation circuit, the voltage-to-current converter being configured to receive the control voltage and convert the control voltage into a current based on a resistance value of a resistor circuit comprising a plurality of resistors, the oscillation circuit being configured to generate an output clock based on a level of the current received from the voltage-to-current converter, wherein the oscillation circuit comprises: one or more delay units each comprising a load, the one or more delay units receiving the current, and the size of the load of each of the one or more delay units being adjusted based on the level of the current.

[0010] According to another aspect of an example embodiment, a system on chip is provided, the system on chip comprising: a clock generator configured to generate a clock signal; and a plurality of circuit blocks configured to receive the clock signal from the clock generator, wherein the clock generator is configured to: in a first operating mode of the system on chip, provide a clock signal having a first jitter characteristic and generated at a first power consumption to a first circuit block among the plurality of circuit blocks, and wherein the clock generator is configured to: when the first operating mode is changed to a second operating mode, provide a clock signal having a second jitter characteristic and generated at a second power consumption to the first circuit block without releasing a locked state of the clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a block diagram illustrating a clock generator according to an example embodiment;

[0013] Figure 2 is a diagram showing a method according to an example embodiment Figure 1 A block diagram of an implementation example of a voltage controlled oscillator;

[0014] Figure 3 is a block diagram illustrating an integrated circuit including a clock generator according to an example embodiment;

[0015] Figure 4 is a flowchart illustrating an operating method of a clock generator according to an example embodiment;

[0016] Figure 5 is a flowchart illustrating an operating method of a clock generator according to another example embodiment;

[0017] Figure 6 is a block diagram showing a detailed implementation example of a clock generator according to an example embodiment;

[0018] Figure 7 is a diagram showing a method according to an example embodiment Figure 6 A circuit diagram of an implementation example of a voltage controlled oscillator shown in;

[0019] Figure 8 is a diagram showing a method according to an example embodiment Figure 7 A circuit diagram of an implementation example of a delay unit;

[0020] Fig. 9 and Fig.10 is a timing diagram showing an operation example of a clock generator according to an example embodiment;

[0021] FIG. 11A to FIG. 11Dis a circuit diagram illustrating an operation example of controlling various switches of an oscillation circuit based on control information according to an example embodiment;

[0022] Fig.12 is a circuit diagram illustrating a clock generator according to an example embodiment;

[0023] Fig.13 is a block diagram illustrating a system including a clock generator according to an example embodiment;

[0024] Fig.14 is a block diagram illustrating a wireless communication device including a clock generator according to an example embodiment; and

[0025] Fig.15 is a block diagram illustrating an application processor including a clock generator according to example embodiments. DETAILED DESCRIPTION

[0026] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0027] Figure 1 is a block diagram illustrating a clock generator 100 according to an example embodiment.

[0028] Reference Figure 1 , the clock generator 100 may receive an input clock Fin to generate an output clock Fout having a specific frequency. As an implementation example, the clock generator 100 may include a phase-locked loop (PLL), but the embodiment is not limited thereto, and the embodiment may be applied to various types of clock generators. In addition, in some embodiments, the clock generator 100 may be implemented as an integrated circuit manufactured by a semiconductor process, and in some other embodiments, the clock generator 100 may include at least one semiconductor package including an integrated circuit and a board on which the semiconductor package is mounted.

[0029] The clock generator 100 may include a phase / frequency detector (PFD) 110, a voltage generator 120, a voltage controlled oscillator (VCO) 130, and a frequency divider 140. In one embodiment, the phase / frequency detector 110 may be replaced by a phase detector. In addition, according to an example embodiment, the VCO 130 may be implemented as a ring VCO and may include a voltage-current converter 131 and an oscillation circuit 132. The voltage-current converter 131 may include a resistor circuit 131_1 including a plurality of resistors. In addition, the oscillation circuit 132 may include a load that affects the frequency of the output clock Fout, and as an example of a load, the oscillation circuit 132 may include a capacitor circuit 132_1 including a plurality of capacitors.

[0030] The input clock Fin may vibrate at a specific frequency, and may be generated by a crystal oscillator (not shown), for example, and may be provided to the clock generator 100. The output clock Fout may have a frequency (i.e., a target frequency) required by a circuit block (e.g., a digital block (not shown)) to which the output clock Fout is supplied. The circuit block may process a signal based on the output clock Fout, and the clock generator 100 may generate an output clock Fout having a jitter characteristic for the circuit block. For example, the clock generator 100 may provide the output clock Fout to at least two circuit blocks using the output clock Fout having the same frequency, and when the jitter characteristic of the first circuit block (e.g., one of the at least two circuit blocks) is relatively low, the output clock Fout having a larger jitter than the other circuit blocks may be provided to the first circuit block. On the other hand, when the jitter characteristic of the second circuit block (e.g., another circuit block of the at least two circuit blocks) is relatively high, the output clock Fout having a smaller jitter than the other circuit blocks may be provided to the second circuit block.

[0031] The phase / frequency detector 110 may receive an input clock Fin provided from outside the clock generator 100, and may receive a divided output clock Fout / N from the frequency divider 140. The phase / frequency detector 110 may detect a phase difference and a frequency difference between the input clock Fin and the divided output clock Fout / N, and may generate a detection signal Det corresponding to the detected phase difference and frequency difference. For example, the detection signal Det may include an up signal and a down signal, and depending on how closely the frequency of the input clock Fin matches the frequency of the divided output clock Fout / N, the phase / frequency detector 110 may activate the up signal and / or the down signal based on the sign of the frequency difference between the input clock Fin and the divided output clock Fout / N.

[0032] The voltage generator 120 may receive the detection signal Det from the phase / frequency detector 110, and may generate the control voltage Vctrl based on the detection signal Det. The control voltage Vctrl may have a level depending on the phase difference represented by the detection signal Det. For example, the voltage generator 120 may include a charge pump and a loop filter. When the phase of the frequency-divided output clock Fout / N is relatively lagging, the level of the control voltage Vctrl may increase, and when the phase of the frequency-divided output clock Fout / N is relatively advanced, the level of the control voltage Vctrl may decrease. Therefore, in a state where the loop is locked, the voltage generator 120 may generate a control voltage Vctrl having a specific level.

[0033] The VCO 130 may receive a control voltage Vctrl and may generate an output frequency Fout having a frequency based on the control voltage Vctrl. In an example embodiment, the voltage-current converter 131 may receive the control voltage Vctrl to generate an internal current Iv corresponding to the control voltage Vctrl, and may provide the generated internal current Iv to the oscillation circuit 132. In addition, the oscillation circuit 132 may generate an output clock Fout having a frequency based on an input current (e.g., a supply current), for example, the oscillation circuit 132 may receive the internal current Iv as a supply current from the voltage-current converter 131 to generate an output clock Fout having a frequency based on the internal current Iv. For example, the frequency of the output clock Fout output from the oscillation circuit 132 may have a value determined based on the level of the internal current Iv and the capacitance value of the capacitor circuit 132_1.

[0034] According to example embodiments, the oscillation circuit 132 may directly receive the internal current Iv generated by the voltage-current converter 131, and as in the embodiments described below, the oscillation circuit 132 may receive the internal current having a level proportional to the internal current Iv as the supply current. That is, when describing example embodiments, the term "internal current" may be a concept including the internal current Iv generated by the voltage-current converter 131 or a current having a level proportional to the internal current Iv by processing (e.g., digital-to-analog conversion, etc.) the internal current Iv from the voltage-current converter 131.

[0035] According to an example embodiment, the voltage-current converter 131 may include a resistor circuit 131_1, and the resistor circuit 131_1 may include a plurality of resistors each having a resistance value (or an equivalent resistance value) that varies based on the control information Ctrl_J. In addition, the oscillation circuit 132 may include a capacitor circuit 132_1, and the capacitor circuit 132_1 may include a plurality of capacitors each having a capacitance value (or an equivalent capacitance value) that varies based on the control information Ctrl_J. Figure 1 , it is shown that the control information Ctrl_J is provided to the resistor circuit 131_1 and the capacitor circuit 132_1, but the embodiment is not limited thereto. For example, in some embodiments, the control information Ctrl_J may include first control information for controlling the resistor circuit 131_1 and second control information for controlling the capacitor circuit 132_1.

[0036] The resistor circuit 131_1 may further include a plurality of switches (e.g., a first switch) provided based on a plurality of resistors to change the resistance value. The control information Ctrl_J may be digital information including a plurality of bits for switching of the first switch, and when the connection relationship between the plurality of resistors changes based on the control information Ctrl_J, the resistance value of the resistor circuit 131_1 may change. Similarly, the capacitor circuit 132_1 may further include a plurality of switches (e.g., a second switch) provided based on a plurality of capacitors to change the equivalent capacitance value. The control information Ctrl_J may be digital information including a plurality of bits for switching of the second switch, and when the connection relationship between the plurality of capacitors changes based on the control information Ctrl_J, the capacitance value of the capacitor circuit 132_1 may change.

[0037] The control information Ctrl_J may be information generated by an internal element of the clock generator 100, or may be information provided from outside the clock generator 100. As an implementation example, an integrated circuit (or semiconductor device) including the clock generator 100 may include a control logic (not shown) for adjusting a jitter characteristic of an output clock Fout output from the clock generator 100, and the control logic may provide control information Ctrl_J for increasing or decreasing the jitter of the output clock Fout. According to one embodiment, in response to the control information Ctrl_J, the clock generator 100 may generate output clocks Fout having the same frequency but different jitter characteristics.

[0038] The output clock Fout may be fed back to the frequency divider 140, and the frequency divider 140 may divide the fed back output clock Fout to generate a divided output clock Fout / N, and may provide the divided output clock Fout / N to the phase / frequency detector 110. For example, the frequency divider 140 may divide the output clock Fout based on a ratio between the frequency of the input clock Fin and the target frequency of the output clock Fout.

[0039] An example of adjusting the jitter characteristics of the output clock Fout will be described below.

[0040] The VCO 130 may generate an output clock Fout having a jitter characteristic that changes in response to the control information Ctrl_J, for example, the VCO 130 may adjust the resistance value of the resistor circuit 131_1 and the capacitance value of the capacitor circuit 132_1 to generate an output clock Fout having the same frequency but having a jitter characteristic that changes based on the resistance value and the capacitance value. The power consumed by the clock generator 100 and the jitter amplitude of the output clock Fout may have an inverse relationship, and therefore, the jitter characteristic of the output clock Fout may change based on the level of the internal current Iv provided to the oscillation circuit 132. For example, when the level of the internal current Iv provided to the oscillation circuit 132 is relatively high, the jitter of the output clock Fout may be reduced, and when the level of the internal current Iv is relatively low, the jitter of the output clock Fout may be increased. The resistance value of the resistor circuit 131_1 may be used to determine the level of the internal current Iv. For example, when the resistance value of the resistor circuit 131_1 is large, the level of the internal current Iv may decrease, and when the resistance value of the resistor circuit 131_1 is small, the level of the internal current Iv may increase.

[0041] The frequency of the output clock Fout output from the oscillation circuit 132 may have a value based on the level of the internal current Iv and the capacitance value of the capacitor circuit 132_1. For example, when the capacitance value of the capacitor circuit 132_1 is relatively small, an output clock Fout having a relatively high frequency may be generated from the internal current Iv having the same level, and when the capacitance value of the capacitor circuit 132_1 is relatively large, an output clock Fout having a relatively low frequency may be generated from the internal current Iv having the same level. According to an example embodiment, the clock generator 100 may adjust the resistance value of the resistor circuit 131_1 based on the control information Ctrl_J, and may adjust the capacitance value of the capacitor circuit 132_1 based on the change in the resistance value, thereby generating an output clock Fout having the same frequency but having a changed jitter characteristic.

[0042] According to an example embodiment, the clock generator 100 may generate and provide an output clock Fout optimized for each of various types of digital blocks requiring different jitter characteristics. That is, for each digital block requiring a relatively low jitter characteristic, the output clock Fout may be generated from an internal current Iv having a relatively low level, and thus, an undesirable increase in power consumption may be prevented. For example, a jitter of 5 ps or less may be required for a digital block performing a Wi-Fi analog-to-digital conversion operation, but when a jitter of 15 ps is acceptable for some digital blocks other than the digital block performing the Wi-Fi analog-to-digital conversion operation but included together with the digital block performing the Wi-Fi analog-to-digital conversion, the clock generator 100 may generate an output clock Fout optimized for each requirement, thereby reducing undesirable power consumption. In addition, in the digital block performing the Wi-Fi analog-to-digital conversion operation, the requirement for jitter may change over time, and based on the changed requirement, the clock generator 100 may change the jitter characteristic of the output clock Fout for the same operation, thereby reducing undesirable power consumption.

[0043] That is, according to the above-mentioned example embodiments, a multi-standard clock generator for generating a wide range of frequencies and for reconfiguring jitter characteristics and power consumption characteristics can be provided, and for example, dynamic scaling (DFS) with a wide range of frequencies from about 9 MHz to about 2.4 GHz can be ensured, and jitter and power consumption optimized for each standard can be provided according to the increase in consumption of multi-standard applications.

[0044] when Figure 1 When the clock generator 100 shown in FIG. 1 is included in an electronic system (or electronic device), one clock generator 100 may be set based on one digital block, or the electronic system may be implemented such that one clock generator 100 is shared by a plurality of digital blocks. For example, when the same clock generator 100 is set based on each of different digital blocks, the clock generator 100 may generate an output clock Fout optimized for the corresponding digital block. In addition, one clock generator 100 may be shared and time-divisionally used by a plurality of digital blocks, and may generate an output clock Fout having a target frequency for each of the digital blocks and having a jitter characteristic optimized for each digital block.

[0045] Figure 2 is a diagram showing a method according to an example embodiment Figure 1 FIG. 1 is a block diagram of an example implementation of the VCO 130. Figure 2 , an example is shown in which the VCO 130 according to the above-described embodiment includes a digital-to-analog converter (DAC) 133 in addition to the voltage-to-current converter 131 and the oscillation circuit 132 .

[0046] Reference Figure 1 and Figure 2, the voltage-current converter 131 may receive the control voltage Vctrl and may generate an internal current Iv corresponding to the control voltage Vctrl. In addition, the DAC 133 may receive a digital control bit C_bit from the outside of the DAC 133 together with receiving the internal current Iv, and may adjust the level of the internal current Iv in response to the digital control bit C_bit, thereby generating a first current βIv (i.e., an internal current whose level is adjusted). For example, the first current βIv may have a level proportional to the internal current Iv, and its proportional value β may vary based on the digital control bit C_bit. In addition, the oscillation circuit 132 may receive the first current βIv as the internal current according to the above-described embodiment and may generate an output clock Fout having a frequency based on the first current βIv.

[0047] The control information Ctrl_J may include first control information Ctrl_JR for controlling the resistor circuit 131_1 and second control information Ctrl_JC for controlling the capacitor circuit 132_1. According to the above embodiment, the voltage-current converter 131 may include a plurality of first switches that are turned on and change the resistance value according to the control based on the first control information Ctrl_JR, and the oscillation circuit 132 may include a plurality of second switches that are turned on and change the capacitance value according to the control based on the second control information Ctrl_JC. Based on the arrangement of the resistor and the first switch of the resistor circuit 131_1 and the arrangement of the capacitor and the second switch of the capacitor circuit 132_1, the first control information Ctrl_JR and the second control information Ctrl_JC may be control information having the same bit value, or may be control information having different bit values.

[0048] The DAC 133 may be set to compensate for a frequency error of the output clock Fout output from the clock generator 100. As an operation example, in the clock generator 100, due to manufacturing process differences, errors may occur in the operating characteristics of the VCO 130 and / or the voltage-to-current conversion characteristics of the voltage-to-current converter 131, and the clock generator 100 may further include an automatic frequency control (AFC) circuit (not shown) as an element for compensating for the error. The AFC circuit may monitor the output clock Fout or a signal Fout / N obtained by dividing the output clock, and may generate a digital control bit C_bit based on the output clock Fout or the signal Fout / N obtained by dividing the output clock, thereby adjusting the level of the first current βIv.

[0049] According to the above-described embodiment, the resistance value of the resistor circuit 131_1 may be adjusted based on the first control information Ctrl_JR, and the capacitance value of the capacitor circuit 132_1 may be adjusted according to the second control information Ctrl_JC, thereby providing the clock generator 100 for reconfiguring jitter and power consumption.

[0050] Figure 3 2 is a block diagram illustrating an integrated circuit 200 including a clock generator according to example embodiments. For example, the integrated circuit 200 may be implemented as a semiconductor device such as a semiconductor chip or a semiconductor package, or may be included in a semiconductor device.

[0051] Reference Figure 3 , the integrated circuit 200 may include a control logic 210, a clock generator 220, and a digital block 230. Various elements included in the integrated circuit 200 may be implemented as various types, for example, the clock generator 220 may be implemented as a separate semiconductor device. Alternatively, as various modification examples, at least one of the control logic 210 and the digital block 230 may be an element included in the same semiconductor device together with the clock generator 220. Figure 3 In the integrated circuit 200 , for convenience of description, only one digital block 230 is shown, but a plurality of various circuit blocks for performing signal processing based on the output clock Fout from the clock generator 220 may be further included in the integrated circuit 200 .

[0052] The clock generator 220 may correspond to Figure 1 and Figure 2 The clock generator of the above-described embodiment is shown. The clock generator 220 may receive an input clock Fin to generate an output clock Fout. For example, the clock generator 220 may include a VCO 221, the VCO 221 may include a voltage-current converter 221-1 and an oscillation circuit 221-2, the voltage-current converter 221-1 may include a resistor circuit, and the oscillation circuit 221-2 may include a capacitor circuit. The output clock Fout from the clock generator 220 may be provided to the digital block 230, and the jitter characteristics of the output clock Fout provided from the clock generator 220 according to the example embodiment may vary based on the control information Ctrl_J[1:A] from the control logic 210. In Figure 3 , for convenience of description, only the VCO 221 included in the clock generator 220 is shown, but various elements each associated with generation of the output clock Fout, such as a phase detector and a voltage generator, may be included in the clock generator 220.

[0053] The control logic 210 may generate the control information Ctrl_J[1:A] and may provide the control information Ctrl_J[1:A] to the clock generator 220. According to the above-described embodiment, the resistance value of the resistor circuit of the VCO 221 may vary based on the control information Ctrl_J[1:A], and the capacitance value of the capacitor circuit may vary based on the control information Ctrl_J[1:A]. For example, in Figure 3, A pieces of control information Ctrl_J[1:A] are shown, and the clock generator 220 can generate an output clock Fout having the same frequency based on each of the A pieces of control information Ctrl_J[1:A]. In addition, the clock generator 220 can generate an output clock Fout having different jitter characteristics based on the A pieces of control information Ctrl_J[1:A]. In addition, according to Figure 3 In the above embodiment shown in , each of the A pieces of control information Ctrl_J[1:A] may include first control information for adjusting a resistance value and second control information for adjusting a capacitance value.

[0054] The control logic 210 may generate the control information Ctrl_J[1:A] based on its determined operation or mode information Info_M from outside the control logic 210. The mode information Info_M may include various information associated with the operation of the clock generator 220. For example, the mode information Info_M may include information indicating a low power mode or a high power mode, and when the integrated circuit 200 operates in the low power mode, the control logic 210 may output the control information Ctrl_J[1:A] so that the power consumed by generating the output clock Fout may be reduced and a relatively large jitter may occur in the output clock Fout based on the control information Ctrl_J[1:A] from the control logic 210. On the other hand, when the integrated circuit 200 operates in the high power mode, the control logic 210 may output the control information Ctrl_J[1:A] so that the power consumed by generating the output clock Fout may be increased and a relatively small jitter may occur in the output clock Fout based on the control information Ctrl_J[1:A] from the control logic 210.

[0055] According to an example embodiment, when the integrated circuit 200 performs a function associated with communication, the mode information Info_M may include a plurality of pieces of information associated with the communication mode. For example, when the mode information Info_M indicates a long term evolution (LTE) communication mode requiring a high jitter characteristic, the control logic 210 may output the control information Ctrl_J[1:A] so that based on the control information Ctrl_J[1:A] from the control logic 210, the power consumed by generating the output clock Fout may be increased and a relatively small jitter may occur in the output clock Fout. On the other hand, when the mode information Info_M indicates a third generation (3G) communication mode requiring a relatively low jitter characteristic, the control logic 210 may output the control information Ctrl_J[1:A] so that based on the control information Ctrl_J[1:A] from the control logic 210, the power consumed by generating the output clock Fout may be reduced and a relatively large jitter may occur in the output clock Fout.

[0056] In addition to the low power mode and the high power mode, the control logic 210 may also generate the control information Ctrl_J[1:A] based on various determination criteria. For example, as described above, when the jitter characteristics required by the digital block 230 vary over time, the control logic 210 may generate the control information Ctrl_J[1:A] for optimizing the jitter characteristics of the output clock Fout provided to the digital block 230 according to the specifications of the jitter characteristics at various times.

[0057] The clock generator 220 may generate an output clock Fout having the same frequency in response to A different control information Ctrl_J[1:A], and may change the jitter characteristics of the output clock Fout. For example, when one control information (e.g., Ctrl_J[1]) is provided to the clock generator 220, the clock generator 220 may control the resistance value of the resistor circuit to decrease (or the internal current may increase), and based on this, the capacitance value of the capacitor circuit increases, so that the output clock Fout with enhanced jitter characteristics may be generated. On the other hand, when other control information (e.g., Ctrl_J[A]) is provided to the clock generator 220, the clock generator 220 may control the resistance value of the resistor circuit to increase, and based on this, the capacitance value of the capacitor circuit decreases, so that the frequency thereof is maintained the same and the output clock Fout whose jitter characteristics are reduced may be generated.

[0058] Figure 4 is a flowchart illustrating an operating method of a clock generator according to example embodiments.

[0059] Reference Figures 1 to 4 , the clock generator according to the example embodiment may include a VCO, and the VCO may generate an output clock having a frequency corresponding to a control voltage input to the VCO. In addition, as described above, the VCO may include a converter that converts the control voltage into a current and an oscillation circuit that generates an output clock having a target frequency based on the converted current.

[0060] In operation S11, the voltage generator may generate a control voltage based on the phase of the input clock detected by the PFD. For example, according to the above-described embodiment, the PFD may detect the phase and frequency of each of the input clock and the signal obtained by dividing the output clock, and the voltage generator may generate a control voltage corresponding to the detection result, and provide the generated control voltage as an input of the VCO.

[0061] When converting the control voltage into the current, the level of the current may vary based on the resistance value of the resistor circuit included in the converter, and the resistance value for converting the control voltage into the internal current may be set in operation S12. The resistance value for converting the control voltage into the internal current may be set based on control information from the inside or outside of the clock generator. The control information may include information for setting the clock generation operation of the clock generator, and based on the control information, the clock generator may consume low power and may generate an output clock with large jitter, or may generate an output clock with small jitter and may consume high power. In operation S13, the clock generator may generate an internal current having a level based on the set resistance value.

[0062] The oscillation circuit may include a capacitor circuit including a plurality of capacitors, and in operation S14, a capacitance value of the capacitor circuit may be set based on a set resistance value of the resistor circuit. In operation S15, the oscillation circuit may generate an output clock having a frequency based on the generated internal current and the set capacitance value.

[0063] Figure 5 is a flow chart showing an operating method of a clock generator according to another example embodiment. Figure 5 , an example of generating output clocks having the same frequency based on a change in a pattern but generating output clocks having different jitter characteristics based on a pattern is shown.

[0064] Reference Figure 5 , in operation S21, the integrated circuit including the clock generator enters the first mode. In operation S22, control information corresponding to the first mode may be provided to the clock generator, and the resistance value of the resistor circuit may be set to the first resistance value based on the control information, and the resistance value of the resistor circuit is provided for the voltage-current conversion performed by the clock generator. In addition, in operation S23, the capacitance value of the capacitor circuit may be set to the first capacitance value based on the control information, and the capacitance value of the capacitor circuit is provided for setting the output frequency of the oscillation circuit of the clock generator. In operation S24, a clock signal having a first frequency and a first jitter characteristic may be generated based on the set resistance value and capacitance value.

[0065] In operation S25, the integrated circuit including the clock generator may enter the second mode. Control information corresponding to the second mode may be provided to the clock generator, and in operation S26, the resistance value of the resistor circuit may be set to the second resistance value based on the control information, and in operation S27, the capacitance value of the capacitor circuit may be set to the second capacitance value. In operation S28, a clock signal having a second jitter characteristic and a first frequency identical to the frequency in the first mode may be generated based on the set resistance value and capacitance value.

[0066] exist Figure 5 In an embodiment, a clock generator according to an example embodiment may change the jitter characteristics of an output clock when performing its operation. For example, the clock generator may change the setting of each of a resistance value and a capacitance value without releasing a locked state in a state where the output clock has a target frequency, thereby increasing or decreasing the jitter of the output clock. That is, without performing on / off control on the clock generator to change the operation mode of the clock generator, the clock generator according to an example embodiment may change the jitter of the output clock while maintaining the target frequency, and thus may change the power consumed by the clock generator. In other words, the clock generator according to an example embodiment may change the jitter of the output clock based only on a mode change while maintaining a locked target frequency.

[0067] Figure 6 is a block diagram illustrating a detailed implementation example of the clock generator 300 according to an example embodiment.

[0068] Reference Figure 6 , the clock generator 300 may include a phase / frequency detector (PFD) 330, a charge pump (CP) 340, a loop filter 350, a VCO 360, and a frequency divider ( / N) 380. In one embodiment, the phase / frequency detector 330 may be replaced by a phase detector. In addition, in some embodiments of the clock generator 300, the charge pump 340 and the loop filter 350 may be included in the voltage generator as in the above-mentioned embodiments. The frequency divider 380 may divide the output clock Fout by N to generate a divided output clock Fout / N.

[0069] The VCO 360 may include a voltage-to-current (V-to-I) converter 361, a digital-to-analog converter (DAC) 362, and an oscillation circuit 363. Figure 6 Although not shown in the figure, according to the above-mentioned embodiment, the voltage-current converter 361 may include a resistor circuit including a plurality of resistors, the oscillation circuit 363 may include a capacitor circuit including a plurality of capacitors, and the resistance value of the resistor circuit and the capacitance value of the capacitor circuit may be adjusted based on the control information Ctrl_J. The voltage-current converter 361 may adjust the level of the current based on the change of the resistance value, and thus may be referred to as a resistive voltage-current converter.

[0070] According to an example embodiment, the clock generator 300 may include a frequency divider ( / M) 310 that divides the input clock Fin by M to generate a first reference clock Fref, and a frequency multiplier 320 that multiplies the frequency of the first reference clock Fref. According to an embodiment, the frequency multiplier 320 may include a duty cycle correction (DCC) circuit and a dual pulse generator (DPG). Figure 6, an example in which the frequency multiplier 320 increases the frequency of the first reference clock Fref by two times to generate the second reference clock 2Fref is shown. However, this is only an example, and the multiple increased by the frequency multiplier 320 may be more than two times.

[0071] The phase / frequency detector 330 may receive the second reference clock 2Fref from the frequency multiplier 320 and the divided output clock Fout / N from the frequency divider 380, and may generate a detection signal Det based on the phase difference and frequency difference between the second reference clock 2Fref and the divided output clock Fout / N. Figure 6 In the embodiment shown in , the phase / frequency detector 330 may receive the second reference clock 2Fref as an input clock and may perform a phase / frequency detection operation on the second reference clock 2Fref.

[0072] The charge pump 340 may generate a pump output voltage Vcp in response to the detection signal Det, and the loop filter 350 may perform signal processing (e.g., integration processing) based on the pump output voltage Vcp to generate a control voltage Vctrl. In addition, according to the above-described embodiment, the voltage-to-current converter 361 may receive the control voltage Vctrl to generate an internal current Iv corresponding to the control voltage Vctrl, and the DAC 362 may generate a first current βIv proportional to the internal current Iv based on the internal current Iv and a control bit (e.g., a 6-bit digital signal), and may provide the first current βIv to the oscillation circuit 363. That is, in Figure 6 In the embodiment shown in , the oscillation circuit 363 may receive the first current βIv as the internal current according to the above-described embodiment, and may generate an output clock Fout corresponding to the internal current.

[0073] According to an example embodiment, the voltage-current converter 361 may also generate a second current αIv proportional to the internal current Iv, and the generated second current αIv may be provided as a pump current Icp used by the charge pump 340. For example, in the operation of the clock generator 300, the level of the current used by the charge pump 340 may vary based on various factors such as a source voltage and a temperature variation (or a process voltage temperature (PVT) variation), and the second current αIv reflecting the PVT variation may be provided to the charge pump 340 by the voltage-current converter 361, thereby compensating for the variation in current.

[0074] exist Figure 6, an example in which the control information Ctrl_J(3b) has a value of 3 bits and is provided to the voltage-current converter 361 and the oscillation circuit 363 is shown, but this is only an example, and the embodiment is not limited thereto. For example, as described above, different control information may be provided to the voltage-current converter 361 and the oscillation circuit 363. Based on the number of switches provided in each of the voltage-current converter 361 and the oscillation circuit 363, the different control information provided to the voltage-current converter 361 and the oscillation circuit 363 may have the same number of bits or different numbers of bits.

[0075] According to an example embodiment, the clock generator 300 may further include an AFC circuit 370 that generates a control bit 6b corresponding to the above-mentioned digital control bit and provides the control bit 6b to the DAC 362. The AFC circuit 370 may receive a feedback signal Fafc associated with AFC from the frequency divider 380, may receive the above-mentioned second reference clock 2Fref, and may generate the above-mentioned control bit 6b based on a result obtained by comparing the feedback signal Fafc with the second reference clock 2Fref. For example, the AFC circuit 370 may generate the control bit 6b for setting the β value of the first current βIv output from the DAC 362 to compensate for a change in the internal current Iv caused by a deviation in a manufacturing process performed on the clock generator 300.

[0076] According to an example embodiment, the clock generator 300 may further include a spread spectrum clock controller 390, and the spread spectrum clock controller 390 may be configured to reduce the effect of electromagnetic interference (EMI) on adjacent circuits. The spread spectrum clock controller 390 may include a spread spectrum clock generator (SSC) and a delta-sigma modulator (DSM), and may provide information for controlling a division rate of the divider 380 to the divider 380. For example, the spread spectrum clock controller 390 may provide information to the divider 380 so that the output clock Fout is divided at a division rate selected from a plurality of integer division rates. When the integer division rate varies for each cycle, the average division rate of the divider 380 may be adjusted in units of prime numbers.

[0077] The following will describe Figure 6 The operating characteristics of the clock generator 300 of the configuration embodiment of the clock generator 300 shown in FIG.

[0078] The loop bandwidth of the clock generator 300 may be determined based on the overall noise characteristics, and in particular, for high jitter characteristics, it may be necessary to maintain an optimized loop bandwidth based on process and PVT variations. For example, the loop bandwidth may be maintained by continuously monitoring the control voltage Vctrl based on a phase / frequency comparison. The internal current Iv generated by the voltage-to-current converter 361 by reflecting the PVT variations therein may be provided to the charge pump 340 and the oscillation circuit 363 based on the mirror factors (e.g., α and β), and thus may be determined as a unit current of each of the charge pump 340 and the oscillation circuit 363. Despite the PVT changes, the loop bandwidth may be maintained in proportion to the first reference clock Fref based on the unit current in which the mirror factor is reflected.

[0079] As described above, since the AFC circuit 370 is included in the clock generator 300, the mismatch of the pump current of the charge pump 340 can be minimized by compensating for the error of the voltage-current variation characteristic. Since the frequency multiplier 320 including the DCC circuit and the DPG circuit is applied to the clock generator 300, the spur corresponding to the jitter type can be reduced by minimizing the duty cycle variation of the input clock Fin of the clock generator 300. Since the second reference clock 2Fref having a frequency increased by the frequency multiplier 320 is used, the in-band noise can be reduced, and further, the quantization noise occurring in the delta-sigma modulation process can be prevented.

[0080] Figure 7 is a diagram showing a method according to an example embodiment Figure 6 A circuit diagram of an implementation example of VCO 360 is shown in FIG. Figure 7 , an implementation example of each of a voltage-to-current converter 361, a digital-to-analog converter (DAC) 362, and an oscillation circuit 363 is shown as an element of a VCO 360, and an AFC circuit 370 for providing a control bit 6b to the VCO 360 is further shown.

[0081] Reference Figure 6 and Figure 7, the voltage-current converter 361 may include an amplifier 361_1, which receives the control voltage Vctrl through one of its input terminals and is connected to the output of the voltage-current converter 361 through another input terminal. The voltage-current converter 361 may also include one or more first transistors 361_2 and a resistor circuit 361_3, the one or more first transistors 361_2 are connected to the output of the amplifier 361_1, and one end of the one or more first transistors 361_2 is commonly connected to the resistor circuit 361_3. That is, one end of each first transistor 361_2 is connected to the resistor circuit 361_3. The resistor circuit 361_3 may include a plurality of resistors Rc, Rc / 2, and Rc / 4 arranged in parallel and a plurality of first switches S11 to S13 corresponding to the resistors Rc, Rc / 2, and Rc / 4, respectively. The switching state of each of the first switches S11 to S13 may be controlled based on the above-mentioned control information Ctrl_J, and therefore, the resistance value (e.g., equivalent resistance value Req) of the resistor circuit 361_3 may vary. For example, resistors Rc, Rc / 2, and Rc / 4 may be arranged in parallel. When all first switches S11 to S13 are turned on, the equivalent resistance value Req may be a minimum value, and based on the control information Ctrl_J, when at least one of the first switches S11 to S13 is turned off, the equivalent resistance value Req may increase relative to the minimum value.

[0082] The output from the amplifier 361_1 may be provided to the gate electrode of each first transistor 361_2, and an internal current Iv having a level based on the switching state of each of the first switches S11 to S13 may be generated. The level of the internal current Iv may be determined based on the control voltage Vctrl and the equivalent resistance value Req, and thus the level of the internal current Iv may be adjusted based on the value of the control information Ctrl_J. That is, when the equivalent resistance value Req increases based on the switching state of each of the first switches S11 to S13, the level of the internal current Iv may decrease, and when the equivalent resistance value Req decreases, the level of the internal current Iv may increase, thereby adjusting the power consumption and jitter having a trade-off relationship in the clock generator 300.

[0083] The DAC 362 may include a plurality of second transistors connected to the output of the voltage-current converter 361, and further, the DAC 362 may include a plurality of switches turned on / off according to control based on the control bit 6b from the AFC circuit 370. For example, the first transistor 361_2 of the voltage-current converter 361 and the second transistor of the DAC 362 may configure a current mirror, and the DAC 362 may generate a first current βIv having a level proportional to the internal current Iv. The level of the first current βIv may be adjusted based on the number of switches turned on in response to the control bit 6b from the AFC circuit 370.

[0084] The oscillation circuit 363 may include a plurality of delay units 363_1 to 363_3, and each of the plurality of delay units 363_1 to 363_3 may receive a first current βIv as a bias current (or supply current). The delay amount of each of the delay units 363_1 to 363_3 may be adjusted based on the level of the first current βIv corresponding to the bias current. That is, the frequency value of the output clock Fout output from the oscillation circuit 363 may vary based on the delay amount of each of the delay units 363_1 to 363_3. The resistance value of the resistor circuit 361_3 of the above-mentioned voltage-current converter 361 may affect the frequency value of the output clock Fout output from the oscillation circuit 363.

[0085] According to an example embodiment, each of the delay units 363_1 to 363_3 may include a load having a size that can be adjusted, for example, each of the delay units 363_1 to 363_3 may include a plurality of capacitors and a plurality of second switches respectively corresponding to the plurality of capacitors. The connection state of the capacitor of each of the delay units 363_1 to 363_3 may be controlled based on the value of the control information Ctrl_J, and thus, the capacitance value of each of the delay units 363_1 to 363_3 may be adjusted.

[0086] As in the above-described embodiment, the clock generator 300 can generate an output clock Fout having the same frequency and different jitter characteristics, and therefore, the capacitance value of the oscillation circuit 363 can be adjusted based on a change in the resistance value of the resistor circuit 361_3 of the voltage-current converter 361. For example, when the level of the first current βIv increases due to a decrease in the resistance value of the resistor circuit 361_3, the capacitance value of the oscillation circuit 363 can be adjusted to have a relatively large value, and when the level of the first current βIv decreases due to an increase in the resistance value of the resistor circuit 361_3, the capacitance value of the oscillation circuit 363 can be adjusted to have a relatively small value. Figure 7 In the embodiment of , for simplicity, only one equivalent capacitance value Ceq based on one delay unit is shown, and for convenience of description, the capacitor forming the equivalent capacitance value Ceq is shown as being outside the delay unit. However, the capacitor may be described as being provided in the delay unit. According to an example embodiment, the oscillation circuit 363 may generate an output clock Fout including a differential signal, and a configuration in which a capacitor operating as a buffer capacitor is provided in addition to the capacitor of the delay unit is shown.

[0087] Figure 8 is a diagram showing a method according to an example embodiment Figure 7 A circuit diagram of an implementation example of a delay unit. Figure 8, an implementation example of the first delay unit 363_1 is shown, but each of the delay units 363_1 to 363_3 may be implemented as having Figure 8 Same configuration as shown in .

[0088] Reference Figures 6 to 8 According to one embodiment, the first delay unit 363_1 may receive a first current βIv as a supply current, and the first delay unit 363_1 may include two or more transistors T11 and T12, a plurality of transistors configuring a differential amplifier DA, and a capacitor block CB. The first delay unit 363_1 may receive differential inputs Vin and Vip to generate differential outputs Vop and Von corresponding to the differential inputs Vin and Vip. The differential outputs Vop and Von may be provided as inputs to another adjacent delay unit, and a differential output of one of the plurality of delay units 363_1 to 363_3 may correspond to the above-mentioned output clock Fout.

[0089] According to an example embodiment, Figure 8 As shown in , the capacitor block CB may include a plurality of capacitors 1Cc, 2Cc, and 4Cc and a plurality of second switches S21 to S23 and S31 to S33, and the switching of the second switches S21 to S23 and S31 to S33 may be controlled based on the above-mentioned control information Ctrl_J. As an operation example, when the second switches S21 to S23 and S31 to S33 are turned on, the plurality of capacitors 1Cc, 2Cc, and 4Cc may be connected in parallel to each other, and thus, the equivalent capacitance value Ceq may be increased. On the other hand, when one or more of the second switches S21 to S23 and S31 to S33 are turned off, the number of capacitors electrically connected to each other may be reduced, and thus, the equivalent capacitance value Ceq may be reduced.

[0090] In order to maintain a constant frequency of the output clock Fout, it may be necessary to reduce the equivalent capacitance value Ceq of each of the plurality of capacitors 1Cc, 2Cc, and 4Cc based on an increase in the resistance value of the resistor circuit 361_3. Figure 7 and Figure 8 In the circuit configuration shown in , when the control information Ctrl_J having the same bit value is applied to the resistor circuit 361_3 and the first delay unit 363_1, in the case where the resistance value of the resistor circuit 361_3 increases, the equivalent capacitance value Ceq may decrease, and in the case where the resistance value of the resistor circuit 361_3 decreases, the equivalent capacitance value Ceq may increase. For example, referring to Figure 7 and Figure 8, when all the first switches S11 to S13 and the second switches S21 to S23 and S31 to S33 are turned on, the equivalent resistance value Req may be a minimum value (e.g., Rc / 7), and based on this, the equivalent capacitance value Ceq may be a maximum value (e.g., 7Cc). On the other hand, when only the first switch S11 is turned on, the equivalent resistance value Req may be a maximum value (e.g., Rc), and when only the second switches S21 and S31 are turned on, based on this, the equivalent capacitance value Ceq may be a minimum value (e.g., 1Cc). In addition, although each of the equivalent resistance value Req and the equivalent capacitance value Ceq varies, the value obtained by multiplying the equivalent resistance value Req and the equivalent capacitance value Ceq may be constant, and therefore, the frequency value of the output clock Fout may be kept constant.

[0091] The configuration of the resistor circuit 361_3, the capacitor block CB and the switch according to the embodiment can be implemented as various types. That is, the circuit can be configured so that the frequency value of the output clock Fout is kept the same or constant within a specific range, and the equivalent capacitance value Ceq is reduced based on the increase of the equivalent resistance value Req, and the equivalent capacitance value Ceq is increased based on the decrease of the equivalent resistance value Req. For example, the number and connection relationship of the resistor and the capacitor can be implemented differently, and the circuit can be implemented so that the desired equivalent resistance value Req and the desired equivalent capacitance value Ceq are set based on the control information Ctrl_J. For example, the resistor of the resistor circuit 361_3 and the capacitor of the capacitor block CB can be connected in series or in parallel, or can be realized by a combination of series connection and parallel connection. In addition, different control information can be provided to the resistor circuit 361_3 and the capacitor block CB, and can have different bit values ​​or different numbers of bits.

[0092] Can provide reference Figures 6 to 8 The clock generator 300 configured in the described manner can therefore reconfigure jitter characteristics and power consumption characteristics based on the trade-off relationship between noise and power. For example, the amplitude of jitter L(f) in the frequency domain can be expressed as the following equation (1).

[0093] [Equation 1]

[0094]

[0095] As shown in equation (1), the jitter L(f) in the frequency domain may have a relationship with the Boltzmann constant k, the temperature T, the source voltage V applied to the transistor of the oscillation circuit 363, and the DD , threshold voltage V th, the target frequency fo, the first current βIv and the value associated with the constant η related to the noise factor of the manufacturing process. Therefore, when the target frequency fo is the same, the amplitude of the jitter L(f) may have a value inversely proportional to the level of the first current βIv. To this end, in the case of performing a charge / discharge operation of a capacitor based on a metal oxide semiconductor (MOS) transistor and an oscillation circuit 363, when the level of the current applied to the transistor is high, although the target frequency fo is the same, the thermal resistance may be reduced, and due to this, the jitter may be reduced. In addition, the reconfiguration of each of the jitter and power consumption of the clock generator 300 can be controlled by passive elements, and therefore, the output frequency can be relatively less affected by temperature changes.

[0096] Fig. 9 and Fig.10 is a timing diagram showing an example of operation of a clock generator according to an example embodiment. Fig. 9 and Fig.10 In the example, the clock generator can be connected with Figures 1 to 8 The clock generator of the above-described embodiment corresponds to, and may be assumed to include, a phase-locked loop (PLL).

[0097] Reference Fig. 9 and Fig.10 , the clock generator may be enabled (PLL enabled), and may receive an input clock to generate an output clock Fout having a target frequency. When the output clock Fout reaches the target frequency, the clock generator may have a locked state (Lock). In a state where the clock generator is locked, control information Ctrl_J for adjusting the jitter characteristics and power characteristics of the clock generator may be provided to the clock generator, and based on the value of the control information Ctrl_J, the jitter (Jitter) of the output clock Fout may be adjusted and the power (Power) consumed by the clock generator may be adjusted.

[0098] For example, the control information Ctrl_J may include digital information having a plurality of bits, and based on the values ​​Val_1 to Val_7 of the control information Ctrl_J, the level of the supply current (or internal current) provided to the oscillation circuit may vary, and the capacitance value for adjusting the delay amount of the delay unit may vary. Fig. 9 and Fig.10 , an example is shown in which as the value of the control information Ctrl_J changes from Val_7 to Val_1, the resistance value increases (or the power consumption decreases), and based on this, the capacitance value decreases.

[0099] When adjusting the jitter characteristics and power characteristics of the clock generator according to the example embodiment, the enable state (PLL enable) may be maintained without adjusting the on / off of the clock generator, and further, the jitter characteristics and power characteristics may be adjusted without releasing the lock state. Fig. 9In FIG. 1 , an example is shown in which the jitter (Jitter) increases incrementally and the power consumption (Power) decreases incrementally as the value of the control information Ctrl_J decreases step by step. Fig.10 , an example is shown in which, when the jitter requirement of a digital block provided with an output clock Fout changes or the digital block provided with the output clock Fout changes, the jitter (Jitter) increases or decreases over time, and accordingly the power (Power) decreases or increases over time.

[0100] FIG. 11A to FIG. 11D is a circuit diagram showing an operation example of controlling various switches of an oscillation circuit based on control information. FIG. 11A to FIG. 11D In the description, only the resistor circuit and the delay unit are shown for the convenience of description. FIG. 11A to FIG. 11D When the configuration of each of the resistor circuit and the delay unit shown in , the same description as that of the above-mentioned embodiment is omitted.

[0101] Reference Fig.11A and Fig. 11B , the first switches S11 to S13 of the resistor circuit and the second switches S21 to S23 and S31 to S33 of the capacitor circuit may be controlled in response to the 3-bit control information Ctrl_J, for example, the 3-bit control information Ctrl_J may be commonly provided to the resistor circuit and the delay unit. Fig.11A As shown in FIG. 1 , in response to the control information Ctrl_J “111”, all the first switches S11 to S13 and the second switches S21 to S23 and S31 to S33 may be turned on, and the plurality of resistors Rc, Rc / 2, and Rc / 4 of the resistor circuit may be electrically connected to each other, and thus, the equivalent resistance value may be reduced. In addition, the plurality of capacitors 1Cc, 2Cc, and 4Cc of the capacitor circuit may be electrically connected to each other, and thus, the capacitance value may be increased. That is, the capacitance value may be increased based on the decrease in the resistance value to maintain a constant frequency.

[0102] like Fig. 11B As shown in FIG. 1 , in response to the control information Ctrl_J “001”, only the switch S11 among the first switches S11 to S13 may be turned on, and the switches S21 and S31 among the second switches S21 to S23 and S31 to S33 may be turned on. Fig.11A The connection status shown in the changes to Fig. 11B, the number of resistors connected in parallel to each other can be reduced, so the equivalent resistance value can be increased, and based on this, the capacitance value can be reduced, so the frequency can be kept constant and the jitter can be changed. Similarly, in response to the control information Ctrl_J "011", S11 and S12 of the first switches S11 to S13 can be turned on, and switches S21, S22, S31, S32 of the second switches S21 to S23 and S31 to S33 can be turned on, and so on. The correspondence between the bits of the control information Ctrl_J and the switches is only an example, and different correspondences may be provided. In other words, according to another example, Ctrl_J "100" may correspond to S11, S21, and S31 being turned on, rather than "001" as discussed above.

[0103] Fig. 11C and Fig.11D An example is shown in which a resistor circuit and a capacitor circuit of an oscillation circuit are controlled based on different control information.

[0104] Reference Fig. 11C , the capacitor of the capacitor circuit can be Fig.11A and 11B The elements shown in are the same. Therefore, the capacitor circuit can receive 3-bit second control information Ctrl_JC, and the capacitance value of the capacitor circuit can vary in the range from 1Cc to 7Cc based on the connection state of multiple capacitors 1Cc, 2Cc and 4Cc connected to multiple second switches S21 to S23 and S31 to S33. The resistor circuit can receive multiple bits (for example, 7 bits) of first control information Ctrl_JR, and the resistance value of the resistor circuit can vary in the range from Rc to Rc / 7 based on the connection state of multiple resistors Rc to Rc / 7 connected in parallel to each other to multiple first switches S11 to S17, and the multiple first switches S11 to S17 are set based on multiple resistors Rc to Rc / 7. For example, a switch corresponding to an arbitrary resistor can be selectively turned on based on the capacitance value of the capacitor circuit, and in addition, the value obtained by multiplying the resistance value by the capacitance value can be kept constant. In Fig. 11C , an example is shown in which the capacitance value corresponds to 2Cc and only the first switch S12 is selectively turned on in the resistor circuit.

[0105] Fig.11DThe case where a plurality of resistors Rc to Rc / 7 of the resistor circuit are connected in series with each other and one of the plurality of resistors Rc to Rc / 7 can be selectively applied to obtain a resistance value is shown. For example, when the capacitance value of the capacitor circuit corresponds to 2Cc, only the first switch S12 set based on the resistor Rc / 2 can be selectively disconnected, and the other switches S11 and S13 to S17 can be turned on. In other words, the resistance value can be changed by various switching methods, and the value obtained by multiplying the resistance value by the capacitance value can be kept constant.

[0106] The embodiments are not limited to Fig. 11C and Fig.11D The configuration shown in the embodiment is contemplated, and various modifications of the embodiment are contemplated. That is, the jitter and power can be reconfigured by controlling the connection states of resistors having different sizes and capacitors having different sizes connected to switches corresponding thereto. The numbers of resistors and capacitors can be changed differently, respectively, and therefore, the jitter and power can be reconfigured in more detail (i.e., with finer granularity).

[0107] Fig.12 is a circuit diagram showing a clock generator 400 according to a modified embodiment. Fig.12 In FIG. 5 , an implementation example of a VCO included in a clock generator is shown.

[0108] The clock generator 400 may include a VCO, and the VCO may include a voltage-current converter 410, a digital-to-analog converter (DAC) 420, and an oscillation circuit 430. The voltage-current converter 410 may include an amplifier, one or more first transistors, and a resistor circuit, which may include a plurality of resistors Rc, Rc / 2, and Rc / 4 arranged in parallel and a plurality of switches corresponding thereto. The DAC 420 may include a plurality of second transistors that construct a current mirror together with the plurality of first transistors, and the oscillation circuit 430 may include a plurality of delay units.

[0109] exist Fig.12 In the embodiment of , an example is shown in which each of the first transistor and the second transistor is implemented as an N-channel MOS (NMOS) transistor, and therefore, a plurality of resistors Rc, Rc / 2, and Rc / 4 may be provided in parallel between the source voltage terminal and one node of each first transistor. A first current βIv having a level proportional to the internal current Iv may be generated by the DAC 420, and the first current βIv may flow through a path passing through the oscillation circuit 430, the second transistor, and the source voltage terminal. Fig.12In the embodiment of the present invention, an implementation example of the delay unit is not shown, but the transistors included in the delay unit may be implemented as P-channel MOS (PMOS) transistors, NMOS transistors, or a combination thereof. That is, the clock generator 400 according to an example embodiment may be designed as various types based on the type of transistors.

[0110] Fig.13 is a block diagram illustrating a system 500 including a clock generator according to an example embodiment.

[0111] Fig.13 The system 500 shown in the figure may be one of various electronic devices. When the system 500 corresponds to a mobile device, the system 500 may be one of various electronic devices such as a mobile phone, a smart phone, a tablet personal computer (PC), a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, and a navigation system.

[0112] The system 500 may include a clock generator 510 implemented according to the above-described embodiment, and may further include various elements such as a radio frequency integrated circuit (RFIC) 520, an application processor 530, a communication processor 540, an image sensor 550, and a smart card 560. However, this is merely an embodiment, and the system 500 may include only some of the elements or may further include other elements. Fig.13 , the clock generator 510 is shown as being commonly provided in the above-mentioned elements, but based on the elements, the clock generator 510 according to one embodiment may be individually provided. In other words, in some embodiments, the clock generator 510 may provide a clock only to a portion of each element 520 to 560, and a separate clock generator (not shown) may be provided to provide a clock to the remaining portion of each element 520 to 560, and so on. According to one embodiment, the clock generator 510 may provide an output clock to one or more elements 520 to 560. Optionally, a plurality of elements 520 to 560 may use the clock generator 510 in a time-division manner, and thus, the clock generator 510 may sequentially provide an output clock to a plurality of elements 520 to 560. As an operation example, in Fig.13 2 shows an example in which the first to fifth output clocks CLK1 to CLK5 generated by the clock generator 510 are provided to the RFIC 520 , the application processor 530 , the communication processor 540 , the image sensor 550 , and the smart card 560 , respectively.

[0113] Each of the RFIC 520, the application processor 530, the communication processor 540, the image sensor 550, and the smart card 560 may include a plurality of processing blocks for performing signal processing by using a corresponding output clock among the first output clock CLK1 to the fifth output clock CLK5, and may include, for example, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), an interface block, a digital block, a modem block, and a radio frequency (RF) block. Each of the first output clock CLK1 to the fifth output clock CLK5 may be generated to be optimized for the frequency and jitter characteristics required by the corresponding elements in the RFIC 520, the application processor 530, the communication processor 540, the image sensor 550, and the smart card 560, for example, the first clock CLK1 and the second clock CLK2 may have the same frequency and different jitter characteristics. At least one of the first output clock CLK1 to the fifth output clock CLK5 may have a specific frequency but have a jitter characteristic that varies with time.

[0114] Fig.14 6 is a block diagram illustrating a wireless communication device 600 including a clock generator according to an example embodiment. The wireless communication device 600 may include an antenna 640, and may transmit or receive a signal through the antenna 640 to communicate with a target device. In a non-limiting embodiment, a wireless communication system for the wireless communication device 600 to communicate with a target device may be a wireless communication system using a cellular network (such as a fifth generation (5G) wireless system, an LTE system, an advanced LTE system, a code division multiple access (CDMA) system, or a global system for mobile communications (GSM) system), or may be a wireless local area network (WLAN) system or another arbitrary wireless communication system.

[0115] According to an implementation embodiment, the wireless communication device 600 may include a signal processor 610, a transceiver 620, and a transmit / receive duplexer 630. The transmit / receive duplexer 630 may provide a signal received through an antenna 640 as an RF input signal RFin to the transceiver 620, and may provide an RF output signal RFout received from the transceiver 620 to the antenna 640.

[0116] The signal processor 610 may process a baseband transmission / reception signal. According to an implementation embodiment, the signal processor 610 may include a control logic 611, and the control logic 611 may control the transceiver 620. For example, the control logic 611 may output the control information Ctrl_J according to the above embodiment.

[0117] The transceiver 620 may include a transmitter 621, a receiver 622, and a clock generator 623, and a PLL is described as an example of the clock generator 623. The transceiver 621 may process a transmit input signal received from the signal processor 610 to generate an RF output signal RFout. As shown, the transmitter 621 may include a variable gain amplifier (VGA), a TX filter, a TX mixer 621_1, and a power amplifier (PA) to process the transmit input signal TXin. The receiver 622 may process the RF input signal RFin to generate a receive input signal RXin, and may provide the receive input signal RXin to the signal processor 610. The receiver 622 may include a low noise amplifier (LNA), an RX mixer 622_1, a VGA, and an RX filter to process the RF input signal RFin.

[0118] The clock generator 623 may generate an output clock having a frequency for sampling the transmission input signal TXin and the reception input signal RXin, and may provide the output clock to the TX mixer 621_1 and the RX mixer 622_1. The clock generator 623 may include the clock generator according to the above-described embodiment, and may generate an output clock having a jitter characteristic adjusted based on the control information Ctrl_J. Fig.14 , an example in which the control information Ctrl_J is provided from the signal processor 610 is shown, but the embodiment is not limited thereto. For example, the control information Ctrl_J may be generated in the transceiver 620, or may be generated by another control circuit provided outside the transceiver 620.

[0119] Fig.15 is a block diagram illustrating an application processor (AP) 700 including a clock generator according to example embodiments. Fig.15 The AP 700 may include modem circuitry and thus may be referred to as a ModAP.

[0120] Reference Fig.15 , the AP 700 may be implemented as a system on chip (SoC) and may include various types of circuit blocks. For example, the AP 700 may include a central processing unit (CPU) 710, a phase-locked loop (PLL) 720, and an internal memory 730. The AP 700 may also include a modem circuit 740 and a global navigation satellite system circuit (GNSS circuit) 750, and may include a near field communication circuit (NFC circuit) 760 as an example of a module for performing different kinds of communications. In addition Fig.15 In addition to the elements shown in FIG. 7 , the AP 700 may further include various communication modules including WLAN and BT.

[0121] The CPU 710 may execute various programs to control the functions of the application processor 700. In addition, the internal memory 730 may store various programs for controlling the operation of the AP 700, and the programs may be executed by various processors such as the CPU 710, a processor (not shown) included in the modem circuit 740, and a processor (not shown) included in the GNSS circuit 750.

[0122] The PLL 720 may correspond to a clock generator according to the above-described embodiment, and may provide an output clock to the modem circuit 740, the GNSS circuit 750, and the NFC circuit 760. For example, according to the above-described embodiment, the PLL 720 may change the jitter of the output clock by using control information (not shown) for adjusting jitter and power, and the control information may be generated by a control operation of the AP 700. Fig.15 , one PLL 720 is shown as being included in the AP 700 , but a plurality of PLLs may be included in the AP 700 .

[0123] For example, to describe one circuit block (e.g., a first circuit block) among the circuit blocks included in the AP 700, the PLL 720 may provide the first circuit block with a clock signal (or output clock) having a first jitter characteristic generated based on a first power consumption in a first operation mode of the AP 700 or a system including the AP 700. When the first operation mode is changed to a second operation mode, the PLL 720 may provide the first circuit block with a clock signal having a second jitter characteristic generated based on the second power consumption without releasing the locked state. In the first operation mode and the second operation mode, the frequency of the clock signal may be kept constant, and when the power consumption is relatively large in the first operation mode, the jitter of the clock signal may have a relatively small amplitude.

[0124] When the PLL 720 is shared by the first circuit block and the second circuit block, the clock signals provided to the first circuit block and the second circuit block may have the same frequency and different jitter characteristics. The first circuit block and the second circuit block may use the PLL 720 based on a time division method, and when the circuit block receiving the clock signal from the PLL 720 is changed from the first circuit block to the second circuit block, the PLL 720 may generate a clock signal with different jitter characteristics without releasing the locked state, and may provide the generated clock signal to the second circuit block.

[0125] In a clock generator, a semiconductor device including the clock generator, and an operating method of the clock generator according to an embodiment, clock signals having various frequencies can be generated by using a single clock generator, and a clock signal optimized for the jitter specification required by a digital block can be generated, thereby effectively reducing power consumption.

[0126] In addition, in a clock generator, a semiconductor device including the clock generator, and an operating method of the clock generator according to the embodiments, jitter characteristics and power consumption can be adjusted without controlling or releasing the on / off operation of the clock generator, thereby reducing unwanted time consumption and power consumption.

[0127] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A clock generator, wherein the clock generator maintains the frequency value of an output clock and changes the jitter characteristics of the output clock in response to first control information and second control information, wherein the clock generator include: a phase detector configured to: detect a phase difference between an input clock and a signal obtained by dividing the output clock; a voltage generator configured to: generate a control voltage having a level based on the phase difference; a voltage-to-current converter including a resistor circuit including a plurality of resistors, the voltage-to-current converter being configured to: convert a control voltage into an internal current having a level based on a resistance value of the resistor circuit, the resistance value being set based on first control information; as well as An oscillation circuit includes a capacitor circuit including a plurality of capacitors, the oscillation circuit generating an output clock having a frequency based on a level of the internal current and a capacitance value of the capacitor circuit, the capacitance value being set based on second control information.

2. The clock generator according to claim 1, in, The resistor circuit further includes a plurality of first switches arranged corresponding to the plurality of resistors, and the capacitor circuit further includes a plurality of second switches arranged corresponding to the plurality of capacitors, and When switching of the plurality of first switches is controlled in response to first control information, a resistance value is set, and when switching of the plurality of second switches is controlled in response to second control information, a capacitance value is set.

3. The clock generator according to claim 2, in, When the resistance value of the resistor circuit is set low, the jitter of the output clock is low, and when the resistance value of the resistor circuit is set high, the jitter of the output clock is high.

4. The clock generator according to claim 1, in, The first control information and the second control information have the same bit value.

5. The clock generator according to claim 1, in, The phase detector is a phase / frequency detector configured to detect a phase difference and a frequency difference between an input clock and a signal obtained by frequency-dividing an output clock.

6. The clock generator according to claim 1, further comprising: include: a digital-to-analog converter connected to the output of the voltage-to-current converter to generate a first current having a level proportional to the internal current from the voltage-to-current converter in response to receiving a control bit, The oscillation circuit is configured to receive a first current from a digital-to-analog converter as a supply current.

7. The clock generator according to claim 6, further comprising: include: The automatic frequency control circuit is configured to generate a control bit by monitoring an output clock or by monitoring a signal obtained by dividing the output clock, and provide the control bit to the digital-to-analog converter.

8. The clock generator according to claim 1, further comprising: include: a frequency multiplier configured to: receive an input clock and multiply the frequency of the input clock to generate a reference clock, Therein, the reference clock from the frequency multiplier is provided as the input of the phase detector.

9. The clock generator according to claim 1, in, The voltage-to-current converter also includes: an amplifier including a first input terminal connected to a control voltage and a second input terminal connected to an output terminal of the voltage-to-current converter; and one or more first transistors configured to be turned on in response to an output of the amplifier to generate the internal current, and The resistor circuit further includes a plurality of first switches arranged corresponding to the plurality of resistors, the plurality of first switches being connected to one end of each of the one or more first transistors and being controlled to be turned on or off according to first control information.

10. The clock generator according to claim 9, further comprising: include: A digital-to-analog converter comprises one or more second transistors which together with the one or more first transistors form a current mirror, and one or more second switches respectively corresponding to the one or more second transistors, wherein the digital-to-analog converter outputs a first current having a level proportional to the internal current according to the switching state of the one or more second switches.

11. The clock generator according to claim 10, in, The oscillation circuit includes a plurality of delay units, each of the plurality of delay units receiving a first current as a supply current, and Each of the plurality of delay units includes a capacitor circuit including the plurality of capacitors and a plurality of third switches arranged corresponding to the plurality of capacitors, and switching of the plurality of third switches is controlled in response to second control information.

12. A semiconductor device, include: A clock generator configured to: receive an input clock to generate an output clock having a target frequency; as well as The control logic is configured to: output control information for controlling the jitter characteristic of the output clock of the clock generator, The clock generator includes: a voltage-controlled oscillator configured to generate an output clock having a frequency based on a control voltage, the control voltage being generated based on a phase difference between an input clock and a signal obtained by dividing the output clock, and When receiving control information having a first value, the voltage-controlled oscillator is configured to generate an output clock having a target frequency and a first jitter, and when receiving control information having a second value, the voltage-controlled oscillator is configured to generate an output clock having a target frequency and a second jitter, wherein the first jitter is smaller than the second jitter.

13. The semiconductor device according to claim 12, in, The control logic is configured to: provide control information having a first value to the clock generator in a first mode, and provide control information having a second value to the clock generator in a second mode, and The target frequency is constant in the first mode and the second mode.

14. The semiconductor device according to claim 13, in, The first mode corresponds to a high power mode, the first value has a value for reducing jitter of the output clock, and the second mode corresponds to a low power mode, and the second value has a value for increasing jitter of the output clock.

15. The semiconductor device according to claim 12, in, The voltage controlled oscillator includes: A voltage-to-current converter including a resistor circuit including a plurality of resistors, the voltage-to-current converter being configured to: convert a control voltage into an internal current, and adjust a resistance value of the resistor circuit based on control information to adjust a level of the internal current; and An oscillation circuit includes a capacitor circuit including a plurality of capacitors, the oscillation circuit being configured to generate an output clock based on a supply current, and to adjust a capacitance value of the capacitor circuit based on control information to adjust a frequency of the output clock.

16. The semiconductor device according to claim 15, in, The voltage controlled oscillator further includes a digital-to-analog converter connected to the output of the voltage-to-current converter to generate a first current having a level proportional to an internal current from the voltage-to-current converter in response to receiving a control bit, and The oscillation circuit is configured to receive a first current as a supply current and generate an output clock having a frequency based on a level of the first current and a capacitance value.

17. The semiconductor device according to claim 15, in, The resistor circuit includes: a plurality of first switches arranged corresponding to the plurality of resistors, The capacitor circuit includes: a plurality of second switches arranged corresponding to the plurality of capacitors, and The plurality of first switches and the plurality of second switches are controlled based on control information.

18. The semiconductor device according to claim 17, in, In response to the control information, when the resistance value of the resistor circuit decreases, the capacitance value of the capacitor circuit increases, and when the resistance value of the resistor circuit increases, the capacitance value of the capacitor circuit decreases.

19. A system on a chip, include: a clock generator configured to generate a clock signal; as well as A plurality of circuit blocks are configured to receive a clock signal from a clock generator, The clock generator is configured to: in a first operation mode of the system on chip, provide a clock signal having a first jitter characteristic and generated at a first power consumption to a first circuit block among the plurality of circuit blocks, and The clock generator is configured to provide a clock signal having a second jitter characteristic and generated at a second power consumption to the first circuit block without releasing a locked state of the clock signal when the first operation mode is changed to the second operation mode.

20. The system on chip according to claim 19, in, In the first operation mode and the second operation mode, the frequency of the clock signal supplied to the first circuit block is kept constant without releasing the locked state of the clock signal.

21. The system on chip according to claim 19, in, The first power consumption is greater than the second power consumption, and the jitter amplitude based on the first jitter characteristic is less than the jitter amplitude based on the second jitter characteristic.

22. The system on chip according to claim 19, in, The clock generator is configured to additionally provide a first clock signal to a second circuit block among the plurality of circuit blocks and to provide a second clock signal to a third circuit block among the plurality of circuit blocks, and The first clock signal and the second clock signal have the same frequency and different jitter characteristics.

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