Fault detection equipment based on 64-channel acoustic signal receiving array

Abstract

The invention discloses a fault detection device based on a 64-channel sound signal receiving array, comprising a shell, a circuit board arranged in the shell, a lens cover arranged on the outer side of the shell, and a sound signal receiving array cover. The circuit board comprises a sound signal receiving array, a driving module, an operational amplifier module, a filtering module, an AD module, a clock frequency division module, an FPGA module, a camera module, a communication module, and a network interface. The sound signal receiving array, the operational amplifier module, and the filtering module are all connected to the driving module. The filtering module, the AD module, the clock frequency division module, the FPGA module, the communication module, and the network interface are connected in sequence. The camera module is connected to the FPGA module. The sound signal receiving array is located on the inner side wall of the shell and close to the sound signal receiving array cover. The camera module is located on the inner side of the shell and close to the lens cover. The advantages of the invention are: automated detection, reduced manpower and material resources, and avoidance of misjudgment and hidden dangers.

Description

Technical Field

[0001] The present invention relates to the field of industrial detection equipment, and more specifically to a fault detection equipment based on a 64-channel acoustic signal receiving array. Background Art

[0002] With the rapid development of science and technology, intelligent industrial equipment and transportation tools have been widely used. These equipment and vehicles have greatly met the needs of people's lives and travel. However, equipment will have operational failures during operation, such as partial discharge of power equipment, train bearing failure, and failure of industrial equipment during operation.

[0003] In response to these faults, many detection methods have emerged in the industry, such as current detection, light measurement, vibration monitoring, etc. However, so far, such detection methods have many problems such as inconvenient layout and incomplete detection. As a result, the detection of many projects is currently completed by professionally trained personnel, and automated monitoring cannot be achieved, which consumes a lot of manpower and material resources. In addition, since it is operated and detected by people, there will be problems such as misjudgment and missed judgment, which will cause hidden dangers. At the same time, the acoustic signal reception uses a separate sensor, which is limited to applicable scenarios. Due to the layout and wiring reasons, the number of sensors set is small and cannot meet the acoustic monitoring of the operating status of large, medium or key electromechanical equipment.

[0004] Chinese patent publication number CN110736906A discloses a multifunctional inspection device, including a main body, a circuit board is arranged inside the main body, a detection head is arranged at the head end of the main body, and the detection head includes a mounting seat that can be plugged with the head end of the main body, a precision adjustment ring rotatably connected to the mounting seat, a frustum detector connected to the mounting seat, a detector support rod arranged along a direction parallel to the axis of the head end of the main body, and an ultrasonic sensor arranged on the detector support rod, and the center of the ultrasonic sensor detection end is opposite to the center of the frustum detector; this patent application can judge the location and fault type of hidden faults without power outage, help inspection personnel accurately find line fault hazards, prevent the occurrence of malignant faults, avoid unnecessary power outages, improve power supply reliability, and also improve the work efficiency of inspection personnel and reduce the labor intensity of inspection personnel. It has the characteristics of light weight, easy to carry, simple operation and flexible application. However, it is unable to realize automatic monitoring, consumes a lot of manpower and material resources, and because it is operated and inspected by humans, there may be problems such as misjudgment and missed judgment, causing hidden dangers. At the same time, the acoustic signal reception uses a separate sensor, which is applicable to limited scenarios, and the small number cannot meet the acoustic monitoring of the operating status of large, medium or key electromechanical equipment. Summary of the invention

[0005] The technical problem to be solved by the present invention is that the fault detection equipment in the prior art cannot realize automatic monitoring, is limited in applicable scenarios, and cannot meet the acoustic monitoring of the operating status of large, medium or key electromechanical equipment.

[0006] The present invention solves the above technical problems through the following technical means: a fault detection device based on a 64-channel acoustic signal receiving array comprises a shell, a circuit board arranged in the shell, a lens cover arranged on the outer side of the shell, and an acoustic signal receiving array cover, the circuit board comprises an acoustic signal receiving array, a driving module, an operational amplifier module, a filtering module, an AD module, a clock frequency division module, an FPGA module, a camera module, a communication module, and a network interface, the acoustic signal receiving array comprises 64 sub-array units, every 8 sub-array units are connected in series to form a group of arrays, and the 64 sub-array units are arranged in an 8*8 array or a cross-shaped array with 32 sub-array units in the horizontal and vertical directions; the acoustic signal receiving array, the operational amplifier module, and the filtering module are all connected to the driving module, the filtering module, the AD module, the clock frequency division module, the FPGA module, the communication module, and the network interface are connected in sequence, the camera module is connected to the FPGA module, the acoustic signal receiving array is located on the inner side wall of the shell and close to the acoustic signal receiving array cover, and the camera module is located on the inner side of the shell and close to the lens cover.

[0007] The present invention designs 64 sub-array units for receiving acoustic signals separately as an independent array. When the device is used in different application scenarios, a suitable acoustic signal receiving array can be selected according to the characteristics of the target acoustic signal to be monitored. In addition, a 64-channel array is designed to realize acoustic monitoring of the operating status of large, medium or key electromechanical equipment. The acoustic signal receiving array receives the signal, and the driving module and the operational amplifier module differentially amplify the received signal to improve the anti-interference ability. The filtering module filters out the interference signal and sends the signal to the AD module. The AD module converts the collected signal into a digital signal and sends it to the FPGA module. The PFGA module performs signal processing, fault identification and positioning and other algorithm processing, and sends the processed result and the image data collected by the camera to the cloud background through the network interface. The direct state of sound is used for monitoring, breaking through the traditional indirect state of monitoring through current and voltage. The whole process realizes automatic monitoring without requiring a lot of manpower and material resources, avoiding misjudgment and missed judgment, and avoiding hidden dangers.

[0008] Furthermore, the sub-array unit is an acoustic sensor or a microphone.

[0009] Furthermore, the acoustic sensor is a MEMS acoustic sensor with a frequency response range of 20 Hz-100 KHz.

[0010] Furthermore, the detection band range of the microphone is 0-100KHz.

[0011] Furthermore, the spacing between the sub-array units ranges from 5 mm to 10 cm.

[0012] Further, the operational amplifier module includes a resistor R389, a resistor R390, a capacitor C140, a capacitor C148, an operational amplifier N65A, a capacitor C150, a resistor R393 and a capacitor C149, one end of the capacitor C140, one end of the capacitor C148, one end of the resistor R389 and the fourth pin of the operational amplifier N65A are all connected to a +5V power supply, one end of the resistor R390, the third pin of the operational amplifier N65A and one end of the capacitor C150 are all connected to the other end of the resistor R389, the second pin of the operational amplifier N65A is connected to the first pin of the operational amplifier N65A, the negative end of the power supply of the operational amplifier N65A is connected to the other end of the capacitor C150 and is grounded, the first pin of the operational amplifier N65A is connected to one end of the capacitor C149 through the resistor R393, and the other end of the capacitor C149, the other end of the capacitor C140, the other end of the capacitor C148 and the other end of the resistor R390 are all grounded.

[0013] Furthermore, the driving module includes a differential amplifier U1, sequentially numbered resistors R200 to R205, a capacitor C200 and a capacitor C201, the model of the differential amplifier U1 is ADA4940-1ARZ, one end of the resistor R200 is connected to a +5V-1# power supply, one end of the capacitor C200, one end of the capacitor C201 and the third pin of the differential amplifier U1 are all connected to the other end of the resistor R200, the second pin of the differential amplifier U1 is connected to one end of the capacitor C149, the fourth pin of the differential amplifier U1 is connected to one end of the resistor R202, and the other end of the resistor R202 is One end of the resistor R201 is connected to the first pin of the differential amplifier U1, and the other end of the resistor R201 is grounded; the fifth pin of the differential amplifier U1 is connected to one end of the resistor R205, the other end of the resistor R205 and one end of the resistor R203 are connected to the eighth pin of the differential amplifier U1, the other end of the resistor R203 is connected to an acoustic sensor in the acoustic signal receiving array through a capacitor, the sixth pin of the differential amplifier U1, the other end of the capacitor C200 and the other end of the capacitor C201 are all grounded, and the seventh pin of the differential amplifier U1 is connected to the +5V-1# power supply through a resistor R204.

[0014] Furthermore, the filtering module includes a capacitor C19, a capacitor C22, a resistor R13, a resistor R14, a resistor R17, a resistor R18, a capacitor C21, a capacitor C20 and a capacitor C25, one end of the capacitor C19 is connected to one end of the resistor R202, one end of the capacitor C22 is connected to one end of the resistor R205, the other end of the capacitor C19 is respectively connected to one end of the resistor R13 and one end of the resistor R14, the other end of the capacitor C22 is respectively connected to one end of the resistor R17 and one end of the resistor R18, the other end of the resistor R14 is connected to the other end of the resistor R17, the other end of the resistor R13 is respectively connected to one end of the capacitor C21 and one end of the capacitor C20, the other end of the resistor R18 is respectively connected to the other end of the capacitor C21 and one end of the capacitor C25, and the other end of the capacitor C20 is connected to the other end of the capacitor C25 and grounded.

[0015] Furthermore, the AD module includes a chip U2, the model of the chip U2 is AD7761BSTZ, the ninth pin of the chip U2 is connected to one end of the capacitor C20, and the tenth pin of the chip U2 is connected to one end of the capacitor C25.

[0016] Furthermore, the FPGA module includes a first processing chip FPGA1, a second processing chip FPGA2 and a third processing chip FPGA3. The DO port, SPI port, SYNC port and STARY port of the first processing chip FPGA1 and the second processing chip FPGA2 are all connected to the corresponding ports of chip U2. The first processing chip FPGA1 and the second processing chip FPGA2 are both connected to the third processing chip FPGA3. The models of the first processing chip FPGA1 and the second processing chip FPGA2 are both AC616, and the model of the third processing chip FPGA3 is AC6045.

[0017] Furthermore, the clock frequency division module includes resistors R30 to R41, a crystal oscillator G1, a capacitor C36, a capacitor C37 and a chip N1 numbered in sequence, the model of the chip N1 is 5PB1110PGG-TSSOP20, one end of the resistor R30 is connected to the power supply 3.3V-CLK, the other end of the resistor R30 is respectively connected to one end of the capacitor C36, one end of the capacitor C37 and the fourth pin of the crystal oscillator G1, the other end of the capacitor C36, the other end of the capacitor C37 and the second pin of the crystal oscillator G1 are all grounded, the third pin of the crystal oscillator G1 is connected to the first pin of the chip N1 through the resistor R31, the second pin, the fifth pin, the ninth pin of the chip N1 and one end of the capacitor C38 are all connected to the power supply 3.3V-CLK, the fourth pin and the seventh pin of the chip N1 are both connected to the other end of the capacitor C38 and grounded The eighth pin, the tenth pin, the twelfth pin, the thirteenth pin, the fifteenth pin, the seventeenth pin, the nineteenth pin and the twentieth pin of the chip N1 are respectively connected to one end of the resistor R38, one end of the resistor R41, one end of the resistor R40, one end of the resistor R39, one end of the resistor R37, one end of the resistor R35, one end of the resistor R33 and one end of the resistor R32, and the other end of the resistor R38, the other end of the resistor R41, the other end of the resistor R40, the other end of the resistor R39, the other end of the resistor R37, the other end of the resistor R35, the other end of the resistor R33 and the other end of the resistor R32 are all connected to the AD interface of the chip U2; the third pin of the chip N1 is connected to the second processing chip FPGA2 through the resistor R34, and the sixth pin of the chip N1 is connected to the first processing chip FPGA1 through the resistor R36.

[0018] Furthermore, the communication module includes a chip N2, sequentially numbered resistors R45 to R63, sequentially numbered capacitors C52 to C62, a crystal oscillator G2, and an inductor L3, one end of the resistor R45 is connected to the power supply 3.3V-LAN, the other end of the resistor R45 is respectively connected to one end of the capacitor C52, one end of the capacitor C53, and the fourth pin of the crystal oscillator G2, the third pin of the crystal oscillator G2 is connected to one end of the resistor R46, and the other end of the resistor R46 is connected to the sixty-first pin of the chip N2; one end of the inductor L3 is respectively connected to the power supply 3.3V-LAN, one end of the capacitor C57, and the capacitor C58. One end of the inductor L3 is connected to one end of the capacitor C54, one end of the capacitor C55, one end of the capacitor C56 and the 60th pin of the chip N2; one end of the resistor R47 is connected to the 58th pin of the chip N2, the 51st pin, the 53rd pin, the 54th pin, the 55th pin, the 56th pin and the 57th pin of the chip N2 are connected to the ground. The pins are respectively connected to one end of the resistor R53 and one end of the resistor R48, and the other end of the resistor R53 and the other end of the resistor R48 are connected to the power supply 3.3V-LAN; one end of the resistor R54 is connected to the 50th pin of the chip N2, one end of the capacitor C59 and one end of the capacitor C60 are connected to the 49th pin of the chip N2 and the power supply 3.3V-LAN, and the 47th pin of the chip N2 is grounded through the resistor R55; one end of the capacitor C61 and one end of the capacitor C62 are connected to the third pin of the chip N2 and connected to the 1.0V power supply, the 18th pin of the chip N2 is grounded through the resistor R58, and the chip N The 30th pin, the 29th pin, the 28th pin and the 27th pin of 2 are respectively connected to one end of the resistor R59 to one end of the resistor R63, and the other end of the resistor R59 to the other end of the resistor R63 are both connected to the power supply 3.3V-LAN; the other end of the capacitor C52 to the other end of the capacitor C62 are both grounded; the 38th pin to the 47th pin, the 34th pin to the 36th pin, the 18th pin, the 19th pin, the 21st pin to the 25th pin, the 27th pin to the 30th pin, and the 53rd pin to the 57th pin of the chip N2 are all connected to the third processing chip FPGA3.

[0019] Furthermore, the network interface is an RJ45 interface, which includes a chip XS1A, a capacitor C49, a capacitor C50 and several resistors. The TRD1+ pin of the chip XS1A is connected to one end of the capacitor C49 and one end of the capacitor C50 through the resistor R1. The TRD1+ pin, the TRCT1 pin, the TRD2+ pin, the TRCT2 pin, the TRD3+ pin, the TRCT3 pin, the TRD4+ pin and the TRCT4 pin of the chip XS1A are respectively connected to the fifth pin, the sixth pin, the eighth pin, the ninth pin, the eleventh pin, the twelfth pin, the fourteenth pin and the fifteenth pin of the chip N2 through a resistor in a one-to-one correspondence. The M1 pin of the chip XS1A is connected to one end of the resistor R42 and one end of the capacitor C51, and the other end of the capacitor C51 and the other end of the resistor R42 are both grounded.

[0020] Furthermore, the network interface is a USB 3.0 interface, and one end of the USB 3.0 interface is connected to the third processing chip FPGA3.

[0021] Furthermore, the fault detection device based on the 64-channel acoustic signal receiving array also includes an industrial computer, which is located in the housing and connected to the other end of the USB3.0 interface.

[0022] Further, the fault detection device based on the 64-channel acoustic signal receiving array also includes a first power module, which supplies power to the device. The first power module includes a rectifier and filter unit, a first buck unit and a second buck unit, which are connected in sequence. The rectifier and filter unit includes a Schottky diode VD1, a capacitor C1, a filter L1, a capacitor C2 and a capacitor C3. The anode of the Schottky diode VD1 is connected to the first end of the power interface, the cathode of the Schottky diode VD1 is connected to one end of the capacitor C1 and the opposite end of the primary coil of the filter L1, the same end of the primary coil of the filter L1 is connected to one end of the capacitor C2 and one end of the capacitor C3, the second end of the power interface is connected to the other end of the capacitor C1 and the opposite end of the secondary coil of the filter L1 and is grounded, and the same end of the secondary coil of the filter L1 is connected to the other end of the capacitor C2 and the other end of the capacitor C3 and is grounded;

[0023] The first step-down unit includes a resistor R25, a resistor R26, a resistor RT2, a capacitor C5, a resistor R27, a light-emitting diode V1', a chip U3, a capacitor C4, a transistor VT1, a resistor R28, a resistor R29, an inductor L2, a Schottky diode VD2, a capacitor C6, a resistor RT1 and a resistor RB1. The model of the chip U3 is LMR16020-G8. One end of the resistor R25, one end of the capacitor C5 and the second pin of the chip U3 are all connected to a 12V power supply. The other end of the resistor R25 is connected to one end of the resistor R26 and the third pin of the chip U3. One end of the resistor RT2 is connected to the fourth pin of the chip U3. One end of the capacitor C4 is connected to the first pin of the chip U3. The other end of the capacitor C4, the eighth pin of the chip U3 and the cathode of the Schottky diode VD2 are all connected to one end of the inductor L2. The other end of L2 is connected to one end of capacitor C6 and one end of resistor RT1, one end of resistor RT1 is used as a 5V power supply output end, one end of resistor RB1 is connected to the other end of resistor RT1 and the fifth pin of chip U3, one end of resistor R27 is connected to a 12V power supply, the other end of resistor R27 is connected to the anode of light-emitting diode V1', the cathode of light-emitting diode V1' is connected to the collector of transistor VT1, the base of transistor VT1 is connected to one end of resistor R29, the other end of resistor R29 is connected to one end of resistor R28, the other end of resistor R28 is used as a 5V power supply output end, the other end of resistor R29 is connected to the sixth pin of chip U3, the other end of resistor R26, the other end of resistor RT2, the emitter of transistor VT1, the seventh pin of chip U3, the anode of Schottky diode VD2 and the other end of resistor RB1 are all grounded;

[0024] The second step-down unit includes capacitor C31, chip U4, capacitor C32, capacitor C33 and capacitor C42. The model of chip U4 is REG1117-3.3. One end of capacitor C31 and the third pin of chip U4 are connected to a 5V power supply. The second pin and the fourth pin of chip U4 are connected to one end of capacitor C32. One end of capacitor C32 serves as a 3.3V power supply output end. One end of capacitor C33 and one end of capacitor C42 are connected to one end of capacitor C32. The other end of capacitor C31, the first pin of chip U4, the other end of capacitor C32, the other end of capacitor C33 and the other end of capacitor C42 are grounded.

[0025] Furthermore, the fault detection device based on the 64-channel acoustic signal receiving array further includes a second power supply module, the second power supply module supplies power to the device, and the second power supply module includes a multi-channel output unit and a third step-down unit.

[0026] The multi-channel output unit includes capacitors C130 to C135, capacitor C165 and several output sub-channels, one of which includes inductor FB2, capacitor C136, capacitor C166, capacitor C167, capacitor C137, light-emitting diode V1 and resistor R386. The positive electrodes of capacitors C130 to C135 and capacitor C165 are all connected to a +5V power supply. The negative electrodes are all grounded, one end of the inductor FB2 is connected to a +5V power supply, the positive electrodes of capacitors C136, C166 and C167 and one end of capacitor C137 are all connected to the other end of the inductor FB2, the negative electrodes of capacitors C136, C166 and C167 and the other end of capacitor C137 are all grounded, one end of capacitor C137 is connected to the anode of the light-emitting diode V1, the cathode of the light-emitting diode V1 is connected to one end of the resistor R386, and the other end of the resistor R386 is grounded.

[0027] The third step-down unit includes capacitor C129, inductor FB1, inductor FB3, capacitor C133, capacitor C134, chip U5, resistor RB2, resistor RT2, capacitor CC1, capacitor C130, capacitor C132, capacitor C131, resistor R385 and light emitting diode V9. The model of chip U5 is ADP1708ARDZ-R7. One end of capacitor C129 is connected to the first end of the power interface and one end of the inductor FB1. The other end of the inductor FB1 serves as the +5V power output end. The first pin of chip U5, the third pin of chip U5, one end of capacitor C133 and one end of capacitor C134 are all connected to the other end of inductor FB1. The other end of capacitor C129, one end of inductor FB3, the second end and the third end of the power interface are all grounded GND-IN. The other end of inductor FB3, the other end of capacitor C133, capacitor C134 are all grounded GND-IN. The other end of 134, the second pin of chip U5, one end of resistor RB2 and one end of capacitor CC1 are all connected and grounded, the other end of capacitor CC1 and the other end of resistor RB2 are connected to the eighth pin of chip U5, the fifth pin, the sixth pin and the seventh pin of chip U5, one end of resistor RT2 and one end of capacitor C135 are all connected, the other end of resistor RT2 and the other end of capacitor C135 are connected to the other end of capacitor CC1; one end of capacitor C130, the positive electrode of capacitor C132, one end of capacitor C131 and the anode of light-emitting diode V9 are all connected to the sixth pin of chip U5, and one end of capacitor C130 serves as the +3.6V power output end; resistor R385 is connected between the other end of capacitor C131 and the cathode of light-emitting diode V9, and the other end of capacitor C131, the negative electrode of capacitor C132 and the other end of capacitor C130 are all grounded.

[0028] The advantages of the present invention are:

[0029] (1) The present invention separately designs 64 sub-array units for receiving acoustic signals into an independent array. When the device is used in different application scenarios, a suitable acoustic signal receiving array can be selected according to the characteristics of the target acoustic signal to be monitored. In addition, a 64-channel array is designed to realize acoustic monitoring of the operating status of large, medium or key electromechanical equipment. The acoustic signal receiving array receives the signal, and the driving module and the operational amplifier module differentially amplify the received signal to improve the anti-interference ability. The filter module filters out the interference signal and sends the signal to the AD module. The AD module converts the collected signal into a digital signal and sends it to the FPGA module. The FPGA module performs signal processing, fault identification and positioning algorithm processing, and sends the processed result and the image data collected by the camera to the cloud background through the network interface. The direct state of sound is used for monitoring, breaking through the traditional indirect state of monitoring through current and voltage. The entire process realizes automatic monitoring without requiring a lot of manpower and material resources, avoiding misjudgment and missed judgment, and avoiding hidden dangers.

[0030] (2) The signal to be tested collected by the driving module of the present invention is an analog signal. The analog signal is converted into a differential amplified signal through the differential amplifier U1 to improve the anti-interference ability of the signal. Then, it is filtered by the filtering module to filter out interference again, thereby providing a clearer signal for the back-end AD acquisition processing. The operational amplifier module is connected to the power supply, and the output end outputs a stable power supply to provide a stable power supply for the driving module to avoid unstable power supply voltage. The signal of the entire driving circuit is stable, the signal interference is small, and the detection result is more accurate.

[0031] (3) The clock division module generates a clock frequency through the crystal oscillator G1, and outputs the clock frequency synchronous phase to each of the eight AD boards through the chip N1, providing the AD boards with a synchronous phase clock to ensure the accuracy of data acquisition.

[0032] (4) By setting up a communication module to receive the detection data output by the fault detection device, the chip N2 sends the processed data to the cloud through the network interface. The degree of automation is high, and there is no need for manual on-site data reading, which avoids misreading and misjudgment, and the data accuracy is high.

[0033] (5) By designing an industrial computer, the signal processing, fault identification and location algorithms executed by the FPGA module are directly performed by the industrial computer. In this way, there is no need to transplant the relevant algorithms to the FPGA module, reducing the difficulty and workload of development, because the difficulty and workload of algorithm transplantation and development on the FPGA module are higher than algorithm development on the industrial computer. The fusion of the sound field data after analysis and fault location and the video image data obtained by the camera can be done on the industrial computer or on the cloud background, which is more flexible.

[0034] (6) The first power module rectifies the power input from the power interface through the Schottky diode VD1 through the rectifying and filtering unit, and filters it through the filter L1 to filter out high-frequency interference and stabilize the voltage to avoid the unstable voltage during the equipment transportation process affecting the detection result. The rectifying and filtering power supply outputs a stable 12V power supply, and then the 12V power supply is stepped down by the first step-down unit to meet the requirements of the module with a lower power supply voltage. The 12V power supply is stepped down again by the second step-down unit to meet the requirements of the module with an even lower power supply voltage. The rectifying and filtering unit, the first step-down unit and the second step-down unit can meet the power supply requirements of different modules and solve the problem of a single power supply method.

[0035] (7) The second power supply module includes a multi-channel output unit and the multi-channel output unit includes several output sub-channels. Each output sub-channel can not only supply power to the device module independently but also has an RC filtering effect to filter out interference and avoid voltage instability. The power supply demand is completed and stable and reliable through the multi-channel equal-voltage output module. The third step-down unit completes the power supply of the module with lower voltage demand. The overall power supply mode is diversified, which meets the power supply demand of multiple modules and the power supply is stable. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic diagram of the mechanical structure of a fault detection device based on a 64-channel acoustic signal receiving array provided in Example 1 of the present invention;

[0037] Figure 2 A schematic diagram of the internal mechanical structure of a fault detection device based on a 64-channel acoustic signal receiving array provided in Example 1 of the present invention;

[0038] Figure 3 A circuit principle block diagram of a fault detection device based on a 64-channel acoustic signal receiving array provided in Embodiment 1 of the present invention;

[0039] Figure 4 A schematic diagram of the structure of an acoustic signal receiving array of a fault detection device based on a 64-channel acoustic signal receiving array provided in Embodiment 1 of the present invention;

[0040] Figure 5 A circuit schematic diagram of an operational amplifier module of a fault detection device based on a 64-channel acoustic signal receiving array provided in Embodiment 1 of the present invention;

[0041] Figure 6 A circuit schematic diagram of a driving module of a fault detection device based on a 64-channel acoustic signal receiving array provided in Embodiment 1 of the present invention;

[0042] Figure 7 A circuit schematic diagram of a filter module of a fault detection device based on a 64-channel acoustic signal receiving array provided in Embodiment 1 of the present invention;

[0043] Figure 8 A circuit schematic diagram of an AD module of a fault detection device based on a 64-channel acoustic signal receiving array provided in Example 1 of the present invention;

[0044] Fig. 9 A circuit schematic diagram of a clock frequency division module of a fault detection device based on a 64-channel acoustic signal receiving array provided in Embodiment 1 of the present invention;

[0045] Fig.10 A circuit schematic diagram of a communication module of a fault detection device based on a 64-channel acoustic signal receiving array provided in Embodiment 1 of the present invention;

[0046] Fig.11 A circuit schematic diagram of a network interface of a fault detection device based on a 64-channel acoustic signal receiving array provided in Example 1 of the present invention;

[0047] Fig.12 A circuit schematic diagram of a rectifying and filtering unit of a fault detection device based on a 64-channel acoustic signal receiving array provided in Embodiment 1 of the present invention;

[0048] Fig.13 A circuit schematic diagram of a first voltage reduction unit of a fault detection device based on a 64-channel acoustic signal receiving array provided in Embodiment 1 of the present invention;

[0049] Fig.14 A circuit schematic diagram of a second voltage reduction unit of a fault detection device based on a 64-channel acoustic signal receiving array provided in Embodiment 1 of the present invention;

[0050] Fig.15 A circuit schematic diagram of a multi-channel output unit of a fault detection device based on a 64-channel acoustic signal receiving array provided in Embodiment 1 of the present invention;

[0051] Fig.16 A circuit schematic diagram of the third voltage reduction unit of the fault detection device based on the 64-channel acoustic signal receiving array provided in Example 1 of the present invention

[0052] Fig.17 A schematic diagram of the structure of an acoustic signal receiving array of a fault detection device based on a 64-channel acoustic signal receiving array provided in Embodiment 2 of the present invention;

[0053] Fig.18 This is a schematic diagram of the structure of the acoustic signal receiving array of the fault detection device based on the 64-channel acoustic signal receiving array provided in Example 3 of the present invention. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in combination with the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0055] Example 1

[0056] The present invention provides a fault detection device based on a 64-channel sound signal receiving array, which is used to monitor and detect faults in various scenarios such as electricity, industry, and vehicles, locate the fault location, and identify the fault type. When the system is in use, the data can be stored in the memory of the FPGA module 10, or the Gigabit Ethernet interface can be used to read the fault location, fault information data, and original audio signal data in the corresponding camera video, and store them in the cloud; the 5G interface can also be used to perform this operation to achieve wireless cloud data storage and reading and data feature comparison; the external audio input device provided by the present invention is described in detail below in conjunction with the accompanying drawings. Figure 1-Figure 3 As shown, a fault detection device based on a 64-channel acoustic signal receiving array comprises a housing 1, a circuit board arranged in the housing 1, a lens cover 2 arranged on the outer side of the housing 1, and an acoustic signal receiving array cover 3. The circuit board comprises an acoustic signal receiving array 4, a driving module 5, an operational amplifier module 6, a filtering module 7, an AD module 8, a clock frequency division module 9, an FPGA module 10, a camera module 11, a communication module 12, and a network interface 13. The acoustic signal receiving array 4, the operational amplifier module 6, and the filtering module 7 are all connected to the driving module 5. The filtering module 7, the AD module 8 , a clock frequency division module 9, an FPGA module 10, a communication module 12 and a network interface 13 are connected in sequence, the camera module 11 is connected to the FPGA module 10, the communication module 12 and the network interface 13 are located on an interface circuit board 14, the driving module 5, the operational amplifier module 6, the filtering module 7, the clock frequency division module 9, etc. are also arranged in the circuit board in the housing 1 but are not shown in the figure. The fault detection device based on the 64-channel sound signal receiving array also includes a first power supply module 15 and a second power supply module 16. The first power supply module 15 and the second power supply module 16 are used to power the device. Figure 1 As shown, the first power module 15 and the second power module 16 are arranged on a power and battery management system board 17, the acoustic signal receiving array 4 is located on the inner wall of the housing 1 and close to the acoustic signal receiving array cover 3, and the camera module 11 is located inside the housing 1 and close to the lens cover 2. It should be noted that due to the need for strict phase synchronization, all data routing must be of equal length. The arrangement of the eight AD modules 8 in the figure causes different signal line lengths, which are compensated by adjusting the length of the bottom board wiring to make the signal lines equal.

[0057] The acoustic signal receiving array 4 is composed of 64 MEMS acoustic sensors with a wide frequency response range (for example, a frequency response range of 20 Hz-100 KHz) forming a matrix array (generally referred to as a surface array) for collecting external audio signals, wherein the sensor layout of the surface array is as follows: Figure 4 As shown, the spacing between all sensors can be the same or different, as long as the spacing between two sensors is within the spacing range, which is 5mm to 10cm; the sound analog signal picked up by the 64-channel sound sensor array is sent to the AD module 8 through the driving module 5, the operational amplifier module 6 and the filtering module 7, and the AD module 8 converts the input analog signal into a digital signal; the converted digital signal is then sent to the FPGA module 10 through a parallel interface or a high-speed SPI for processing, including signal processing, fault identification and positioning algorithms, etc., wherein the signal processing, fault identification and positioning algorithms belong to the prior art and are not within the scope of protection of this application. For example, the method described in the partial discharge detection method and device based on a two-dimensional sensor array disclosed in Chinese patent application No. CN201811548556.9 can be used for partial discharge detection, and the processed results and the high-definition image data collected by the camera are sent to the cloud backend through the network interface 13 (Gigabit Ethernet interface or 4G / 5G interface or WIFI interface). This design helps optimize the device in terms of miniaturization and low power consumption. In addition, users can not only configure a matching acoustic sensor array daughter board based on the fault sound characteristics in the usage scenario, but also flexibly choose wired or wireless interface for data transmission, which facilitates implementation and deployment.

[0058] In this embodiment, Figure 4 As shown, the acoustic signal receiving array 4 includes 64 sub-array units, which are acoustic sensors or microphones. In this embodiment, a microphone is used as an example. Every 8 sub-array units are connected in series to form an array, and the 64 sub-array units are arranged in an 8*8 array. 64 microphone sensors with high signal-to-noise ratio and low power consumption are used to detect audible sound and ultrasonic bands of 0-100KHz. The spacing of the microphone sensors is calculated and arranged according to the band to be measured, and the typical spacing is 5mm to 10cm.

[0059] The following is a detailed introduction to the circuit principles of each module, such as Figure 5As shown, the operational amplifier module 6 includes a resistor R389, a resistor R390, a capacitor C140, a capacitor C148, an operational amplifier N65A, a capacitor C150, a resistor R393 and a capacitor C149, one end of the capacitor C140, one end of the capacitor C148, one end of the resistor R389 and the fourth pin of the operational amplifier N65A are all connected to the +5V power supply, one end of the resistor R390, the third pin of the operational amplifier N65A and one end of the capacitor C150 are all connected to the other end of the resistor R389, the second pin of the operational amplifier N65A is connected to the first pin of the operational amplifier N65A, the negative end of the power supply of the operational amplifier N65A is connected to the other end of the capacitor C150 and grounded, the first pin of the operational amplifier N65A is connected to one end of the capacitor C149 through the resistor R393, and the other end of the capacitor C149, the other end of the capacitor C140, the other end of the capacitor C148 and the other end of the resistor R390 are all grounded.

[0060] like Figure 6 As shown, the driving module 5 includes a differential amplifier U1, sequentially numbered resistors R200 to R205, a capacitor C200 and a capacitor C201, the model of the differential amplifier U1 is ADA4940-1ARZ, one end of the resistor R200 is connected to a +5V-1# power supply, one end of the capacitor C200, one end of the capacitor C201 and the third pin of the differential amplifier U1 are all connected to the other end of the resistor R200, the second pin of the differential amplifier U1 is connected to one end of the capacitor C149, the fourth pin of the differential amplifier U1 is connected to one end of the resistor R202, and the other end of the resistor R202 is connected to the and one end of the resistor R201 are connected to the first pin of the differential amplifier U1, and the other end of the resistor R201 is grounded; the fifth pin of the differential amplifier U1 is connected to one end of the resistor R205, the other end of the resistor R205 and one end of the resistor R203 are connected to the eighth pin of the differential amplifier U1, the other end of the resistor R203 is connected to an acoustic sensor in the acoustic signal receiving array 4 through a capacitor, the sixth pin of the differential amplifier U1, the other end of the capacitor C200 and the other end of the capacitor C201 are all grounded, and the seventh pin of the differential amplifier U1 is connected to the +5V-1# power supply through a resistor R204. The analog signal is converted into a differential amplified signal through the differential amplifier U1 signal, which improves the anti-interference ability of the signal and provides a clearer signal for the back-end AD acquisition processing.

[0061] like Figure 7As shown, the filtering module 7 includes a capacitor C19, a capacitor C22, a resistor R13, a resistor R14, a resistor R17, a resistor R18, a capacitor C21, a capacitor C20 and a capacitor C25, one end of the capacitor C19 is connected to one end of the resistor R202, one end of the capacitor C22 is connected to one end of the resistor R205, the other end of the capacitor C19 is respectively connected to one end of the resistor R13 and one end of the resistor R14, the other end of the capacitor C22 is respectively connected to one end of the resistor R17 and one end of the resistor R18, the other end of the resistor R14 is connected to the other end of the resistor R17, the other end of the resistor R13 is respectively connected to one end of the capacitor C21 and one end of the capacitor C20, the other end of the resistor R18 is respectively connected to the other end of the capacitor C21 and one end of the capacitor C25, and the other end of the capacitor C20 is connected to the other end of the capacitor C25 and grounded.

[0062] like Figure 8 As shown, the AD module 8 includes a chip U2, the model of the chip U2 is AD7761BSTZ, the ninth pin of the chip U2 is connected to one end of the capacitor C20, and the tenth pin of the chip U2 is connected to one end of the capacitor C25. Each AD module 8 can provide conversion of 8-channel differential signals. The sampling rate of each channel can reach 256K, the dynamic range of the AD module 8 can reach 97.7dB, the input bandwidth is 110.8kHz, and the typical harmonic distortion is -120dB.

[0063] The FPGA module 10 includes a first processing chip FPGA1, a second processing chip FPGA2 and a third processing chip FPGA3. The DO port, SPI port, SYNC port and STARY port of the first processing chip FPGA1 and the second processing chip FPGA2 are all connected to the corresponding ports of the chip U2. The first processing chip FPGA1 and the second processing chip FPGA2 are both connected to the third processing chip FPGA3. The models of the first processing chip FPGA1 and the second processing chip FPGA2 are both AC616, and the model of the third processing chip FPGA3 is AC6045.

[0064] like Fig. 9As shown, the clock frequency division module 9 includes resistors R30 to R41, a crystal oscillator G1, a capacitor C36, a capacitor C37 and a chip N1, which are numbered in sequence. The model of the chip N1 is 5PB1110PGG-TSSOP20, one end of the resistor R30 is connected to the power supply 3.3V-CLK, the other end of the resistor R30 is respectively connected to one end of the capacitor C36, one end of the capacitor C37 and the fourth pin of the crystal oscillator G1, the other end of the capacitor C36, the other end of the capacitor C37 and the second pin of the crystal oscillator G1 are all grounded, the third pin of the crystal oscillator G1 is connected to the first pin of the chip N1 through the resistor R31, the second pin, the fifth pin, the ninth pin of the chip N1 and one end of the capacitor C38 are all connected to the power supply 3.3V-CLK, and the fourth pin and the seventh pin of the chip N1 are both connected to the other end of the capacitor C38 and grounded; The eighth pin, the tenth pin, the twelfth pin, the thirteenth pin, the fifteenth pin, the seventeenth pin, the nineteenth pin and the twentieth pin of the chip N1 are respectively connected to one end of the resistor R38, one end of the resistor R41, one end of the resistor R40, one end of the resistor R39, one end of the resistor R37, one end of the resistor R35, one end of the resistor R33 and one end of the resistor R32, and the other end of the resistor R38, the other end of the resistor R41, the other end of the resistor R40, the other end of the resistor R39, the other end of the resistor R37, the other end of the resistor R35, the other end of the resistor R33 and the other end of the resistor R32 are all connected to the AD interface of the chip U2; the third pin of the chip N1 is connected to the second processing chip FPGA2 through the resistor R34, and the sixth pin of the chip N1 is connected to the first processing chip FPGA1 through the resistor R36. The clock synchronization module 9 is used to provide 8 clocks with synchronous phases to the 8 AD modules 8 to ensure the accuracy of data acquisition.

[0065] like Fig.10The communication module 12 includes a chip N2, sequentially numbered resistors R45 to R63, sequentially numbered capacitors C52 to C62, a crystal oscillator G2, and an inductor L3. One end of the resistor R45 is connected to the power supply 3.3V-LAN, and the other end of the resistor R45 is respectively connected to one end of the capacitor C52, one end of the capacitor C53, and the fourth pin of the crystal oscillator G2. The third pin of the crystal oscillator G2 is connected to one end of the resistor R46, and the other end of the resistor R46 is connected to the sixty-first pin of the chip N2; one end of the inductor L3 is respectively connected to the power supply 3.3V-LAN, one end of the capacitor C57, one end of the capacitor C58, and the fourth pin of the crystal oscillator G2. The other end of the inductor L3 is connected to one end of the capacitor C54, one end of the capacitor C55, one end of the capacitor C56 and the 60th pin of the chip N2; one end of the resistor R47 is connected to the 58th pin of the chip N2, the 51st pin, the 53rd pin, the 54th pin, the 55th pin, the 56th pin and the 57th pin of the chip U2. One end of the resistor R53 is connected to one end of the resistor R48 respectively, and the other end of the resistor R53 and the other end of the resistor R48 are both connected to the power supply 3.3V-LAN; one end of the resistor R54 is connected to the 50th pin of the chip N2, one end of the capacitor C59 and one end of the capacitor C60 are both connected to the 49th pin of the chip N2 and the power supply 3.3V-LAN, and the 47th pin of the chip N2 is grounded through the resistor R55; one end of the capacitor C61 and one end of the capacitor C62 are connected to the third pin of the chip N2 and connected to the 1.0V power supply, the 18th pin of the chip N2 is grounded through the resistor R58, and the chip N2 The 30th pin, the 29th pin, the 28th pin and the 27th pin are respectively connected to one end of the resistor R59 to one end of the resistor R63, and the other end of the resistor R59 to the other end of the resistor R63 are both connected to the power supply 3.3V-LAN; the other end of the capacitor C52 to the other end of the capacitor C62 are both grounded; the 38th pin to the 47th pin, the 34th pin to the 36th pin, the 18th pin, the 19th pin, the 21st pin to the 25th pin, the 27th pin to the 30th pin, and the 53rd pin to the 57th pin of the chip N2 are all connected to the third processing chip FPGA3.

[0066] like Fig.11The network interface 13 is an RJ45 interface, and the network interface 13 includes a chip XS1A, a capacitor C49, a capacitor C50 and a plurality of resistors. The TRD1+ pin of the chip XS1A is connected to one end of the capacitor C49 and one end of the capacitor C50 through the resistor R1. The TRD1+ pin, the TRCT1 pin, the TRD2+ pin, the TRCT2 pin, the TRD3+ pin, the TRCT3 pin, the TRD4+ pin and the TRCT4 pin of the chip XS1A are respectively connected to the fifth pin, the sixth pin, the eighth pin, the ninth pin, the eleventh pin, the twelfth pin, the fourteenth pin and the fifteenth pin of the chip N2 through a resistor in a one-to-one correspondence. The M1 pin of the chip XS1A is connected to one end of the resistor R42 and one end of the capacitor C51, and the other end of the capacitor C51 and the other end of the resistor R42 are both grounded.

[0067] like Figure 12-14 As shown, the first power module 15 includes a rectifier and filter unit, a first buck unit and a second buck unit, and the rectifier and filter unit, the first buck unit and the second buck unit are connected in sequence. Fig.12 As shown, the rectification and filtering unit includes a Schottky diode VD1, a capacitor C1, a filter L1, a capacitor C2 and a capacitor C3, the anode of the Schottky diode VD1 is connected to the first end of the power interface, the cathode of the Schottky diode VD1 is connected to one end of the capacitor C1 and the opposite end of the primary coil of the filter L1, the same end of the primary coil of the filter L1 is connected to one end of the capacitor C2 and one end of the capacitor C3, the second end of the power interface is connected to the other end of the capacitor C1 and the opposite end of the secondary coil of the filter L1 and is grounded, and the same end of the secondary coil of the filter L1 is connected to the other end of the capacitor C2 and the other end of the capacitor C3 and is grounded;

[0068] like Fig.13As shown, the first step-down unit includes a resistor R25, a resistor R26, a resistor RT2, a capacitor C5, a resistor R27, a light-emitting diode V1', a chip U3, a capacitor C4, a transistor VT1, a resistor R28, a resistor R29, an inductor L2, a Schottky diode VD2, a capacitor C6, a resistor RT1 and a resistor RB1. The model of the chip U3 is LMR16020-G8. One end of the resistor R25, one end of the capacitor C5 and the second pin of the chip U3 are all connected to a 12V power supply. The other end of the resistor R25 is connected to one end of the resistor R26 and the third pin of the chip U3. One end of the resistor RT2 is connected to the fourth pin of the chip U3. One end of the capacitor C4 is connected to the first pin of the chip U3. The other end of the capacitor C4, the eighth pin of the chip U3 and the cathode of the Schottky diode VD2 are all connected to one end of the inductor L2. The other end of the inductor L2 is connected to one end of the capacitor C6 and one end of the resistor RT1, one end of the resistor RT1 is used as a 5V power supply output end, one end of the resistor RB1 is connected to the other end of the resistor RT1 and the fifth pin of the chip U3, one end of the resistor R27 is connected to the 12V power supply, the other end of the resistor R27 is connected to the anode of the light-emitting diode V1', the cathode of the light-emitting diode V1' is connected to the collector of the transistor VT1, the base of the transistor VT1 is connected to one end of the resistor R29, the other end of the resistor R29 is connected to one end of the resistor R28, the other end of the resistor R28 is used as a 5V power supply output end, the other end of the resistor R29 is connected to the sixth pin of the chip U3, the other end of the resistor R26, the other end of the resistor RT2, the emitter of the transistor VT1, the seventh pin of the chip U3, the anode of the Schottky diode VD2 and the other end of the resistor RB1 are all grounded;

[0069] like Fig.14 As shown, the second step-down unit includes a capacitor C31, a chip U4, a capacitor C32, a capacitor C33 and a capacitor C42, the model of the chip U4 is REG1117-3.3, one end of the capacitor C31 and the third pin of the chip U4 are both connected to a 5V power supply, the second pin and the fourth pin of the chip U4 are both connected to one end of the capacitor C32, one end of the capacitor C32 serves as a 3.3V power supply output end, one end of the capacitor C33 and one end of the capacitor C42 are both connected to one end of the capacitor C32, and the other end of the capacitor C31, the first pin of the chip U4, the other end of the capacitor C32, the other end of the capacitor C33 and the other end of the capacitor C42 are all grounded.

[0070] like Figure 15 to Figure 16 As shown, the second power module 16 includes a multi-channel output unit and a third step-down unit, such as Fig.15As shown, the multi-channel output unit includes capacitors C130 to C135, capacitor C165 and several output sub-channels, one of which includes inductor FB2, capacitor C136, capacitor C166, capacitor C167, capacitor C137, light-emitting diode V1 and resistor R386. The positive electrodes of capacitors C130 to C135 and capacitor C165 are all connected to a +5V power supply. The negative electrodes of capacitors C136, C166 and C167 and one end of capacitor C137 are connected to the other end of inductor FB2, the negative electrodes of capacitors C136, C166 and C167 and the other end of capacitor C137 are connected to ground, one end of capacitor C137 is connected to the anode of light emitting diode V1, the cathode of light emitting diode V1 is connected to one end of resistor R386, and the other end of resistor R386 is grounded.

[0071] like Fig.16 As shown, the third step-down unit includes a capacitor C129, an inductor FB1, an inductor FB3, a capacitor C133, a capacitor C134, a chip U5, a resistor RB2, a resistor RT2, a capacitor CC1, a capacitor C130, a capacitor C132, a capacitor C131, a resistor R385 and a light-emitting diode V9. The model of the chip U5 is ADP1708ARDZ-R7. One end of the capacitor C129 is connected to the first end of the power interface and one end of the inductor FB1. The other end of the inductor FB1 serves as a +5V power output end. The first pin of the chip U5, the third pin of the chip U5, one end of the capacitor C133 and one end of the capacitor C134 are all connected to the other end of the inductor FB1. The other end of the capacitor C129, one end of the inductor FB3, the second end and the third end of the power interface are all grounded GND-IN. The other end of the inductor FB3, the other end of the capacitor C133, the The other end of capacitor C134, the second pin of chip U5, one end of resistor RB2 and one end of capacitor CC1 are all connected and grounded, the other end of capacitor CC1 and the other end of resistor RB2 are connected to the eighth pin of chip U5, the fifth pin, the sixth pin and the seventh pin of chip U5, one end of resistor RT2 and one end of capacitor C135 are all connected, the other end of resistor RT2 and the other end of capacitor C135 are connected to the other end of capacitor CC1; one end of capacitor C130, the positive electrode of capacitor C132, one end of capacitor C131 and the anode of light-emitting diode V9 are all connected to the sixth pin of chip U5, and one end of capacitor C130 serves as the +3.6V power supply output end; resistor R385 is connected between the other end of capacitor C131 and the cathode of light-emitting diode V9, and the other end of capacitor C131, the negative electrode of capacitor C132 and the other end of capacitor C130 are all grounded.

[0072] Through the above technical scheme, the present invention provides a fault detection device based on a 64-channel sound signal receiving array, which receives signals through the sound signal receiving array, and the driving module and the operational amplifier module differentially amplify the received signals to improve the anti-interference ability. The filtering module filters out the interference signal and sends the signal to the AD module. The AD module converts the collected signal into a digital signal and sends it to the FPGA module. The PFGA module performs signal processing, fault identification and positioning and other algorithm processing, and sends the processed results and the image data collected by the camera to the cloud backend through the network interface. The direct state of sound is used for monitoring, breaking through the traditional indirect state of monitoring through current, voltage, etc. The whole process realizes automatic monitoring, does not require a lot of manpower and material resources, avoids misjudgment and missed judgment, and avoids hidden dangers.

[0073] Example 2

[0074] The difference between Example 2 of the present invention and Example 1 is that: Fig.17 As shown, every 8 sub-array units are connected in series to form an array, and the 64 sub-array units are in a cross-shaped array with 32 sub-array units in the horizontal and vertical directions. Under the condition of the same number of sensors, the cross-shaped array can achieve more accurate three-dimensional spatial positioning, and the algorithm complexity is relatively low.

[0075] Example 3

[0076] The difference between Example 3 of the present invention and Example 1 is that the industrial computer 18 is responsible for the signal processing, fault identification and positioning algorithms executed by the FPGA module 10 in Example 1, so there is no need to transplant the relevant algorithms to the FPGA module 10, because the difficulty and workload of algorithm transplantation and development on the FPGA module 10 are higher than algorithm development on the industrial computer 18. Another point is that the fusion of the sound field data after analysis and fault location and the video image data obtained by the camera can be done on the industrial computer 18 or on the cloud background. The following is a detailed introduction to the scheme of this embodiment. Fig.18 As shown, the network interface 13 is a USB3.0 interface, and one end of the USB3.0 interface is connected to the third processing chip FPGA3. The fault detection device based on the 64-channel sound signal receiving array also includes an industrial computer 18, which is located in the housing 1 and is connected to the other end of the USB3.0 interface. When the system is working, the USB3.0 interface or the Gigabit Ethernet interface can be used to obtain the original sound signal data, and then the industrial computer 18 can be used to obtain the video data of the monitoring target through the camera connected to the USB3.0 interface, and finally the result data after the fault location monitoring is sent to the cloud backend through the Ethernet interface for presentation.

[0077] The analog signal is converted into an analog differential signal by the driving module 5 and then input into the AD module 8, and the AD module 8 converts the input analog differential signal into a digital signal; then the AD module 8 sends the converted digital signal to the FPGA module 10 for preprocessing through the parallel interface or the high-speed SPI interface. Specifically, the digitized digital signal is encoded according to the channel corresponding to the microphone array bit number, encapsulated according to the USB and Ethernet data transmission protocol, and a data synchronization code is added; the data processed by the FPGA module is then sent to the network interface 13; the network interface 13 or the Gigabit Ethernet port is connected to the USB3.0 interface or Gigabit Ethernet interface of the embedded industrial computer 18, and finally the sound data picked up and digitized is transmitted to the industrial computer 18 for related acoustic algorithm software processing. The acoustic algorithm belongs to the prior art and is not described here; the industrial computer 18 is also connected to the camera module 11 to collect the image data of the monitored device, and the result of the acoustic algorithm processing and the image data are transmitted to the cloud backend through the Gigabit Ethernet interface or the wireless network transmission interface. This embodiment can improve the practicality and operability of the device, and the user can flexibly select the interface for use. Moreover, the audio acquisition end also facilitates the upgrade and replacement of the array sub-board through the independently designed sensor array sub-board.

[0078] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A fault detection device based on a 64-channel acoustic signal receiving array, characterized in that: It comprises a shell, a circuit board arranged in the shell, a lens cover arranged on the outer side of the shell, and an acoustic signal receiving array cover, wherein the circuit board comprises an acoustic signal receiving array, a driving module, an operational amplifier module, a filtering module, an AD module, a clock frequency division module, an FPGA module, a camera module, a communication module, and a network interface, wherein the acoustic signal receiving array comprises 64 sub-array units, wherein every 8 sub-array units are connected in series to form a group of arrays, and the 64 sub-array units are arranged in an 8*8 array or a cross-shaped array with 32 sub-array units in both the horizontal and vertical directions; the acoustic signal receiving array, the operational amplifier module, and the filtering module are all connected to the driving module, and the filtering module, the AD module, the clock frequency division module, the FPGA module, the communication module, and the network interface are connected in sequence, and the camera module is connected to the FPGA module, the acoustic signal receiving array is located on the inner side wall of the shell and close to the acoustic signal receiving array cover, and the camera module is located on the inner side of the shell and close to the lens cover; the driving module converts the collected signal to be tested into a differential amplified signal through a differential amplifier; Wherein, the clock frequency division module includes resistors R30 to R41, a crystal oscillator G1, a capacitor C36, a capacitor C37 and a chip N1 which are numbered in sequence; one end of the resistor R30 is connected to the power supply 3.3V-CLK, and the other end of the resistor R30 is respectively connected to one end of the capacitor C36, one end of the capacitor C37 and the fourth pin of the crystal oscillator G1, the other end of the capacitor C36, the other end of the capacitor C37 and the second pin of the crystal oscillator G1 are all grounded, the third pin of the crystal oscillator G1 is connected to the first pin of the chip N1 through the resistor R31, the second pin, the fifth pin, the ninth pin of the chip N1 and one end of the capacitor C38 are all connected to the power supply 3.3V-CLK, the fourth pin and the seventh pin of the chip N1 are both connected to the other end of the capacitor C38 and grounded; the eighth pin, the tenth pin, the twelfth pin, the thirteenth pin of the chip N1 The fifteenth pin, the seventeenth pin, the nineteenth pin and the twentieth pin are respectively connected to one end of resistor R38, one end of resistor R41, one end of resistor R40, one end of resistor R39, one end of resistor R37, one end of resistor R35, one end of resistor R33 and one end of resistor R32, and the other end of resistor R38, the other end of resistor R41, the other end of resistor R40, the other end of resistor R39, the other end of resistor R37, the other end of resistor R35, the other end of resistor R33 and the other end of resistor R32 are all connected to the AD interface of chip U2 in the AD module; the third pin of chip N1 is connected to the second processing chip FPGA2 in the FPGA module through resistor R34, and the sixth pin of chip N1 is connected to the first processing chip FPGA1 in the FPGA module through resistor R36.

2. The fault detection device based on the 64-channel acoustic signal receiving array according to claim 1 is characterized in that: The sub-array unit is an acoustic sensor or a microphone.

3. The fault detection device based on the 64-channel acoustic signal receiving array according to claim 2 is characterized in that: The acoustic sensor is a MEMS acoustic sensor with a frequency response range of 20 Hz-100 KHz.

4. The fault detection device based on the 64-channel acoustic signal receiving array according to claim 2 is characterized in that: The detection band range of the microphone is 0-100KHz.

5. The fault detection device based on the 64-channel acoustic signal receiving array according to claim 1, characterized in that: The spacing between the sub-array units ranges from 5 mm to 10 cm.

6. The fault detection device based on the 64-channel acoustic signal receiving array according to claim 1, characterized in that: The operational amplifier module includes a resistor R389, a resistor R390, a capacitor C140, a capacitor C148, an operational amplifier N65A, a capacitor C150, a resistor R393 and a capacitor C149, one end of the capacitor C140, one end of the capacitor C148, one end of the resistor R389 and the fourth pin of the operational amplifier N65A are all connected to a +5V power supply, one end of the resistor R390, the third pin of the operational amplifier N65A and one end of the capacitor C150 are all connected to the other end of the resistor R389, the second pin of the operational amplifier N65A is connected to the first pin of the operational amplifier N65A, the negative end of the power supply of the operational amplifier N65A is connected to the other end of the capacitor C150 and is grounded, the first pin of the operational amplifier N65A is connected to one end of the capacitor C149 through the resistor R393, and the other end of the capacitor C149, the other end of the capacitor C140, the other end of the capacitor C148 and the other end of the resistor R390 are all grounded; The driving module includes a differential amplifier U1, sequentially numbered resistors R200 to R205, a capacitor C200 and a capacitor C201. The model of the differential amplifier U1 is ADA4940-1ARZ. One end of the resistor R200 is connected to a +5V-1# power supply, one end of the capacitor C200, one end of the capacitor C201 and the third pin of the differential amplifier U1 are all connected to the other end of the resistor R200, the second pin of the differential amplifier U1 is connected to one end of the capacitor C149, the fourth pin of the differential amplifier U1 is connected to one end of the resistor R202, the other end of the resistor R202 and the capacitor C201 are connected to the first and second pins of the differential amplifier U1. One end of the resistor R201 is connected to the first pin of the differential amplifier U1, and the other end of the resistor R201 is grounded; the fifth pin of the differential amplifier U1 is connected to one end of the resistor R205, the other end of the resistor R205 and one end of the resistor R203 are connected to the eighth pin of the differential amplifier U1, the other end of the resistor R203 is connected to an acoustic sensor in the acoustic signal receiving array through a capacitor, the sixth pin of the differential amplifier U1, the other end of the capacitor C200 and the other end of the capacitor C201 are all grounded, and the seventh pin of the differential amplifier U1 is connected to the +5V-1# power supply through the resistor R204; The filtering module includes a capacitor C19, a capacitor C22, a resistor R13, a resistor R14, a resistor R17, a resistor R18, a capacitor C21, a capacitor C20 and a capacitor C25, one end of the capacitor C19 is connected to one end of the resistor R202, one end of the capacitor C22 is connected to one end of the resistor R205, the other end of the capacitor C19 is respectively connected to one end of the resistor R13 and one end of the resistor R14, the other end of the capacitor C22 is respectively connected to one end of the resistor R17 and one end of the resistor R18, the other end of the resistor R14 is connected to the other end of the resistor R17, the other end of the resistor R13 is respectively connected to one end of the capacitor C21 and one end of the capacitor C20, the other end of the resistor R18 is respectively connected to the other end of the capacitor C21 and one end of the capacitor C25, and the other end of the capacitor C20 is connected to the other end of the capacitor C25 and grounded; The AD module includes a chip U2, the model of the chip U2 is AD7761BSTZ, the ninth pin of the chip U2 is connected to one end of the capacitor C20, and the tenth pin of the chip U2 is connected to one end of the capacitor C25; the FPGA module includes a first processing chip FPGA1, a second processing chip FPGA2 and a third processing chip FPGA3, the DO port, SPI port, SYNC port and STARY port of the first processing chip FPGA1 and the second processing chip FPGA2 are all connected to the corresponding port of the chip U2, the first processing chip FPGA1 and the second processing chip FPGA2 are both connected to the third processing chip FPGA3, the models of the first processing chip FPGA1 and the second processing chip FPGA2 are both AC616, and the model of the third processing chip FPGA3 is AC6045; The model of the chip N1 is 5PB1110PGG-TSSOP20.

7. The fault detection device based on the 64-channel acoustic signal receiving array according to claim 6, characterized in that: The communication module includes a chip N2, sequentially numbered resistors R45 to R63, sequentially numbered capacitors C52 to C62, a crystal oscillator G2 and an inductor L3, one end of the resistor R45 is connected to the power supply 3.3V-LAN, the other end of the resistor R45 is respectively connected to one end of the capacitor C52, one end of the capacitor C53 and the fourth pin of the crystal oscillator G2, the third pin of the crystal oscillator G2 is connected to one end of the resistor R46, and the other end of the resistor R46 is connected to the sixty-first pin of the chip N2; one end of the inductor L3 is respectively connected to the power supply 3.3V-LAN, one end of the capacitor C57, one end of the capacitor C58 and The sixty-fourth pin of chip N2 is connected, the other end of capacitor C57, the other end of capacitor C58, the sixty-fifth pin of chip N2, the sixty-third pin of chip N2, the second pin of chip N2 and the fourth pin of chip N2 are connected and grounded, the other end of inductor L3 is respectively connected to one end of capacitor C54, one end of capacitor C55, one end of capacitor C56 and the sixtieth pin of chip N2; one end of resistor R47 is connected to the fifty-eighth pin of chip N2, the fifty-first pin, the fifty-third pin, the fifty-fourth pin, the fifty-fifth pin, the fifty-sixth pin and the fifty-seventh pin of chip N2 are respectively connected. One end of the resistor R53 is connected to one end of the resistor R48, and the other end of the resistor R53 and the other end of the resistor R48 are both connected to the power supply 3.3V-LAN; one end of the resistor R54 is connected to the 50th pin of the chip N2, one end of the capacitor C59 and one end of the capacitor C60 are both connected to the 49th pin of the chip N2 and the power supply 3.3V-LAN, and the 47th pin of the chip N2 is grounded through the resistor R55; one end of the capacitor C61 and one end of the capacitor C62 are connected to the third pin of the chip N2 and connected to the 1.0V power supply, the 18th pin of the chip N2 is grounded through the resistor R58, and the The 30th pin, the 29th pin, the 28th pin and the 27th pin are respectively connected to one end of the resistor R59 to one end of the resistor R63, and the other end of the resistor R59 to the other end of the resistor R63 are connected to the power supply 3.3V-LAN; the other end of the capacitor C52 to the other end of the capacitor C62 are grounded; the 38th pin to the 47th pin, the 34th pin to the 36th pin, the 18th pin, the 19th pin, the 21st pin to the 25th pin, the 27th pin to the 30th pin, and the 53rd pin to the 57th pin of the chip N2 are all connected to the third processing chip FPGA3; The network interface is an RJ45 interface, which includes a chip XS1A, a capacitor C49, a capacitor C50 and several resistors. The TRD1+ pin of the chip XS1A is connected to one end of the capacitor C49 and one end of the capacitor C50 through the resistor R1. The TRD1+ pin, the TRCT1 pin, the TRD2+ pin, the TRCT2 pin, the TRD3+ pin, the TRCT3 pin, the TRD4+ pin and the TRCT4 pin of the chip XS1A are respectively connected to the fifth pin, the sixth pin, the eighth pin, the ninth pin, the eleventh pin, the twelfth pin, the fourteenth pin and the fifteenth pin of the chip N2 through a resistor in a one-to-one correspondence. The M1 pin of the chip XS1A is connected to one end of the resistor R42 and one end of the capacitor C51. The other end of the capacitor C51 and the other end of the resistor R42 are both grounded.

8. The fault detection device based on the 64-channel acoustic signal receiving array according to claim 6, characterized in that: The network interface is a USB3.0 interface, one end of which is connected to the third processing chip FPGA3; the fault detection device also includes an industrial computer, which is located in the shell and is connected to the other end of the USB3.0 interface.

9. The fault detection device based on the 64-channel acoustic signal receiving array according to claim 1, characterized in that: It also includes a first power module, which supplies power to the device. The first power module includes a rectifier and filter unit, a first step-down unit, and a second step-down unit. The rectifier and filter unit, the first step-down unit, and the second step-down unit are connected in sequence. The rectifier and filter unit includes a Schottky diode VD1, a capacitor C1, a filter L1, a capacitor C2, and a capacitor C3. The anode of the Schottky diode VD1 is connected to the first end of the power interface, the cathode of the Schottky diode VD1 is connected to one end of the capacitor C1 and the opposite end of the primary coil of the filter L1, the same end of the primary coil of the filter L1 is connected to one end of the capacitor C2 and one end of the capacitor C3, the second end of the power interface is connected to the other end of the capacitor C1 and the opposite end of the secondary coil of the filter L1 and is grounded, and the same end of the secondary coil of the filter L1 is connected to the other end of the capacitor C2 and the other end of the capacitor C3 and is grounded; The first step-down unit includes a resistor R25, a resistor R26, a resistor RT2, a capacitor C5, a resistor R27, a light-emitting diode V1', a chip U3, a capacitor C4, a transistor VT1, a resistor R28, a resistor R29, an inductor L2, a Schottky diode VD2, a capacitor C6, a resistor RT1 and a resistor RB1. The model of the chip U3 is LMR16020-G8. One end of the resistor R25, one end of the capacitor C5 and the second pin of the chip U3 are all connected to a 12V power supply. The other end of the resistor R25 is connected to one end of the resistor R26 and the third pin of the chip U3. One end of the resistor RT2 is connected to the fourth pin of the chip U3. One end of the capacitor C4 is connected to the first pin of the chip U3. The other end of the capacitor C4, the eighth pin of the chip U3 and the cathode of the Schottky diode VD2 are all connected to one end of the inductor L2. The other end of L2 is connected to one end of capacitor C6 and one end of resistor RT1, one end of resistor RT1 is used as a 5V power supply output end, one end of resistor RB1 is connected to the other end of resistor RT1 and the fifth pin of chip U3, one end of resistor R27 is connected to a 12V power supply, the other end of resistor R27 is connected to the anode of light-emitting diode V1', the cathode of light-emitting diode V1' is connected to the collector of transistor VT1, the base of transistor VT1 is connected to one end of resistor R29, the other end of resistor R29 is connected to one end of resistor R28, the other end of resistor R28 is used as a 5V power supply output end, the other end of resistor R29 is connected to the sixth pin of chip U3, the other end of resistor R26, the other end of resistor RT2, the emitter of transistor VT1, the seventh pin of chip U3, the anode of Schottky diode VD2 and the other end of resistor RB1 are all grounded; The second step-down unit includes capacitor C31, chip U4, capacitor C32, capacitor C33 and capacitor C42. The model of chip U4 is REG1117-3.

3. One end of capacitor C31 and the third pin of chip U4 are connected to a 5V power supply. The second pin and the fourth pin of chip U4 are connected to one end of capacitor C32. One end of capacitor C32 serves as a 3.3V power supply output end. One end of capacitor C33 and one end of capacitor C42 are connected to one end of capacitor C32. The other end of capacitor C31, the first pin of chip U4, the other end of capacitor C32, the other end of capacitor C33 and the other end of capacitor C42 are grounded.

10. The fault detection device based on a 64-channel acoustic signal receiving array according to claim 1, characterized in that: It also includes a second power supply module, the second power supply module supplies power to the device, and the second power supply module includes a multi-channel output unit and a third step-down unit, The multi-channel output unit includes capacitors C130 to C135, capacitor C165 and several output sub-channels, one of which includes inductor FB2, capacitor C136, capacitor C166, capacitor C167, capacitor C137, light-emitting diode V1 and resistor R386. The positive electrodes of capacitors C130 to C135 and capacitor C165 are all connected to a +5V power supply. The negative electrodes are all grounded, one end of the inductor FB2 is connected to a +5V power supply, the positive electrodes of the capacitors C136, C166 and C167, and one end of the capacitor C137 are all connected to the other end of the inductor FB2, the negative electrodes of the capacitors C136, C166 and C167, and the other end of the capacitor C137 are all grounded, one end of the capacitor C137 is connected to the anode of the light emitting diode V1, the cathode of the light emitting diode V1 is connected to one end of the resistor R386, and the other end of the resistor R386 is grounded; The third step-down unit includes capacitor C129, inductor FB1, inductor FB3, capacitor C133, capacitor C134, chip U5, resistor RB2, resistor RT2, capacitor CC1, capacitor C130, capacitor C132, capacitor C131, resistor R385 and light emitting diode V9. The model of chip U5 is ADP1708ARDZ-R7. One end of capacitor C129 is connected to the first end of the power interface and one end of the inductor FB1. The other end of the inductor FB1 serves as the +5V power output end. The first pin of chip U5, the third pin of chip U5, one end of capacitor C133 and one end of capacitor C134 are all connected to the other end of inductor FB1. The other end of capacitor C129, one end of inductor FB3, the second end and the third end of the power interface are all grounded GND-IN. The other end of inductor FB3, the other end of capacitor C133, capacitor C134 are all grounded GND-IN. The other end of 134, the second pin of chip U5, one end of resistor RB2 and one end of capacitor CC1 are all connected and grounded, the other end of capacitor CC1 and the other end of resistor RB2 are connected to the eighth pin of chip U5, the fifth pin, the sixth pin and the seventh pin of chip U5, one end of resistor RT2 and one end of capacitor C135 are all connected, the other end of resistor RT2 and the other end of capacitor C135 are connected to the other end of capacitor CC1; one end of capacitor C130, the positive electrode of capacitor C132, one end of capacitor C131 and the anode of light-emitting diode V9 are all connected to the sixth pin of chip U5, and one end of capacitor C130 serves as the +3.6V power output end; resistor R385 is connected between the other end of capacitor C131 and the cathode of light-emitting diode V9, and the other end of capacitor C131, the negative electrode of capacitor C132 and the other end of capacitor C130 are all grounded.

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