Semiconductor packaging method and structure thereof

Abstract

The present invention discloses a semiconductor packaging method and structure. The semiconductor packaging structure includes a lead frame, which has a plurality of pins, and the pins have a receiving wire, wherein a spacing area is formed between adjacent symmetrically arranged receiving wires, and an inner concave portion is formed at the bottom of the receiving wire; a chip is placed on the receiving wire and shields the spacing area; a lead wire electrically connects the chip and the pin; and a sealing body covers the chip, the receiving wire, the lead wire and partially exposes the pin. The present invention provides an adhesive in the contact area between the chip and the receiving wire, and the adhesive will be distributed in the spacing area and the inner concave portion after solidification, thereby enhancing the supporting force of the receiving wire and preventing the receiving wire from sinking and deforming during the wire bonding operation.

Description

Technical Field

[0001] The invention belongs to the technical field of a semiconductor packaging method and structure, and in particular to a design that can improve the structural strength when a chip is bonded to a lead frame. Background Art

[0002] In semiconductor packaging structures, lead frames have been used for a long time due to their low material cost and high reliability. Depending on the location of the chip, lead frames can be divided into traditional lead frames using chip holders, lead-on-chip (LOC) lead frames, and chip-on-lead (COL) lead frames. The difference between lead-on-chip (LOC) and chip-on-lead (COL) is that lead-on-chip is to attach the lead of the lead frame to the active surface of the chip, while chip-on-lead is to attach the back of the chip to the lead of the lead frame.

[0003] like Figure 1 FIG. 1 is a schematic diagram of a chip-on-lead (COL) package structure. The lead frame 1 has a plurality of pins 11, and the pins 11 have a receiving wire 111. The chip 12 is fixed to the receiving wire 111 by using a die attach film (DAF) 13. During the pressurization process of the wire bonding operation, the receiving wire 111 is easily pressed down to cause deformation, so that the chip 12 cannot be adhered to the receiving wire 111, resulting in poor bearing capacity. In the subsequent sealing operation, it is easy to be affected by mold flow and cause the chip 12 to deviate. Summary of the invention

[0004] To solve the above problems, the main purpose of the present invention is to provide a semiconductor chip packaging method and structure thereof, which mainly allows part of the adhesive to sink when the chip is adhered to the lead frame, and forms a hook-shaped structure after solidification, thereby improving the supporting strength of the lead frame and preventing the supporting wire from sinking and deforming.

[0005] To achieve the above-mentioned purpose, the present invention adopts the following technical solutions:

[0006] The present invention is a semiconductor packaging structure, comprising: a lead frame, having a plurality of pins, the pins having a receiving wire, a spacing area is formed between two adjacent receiving wires, and the receiving wires form an inner concave portion at the bottom of the adjacent spacing areas; a chip, placed on the receiving wires and shielding the spacing area; a lead, electrically connecting the chip and the pins; a sealing body, covering the chip, the receiving wires, the leads and leaving the pins partially exposed, an adhesive body is provided in the contact area between the chip and the receiving wires, and the adhesive body is distributed in the spacing area and the inner concave portion.

[0007] Furthermore, the present invention is a semiconductor packaging method, the steps of which include: applying adhesive to a wafer; attaching an adhesive film to the adhesive; cutting the wafer to form a plurality of chips, the chips being adhered to the adhesive; removing the chips adhered to the adhesive from the adhesive film; placing the chips on symmetrically arranged receiving wires of a lead frame with the adhesive, the adhesive filling the spacing between the receiving wires and being distributed in the inner concave portion at the bottom of the receiving wires; performing a wire bonding operation so that the two ends of the leads are electrically connected to the chip and the pins respectively; and encapsulating the chip, the receiving wires, and the leads with the encapsulating body and leaving the pins partially exposed.

[0008] As one of the preferred embodiments, the lead frame forms an inner recess at the bottom of the lead holder by half etching.

[0009] As one of the preferred embodiments, the longitudinal dimension of the spacing zone increases gradually from top to bottom.

[0010] As one of the preferred embodiments, the position of the supporting wire corresponding to the spacing area forms an inclined surface.

[0011] As one of the preferred embodiments, the position of the supporting wire corresponding to the spacing area forms an arc surface.

[0012] As one of the preferred embodiments, the area where the supporting wire contacts the viscose is a rough surface.

[0013] As one of the preferred embodiments, the rough surface is located on the top surface, side surface and bottom surface of the conductor support.

[0014] As one of the preferred embodiments, the chip is placed on the symmetrically arranged supporting wires and heated simultaneously, so that the adhesive softens and fills the spacing area and flows into the inner concave part.

[0015] As one of the preferred embodiments, the chip is placed on the symmetrical supporting wires with adhesive, and the chip and the adhesive are pressed down by a chip bonding head, so that part of the adhesive fills the spacing area and flows into the inner concave part.

[0016] Compared with the prior art, the present invention has the following specific effects:

[0017] 1. The chip of the present invention has an adhesive between it and the supporting wire, and the adhesive is distributed in the spacing area and the inner concave part. When the adhesive is solidified, a hook-shaped structure is formed, which can increase the strength of the supporting wire, improve the supporting strength of the wire bonding process, and prevent the supporting wire from sinking and deforming.

[0018] 2. Because the support wire will not sink or deform, the chip can be tightly attached to the support wire, and it is not easy to be affected by mold flow and cause the chip to shift during the subsequent sealing operation.

[0019] 3. It can improve the yield of wire bonding without spending a lot of cost, and is particularly suitable for small-sized packaging components of 1mm*1mm. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of the packaging structure of the chip on pin (COL) in the existing technology.

[0021] Figure 2 FIG. 4 is a cross-sectional schematic diagram of a first embodiment of a semiconductor package structure of the present invention.

[0022] Figure 3 FIG. 4 is a cross-sectional schematic diagram of a second embodiment of a semiconductor package structure of the present invention.

[0023] Figure 4 FIG. 4 is a cross-sectional schematic diagram of a third embodiment of a semiconductor package structure of the present invention.

[0024] Figure 5 FIG. 4 is a cross-sectional schematic diagram of a fourth embodiment of a semiconductor package structure of the present invention.

[0025] Figure 6 The semiconductor packaging structure of the present invention is a flow chart of a chip-on-lead (COL) packaging method of the first embodiment.

[0026] Figure 7A to Figure 7H FIG. 1 is a schematic diagram of an operation of a chip-on-lead (COL) packaging method of a semiconductor packaging structure of a first embodiment of the present invention.

[0027] Explanation of the reference numerals: 1-lead frame, 11-pin, 111-supporting wire, 12-chip, 13-chip adhesive film, 2-lead frame, 21-pin, 211-supporting wire, 212-inner concave portion, 213-inclined surface, 214-arc surface, 215-rough surface, 22-spacer, 3-chip, 4-adhesive body, 5-lead, 6-sealing body, 7-cutting device, 8-chip bonding head. DETAILED DESCRIPTION

[0028] The following describes the implementation of the present invention by means of specific embodiments. People familiar with the technical field can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied by means of other different specific examples, and the details in the present invention specification can also be modified and changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0029] like Figure 2The figure shows a cross-sectional schematic diagram of the first embodiment of the semiconductor packaging structure of the present invention. This embodiment includes: a lead frame 2, having a plurality of pins 21. One end of the pin 21 has a receiving wire 211. Adjacent symmetrical receiving wires 211 form a spacing area 22, and the receiving wires 211 are connected to the bottom of the spacing area 22 to form an inner recess 212. The chip 3 is placed on the receiving wire 211 and shields the spacing area 22. The contact area between the chip 3 and the receiving wire 211 is provided with an adhesive 4, and the adhesive 4 is also distributed in the spacing area 22 and the inner recess 212. The lead 5 has two ends electrically connecting the chip 3 and the pin 21. The encapsulation body 6 covers the chip 3, the receiving wire 211, the lead 5 and allows the pin 21 to be partially exposed.

[0030] The design of the present invention is that when the chip 3 is adhered to the receiving wire 211 with the adhesive 4, heating and pressure will soften the adhesive 4 to further fill the spacing area 22 and extend into the inner recess 212. In this way, when the adhesive 4 is cured, it will be tightly fixed to the receiving wire 211 like a barb, and the chip 3 will be tightly adhered to the receiving wire 211. In the subsequent wire bonding operation, the adhesive 4 cured in the inner recess 212 provides appropriate support force, which can effectively prevent the receiving wire 211 from sinking, reduce the production of defective products, and improve production quality. In addition, the chip 3 is tightly adhered to the receiving wire 211, and it is not easy to be affected by mold flow and cause the chip 3 to deviate in the subsequent sealing operation.

[0031] In the above embodiment, the longitudinal dimensions of the spacer 22 from top to bottom are the same, but the invention is not limited thereto. In order to increase the flow of the adhesive 4 or the strength after curing, the present invention further provides the following different embodiments. Figure 3 , which is a cross-sectional view of a second embodiment of a semiconductor package structure of the present invention. In this embodiment, the longitudinal dimension of the spacer 22 increases gradually from top to bottom. In this embodiment, an inclined surface 213 is formed at the position of the supporting wire 211 corresponding to the spacer 22, so as to make it easier for the adhesive 4 to flow along the inclined surface 213 to the spacer 22 and the inner concave portion 212.

[0032] like Figure 4 FIG. 2 is a cross-sectional view of a third embodiment of a semiconductor package structure of the present invention. In this embodiment, the longitudinal dimension of the spacer 22 is still gradually increased from top to bottom. However, in this embodiment, a curved surface 214 is formed at the position of the supporting wire 211 corresponding to the spacer 22. The curved surface 214 also helps the adhesive 4 to flow into the spacer 22 and the inner concave portion 212.

[0033] like Figure 5. It is a cross-sectional schematic diagram of the fourth embodiment of the semiconductor packaging structure of the present invention. In this embodiment, rough surfaces 215 are formed on the top surface, side surface and bottom surface of the receiving wire 211. The rough surfaces 215 are distributed in the area where the receiving wire 211 contacts the adhesive 4, which can increase the contact area between the adhesive 4 and the receiving wire 211, and improve the bonding strength of the adhesive 4 set on the receiving wire 211.

[0034] Then as Figure 6 The figure is a flow chart of the semiconductor packaging method of the present invention. Figure 7A to Figure 7H The steps of the packaging method of the present invention include:

[0035] Step 301, coating the adhesive 4 on the wafer 30; Fig. 7A As shown, a layer of adhesive 4 is coated on the bottom of the wafer 30 .

[0036] Step 302, attaching the adhesive film 6 to the adhesive body 4; Figure 7B As shown, a layer of adhesive film 6 is adhered to the bottom of the adhesive body 4 .

[0037] Step 303, cutting the wafer 30 into a plurality of chips 3, and the chips 3 are adhered to the adhesive 4; Figure 7C As shown, a wafer 30 is cut by a cutting device 7 to form a plurality of chips 3 , and each chip 3 is individually adhered to an adhesive 4 .

[0038] Step 304, remove the chip 3 adhered to the adhesive 4 from the adhesive film 6; Fig.7D As shown, a single chip 3 is picked up by a die bonding head 8 , and the adhesive 4 is also peeled off from the adhesive film 6 .

[0039] Step 305, place the chip 3 on the symmetrically arranged supporting wires 211 of the lead frame 2 with the adhesive 4, and fill the space 22 between the supporting wires 211 with the adhesive 4, and distribute in the inner concave portion 212 at the bottom of the supporting wires 211. Fig. 7E As shown, the lead frame 2 used has a plurality of pins 21, and the pins 21 have a receiving wire 211. The lead frame 2 can form an inner concave portion 212 at the bottom of the receiving wire 211 by half etching. A through spacing area 22 is formed between the symmetrically arranged receiving wires 211. Please refer to Figure 7F As shown, when the chip 3 is placed on the supporting wire 211 by the die bonding head 8, the adhesive 4 is also heated synchronously, so that the adhesive 4 softens and is distributed between the chip 3 and the supporting wire 211. Furthermore, the die bonding head 8 also provides a pressure to the chip 3, so that the adhesive 4 fills the spacer 22 and the inner concave portion 212. After the adhesive 4 is solidified, it will be tightly bonded to the supporting wire 211 like a barb.

[0040] Step 306, perform wire bonding to electrically connect the two ends of the lead 5 to the chip 3 and the pin 21 respectively; Figure 7G As shown, two ends of the lead 5 are connected to the chip 3 and the pin 21 .

[0041] Step 307, the chip 3 is encapsulated by the encapsulating plastic 6, and the wires 211 and the leads 5 are placed thereon, and the pins 21 are partially exposed. Figure 7H As shown, the chip 3, the supporting wire 211, the lead 5, and the pin 21 are covered with a sealing body 6. The pin 21 is partially exposed to serve as an electrical connection terminal.

[0042] In summary, the chip-on-lead (COL) packaging method and structure of the present invention is that the chip 3 is adhered to the supporting wire 211 by the adhesive 4, and the adhesive 4 is further distributed in the spacing area 22 and the inner concave portion 212. When the adhesive 4 is solidified, it will be tightly fixed to the supporting wire 211 like a barb, thereby improving the support strength of the lead frame 2, preventing the supporting wire 211 from sinking and deforming, and achieving the greatest effect at the lowest cost, which meets the application requirements of the patent.

[0043] However, the above embodiments are only illustrative of the effects of the present invention, and are not intended to limit the present invention. Any person skilled in the art may modify and change the above embodiments without violating the spirit and scope of the present invention. In addition, the number of components in the above embodiments is only illustrative, and is not intended to limit the present invention. Therefore, the scope of protection of the present invention should be as listed in the following patent application scope.

Claims

1. A semiconductor packaging method, characterized in that: The semiconductor packaging method comprises the following steps: Applying adhesive to the wafer; Attaching an adhesive film to the adhesive body; Cutting the wafer into a plurality of chips, wherein the chips are adhered to the adhesive; Remove the chip adhered to the adhesive from the adhesive film; The chip is placed on the symmetrically arranged supporting wires of the lead frame through the adhesive, and the adhesive fills the space between the supporting wires and is distributed in the inner concave part at the bottom of the supporting wires; Performing wire bonding to electrically connect the two ends of the lead wire to the chip and the pin respectively; The chip, the receiving wire, and the lead are sealed with a sealing gel and the pins are partially exposed to obtain a semiconductor packaging structure, the semiconductor packaging structure comprising: a lead frame having a plurality of pins, the pins having receiving wires, a spacing area formed between two adjacent receiving wires, the receiving wires connected to the bottom of the spacing area to form an inner concave portion; a chip placed on the receiving wires and shielding the spacing area; The lead electrically connects the chip and the pin; the encapsulation body covers the chip, the supporting wire, the lead and exposes the pin part; the contact area between the chip and the supporting wire is provided with an adhesive body, and the adhesive body is distributed in the spacing area and the inner concave part.

2. The semiconductor packaging method according to claim 1, wherein: The lead frame forms the inner concave portion at the bottom of the lead receiving portion by half etching.

3. The semiconductor packaging method according to claim 1, wherein: The longitudinal dimension of the spacer area increases gradually from top to bottom.

4. The semiconductor packaging method according to claim 3, wherein: The position of the supporting wire corresponding to the spacing area forms an inclined surface.

5. The semiconductor packaging method according to claim 3, wherein: The position of the supporting wire corresponding to the spacing area forms an arc surface.

6. The semiconductor packaging method according to claim 1, wherein: The area where the supporting wire contacts the viscose is a rough surface.

7. The semiconductor packaging method according to claim 6, wherein: The rough surface is located on the top surface, side surface and bottom surface of the supporting wire.

8. The semiconductor packaging method according to claim 1, wherein: When the chip is placed on the symmetrical supporting wires, it is heated synchronously, so that the adhesive is softened to fill the spacing area and flow into the inner concave part.

9. The semiconductor packaging method according to claim 1, wherein: The chip is placed on the symmetrical supporting wire through the adhesive, and the chip and the adhesive are pressed down by a chip bonding head, so that part of the adhesive fills the spacing area and flows into the inner concave part.

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