Vertical memory device

Abstract

A vertical memory device is provided. The vertical memory device includes: a circuit pattern located on a first substrate; an insulating interlayer located on the first substrate, the insulating interlayer covering the circuit pattern; a bending prevention layer located on the insulating interlayer, the bending prevention layer extending in a first direction substantially parallel to an upper surface of the first substrate; a second substrate located on the bending prevention layer; gate electrodes spaced apart from each other along a second direction on the second substrate, the second direction being substantially perpendicular to an upper surface of the first substrate; and a channel extending through the gate electrode in the second direction.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2019-0074144 filed on June 21, 2019 in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] Example embodiments of the inventive concept relate to a vertical memory device. Background Art

[0003] A VNAND flash memory device may include horizontal layers of memory cells stacked in a vertical direction. In a VNAND flash memory device, as the number of gate electrodes stacked in a vertical direction increases, the substrate may be more easily bent. However, in this case, the VNAND flash memory device may not have uniform electrical characteristics. Summary of the invention

[0004] According to an exemplary embodiment of the inventive concept, a vertical memory device is provided, comprising: a circuit pattern on a first substrate; an insulating interlayer on the first substrate, the insulating interlayer covering the circuit pattern; a bending prevention layer on the insulating interlayer, the bending prevention layer extending in a first direction substantially parallel to an upper surface of the first substrate; a second substrate on the bending prevention layer; gate electrodes spaced apart from each other on the second substrate along a second direction, the second direction being substantially perpendicular to an upper surface of the first substrate; and a channel extending through the gate electrode in the second direction.

[0005] According to an exemplary embodiment of the inventive concept, a vertical memory device is provided, comprising: a circuit pattern on a first substrate, the first substrate comprising a cell region and a peripheral circuit region adjacent to the cell region; a first insulating interlayer on the first substrate, the first insulating interlayer covering the circuit pattern; a first bending prevention layer located on the first insulating interlayer on the cell region and the peripheral circuit region; a second substrate located on the first bending prevention layer on the cell region; gate electrodes spaced apart from each other on the second substrate along a first direction on the cell region, the first direction being substantially perpendicular to an upper surface of the first substrate; a channel extending through the gate electrode along the first direction on the cell region; and a first contact plug extending through the first bending prevention layer along the first direction on the peripheral circuit region, the first contact plug being electrically connected to the circuit pattern.

[0006] According to an exemplary embodiment of the inventive concept, a vertical memory device is provided, the vertical memory device comprising: a transistor, on a first substrate; a lower wiring, on the first substrate, the lower wiring being electrically connected to the transistor; a first insulating interlayer, on the first substrate, the first insulating interlayer covering the transistor and the lower wiring; a bending prevention layer, on the first insulating interlayer, the bending prevention layer extending in a first direction substantially parallel to an upper surface of the first substrate; a second substrate, on the bending prevention layer; gate electrodes, on the second substrate, spaced apart from each other along a second direction, the second direction being substantially perpendicular to an upper surface of the first substrate; a second insulating interlayer, on the second substrate, the second insulating interlayer covering a sidewall of the gate electrode; a channel extending through the gate electrode in the second direction; an upper wiring, on the gate electrode, the upper wiring being electrically connected to the gate electrode; a first contact plug structure extending through the gate electrode, the second substrate and the bending prevention layer, the first contact plug structure being electrically connected to a first lower wiring among the lower wirings; and a second contact plug extending through the second insulating interlayer and the bending prevention layer, the second contact plug being electrically connected to a second lower wiring among the lower wirings.

[0007] According to an exemplary embodiment of the inventive concept, a vertical memory device is provided, comprising: a circuit pattern on a first substrate; an insulating interlayer on the first substrate, the insulating interlayer covering the circuit pattern; a bending prevention layer on the insulating interlayer, the bending prevention layer comprising a plurality of protrusions and a plurality of recesses, a second substrate on the bending prevention layer; a gate electrode stacked in a first direction substantially perpendicular to an upper surface of the first substrate; and a channel extending through the gate electrode in the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 , Figure 2 , Figure 3 and Figure 4 are a plan view and a cross-sectional view illustrating a vertical memory device according to an exemplary embodiment of the inventive concept.

[0009] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 and Fig.18 are plan views and cross-sectional views illustrating a method of manufacturing a vertical memory device according to an exemplary embodiment of the inventive concept.

[0010] Fig.19is a plan view illustrating a layout of a first concave portion at an upper portion of a first bending prevention layer according to an exemplary embodiment of the inventive concept.

[0011] Fig. 20 , Fig.21 , Fig.22A , Fig. 22B , Fig.23 , Fig.24 , Fig.25 and Fig.26 is a cross-sectional view illustrating a vertical memory device according to an exemplary embodiment of the inventive concept.

[0012] Fig. 27 is a cross-sectional view illustrating a vertical memory device according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0013] A vertical memory device and a method of manufacturing the same according to exemplary embodiments of the inventive concept will hereinafter be described more fully with reference to the accompanying drawings.

[0014] Figures 1 to 4 1 is a plan view and a cross-sectional view showing a vertical memory device according to an exemplary embodiment of the inventive concept. Specifically, Figure 1 and Figure 4 It is a floor plan. Figure 2 and Figure 3 It is a cross-sectional view.

[0015] Figure 2 is along Figure 1 A cross-sectional view taken along line A-A', Figure 3 is along Figure 1 In order to avoid complicated drawings, Figure 1 The circuit pattern is not shown. Figure 4 is a plan view of the first bending preventing layer.

[0016] Hereinafter, a vertical direction substantially perpendicular to the upper surface of the first substrate may be a first direction, and two directions intersecting each other among horizontal directions substantially parallel to the upper surface of the first substrate may be a second direction and a third direction, respectively. In an exemplary embodiment of the inventive concept, the second direction and the third direction may be orthogonal to each other.

[0017] Reference Figures 1 to 4, the vertical memory device may include a lower circuit pattern on the first substrate 100, a first bending prevention layer 240 above the lower circuit pattern, a memory cell on the first bending prevention layer 240, a contact plug 280, a contact plug 484, a contact plug 492 and a contact plug 494, and an upper circuit pattern. The vertical memory device may also include a second substrate 290, a first buffer layer 270, a common source line (CSL) 482, a first insulating interlayer 160 and a second insulating interlayer 230, a third insulating interlayer pattern 300, and a fourth insulating interlayer 340, a fifth insulating interlayer 350, a sixth insulating interlayer 420, a seventh insulating interlayer 500, an eighth insulating interlayer 520, a ninth insulating interlayer 540, a tenth insulating interlayer 560, an eleventh insulating interlayer 580, and a twelfth insulating interlayer 600.

[0018] Each of the first substrate 100 and the second substrate 290 may include a semiconductor material (e.g., silicon, germanium, silicon-germanium, etc.) or a III-V compound (e.g., GaP, GaAs, GaSb, etc.). In an exemplary embodiment of the inventive concept, each of the first substrate 100 and the second substrate 290 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0019] The first substrate 100 may include a field region on which an isolation pattern 110 is formed and an active region 105 on which no isolation pattern is formed. The isolation pattern 110 may include an oxide, for example, silicon oxide.

[0020] In an exemplary embodiment of the inventive concept, the first substrate 100 may include a first region I, a second region II, and a third region III. The first region I may be a cell array region in which a memory cell may be formed, the second region II may be an extension region or a pad (also referred to as a "pad") region in which a contact plug for transmitting an electrical signal to the memory cell may be formed, and the third region III may be a peripheral circuit region at least partially surrounding the second region II in which an upper circuit pattern for applying an electrical signal to the memory cell through the contact plug may be formed. The first region I and the second region II may form a cell region. The peripheral circuit region may at least partially surround the cell region. Figures 1 to 4 A portion of each of the first region I, the second region II, and the third region III is shown.

[0021] In an exemplary embodiment of the inventive concept, the vertical memory device may have a cell-over-peri (COP) structure. In other words, a lower circuit pattern may be formed on the first substrate 100, and a memory cell, a contact plug, and an upper circuit pattern may be formed over the lower circuit pattern.

[0022] The lower circuit pattern may include a transistor, a lower contact plug, a lower wiring, a lower via, etc. In an exemplary embodiment of the inventive concept, a first transistor including a first lower gate structure 152 on a first substrate 100 and a first impurity region 102 at an upper portion of an active region 105 adjacent to the first lower gate structure 152 may be formed; a second transistor including a second lower gate structure 154 on the first substrate 100 and a second impurity region 104 at an upper portion of an active region 105 adjacent to the second lower gate structure 154; and a third impurity region 106 at an upper portion of the active region 105 may be formed.

[0023] In the drawings, the third impurity region 106 is formed on the first region I of the first substrate 100 , and the first transistor and the second transistor are formed on the first region I and the second region II of the first substrate 100 , respectively, however, the inventive concept may not be limited thereto.

[0024] The first lower gate structure 152 may include a first lower gate insulating pattern 122, a first lower gate electrode 132 and a first lower gate mask 142 sequentially stacked on the first substrate 100, and the second lower gate structure 154 may include a second lower gate insulating pattern 124, a second lower gate electrode 134 and a second lower gate mask 144 sequentially stacked on the first substrate 100.

[0025] A first insulating interlayer 160 may be formed on the first substrate 100 to cover the first transistor and the second transistor and the third impurity region 106, and a first lower contact plug 172, a second lower contact plug 174, and a third lower contact plug 176 may be formed through the first insulating interlayer 160 to contact the first impurity region 102, the second impurity region 104, and the third impurity region 106, respectively.

[0026] The first lower wiring 182, the second lower wiring 184, and the third lower wiring 186 may be formed on the first insulating interlayer 160 to respectively contact the first lower contact plug 172, the second lower contact plug 174, and the third lower contact plug 176. The first lower via 192, the fourth lower wiring 202, the fourth lower via 212, and the seventh lower wiring 222 may be sequentially stacked on the first lower wiring 182, the second lower via 194, the fifth lower wiring 204, the fifth lower via 214, and the eighth lower wiring 224 may be sequentially stacked on the second lower wiring 184, and the third lower via 196, the sixth lower wiring 206, the sixth lower via 216, and the ninth lower wiring 226 may be sequentially stacked on the third lower wiring 186.

[0027] The first lower contact plug 172, the second lower contact plug 174 and the third lower contact plug 176, the first lower via 192, the second lower via 194, the third lower via 196, the fourth lower via 212, the fifth lower via 214 and the sixth lower via 216 and the first lower wiring 182, the second lower wiring 184, the third lower wiring 186, the fourth lower wiring 202, the fifth lower wiring 204, the sixth lower wiring 206, the seventh lower wiring 222, the eighth lower wiring 224 and the ninth lower wiring 226 may include conductive materials, for example, metal, metal nitride, metal silicide, doped polysilicon, etc.

[0028] The second insulating interlayer 230 may be formed on the first insulating interlayer 160 to cover the first lower wiring 182, the second lower wiring 184, the third lower wiring 186, the fourth lower wiring 202, the fifth lower wiring 204, the sixth lower wiring 206, the seventh lower wiring 222, the eighth lower wiring 224, and the ninth lower wiring 226, and the first lower via 192, the second lower via 194, the third lower via 196, the fourth lower via 212, the fifth lower via 214, and the sixth lower via 216. The second insulating interlayer 230 and the first insulating interlayer 160 may form a lower insulating interlayer structure, and in some cases, because the first insulating interlayer 160 and the second insulating interlayer 230 may be merged with each other, the lower insulating interlayer structure may include a single layer.

[0029] The first bending preventing layer 240 may be formed on the second insulating interlayer 230. In an exemplary embodiment of the inventive concept, the first bending preventing layer 240 may be formed throughout all of the first substrate 100, in other words, throughout the first, second, and third regions I, II, and III of the first substrate 100.

[0030] In an exemplary embodiment of the inventive concept, the first bending prevention layer 240 may include a pattern at an upper portion thereof, and the pattern may extend in a direction substantially parallel to the upper surface of the first substrate 100 (e.g., in the third direction). In an exemplary embodiment of the inventive concept, the pattern may be a first concave portion 250 on the upper surface of the first bending prevention layer 240. The first concave portion 250 may have a strip shape extending in the third direction, and a plurality of first concave portions 250 may be formed to be spaced apart from each other in the second direction.

[0031] The first bending preventing layer 240 may include a pattern extending in the third direction, and thus, stress may be applied in the third direction to the first substrate 100 on which the first bending preventing layer 240 is formed. Therefore, when the first substrate 100 is bent downward in the third direction, the first bending preventing layer 240 may apply stress upward to the first substrate 100 in the third direction to reduce the bending of the first substrate 100. In other words, the first bending preventing layer 240 may limit the amount by which the first substrate 100 is bent in the third direction.

[0032] In an exemplary embodiment of the inventive concept, the first bending prevention layer 240 can apply compressive stress to the first substrate 100, and a portion of the first bending prevention layer 240 without a recess thereon (in other words, a protrusion of the first bending prevention layer 240) can apply a compressive stress higher than the compressive stress applied by a portion of the first bending prevention layer 240 having the first recess 250 thereon to reduce the downward bending of the first recess 250.

[0033] Alternatively, the first bending preventing layer 240 may apply tensile stress to the first substrate 100, and a portion of the first bending preventing layer 240 having no recess thereon (in other words, a protrusion of the first bending preventing layer 240) may apply a tensile stress higher than a tensile stress applied by a portion of the first bending preventing layer 240 having the first recess 250 thereon, to reduce the upward bending of the first substrate 100. In other words, the protrusion of the first bending preventing layer 240 may reduce bending of the first substrate 100 in two opposite directions.

[0034] The pattern at the upper portion of the first bending preventing layer 240 may also be referred to as a protrusion instead of the first concave portion 250 .

[0035] The pattern at the upper portion of the first bending prevention layer 240 may not extend in the third direction. For example, the pattern may extend in any direction substantially parallel to the upper surface of the first substrate 100. The extending direction of the pattern may depend on the intended bending direction of the first substrate 100.

[0036] In an exemplary embodiment of the inventive concept, the first bending prevention layer 240 may include a material that applies compressive stress or tensile stress to an adjacent structure. In an exemplary embodiment of the inventive concept, the first bending prevention layer 240 may include a nitride, for example, silicon nitride. Alternatively, the first bending prevention layer 240 may include a conductive material, for example, a metal such as tungsten or doped polysilicon. However, when the first bending prevention layer 240 includes a conductive material, it may be separated from other conductive structures to be electrically insulated from other conductive structures, or an insulating material covering the conductive material may also be formed.

[0037] The first buffer layer 270 may be formed on the first bending prevention layer 240 to cover the pattern and may have a flat upper surface. Therefore, when the first concave portion 250 is formed on the first bending prevention layer 240, the first buffer layer 270 may be formed on the first bending prevention layer 240 to fill the first concave portion 250. The first buffer layer 270 may include an oxide, for example, silicon oxide.

[0038] The second substrate 290 may be formed on the first bending prevention layer 240 and the first buffer layer 270. In an exemplary embodiment of the inventive concept, the second substrate 290 may be formed on the first region I and the second region II of the first substrate 100, and a sidewall of the second substrate 290 may be covered by a third insulating interlayer pattern 300 on the second insulating interlayer 230. The third insulating interlayer pattern 300 may include an oxide (e.g., silicon oxide) and may be merged with the second insulating interlayer 230.

[0039] The first contact plug 280 may extend through the first buffer layer 270, the first bending prevention layer 240, and the second insulating interlayer 230 to contact the lower surface of the second substrate 290 and the upper surface of the ninth lower wiring 226, so that an electrical signal may be transmitted therebetween. In an exemplary embodiment of the inventive concept, the first contact plug 280 may extend through and contact the first bending prevention layer 240. However, when the first bending prevention layer 240 includes a conductive material, an insulating spacer may also be formed to cover the sidewall of the first contact plug 280. Optionally, as will be described later with reference to Fig.21 , Fig.22A and Fig. 22B As shown, the first contact plug 280 may extend through the first bending preventing layer 240 , but be spaced apart from a sidewall of the first bending preventing layer 240 .

[0040] In the drawings, the first contact plug 280 extends through the first recess 250 of the first bending prevention layer 240; however, the inventive concept may not be limited thereto. For example, the first contact plug 280 may extend through a portion of the first bending prevention layer 240 on which the first recess 250 is not formed. In addition, in the drawings, the first contact plug 280 is formed on the first region I of the first substrate 100; however, the inventive concept may not be limited thereto, and the first contact plug 280 may be formed on the second region II of the first substrate 100.

[0041] The memory cells may be formed on the second substrate 290 on the first region I and the second region II of the first substrate 100 .

[0042] Memory cells may be arranged in each of the second and third directions to form a memory cell array. The memory cell array may include a plurality of memory cell blocks spaced apart from each other in the third direction, which may be divided by the CSL 482 extending in the second direction.

[0043] Each memory cell block may include a channel block therein. Each channel block may include a plurality of channel columns including a plurality of channels 380 arranged along the second direction. In the drawings, each channel block includes nine channel columns sequentially arranged in the third direction; however, the inventive concept may not be limited thereto.

[0044] Each memory cell block may include a plurality of gate electrodes 462 , 464 and 466 separated from each other in a first direction, an insulating pattern 315 , a columnar structure, and a capping pattern 400 , wherein the insulating pattern 315 is between adjacent ones of the gate electrodes 462 , 464 and 466 , and the columnar structure extends through the gate electrodes 462 , 464 , 466 and the insulating pattern 315 .

[0045] The gate electrodes 462, 464, and 466 may be formed on the first region I and the second region II of the first substrate 100, and the gate electrodes 462, 464, and 466 may be respectively formed at a plurality of levels (or heights) to be spaced apart from each other. Each of the gate electrodes 462, 464, and 466 may extend in the second direction on the first region I and the second region II of the first substrate 100. The extension length of the gate electrodes 462, 464, and 466 in the second direction may gradually decrease from the lowest level to the highest level, and therefore, the gate electrodes 462, 464, and 466 may form a stepped shape.

[0046] The gate electrodes 462, 464, and 466 may include a first gate electrode 462, a second gate electrode 464, and a third gate electrode 466 sequentially stacked in a first direction. The first gate electrode 462 may be a ground selection line (GSL), the second gate electrode 464 may be a word line, and the third gate electrode 466 may be a string selection line (SSL).

[0047] Each of the first gate electrode 462, the second gate electrode 464, and the third gate electrode 466 may be formed at one level or at multiple levels. In an exemplary embodiment of the inventive concept, the first gate electrode 462 may be formed at the lowest level, the third gate electrode 466 may be formed at the highest level and at a level just below the highest level (e.g., the second level from above), and the second gate electrode 464 may be formed at multiple levels between the first gate electrode 462 and the third gate electrode 466.

[0048] In an exemplary embodiment of the inventive concept, an end portion of at least one of the gate electrodes 462, 464, and 466 at a corresponding level in the second direction may have a thickness greater than a thickness of other portions of at least one of the gate electrodes 462, 464, and 466 at a corresponding level. The thick end portion of at least one of the gate electrodes 462, 464, and 466 may be referred to as a conductive pad. In the drawings, the uppermost third gate electrode of the first gate electrode 462 and the third gate electrode 466 does not have a conductive pad, however, the inventive concept may not be limited thereto.

[0049] Each of the gate electrodes 462, 464, and 466 may include a conductive pattern and a barrier pattern, the barrier pattern covering the upper surface, lower surface, and sidewalls of the conductive pattern. The conductive pattern may include a low-resistance metal (e.g., tungsten, titanium, tantalum, platinum, etc.), and the barrier pattern may include a metal nitride (e.g., titanium nitride, tantalum nitride, etc.).

[0050] The sidewalls of the gate electrodes 462, 464, and 466, which may be stacked in a stair shape, may be covered by the fourth insulating interlayer 340 on the third insulating interlayer pattern 300, and the fifth insulating interlayer 350, the sixth insulating interlayer 420, the seventh insulating interlayer 500, the eighth insulating interlayer 520, the ninth insulating interlayer 540, the tenth insulating interlayer 560, the eleventh insulating interlayer 580, and the twelfth insulating interlayer 600 may be sequentially stacked on the uppermost one of the insulating patterns 315 and the fourth insulating interlayer 340. The fourth insulating interlayer 340, the fifth insulating interlayer 350, the sixth insulating interlayer 420, the seventh insulating interlayer 500, the eighth insulating interlayer 520, the ninth insulating interlayer 540, the tenth insulating interlayer 560, the eleventh insulating interlayer 580, and the twelfth insulating interlayer 600 may include oxide (e.g., silicon oxide), and thus may be merged with each other and / or with the third insulating interlayer pattern 300.

[0051] The upper surface, lower surface, and sidewall of each of the gate electrodes 462, 464, and 466 adjacent to the channel 380 or the semiconductor pattern 360 may be covered by the second barrier layer 450. The second barrier layer 450 may include a metal oxide (e.g., aluminum oxide, hafnium oxide, etc.), and may also cover the sidewall of each of the insulating patterns 315.

[0052] The insulating pattern 315 may include oxide (eg, silicon oxide).

[0053] Each of the columnar structures may include a semiconductor pattern 360 , a charge storage structure 370 , a channel 380 , and a filling pattern 390 on a second substrate 290 , and a capping pattern 400 may be formed on each of the columnar structures.

[0054] The semiconductor pattern 360 may include single crystal silicon or single crystal germanium according to the material of the second substrate 290, and in some embodiments of the inventive concept, the semiconductor pattern 360 may be doped with impurities. In an exemplary embodiment of the inventive concept, the semiconductor pattern 360 may have a columnar shape, and the upper surface of the semiconductor pattern 360 may be located between the upper surface and the lower surface of one of the insulating patterns 315 at a second level (second height) from below along the first direction. The semiconductor pattern 360 may be a channel like the overlying channel 380, and thus may be referred to as a lower channel.

[0055] The channel 380 may extend in the first direction on the central upper surface of the semiconductor pattern 360 to have a cup shape. The charge storage structure 370 may extend in the first direction on the edge upper surface of the semiconductor pattern 360 to cover the outer sidewall of the channel 380, and may have a cup shape with its central lower surface open. The filling pattern 390 may have a columnar shape for filling the inner space defined by the channel 380 of the cup shape.

[0056] The charge storage structure 370 may include a first barrier pattern, a charge storage pattern, and a tunnel insulation pattern sequentially stacked in a horizontal direction from an outer sidewall of the channel 380 .

[0057] The channel 380 may include doped single crystal silicon or undoped single crystal silicon. The first blocking pattern of the charge storage structure 370 may include oxide (e.g., silicon oxide), the charge storage pattern of the charge storage structure 370 may include nitride (e.g., silicon nitride), and the tunnel insulation pattern of the charge storage structure 370 may include oxide (e.g., silicon oxide). The filling pattern 390 may include oxide (e.g., silicon oxide).

[0058] The capping pattern 400 may include doped or undoped single crystalline silicon or polycrystalline silicon. The capping pattern 400 may extend through an upper portion of an uppermost one of the fifth insulating interlayer 350 and the insulating pattern 315 .

[0059] The CSL 482 may extend in the first direction on the second substrate 290 and may contact the upper surface of the fourth impurity region 292 at the upper portion of the second substrate 290. The CSL 482 may extend in the second direction to separate the gate electrodes 462, 464, and 466 from each other in the third direction. However, both sidewalls of the CSL 482 may be covered by a third spacer 472 including an insulating material to be electrically insulated from the gate electrodes 462, 464, and 466.

[0060] The second contact plug 484 may extend in the first direction on the second region II of the first substrate 100 to be connected to the seventh lower wiring 222, and may extend through the fifth and sixth insulating interlayers 350 and 420, the insulating pattern 315, the gate electrodes 462, 464, and 466, the second substrate 290, the first buffer layer 270, the first bending prevention layer 240, and a portion of the second insulating interlayer 230. A second spacer 474 including an insulating material (e.g., silicon oxide) may be formed on a sidewall of the second contact plug 484, and the second contact plug 484 and the second spacer 474 may form a second contact plug structure.

[0061] In an exemplary embodiment of the inventive concept, the second contact plug structure may extend through and contact the first bending prevention layer 240. However, even if the first bending prevention layer 240 includes a conductive material, the second contact plug 484 whose sidewall may be covered by the second spacer 474 is not electrically shorted with the first bending prevention layer 240.

[0062] In the drawings, the second contact plug structure extends through the first concave portion 250 of the first bending prevention layer 240; however, the inventive concept may not be limited thereto. For example, the second contact plug structure may extend through another portion of the first bending prevention layer 240. In addition, the second contact plug structure may be formed not only on the second region II of the first substrate 100, but also on a portion of the first region I of the first substrate 100 adjacent to the second region II.

[0063] The third contact plug 492 may extend through the fourth insulating interlayer 340, the fifth insulating interlayer 350, the sixth insulating interlayer 420, the insulating pattern 315, and the second barrier layer 450 on the second region II of the first substrate 100 to contact one of the first gate electrode 462, the second gate electrode 464, and the third gate electrode 466. In addition, the fourth contact plug 494 may extend through the second insulating interlayer 230, the fourth insulating interlayer 340, the fifth insulating interlayer 350, the sixth insulating interlayer 420, the third insulating interlayer pattern 300, the first buffer layer 270, and the first bending preventing layer 240 on the third region III of the first substrate 100 to contact the eighth lower wiring 224.

[0064] The third contact plug 492 may contact a conductive pad of a corresponding one of the first gate electrode 462 , the second gate electrode 464 , and the third gate electrode 466 .

[0065] In an exemplary embodiment of the inventive concept, the fourth contact plug 494 may contact the first bending prevention layer 240. However, when the first bending prevention layer 240 includes a conductive material, the first contact plug 280 may extend through but not contact the first bending prevention layer 240. In this case, as will be described with reference to Fig.21 , Fig.22A and Fig. 22B As shown, additional insulating spacers may also be formed on sidewalls of the fourth contact plug 494 , or the fourth contact plug 494 may be spaced apart from sidewalls of the first bending preventing layer 240 .

[0066] In the drawings, the fourth contact plug 494 extends through the first concave portion 250 of the first bending prevention layer 240 ; however, the inventive concept may not be limited thereto. For example, the fourth contact plug 494 may extend through another portion of the first bending prevention layer 240 .

[0067] The upper circuit pattern may include, for example, an upper contact plug, an upper wiring, an upper via, and the like.

[0068] The first upper contact plug 512, the second upper contact plug 514, the third upper contact plug 516, and the fourth upper contact plug 517 may extend through the seventh insulating interlayer 500 on the sixth insulating interlayer 420, the CSL 482, and the second, third, and fourth contact plugs 484, 492, and 494 to respectively contact an upper surface of the third contact plug 492, an upper surface of the fourth contact plug 494, an upper surface of the CSL 482, and an upper surface of the second contact plug 484. In addition, the fifth upper contact plug 518 may extend through the sixth insulating interlayer 420 and the seventh insulating interlayer 500 to contact an upper surface of the capping pattern 400.

[0069] The first upper wiring 532, the second upper wiring 534, the third upper wiring 536, the fourth upper wiring 537 and the fifth upper wiring 538 can extend through the eighth insulating interlayer 520 on the seventh insulating interlayer 500, the first upper contact plug 512, the second upper contact plug 514, the third upper contact plug 516, the fourth upper contact plug 517 and the fifth upper contact plug 518 to contact the upper surface of the first upper contact plug 512, the upper surface of the second upper contact plug 514, the upper surface of the third upper contact plug 516, the upper surface of the fourth upper contact plug 517 and the upper surface of the fifth upper contact plug 518, respectively.

[0070] The first upper via 552, the second upper via 554, the third upper via 556, the fourth upper via 557 and the fifth upper via 558 can extend through the ninth insulating interlayer 540 on the eighth insulating interlayer 520, the first upper wiring 532, the second upper wiring 534, the third upper wiring 536, the fourth upper wiring 537 and the fifth upper wiring 538 to contact the upper surface of the first upper wiring 532, the upper surface of the second upper wiring 534, the upper surface of the third upper wiring 536, the upper surface of the fourth upper wiring 537 and the upper surface of the fifth upper wiring 538, respectively.

[0071] The sixth upper wiring 572, the seventh upper wiring 574, the eighth upper wiring 576, the ninth upper wiring 577 and the tenth upper wiring 578 can extend through the tenth insulating interlayer 560 on the ninth insulating interlayer 540, the first upper via 552, the second upper via 554, the third upper via 556, the fourth upper via 557 and the fifth upper via 558 to contact the upper surface of the first upper via 552, the upper surface of the second upper via 554, the upper surface of the third upper via 556, the upper surface of the fourth upper via 557 and the upper surface of the fifth upper via 558, respectively.

[0072] The sixth upper via 594, the seventh upper via 596 and the eighth upper via 597 can extend through the eleventh insulating interlayer 580 on the tenth insulating interlayer 560, the sixth upper wiring 572, the seventh upper wiring 574, the eighth upper wiring 576, the ninth upper wiring 577 and the tenth upper wiring 578 to contact the upper surface of the sixth upper wiring 572, the upper surface of the seventh upper wiring 574, the upper surface of the eighth upper wiring 576, the upper surface of the ninth upper wiring 577 and the upper surface of the tenth upper wiring 578, respectively.

[0073] The eleventh upper wiring 614, the twelfth upper wiring 616 and the thirteenth upper wiring 617 can extend through the twelfth insulating interlayer 600 on the eleventh insulating interlayer 580, the sixth upper via 594, the seventh upper via 596 and the eighth upper via 597 to contact the upper surface of the sixth upper via 594, the upper surface of the seventh upper via 596 and the upper surface of the eighth upper via 597, respectively.

[0074] In an exemplary embodiment of the inventive concept, the tenth upper wiring 578 may extend in the third direction, and a plurality of tenth upper wirings 578 may be spaced apart from each other in the second direction. The tenth upper wiring 578 may be a bit line of a vertical memory device.

[0075] The vertical memory device may include a first bending prevention layer 240 between a lower insulating interlayer structure covering a lower circuit pattern and a second substrate 290, and a pattern may be formed at an upper portion of the first bending prevention layer 240 to extend in a horizontal direction so that bending of the first substrate 100 (e.g., in a specific direction) may be reduced or prevented.

[0076] Figures 5 to 18 1 is a plan view and a cross-sectional view showing a method of manufacturing a memory device according to an exemplary embodiment of the inventive concept. Figure 5 , Fig.11 , Fig.13 and Fig.16 It is a floor plan. Figures 6 to 10 , Fig.12 , Fig.14 and Fig.15 as well as Fig.17 and Fig.18 It is a cross-sectional view.

[0077] Figures 6 to 10 , Fig.12 , Fig.15 and Fig.17 are sectional views taken along the line AA' of the corresponding plan view, Fig.14 and Fig.18 They are respectively cross-sectional views taken along line BB' of the corresponding plan view.

[0078] Reference Figure 5 and Figure 6 , a lower circuit pattern may be formed on the first substrate 100 , and a first insulating interlayer 160 and a second insulating interlayer 230 may be sequentially formed on the first substrate 100 to cover the lower circuit pattern.

[0079] The isolation pattern 110 may be formed on the first substrate 100 by, for example, a shallow trench isolation (STI) process. The first impurity region 102, the second impurity region 104, and the third impurity region 106 may be formed by, for example, an ion implantation process. The first lower gate structure 152, the second lower gate structure 154, the first lower contact plug 172, the second lower contact plug 174, the third lower contact plug 176, the first lower via 192, the second lower via 194, the third lower via 196, the fourth lower via 212, the fifth lower via 214, the sixth lower via 216, the first lower wiring 182, the second lower wiring 184, the third lower wiring 186, the fourth lower wiring 202, the fifth lower wiring 204, the sixth lower wiring 206, the seventh lower wiring 222, the eighth lower wiring 224, and the ninth lower wiring 226, which may form a lower circuit pattern, may be formed by a patterning process or a damascene process.

[0080] A first insulating interlayer 160 may be formed on the first substrate 100 to cover the first, second, and third impurity regions 102, 104, and 106, as well as the first and second lower gate structures 152 and 154, and to surround sidewalls of the first, second, and third lower contact plugs 172, 174, and 176. A second insulating interlayer 230 may be formed on the first insulating interlayer 160 to cover the first, second, and third lower wirings 182, 184, 186, the fourth, fifth, and sixth lower wirings 202, 204, 206, the seventh, eighth, and ninth lower wirings 226, and the first, second, third, and sixth lower vias 192, 194, 196, the fourth, fifth, and sixth lower vias 212, 214, and 216.

[0081] Reference Figure 7 , a first bending prevention layer 240 and a first buffer layer 270 may be formed on the second insulating interlayer 230 .

[0082] In an exemplary embodiment of the inventive concept, the first bending prevention layer 240 may include a pattern extending in the third direction at an upper portion thereof. In an exemplary embodiment of the inventive concept, the pattern may be a first recess 250 on an upper surface of the first bending prevention layer 240. The first recess 250 may have a strip shape extending in the third direction, and a plurality of first recesses 250 may be formed to be spaced apart from each other in the second direction. The first recess 250 may be formed by forming the first bending prevention layer 240 and partially etching the upper portion of the first bending prevention layer 240 using a first etching mask. Alternatively, a protrusion may be formed on the first bending prevention layer 240 by a deposition process to form a pattern.

[0083] When the first bending preventing layer 240 includes a conductive material, the first bending preventing layer 240 may be formed so as not to directly contact other conductive structures through which the first bending preventing layer 240 extends. If the first bending preventing layer 240 contacts other conductive structures, an insulating structure may also be formed to cover the sidewalls of the conductive material of the first bending preventing layer 240.

[0084] The first buffer layer 270 may be formed on the first bending prevention layer 240 to cover the pattern, and the first buffer layer 270 may have a flat upper surface. Therefore, when the first concave portion 250 is formed on the first bending prevention layer 240, the first buffer layer 270 may be formed on the first bending prevention layer 240 to fill the first concave portion 250.

[0085] Reference Figure 8, a first contact plug 280 may be formed through the first buffer layer 270, the first bending prevention layer 240, and the second insulating interlayer 230 on the first region I of the first substrate 100 to contact the upper surface of the ninth lower wiring 226. In an exemplary embodiment of the inventive concept, the first contact plug 280 may contact the first bending prevention layer 240. However, when the first bending prevention layer 240 includes a conductive material, the first contact plug 280 may extend through but not contact the first bending prevention layer 240. In this case, an additional insulating spacer may be formed to cover the sidewall of the first contact plug 280, or the first contact plug 280 may be formed to be separated from the sidewall of the first bending prevention layer 240, which will be shown later. In other words, there may be a gap in the recess 250 to allow the first contact plug 280 to pass through the first bending prevention layer 240 without contacting the first bending prevention layer 240.

[0086] In the drawings, the first contact plug 280 extends through the first recess 250 of the first bending prevention layer 240 ; however, the inventive concept may not be limited thereto.

[0087] Reference Figure 8 , a second substrate 290 may be formed on the first buffer layer 270 and the first contact plug 280 , and a third insulating interlayer pattern 300 may be formed on the second insulating interlayer 230 to cover a sidewall of the second substrate 290 .

[0088] The second substrate 290 may be formed on the second insulating interlayer 230 , and then the second substrate 290 may be patterned to remain only on the first region I and the second region II of the first substrate 100 .

[0089] A third insulating interlayer pattern 300 may be formed on the second insulating interlayer 230 to cover the second substrate 290 , and the third insulating interlayer pattern 300 may be planarized until an upper surface of the second substrate 290 may be exposed.

[0090] The insulating layers 310 and the sacrificial layers 320 may be alternately and repeatedly stacked on the second substrate 290 and the third insulating interlayer pattern 300. Thus, a plurality of insulating layers 310 and a plurality of sacrificial layers 320 may be alternately stacked in the first direction.

[0091] The insulating layer 310 may include an oxide (eg, silicon oxide), and the sacrificial layer 320 may include a material having an etching selectivity with respect to the insulating layer 310 (eg, a nitride such as silicon nitride).

[0092] Reference Fig. 9, an etch stop layer 330 may be formed on the uppermost one of the insulating layers 310, a photoresist pattern partially covering the etch stop layer 330 may be formed on the etch stop layer 330, and the etch stop layer 330, the uppermost one of the insulating layers 310, and the uppermost one of the sacrificial layers 320 below the insulating layers 310 may be etched using the photoresist pattern as an etching mask. Thus, a portion of one of the insulating layers 310 directly below the uppermost sacrificial layer 320 may be exposed.

[0093] After performing a trimming process for reducing the area of ​​the photoresist pattern at a given ratio, an etching process may be performed so that the etching stop layer 330, the uppermost one of the insulating layers 310, the uppermost one of the sacrificial layers 320, the exposed one of the insulating layers 310, and one of the sacrificial layers 320 thereunder may be etched using the reduced photoresist pattern as an etching mask. As the trimming process and the etching process are repeatedly performed, a mold including a plurality of stepped layers including the sacrificial layers 320 and the insulating layers 310 sequentially stacked and having a stepped shape may be formed.

[0094] Hereinafter, each of the "step layers" may include not only an exposed portion but also a portion thereof covered by a step layer of an upper level (height), and thus, each of the "step layers" may refer to the entire portion of the sacrificial layer 320 and the entire portion of the insulating layer 310 at the same level. The exposed portion of the step layer that is not covered by the upper step layer may be referred to as a "step". In an exemplary embodiment of the inventive concept, the steps may be arranged along the second direction and may also be arranged along the third direction.

[0095] The mold may be formed on the second substrate 290 on the first region I and the second region II of the first substrate 100. In this case, a step in the mold may be formed in the second region II of the first substrate 100.

[0096] Reference Fig.10 , a thickness of an end portion of at least one of the sacrificial layers 320 in the second direction may be increased to form an insulating pad.

[0097] In an exemplary embodiment of the inventive concept, an insulating pad may be formed by removing an end portion of the insulating layer 310 included in each step in the second direction to expose an end portion of the sacrificial layer 320 in the second direction in each step, forming a pad layer on the etch stop layer 330, the mold, the second substrate 290, and the third insulating interlayer pattern 300, and removing a portion of the pad layer on the sidewall of the mold. A portion of the pad layer on the upper surface of the etch stop layer 330, the upper surface of the lowest one of the insulating layers 310, the upper surface of the second substrate 290, and the upper surface of the third insulating interlayer pattern 300 may also be removed.

[0098] The pad layer may include substantially the same material as the sacrificial layer 320 and thus may be merged with the sacrificial layer 320 to form an insulating pad. The thickness of the end portion of each sacrificial layer 320 in the second direction where the insulating pad is formed may be greater than the thickness of the other portion of each sacrificial layer 320.

[0099] A fourth insulating interlayer 340 may be formed on the third insulating interlayer pattern 300 to cover the mold and the etch stop layer 330, and the fourth insulating interlayer 340 may be planarized until an upper surface of the uppermost one of the insulating layers 310 may be exposed. Thus, the etch stop layer 330 may be removed, and a sidewall of the mold may be covered by the fourth insulating interlayer 340.

[0100] A fifth insulating interlayer 350 may be formed on an upper surface of the mold and an upper surface of the fourth insulating interlayer 340 .

[0101] Reference Fig.11 and Fig.12 After forming a second etching mask on the fifth insulating interlayer 350, the second mask can be used as an etching mask to etch the fifth insulating interlayer 350, the insulating layer 310 and the sacrificial layer 320 thereunder to form a channel hole passing through them, thereby exposing the upper surface of the second substrate 290.

[0102] After removing the second etching mask, a semiconductor pattern 360 partially filling the channel hole may be formed. A plurality of channel holes may be formed at this time. The semiconductor pattern 360 may be formed by a selective epitaxial growth (SEG) process using the upper surface of the second substrate 290 exposed by the channel hole as a seed to fill the lower portion of the channel hole.

[0103] A charge storage structure layer and a first spacer layer may be sequentially formed on the sidewalls of the channel hole, the upper surface of the semiconductor pattern 360, and the upper surface of the fifth insulating interlayer 350, the first spacer layer may be anisotropically etched to form a first spacer only on the sidewalls of the channel hole, and the charge storage structure layer may be etched using the first spacer as an etching mask to form a charge storage structure 370 on each sidewall of the channel hole, the charge storage structure 370 having a cup-like shape with its central lower surface open on the semiconductor pattern. During the etching process, the upper portion of the semiconductor pattern 360 may also be partially removed.

[0104] After removing the first spacer, a channel layer may be formed on the exposed semiconductor pattern 360, the charge storage structure 370, and the fifth insulating interlayer 350, and a filling layer may be formed on the channel layer to fill the remaining portion of the channel hole. The filling layer and the channel layer may be planarized until the upper surface of the fifth insulating interlayer 350 may be exposed to form a filling pattern 390 for filling the remaining portion of each channel hole, and the channel layer may be transformed into a channel 380.

[0105] An upper portion of the pillar structure including the sequentially stacked semiconductor pattern 360 , the charge storage structure 370 , the channel 380 , and the filling pattern 390 may be removed to form a trench, and a capping pattern 400 may be formed to fill the trench.

[0106] A third etching mask may be formed on the fifth insulating interlayer 350 , a first opening may be formed through the fifth insulating interlayer 350 and some of the insulating layer 310 and the sacrificial layer 320 , and a dividing pattern 410 may be formed to fill the first opening.

[0107] In an exemplary embodiment of the inventive concept, the dividing pattern 410 may extend through the upper portion of some of the channels 380. In addition, the dividing pattern 410 may extend through the fifth insulating interlayer 350, the separate sacrificial layers at the upper two levels (i.e., the higher two heights) of the sacrificial layers 320, and the separate insulating layers at the upper two levels of the insulating layers 310, and may partially extend through one of the insulating layers 310 at the third level from above. The dividing pattern 410 may extend in the second direction on the first region I and the second region II of the first substrate 100, and may extend through the two upper step layers in the mold. Therefore, the respective sacrificial layers 320 at the two upper levels may be divided by the dividing pattern 410 in the third direction.

[0108] Reference Figures 13 to 15A sixth insulating interlayer 420 can be formed on the fifth insulating interlayer 350 and the covering pattern 400, a second opening 430 extending through the fifth insulating interlayer 350, the sixth insulating interlayer 420, the insulating layer 310, the sacrificial layer 320, the second substrate 290, the first buffer layer 270, the first bending prevention layer 240, and a portion of the second insulating interlayer 230 can be formed to expose the upper surface of the seventh lower wiring 222, and a second contact plug structure can be formed to fill the second opening 430.

[0109] A second contact plug structure may be formed by forming a second spacer layer on the sidewalls of the second opening 430, the upper surface of the seventh lower wiring 222 exposed by the second opening 430, and the upper surface of the sixth insulating interlayer 420, anisotropically etching the second spacer layer to form a second spacer 474 on the sidewalls of the second opening 430, forming a second contact plug layer on the second spacer 474, the seventh lower wiring 222, and the sixth insulating interlayer 420 to fill the remaining portion of the second opening 430, and planarizing the second contact plug layer until the upper surface of the sixth insulating interlayer 420 may be exposed. Therefore, the second contact plug structure may include a second contact plug 484 and a second spacer 474 covering the sidewalls of the second contact plug 484, and the second contact plug 484 may contact the seventh lower wiring 222.

[0110] In an exemplary embodiment of the inventive concept, the second contact plug structure may extend through and contact the first bending prevention layer 240. However, the sidewall of the second contact plug 484 included in the second contact plug structure may be covered by the second spacer 474 including an insulating material. In this case, even if the first bending prevention layer 240 includes a conductive material, an electrical short circuit is not generated between the second contact plug 484 and the first bending prevention layer 240.

[0111] In the drawings, the second contact plug structure extends through the first concave portion 250 of the first bending prevention layer 240; however, the inventive concept may not be limited thereto. The second contact plug structure may be formed not only on the second region II of the first substrate 100 but also on the first region I of the first substrate 100.

[0112] A fourth etching mask may be formed on the sixth insulating interlayer 420 and the second contact plug structure, and a third opening 440 may be formed through the fifth insulating interlayer 350 , the sixth insulating interlayer 420 , the insulating layer 310 , and the sacrificial layer 320 to expose an upper surface of the second substrate 290 .

[0113] The third openings 440 may extend in the second direction on the first region I and the second region II of the first substrate 100, and a plurality of third openings 440 may be spaced apart from each other in the third direction. The third openings 440 may extend through the mold in the second direction, the insulating layer 310 may be divided into a plurality of insulating patterns 315, and the sacrificial layer 320 may be divided into a plurality of sacrificial patterns.

[0114] After removing the fourth etching mask, the sacrificial pattern exposed by the third opening 440 may be removed to form gaps between the insulating patterns 315 at various levels. In this case, the outer sidewalls of the charge storage structure 370 and the sidewalls of the semiconductor pattern 360 may be partially exposed. In an exemplary embodiment of the inventive concept, the sacrificial pattern exposed by the third opening 440 may be removed by a wet etching process using an etchant including phosphoric acid or sulfuric acid.

[0115] A second barrier layer 450 may be formed on the sidewalls of the third opening 440, the exposed outer sidewalls of the charge storage structure 370, the exposed sidewalls of the semiconductor pattern 360, the inner wall of the gap, the upper surface of the second substrate 290, and the upper surface of the sixth insulating interlayer 420, and a conductive layer may be formed on the second barrier layer 450 to fill the remaining portion of the gap. A barrier layer may also be formed between the second barrier layer 450 and the conductive layer formed on the second barrier layer 450.

[0116] Portions of the conductive layer in the third opening 440 and portions of the third gap adjacent thereto may be removed to form a conductive pattern in the gap. As described above, when the barrier layer is further formed, a barrier pattern covering the lower surface, upper surface and sidewalls of the conductive pattern may also be formed.

[0117] In an exemplary embodiment of the inventive concept, the conductive pattern may extend in the second direction on the first region I and the second region II of the first substrate 100 , and a plurality of first conductive patterns may be formed in the third direction.

[0118] In an exemplary embodiment of the inventive concept, the conductive pattern may include a first gate electrode 462 , a second gate electrode 464 , and a third gate electrode 466 sequentially stacked in the first direction.

[0119] Reference Figures 16 to 18 A fourth impurity region 292 may be formed at an upper portion of the second substrate 290 exposed by the third opening 440 , a third spacer 472 may be formed on a sidewall of the third opening 440 , and a common source line (CSL) 482 may be formed to fill a remaining portion of the third opening 440 .

[0120] The third spacer 472 may be formed by forming a third spacer layer on the exposed upper surface of the second substrate 290, the sidewalls of the third openings 440, and the upper surface of the sixth insulating interlayer 420 and anisotropically etching the third spacer layer formed on the sidewalls of the third openings 440. The CSL 482 may be formed by forming a CSL layer on the upper surface of the second substrate 290 exposed by the third openings 440, the third spacer 472, and the sixth insulating interlayer 420 and planarizing the CSL layer until the upper surface of the sixth insulating interlayer 420 may be exposed.

[0121] In an exemplary embodiment of the inventive concept, the CSL 482 may extend in the second direction to divide each of the first gate electrode 462 , the second gate electrode 464 , and the third gate electrode 466 at the same level in the third direction.

[0122] A third contact plug 492 extending through the fourth insulating interlayer 340, the fifth insulating interlayer 350, the sixth insulating interlayer 420, the insulating pattern 315 and the second barrier layer 450 to contact the first gate electrode 462, the second gate electrode 464 and one of the third gate electrodes 466 can be formed on the second region II of the first substrate 100, and a fourth contact plug 494 extending through a portion of the second insulating interlayer 230, the fourth insulating interlayer 340, the fifth insulating interlayer 350, the sixth insulating interlayer 420, the third insulating interlayer pattern 300, the first buffer layer 270 and the first bending prevention layer 240 to contact the eighth lower wiring 224 can be formed on the third region III of the first substrate 100.

[0123] The third contact plug 492 may contact an end portion of each of the first gate electrode 462 , the second gate electrode 464 , and the third gate electrode 466 in the second direction. In other words, the third contact plug 492 may contact a conductive pad of each of the first gate electrode 462 , the second gate electrode 464 , and the third gate electrode 466 .

[0124] In an exemplary embodiment of the inventive concept, the fourth contact plug 494 may extend through and contact the first bending prevention layer 240. However, when the first bending prevention layer 240 includes a conductive material, the fourth contact plug 494 may extend through but not contact the first bending prevention layer 240. In this case, an additional insulating spacer may be formed to cover a sidewall of the fourth contact plug 494, or the fourth contact plug 494 may be spaced apart from the sidewall of the first bending prevention layer 240.

[0125] In the drawings, the fourth contact plug 494 extends through the first recess 250 of the first bending prevention layer 240 ; however, the inventive concept may not be limited thereto.

[0126] Refer again Figure 2 and Figure 3 A seventh insulating interlayer 500, an eighth insulating interlayer 520, a ninth insulating interlayer 540, a tenth insulating interlayer 560, an eleventh insulating interlayer 580 and a twelfth insulating interlayer 600 may be sequentially formed on the sixth insulating interlayer 420, the CSL 482, the second contact plug structure, the third contact plug 492 and the fourth contact plug 494, and a first upper contact plug 512, a second upper contact plug 514, a third upper contact plug 516, a fourth upper contact plug 517, a fifth upper contact plug 518, a first upper wiring 532, a second upper wiring 534, a third upper wiring 535, a Wiring 536, fourth upper wiring 537, fifth upper wiring 538, sixth upper wiring 572, seventh upper wiring 574, eighth upper wiring 576, ninth upper wiring 577 and tenth upper wiring 578, eleventh upper wiring 614, twelfth upper wiring 616 and thirteenth upper wiring 617 and first upper via 552, second upper via 554, third upper via 556, fourth upper via 557, fifth upper via 558, sixth upper via 594, seventh upper via 596 and eighth upper via 597, thereby completing the manufacture of the vertical memory device.

[0127] As described above, the first bending preventing layer 240 may be formed between the second insulating interlayer 230 and the second substrate 290 on the first region I, the second region II, and the third region III of the first substrate 100, so that bending of the first bending preventing layer 240 may be reduced or prevented. The first bending preventing layer 240 may include a pattern at its upper portion, which may extend in a specific direction (e.g., a third direction). Therefore, the first bending preventing layer 240 may apply compressive stress or tensile stress to the first substrate 100 in the direction, so that upward bending or downward bending of the first substrate 100 may be reduced or prevented.

[0128] Fig.19 is a plan view illustrating a layout of a first concave portion 250 at an upper portion of a first bending prevention layer 240 according to an exemplary embodiment of the inventive concept.

[0129] Reference Fig.19 In the upper left corner of the first bending preventing layer 240, in an exemplary embodiment of the inventive concept, a first recess group RG1 including a plurality of first recesses 250 spaced apart from each other in the second direction and extending in the third direction and a second recess group RG2 spaced apart from the first recess group RG1 in the third direction and including a plurality of first recesses 250 spaced apart from each other in the second direction and extending in the third direction may be formed at an upper portion of the first bending preventing layer 240. Each first recess 250 is a pattern at an upper portion of the first bending preventing layer 240, and therefore, the first recess group and the second recess group may be referred to as a first pattern group and a second pattern group, respectively.

[0130] exist Fig.19 In another exemplary embodiment of the inventive concept shown in the upper right corner of , a plurality of first concave portions 250 each extending in the second direction and spaced apart from each other in the third direction may be formed at an upper portion of the first bending prevention layer 240 .

[0131] exist Fig.19 In another exemplary embodiment of the inventive concept shown in the lower left corner of , a third recess group RG3 including a plurality of first recesses 250 spaced apart from each other in the third direction and extending in the second direction and a fourth recess group RG4 spaced apart from the third recess group RG3 in the second direction and including a plurality of first recesses 250 spaced apart from each other in the third direction and extending in the second direction may be formed at an upper portion of the first bending prevention layer 240. The third recess group and the fourth recess group may be referred to as a third pattern group and a fourth pattern group, respectively.

[0132] exist Fig.19 In another exemplary embodiment of the inventive concept shown in the lower right corner of , a plurality of first recesses 250 separated from each other along a fifth direction intersecting the fourth direction and extending along the fourth direction can be formed at the upper portion of the first bending prevention layer 240, wherein the fourth direction forms an acute angle with the second direction which is the extension direction of each gate electrode 462, 464 and 466 or a third direction substantially perpendicular to the second direction.

[0133] On the first bending prevention layer 240 in the vertical memory device, the first recess 250 may have Fig.19 However, the first bending preventing layer 240 may have various types of layouts so that stress may be applied to the first substrate 100 to reduce or prevent bending of the first substrate 100 .

[0134] Figure 20 to Figure 26 is a cross-sectional view showing a vertical memory device according to an exemplary embodiment of the inventive concept. In addition to the bending prevention layer, the vertical memory device may be Figures 1 to 4 Therefore, the same reference numerals may denote the same elements, and a detailed description thereof may be omitted.

[0135] Reference Fig. 20 , the first bending preventing layer 240 may not have a pattern, in which case the entire first bending preventing layer 240 may apply compressive stress or tensile stress to the first substrate 100 to reduce or prevent bending of the first substrate 100. Fig. 20 In the embodiment, the first bending prevention layer 240 may be formed with a flat upper surface.

[0136] Reference Fig.21 and Fig.22A, each of the first contact plug 280, the second contact plug 484, and the fourth contact plug 494 may pass through the fourth opening 245 extending through the first bending prevention layer 240. The fourth opening 245 may have a diameter greater than that of the first contact plug 280, the second contact plug 484, and the fourth contact plug 494, and thus, each of the first contact plug 280, the second contact plug 484, and the fourth contact plug 494 may extend through but not contact the first bending prevention layer 240. Although Fig.21 FIG. 2 shows that the fourth opening 245 is formed in the first bending prevention layer 240 having the concave portion 250, but the fourth opening 245 may be formed in Fig. 20 In the first bending prevention layer 240 .

[0137] Reference Fig.21 and Fig. 22B , the first bending preventing layer 240 may be divided into a plurality of pieces by the fifth opening 247 extending therethrough in the third direction, and each of the first contact plug 280, the second contact plug 484, and the fourth contact plug 494 may pass through the fifth opening 247. Therefore, each of the first contact plug 280, the second contact plug 484, and the fourth contact plug 494 may be spaced apart from the first bending preventing layer 240 so as not to contact the first bending preventing layer 240.

[0138] Reference Fig.23 , a second bending prevention layer 260 including an adhesive pattern 262 and a metal pattern 264 stacked sequentially may be formed instead of the first bending prevention layer 240 as a single layer. The adhesive pattern 262 may include, for example, a metal nitride, and the metal pattern 264 may include, for example, a metal. The second bending prevention layer 260 includes a conductive material, and thus may have a reference Fig.21 , Fig.22A and Fig. 22B The second bending prevention layer 260 may also be formed to have a flat upper surface.

[0139] Reference Fig.24 A plurality of first bending prevention layers 240 may be formed in a first direction between the lower insulating interlayer structure and the second substrate 290. The first bending prevention layers 240 may have patterns extending in the same direction or in different directions. A first buffer layer 270 may be formed between the first bending prevention layers 240.

[0140] Reference Fig.25, in addition to the first bending preventing layer 240, a third bending preventing layer 630 may be formed on the upper circuit pattern. A second concave portion 640 may be formed on the third bending preventing layer 630, and a second buffer layer 650 may be formed on the third bending preventing layer 630 to cover the second concave portion 640. In some exemplary embodiments of the inventive concept, the first bending preventing layer 240 may not be formed, but only the third bending preventing layer 630 may be formed. In other exemplary embodiments of the inventive concept, the third bending preventing layer 630 may not include the second concave portion.

[0141] Reference Fig.26 , in addition to the first bending preventing layer 240, a fourth bending preventing layer 660 may be formed on the first substrate 100. The third concave portion 670 may be formed on the fourth bending preventing layer 660, and the first insulating interlayer 160 may cover the third concave portion 670. In some exemplary embodiments of the inventive concept, the first bending preventing layer 240 may not be formed, but only the fourth bending preventing layer 660 may be formed.

[0142] The fourth bending preventing layer 660 may have a reference Fig.21 , Fig.22A and Fig. 22B One of the structures shown, so that the first transistor and the second transistor and the third impurity region 106 can extend through but not contact the fourth bending prevention layer 660.

[0143] Fig. 27 is a cross-sectional view showing a vertical memory device according to an exemplary embodiment of the inventive concept. The vertical memory device may be similar to Figures 1 to 4 Therefore, the same reference numerals may denote the same elements, and a detailed description thereof may be omitted.

[0144] Reference Fig. 27 , a channel connection pattern 700 and a support layer 710 may be sequentially formed on the second substrate 290 , and the insulating pattern 315 and the gate electrodes 462 , 464 , and 466 may be alternately and repeatedly stacked on the support layer 710 .

[0145] The channel connection pattern 700 may connect the channels 380 in the same memory cell block, and may include, for example, doped polysilicon. Therefore, the charge storage structure 370 may be divided at the lower portion of each channel 380 to expose the outer sidewall of each channel 380, and the exposed outer sidewall of the channel 380 may contact the channel connection pattern 700. The upper portion of the charge storage structure 370 may cover the outer sidewall of the upper portion of each channel 380, and the lower portion of the charge storage structure 370 may be formed on the second substrate 290 to cover the bottom surface and the outer sidewall of the lower portion of each channel 380.

[0146] The support layer 710 may include undoped polysilicon or doped polysilicon.

[0147] A vertical memory device according to an exemplary embodiment of the inventive concept may include a bending prevention layer between an upper substrate and a lower insulating interlayer structure covering a lower circuit pattern, or on the upper circuit pattern or on the lower substrate. Therefore, the bending of the lower substrate can be reduced or prevented by a pattern extending along an upper portion of the bending prevention layer. Therefore, an exemplary embodiment of the inventive concept provides a vertical memory device having uniform electrical characteristics.

[0148] While the inventive concept has been shown and described with reference to exemplary embodiments thereof, those skilled in the art will readily appreciate that various modifications may be made thereto without departing from the scope of the inventive concept.

Claims

1. A vertical memory device, the vertical memory device comprising: A circuit pattern is located on the first substrate; An insulating intermediate layer is located on the first substrate, and the insulating intermediate layer covers the circuit pattern; a bending prevention layer, located on the insulating interlayer, the bending prevention layer extending in a first direction substantially parallel to an upper surface of the first substrate; a second substrate disposed on the bending prevention layer; gate electrodes, spaced apart from each other along a second direction on the second substrate, the second direction being substantially perpendicular to the upper surface of the first substrate; as well as a channel extending in a second direction through the gate electrode, The bending prevention layer includes a plurality of recesses, each of which extends in a direction substantially parallel to an upper surface of the first substrate, and a side wall of one of the plurality of recesses is separated from a first contact plug extending through the one recess, so that the buffer layer is disposed in the one recess having the first contact plug.

2. The vertical memory device according to claim 1, wherein: The bending prevention layer includes a plurality of patterns spaced apart from each other in a third direction substantially parallel to an upper surface of the first substrate and substantially perpendicular to the first direction.

3. The vertical memory device according to claim 2, wherein: The plurality of patterns include: a first group including first patterns spaced apart from each other in a third direction; and The second group includes second patterns spaced apart from each other in the third direction, and the second group is spaced apart from the first group in the first direction.

4. The vertical memory device according to claim 1, wherein: Each gate electrode extends in a first direction.

5. The vertical memory device according to claim 1, wherein: Each gate electrode extends in the third direction.

6. The vertical memory device according to claim 1, wherein: Each of the plurality of recesses makes an acute angle with the first direction.

7. The vertical memory device according to claim 1, wherein: The bending prevention layer includes a pattern, wherein the pattern is a concave portion having a stripe shape extending in a first direction on an upper surface of the bending prevention layer. 8 . The vertical memory device of claim 7 , further comprising a buffer layer on the bending prevention layer, the buffer layer filling the recess and having a flat upper surface.

9. The vertical memory device according to claim 1, wherein: The bending prevention layer is a first bending prevention layer, Wherein, the vertical memory device further comprises: a wiring located on the gate electrode, the wiring being electrically connected to the gate electrode; and The second bending prevention layer is located on the wiring.

10. The vertical memory device of claim 1, wherein: The bending prevention layer is a first bending prevention layer, The vertical memory device further includes a second bending prevention layer located between the first substrate and the insulating intermediate layer.

11. The vertical memory device according to claim 1 , further comprising a contact plug structure extending through the gate electrode and the second substrate in the second direction to be electrically connected to the circuit pattern, in, The contact plug structure includes a first contact plug and an insulating spacer covering a sidewall of the first contact plug.

12. The vertical memory device according to claim 11, wherein: The contact plug structure extends through the bending prevention layer and contacts the bending prevention layer.

13. The vertical memory device according to claim 11, wherein: The contact plug structure extends through the bending prevention layer, is spaced apart from the bending prevention layer, and does not contact the bending prevention layer.

14. The vertical memory device according to claim 11, wherein: the bending preventing layer is a first bending preventing layer, the vertical memory device further comprising a second bending preventing layer spaced apart from the first bending preventing layer and extending in a horizontal direction substantially parallel to an upper surface of the first substrate, The contact plug structure extends between the first bending prevention layer and the second bending prevention layer and does not contact the first bending prevention layer and the second bending prevention layer.

15. The vertical memory device of claim 1, wherein: The bending prevention layer includes silicon nitride.

16. The vertical memory device of claim 1, wherein: The bending prevention layer includes a first layer and a second layer sequentially stacked, The first layer includes metal nitride, and the second layer includes metal.

17. The vertical memory device of claim 1, wherein: The insulating interlayer is a first insulating interlayer, Wherein, the vertical memory device further comprises: an insulating interlayer pattern located on the bending prevention layer at the same level as the second substrate, the insulating interlayer pattern covering a sidewall of the second substrate; a second insulating interlayer, located on the second substrate and the insulating interlayer pattern, the second insulating interlayer covering the sidewall of the gate electrode; and A first contact plug extends in the second direction through the second insulating interlayer and the insulating interlayer pattern, the first contact plug being electrically connected to the circuit pattern.

18. The vertical memory device of claim 17, wherein: The first contact plug extends through and contacts the bending prevention layer.

19. The vertical memory device of claim 17, wherein: The first contact plug extends through the bending preventing layer, is spaced apart from the bending preventing layer, and does not contact the bending preventing layer.

20. The vertical memory device of claim 17, wherein: The first contact plug is spaced apart from a sidewall of the bending preventing layer and does not contact the bending preventing layer. 21 . The vertical memory device of claim 1 , further comprising a first contact plug extending from a bottom surface of the second substrate in the second direction to be electrically connected to the circuit pattern.

22. The vertical memory device of claim 21, wherein: The first contact plug extends through and contacts the bending prevention layer.

23. A vertical memory device, the vertical memory device comprising: A circuit pattern is located on a first substrate, wherein the first substrate includes a unit area and a peripheral circuit area adjacent to the unit area; A first insulating intermediate layer is located on the first substrate, and the first insulating intermediate layer covers the circuit pattern; a first bending preventing layer located on the first insulating interlayer on the cell region and the peripheral circuit region, the first bending preventing layer having at least one concave portion on an upper surface of the first bending preventing layer; a second substrate located on the first bending prevention layer at the cell area; Gate electrodes are spaced apart from each other on the second substrate along a first direction on the cell region, the first direction being substantially perpendicular to an upper surface of the first substrate; A channel extending along a first direction through the gate electrode on the cell region; as well as a first contact plug extending through the first bending prevention layer in a first direction on the peripheral circuit region, the first contact plug being electrically connected to the circuit pattern, The first bending prevention layer includes a plurality of patterns spaced apart from each other in a direction substantially parallel to an upper surface of the first substrate and substantially perpendicular to the first direction.

24. A vertical memory device, the vertical memory device comprising: A transistor is located on the first substrate; A lower wiring is located on the first substrate, and the lower wiring is electrically connected to the transistor; A first insulating interlayer is located on the first substrate, and the first insulating interlayer covers the transistor and the lower wiring; a bending prevention layer, located on the first insulating interlayer, the bending prevention layer extending in a first direction substantially parallel to an upper surface of the first substrate; a second substrate disposed on the bending prevention layer; gate electrodes, spaced apart from each other along a second direction on the second substrate, the second direction being substantially perpendicular to the upper surface of the first substrate; A second insulating interlayer is located on the second substrate, and the second insulating interlayer covers the sidewall of the gate electrode; a channel extending in a second direction through the gate electrode; an upper wiring, located on the gate electrode, the upper wiring being electrically connected to the gate electrode; a first contact plug structure extending through the gate electrode, the second substrate, and the bending prevention layer, the first contact plug structure being electrically connected to a first lower wiring among the lower wirings; as well as a second contact plug extending through the second insulating interlayer and the bending prevention layer, the second contact plug being electrically connected to a second lower wiring among the lower wirings, The bending prevention layer includes a plurality of recesses, each of which extends in a direction substantially parallel to an upper surface of the first substrate, a side wall of a first recess among the plurality of recesses is separated from a first contact plug structure extending through the first recess, and a side wall of a second recess among the plurality of recesses is separated from a second contact plug extending through the second recess, so that a buffer layer is disposed in the first recess having the first contact plug structure and in the second recess having the second contact plug.

25. The vertical memory device of claim 24, wherein: The bending prevention layer includes a plurality of patterns spaced apart from each other in a third direction substantially parallel to an upper surface of the first substrate and crossing the first direction.

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