Semiconductor device, system and control method

Abstract

Embodiments of the present disclosure relate to a semiconductor device, a system and a control method. To provide a semiconductor device having a digitally controlled DC-DC converter, which is capable of stabilizing feedback operation while suppressing an increased area, the semiconductor device 10 includes a DC-DC converter 14, a flash memory 17 and a processor 18 that controls the flash memory 17, a characteristic of the DC-DC converter 14 being determined by a control parameter 21, wherein both the flash memory 17 and the processor 18 are operated with a power supply based on an output of the DC-DC converter 14. The control parameter 21 is stored in the flash memory 17, and when the DC-DC converter 14 is operated, the control parameter 21 is read from the flash memory 17 by the processor 18, and is set in the DC-DC converter 14.

Description

[0001] Cross-reference to related applications

[0002] The publication of Japanese patent application No. 2019-115547, filed on June 21, 2019, including its description, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] This invention relates to semiconductor devices, systems, and control methods, such as semiconductor devices and systems having a non-volatile memory device and a DC voltage converter (hereinafter referred to as a DC-DC converter, or simply a converter), and control methods for the same semiconductor devices. Background Technology

[0004] As DC-DC converters, there are analog control systems and digital control systems. For example, DC-DC converters using typical analog and digital control methods include configurations as shown in Figure 11. Figure 11A The configuration of an analog controlled DC-DC converter is shown. Figure 11B The configuration of a digitally controlled DC-DC converter is shown.

[0005] In an analog controlled DC-DC converter, transistors MP1 and MN1 are switched by gate drivers to generate an output voltage Vout by switching the current flowing through inductor (coil) Lout and capacitor Cout. The generated output voltage Vout is compensated (e.g., by phase compensation using a compensation circuit including resistors and capacitors), and the generated output voltage Vout is compared with a reference voltage by comparator CMP1. The difference or error between the output voltage Vout and the reference voltage is provided from comparator CMP1 to the pulse width modulation (PWM) generation circuitry.

[0006] In the PWM generation circuit, comparator CMP2 compares the periodic sawtooth wave with the error, and a pulse-width PWM signal corresponding to the error is generated and provided to the gate driver. Since the pulse width of the PWM signal varies according to the magnitude of the error, the duty cycle, i.e., the ratio of a high-level period (or a low-level period) to a given period, changes according to the error. Therefore, for example, in a DC-DC converter, the period during which transistor MP1 is turned on will change according to the error, and a feedback operation is performed to reduce the error; that is, an output voltage Vout corresponding to the reference voltage is generated.

[0007] Digitally controlled DC-DC converters are configured such that the compensation circuitry and PWM generation circuitry provided by analog-controlled DC-DC converters are implemented using digital circuitry. Figure 11B In this circuit, the compensation circuit is configured by a proportional-integral-derivative (PID) control circuit, and the PWM generation circuit is configured by comparator CMP2. Comparator CMP2 compares the sawtooth wave from the counter with the output of the PID control circuit. Because of the digital control, the output from comparator CMP1 is converted into a digital signal by an analog-to-digital converter (hereinafter referred to as the ADC circuit) and supplied to the PID control circuit. For example, in... Figure 11B In the digitally controlled DC-DC converter shown, when power is turned on, the soft-start control circuit operates, and the gate driver operates based on signals from the soft-start control circuit.

[0008] For example, a digitally controlled DC-DC converter technology with a PID control circuit is described in Japanese Patent No. 6,445,348 (Patent Document 1). Summary of the Invention

[0009] In order to stabilize the feedback operation in the DC-DC converter, the compensation circuit is configured to provide characteristics corresponding to the switching frequency of transistors MP1, MN1, etc., shown in Figure 11, the value of inductor Lout (i.e., inductance), and the value of capacitor Cout (i.e., capacitance).

[0010] In analog controlled DC-DC converters, since the switching frequency of transistors, the value of inductor Lout, and the value of capacitor Cout are preset, the resistors and capacitors constituting the compensation circuit are predetermined and fixed, so that the compensation circuit includes characteristics suitable for these preset frequencies and values.

[0011] In contrast, in a digitally controlled DC-DC converter, the transfer function, a characteristic of the PID control circuit, can be altered by changing the control parameters supplied to it. This means that the switching frequency, the values ​​of the inductor Lout, and the capacitor Cout can be varied. In other words, even if the switching frequency, the values ​​of the inductor Lout, and the capacitor Cout are set to any frequency and value, stable feedback operation can be achieved by changing the control parameters.

[0012] This digital control scheme allows users to optimize the switching frequency, inductor Lout, and capacitor Cout values ​​based on the desired DC-DC converter. For example, when the switching frequency, inductor Lout, and capacitor Cout values ​​are selected to reduce the cost of mounting components, feedback operation can be stabilized by selecting control parameters corresponding to the selected components. Furthermore, for example, electromagnetic interference (EMI) requirements become more stringent as the switching frequency increases. However, electromagnetic compatibility (EMC) tolerance can also be improved by selecting control parameters, ensuring stable feedback operation even at low switching frequencies.

[0013] Because the control parameters are provided as in Figure 11B The PID control circuit shown has a proportional constant KP related to the proportional, a derivative constant KD related to the derivative, an offset constant OFFSET related to the voltage offset, and an integral constant KI related to the integral.

[0014] The inventors have studied a system with a DC-DC converter that can change control parameters in response to changes in switching frequency, the value of inductor Lout, and the value of capacitor Cout. Figure 10 This is a circuit diagram illustrating a schematic configuration of a system conceived by the inventors prior to this invention. System 1 includes transistors MP1 and MN1, inductor Lout, capacitor Cout, DC-DC converter 2, and controller 3. DC-DC converter 2 includes... Figure 11B The diagram shows comparators CMP1 and CMP2, an ADC circuit, a PID control circuit, a counter, and a gate driver. Additionally, although in Figure 10 The value in the middle is omitted, but the output voltage Vout is supplied to controller 3.

[0015] The controller 3 provides a non-volatile storage device 5 and a control circuit 4. Multiple control parameters corresponding to each value of the switching frequency, inductor Lout, and capacitor Cout are pre-stored in the storage device 5. The control circuit 4 accesses the storage device 5 to read the control parameters corresponding to the set values ​​of the switching frequency, inductor Lout, and capacitor Cout, and then sets the read control parameters to the DC-DC converter 2. Therefore, the characteristics of the PID control circuit in the DC-DC converter 2 become suitable for the user-set values ​​of the switching frequency, inductor Lout, and capacitor Lout, enabling stable feedback operation to be performed.

[0016] However, the need for controller 3 increases the installation area when implementing system 1. Furthermore, the inventors have considered that controller 3 operates via the output voltage Vout generated by DC-DC converter 2. However, in order to operate controller 3, DC-DC converter 2 needs to generate the output voltage Vout. On the other hand, DC-DC converter 2 remains inactive until control parameters are provided to it. Therefore, the operating voltage is not fed to controller 3, and a deadlock state occurs, in which an inoperable state persists.

[0017] Patent Document 1 describes a technology involving a digitally controlled DC-DC converter, but Patent Document 1 does not describe or recognize the problems mentioned above.

[0018] Other objects and novel features will become apparent from the description in this specification and the accompanying drawings.

[0019] The semiconductor device according to one embodiment is as follows.

[0020] That is, the semiconductor device includes a converter whose characteristics are determined according to control parameters; a non-volatile memory device; and a processor that operates using the output voltage of the converter as its operating power supply. The control parameters are stored in the non-volatile memory device, and during the period when the output voltage is being output from the converter, the processor reads the control parameters from the non-volatile memory device and sets them in the converter.

[0021] According to one embodiment, a semiconductor device with a digitally controlled converter can be provided, which can stabilize feedback operation while suppressing an increase in mounting area. Attached Figure Description

[0022] Figure 1 This is a circuit diagram illustrating the configuration of the system according to the first embodiment;

[0023] Figure 2 This is a circuit diagram illustrating the configuration of a DC-DC converter according to the first embodiment.

[0024] Figure 3 This is a waveform diagram illustrating the operation of the DC-DC converter according to the first embodiment.

[0025] Figure 4 This is a block diagram illustrating the configuration of the mode switching circuit according to the first embodiment.

[0026] Figure 5 It is used in Figure 4 The waveform diagram of the DC-DC converter of the mode switching circuit is shown in the figure.

[0027] Figure 6 This is a block diagram illustrating the configuration of the mode switching circuit according to the second embodiment.

[0028] Figure 7 This is a waveform diagram illustrating the operation of the mode switching circuit according to the second embodiment.

[0029] Figure 8 This is a block diagram illustrating the configuration of the mode switching circuit according to the third embodiment.

[0030] Figure 9 This is a block diagram illustrating another configuration of the semiconductor device according to the first embodiment.

[0031] Figure 10 This is a circuit diagram illustrating a schematic configuration of a system that the inventors had studied prior to this invention.

[0032] Figure 11A This is a diagram illustrating the configuration of an analog controlled DC-DC converter.

[0033] Figure 11B This is a diagram illustrating the configuration of a digitally controlled DC-DC converter. Detailed Implementation

[0034] Embodiments of the present invention will now be described with reference to the accompanying drawings. It should be noted that this disclosure is merely illustrative, and suitable modifications will readily conceive of by those skilled in the art while maintaining the spirit of the invention; these modifications are naturally included within the scope of the invention. Additionally, although the drawings may schematically represent the width, thickness, shape, etc., of each portion compared to actual embodiments for clarity of illustration, the drawings are merely illustrative and do not limit the interpretation of the invention.

[0035] In this specification and each of the accompanying drawings, the same reference numerals are assigned to the same elements as those in the foregoing drawings, and their detailed descriptions may be appropriately omitted.

[0036] Figure 1 This is a circuit diagram illustrating the configuration of the system according to the first embodiment. Figure 1 In this context, 1 represents the system. Although system 1 includes multiple semiconductor devices, multiple transistors, and multiple passive components (inductors, resistors, capacitors, etc.), in... Figure 1 Only the content required for illustration is shown.

[0037] In the figure, 10 shows a semiconductor device. Semiconductor device 10 is a microcontroller in which multiple circuit blocks are formed in a semiconductor chip. T1 to T5 show external terminals provided on semiconductor device 10. External terminals T1, T4, and T5 are power supply terminals. A first power supply voltage Vd1 supplies power to external terminal T1, and a second power supply voltage Vd2 supplies power to external terminal T5. Furthermore, for external terminal T4, the output voltage Vout generated by the DC-DC converter, which will be described later, is fed.

[0038] Semiconductor device 10 includes a primary power supply region 11, to which a first power supply voltage is supplied as an operating voltage; a secondary power supply region 12, to which an output voltage Vout is supplied as an operating voltage; and a system power supply region 13, to which a second power supply voltage Vd2 is supplied as an operating voltage. Each circuit block in the circuit frame provided by semiconductor device 10 is operated by an operating voltage disposed on any one or more of the primary power supply region 11, the secondary power supply region 12, and the system power supply region 13, and each circuit block is supplied with the operating voltage of the disposed region.

[0039] exist Figure 1 In the diagram, a circuit block representing a portion of a plurality of circuit blocks provided by semiconductor device 10 is illustrated. Specifically, a processor 18, a static RAM (SRAM) 19 as a volatile memory device, a flash memory 17 as a non-volatile memory device, and peripheral logic 20 are illustrated as circuit blocks arranged in the secondary power region 12, and these circuit blocks operate via an output voltage Vout. Furthermore, system control logic 16 is illustrated as a circuit block arranged in the system power region 13, and this circuit block operates via a second power supply voltage Vd2. Additionally, a gate driver 15 is illustrated as a circuit block arranged in the primary power region 11, which operates via a first power supply voltage Vd1. As will be described later, a DC-DC converter 14 is arranged in both the primary power region 11 and the system power region 13, and the DC-DC converter 14 operates via the first power supply voltage Vd1 and the second power supply voltage Vd2.

[0040] Flash memory 17 stores, for example, a program for implementing a desired function, which is performed by semiconductor device 10. Processor 18 reads and executes the program stored in flash memory 17, thereby implementing the desired function in semiconductor device 10. Static memory 19 is used, for example, to store data when the program is executed, while peripheral logic is used, for example, to transfer data to and receive data from other semiconductor devices included in system 1 when the program is executed.

[0041] In the first embodiment, the control parameters of the DC-DC converter 14 are also pre-stored in the flash memory 17. The control program associated with the DC-DC converter is also pre-stored in the flash memory 17. The processor 18 reads the control parameters 21 from the flash memory 17 by executing the control program, and the processor 18 supplies the read control parameters 21 to the system control logic 16 and the DC-DC converter 14.

[0042] For reference Figure 2 As described in detail below, the DC-DC converter 14 includes a digital control loop, an analog control loop, and a mode switching circuit. The digital control loop sets the characteristics using supplied control parameters 21 and generates a PWM signal. In this first embodiment, the analog control loop generates a pulse frequency modulation (PFM) signal. The mode switching circuit selects either the PWM or PFM signal, and the selected signal is provided to the gate driver 15 as a gate drive signal 22. In the figures, the gate drive signal 22 is shown as a single signal, although it can be multiple signals.

[0043] Based on the supplied gate drive signal 22, the gate driver 15 generates gate signals 23P and 23N and supplies gate signals 23P and 23N to external terminals T2 and T3.

[0044] External terminals T1 to T4 are coupled to an external switching circuit 30 provided on the outside of the semiconductor device 10.

[0045] In the first embodiment, the switching circuit 30 includes transistors MP1 and MN1, inductor Lout, and capacitor Cout, without particular limitation. In the first embodiment, transistor MP1 includes a P-channel MOSFET, and transistor MN1 includes an N-channel MOSFET. Of course, transistors MP1 and MN1 are not limited to MOSFETs; transistors MP1 and MN1 can be IGBTs, etc.

[0046] Transistors MP1 and MN1 are coupled such that each term in the source-drain path is connected in series between the first power supply voltage Vd1 and the ground voltage Vs, and the drains of transistor MP1 and MN1 are coupled to each other. Furthermore, the gate of transistor MP1 is coupled to external terminal T2, and the gate of transistor MN1 is coupled to external terminal T3. The drains of transistors MP1 and MN1 are coupled to one end of inductor Lout. Additionally, capacitor Cout is coupled between the other end of inductor Lout and the ground voltage Vs, and the output voltage Vout from the other end of inductor Lout is output to external terminal T4.

[0047] Although omitted in the figure, a reference voltage is supplied, and the DC-DC converter 14 outputs a time-varying gate drive signal 22, thereby matching the output voltage Vout with the reference voltage. Based on the gate drive signal 22, the gate driver 15 provides time-varying gate drive signals 23P and 23N to the gates of transistors MP1 and MN1. Therefore, transistors MP1 and MN1 perform switching operations, and time-varying current flows into inductor Lout and capacitor Cout, thereby changing the output voltage Vout so that an output voltage Vout matching the reference voltage is output.

[0048] Although there are no specific limitations, the first power supply voltage Vd1 and the second power supply voltage Vd2 are the same voltage value (e.g., 3.3V to 5V). When matched with a reference voltage, the output voltage Vout is, for example, 1.8V. Since the first power supply voltage Vd1 and the second power supply voltage Vd2 are, for example, the same voltage value, the system power supply region 13 can be supplied with the first power supply voltage Vd1 from the external terminal T1 without the external terminal T5 being supplied to the semiconductor device 10. However, in the switching circuit 30, since transistors MP1 and MN1 perform switching operations, there is a possibility that noise caused by the switching operation can be transmitted to the system power supply region 13. Therefore, it is desirable to provide the first power supply voltage Vd1 and the second power supply voltage Vd2 separately.

[0049] (Configuration of DC-DC converter) Figure 2 This is a circuit diagram illustrating the configuration of the DC-DC converter according to the first embodiment. In the figure, the dotted line with a single point is a virtual line used to separate the region operated by the primary power supply and fed with the first power supply voltage Vd1, and the region operated by the system power supply and fed with the second power supply voltage Vd2. Figure 1 The primary power supply region 11 and the switching circuit 30 described herein are arranged in the region operated by the primary power supply. (See reference...) Figure 1 The described system power supply area 13 is arranged in the area operated by the system power supply. Figure 2 In, with Figure 1 The difference is that it shows an example in which the circuit block constituting the DC-DC converter 14 is arranged in an area operated by the system power supply, but is not limited thereto.

[0050] exist Figure 2 In this context, due to the switching circuit 30 and the gate driver 15 being in... Figure 1 The switching circuit 30 and the gate driver 15 are the same, so their description will be omitted.

[0051] The DC-DC converter 14 includes a digital control loop 35, an analog control loop 36 coupled in parallel with the digital control loop 35, and a mode switching circuit 37. Furthermore, although not specifically limited, in Figure 1 The system control logic 16 shown includes register 39 and control circuitry 40. Of course, both register 39 and control circuitry 40 could be provided in the DC-DC converter 14 instead of in the system control logic 16. The digital control loop 35 and analog control loop 36 will be described next.

[0052] (Digital control loop) The digital control loop 35 includes an error amplifier 41, an ADC circuit 42, a PID control circuit 43, a soft-start control circuit 44, a selector 45, a comparator 47, a counter 46, and a timing circuit 48.

[0053] Error amplifier 41 includes an input terminal (+) supplied with a reference voltage 38 and an input terminal (-) supplied with an output voltage Vout. Error amplifier 41 detects the potential difference between the reference voltage 38 supplied to the input terminal (+) and the output voltage Vout supplied to the input terminal (-), and outputs an error signal (analog signal) corresponding to the error to ADC circuit 42. ADC circuit 42 converts the error signal into a corresponding digital signal and outputs the corresponding digital signal to PID control circuit 43.

[0054] The PID control circuit 43 is supplied with control parameters 21 from register 39. As control parameters 21, an offset constant OFFSET related to voltage offset, a proportional constant KP related to proportionality, a derivative constant KD related to derivative, and an integral constant KI related to integral are supplied and set to the PID control circuit 43. The transfer function of the PID control circuit 43 is determined by the proportional constant KP, the derivative constant KD, and the integral constant KI, and the level of the propagation signal is adjusted according to the offset constant OFFSET. The PID control circuit 43 acts as a compensation circuit, changing the proportional constant KP, the derivative constant KD, the integral constant KI, and the offset constant OFFSET based on changes in the phase of the output voltage Vout supplied to the digital control loop 35. The PID control circuit 43 alters its characteristics and performs appropriate compensation for the output voltage Vout supplied to the digital control loop 35.

[0055] The soft-start control circuit 44 is a circuit used to suppress large inrush currents flowing in the current path when, for example, the first power supply voltage Vd1 and the second power supply voltage Vd2 are turned on and the DC-DC converter 14 is started. Without the soft-start control circuit 44, a large inrush current exists in the current path, including the transistor MP1, when the DC-DC converter 14 is started. For example, the large inrush current can cause a voltage drop across the first power supply voltage Vd1 and / or breakdown (burnout) of components constituting the current path. Furthermore, the output voltage Vout rises rapidly, and overshoot occurs in the output voltage Vout. When the DC-DC converter 14 is started, the soft-start control circuit 44 starts operating before the PID control circuit 43 and outputs a signal to control the transistor MP1, causing the output voltage Vout to gradually increase. Figure 2In this circuit, the soft-start control circuit 44 is provided in the digital control loop 35, but is not limited to being provided therein. For example, the soft-start control circuit 44 may be provided in the analog control loop 36 or outside the DC-DC converter 14.

[0056] The PID output signal PIO from the PID control circuit 43 is provided to the input terminal 45(0) of the selector, and the soft start signal STO from the soft start control circuit 44 is provided to the input terminal 45(1) of the selector. The selector 45 selects and outputs either the PID output signal PIO or the soft start signal STO according to the logic value of the mode switching signal mod1. When the mode switching signal mod1 is a logic value "1", the selector 45 selects the soft start signal STO supplied to the input terminal (1), and when the mode switching signal mod1 is a logic value "0", the selector 45 selects the PID output signal PIO supplied to the input terminal (0).

[0057] The output of selector 45 is supplied to the input terminal (+) of comparator 47. Conversely, the output signal of counter 46 is supplied to the input terminal (-) of comparator 47. Counter 46 counts the clock signal from timing circuit 48 to generate a clock signal as shown in the figure. Figure 2 The sawtooth pattern (comparison signal) is shown in 46P. That is, counter 46 generates a periodic sawtooth wave whose value increases from an initial value over time and returns to the initial value when a predetermined value is reached. Incidentally, timing circuit 48 also generates synchronization signals for ADC circuit 42, PID control circuit 43, soft-start control circuit 44, and comparator 47, and supplies these synchronization signals to these circuit blocks.

[0058] Comparator 47 compares the voltage value of the output of selector 45 supplied to input terminal (+) with the voltage value of the sawtooth wave supplied to input terminal (-), and comparator 47 provides the PWM signal D_PWM to input terminal (0) of mode switching circuit 37. The duty cycle of PWM signal D_PWM is determined according to the voltage value of the output of selector 45.

[0059] (Analog Control Loop) Analog control loop 36 includes an error amplifier 49 and a comparator 50. The error amplifier 49 includes an input terminal (+) supplied with a reference voltage 38 and an input terminal (-) supplied with an output voltage Vout, and the error amplifier 49 outputs the potential difference between the reference voltage 38 and the output voltage Vout as an analog error signal.

[0060] Comparator 50 includes an input terminal (+) and two input terminals (-) to which a high-side threshold voltage VT_H and a low-side threshold voltage VT_L are supplied, respectively. An error signal is supplied from error amplifier 49 to the input terminal (+). Comparator 50 performs a comparison between the voltage value of the error signal and the threshold voltages VT_H and VT_L, and outputs a PFM signal of the voltage based on the result of the comparison. For example, if the error signal exceeds the threshold voltage VT_H, comparator 50 sets the PFM signal high, and if the error signal drops below the threshold voltage VT_L, comparator 50 changes the PFM signal low.

[0061] In the first embodiment, analog control loop 36 will be described as an example of generating a PFM signal based on the difference between the output voltage Vout and the reference voltage 38, but analog control loop 36 is not limited thereto. For example, as in Figure 11A As shown, both the analog control loop and the digital control loop can generate PWM signals. The characteristics of the error amplifier 49 and the comparator 50 are predetermined. Therefore, even if the analog control loop generates a PWM signal or a PFM signal, the characteristics of the analog control loop 36 have already become those predetermined characteristics. That is, since the digital control loop 35 includes a PID control circuit 43, the characteristics of the analog control loop 36 are difficult to change by the control parameter 21. In other words, the analog control loop 36 can be a control loop that does not require the control parameter 21.

[0062] In the DC-DC converter 14 according to the first embodiment, the digital control loop 35 serves as a control loop constituting the main power supply relative to the secondary power supply region 12, and the analog control loop 36 serves as a control loop constituting an additional auxiliary power supply to enable the digital control loop 35 constituting the main power supply to function. That is, the analog control loop 36 supplies the power required to read the control parameters 21 from the flash memory 17 and transmit them to the PID control circuit 43. The analog control loop 36 can be configured within a range capable of supplying this power. Therefore, in the first embodiment, to minimize the area overhead in the analog control loop 36, a simplified PFM control configuration is employed in the analog control loop 36.

[0063] The PFM signal output from comparator 50 is supplied as PFM signal A_PFM to the input terminal (1) of mode switching circuit 37.

[0064] The mode switching signal mod2 is supplied to the mode switching circuit 37. Based on the logic value of the mode switching signal mod2, the mode switching circuit 37 selects either the PFM signal A_PFM supplied to the input terminal (1) or the PWM signal D_PWM supplied to the input terminal (0), and outputs it as the gate drive signal 22. Although there are no specific limitations, in the first embodiment, when the logic value of the mode switching signal mod2 is "0", the mode switching circuit 37 selects the PWM signal D_PWM supplied to the input terminal (0), and when the logic value of the mode switching signal mod2 is "1", the mode switching circuit 37 selects the PFM signal A_PFM supplied to the input terminal (1).

[0065] As described above, gate driver 15 generates output voltage Vout through the switching operation of transistors MP1 and MN1 based on gate drive signal 22. The generated output voltage Vout is supplied to the gate driver 15. Figure 1 The secondary power supply region 12 shown is supplied to error amplifiers 41 and 49. Therefore, the flash memory 17 and processor 18, etc., arranged in the secondary power supply region 12, operate, and the error between the reference voltage 38 and the output voltage Vout in the error amplifiers 41 and 49 is determined.

[0066] Based on the mode switching signal mod2, the mode switching circuit 37 selects either the PWM signal D_PWM or the PFM signal A_PFM. In other words, the digital control loop 35 or the analog control loop 36 is selected via the mode switching signal mod2. As a result, the selected control loop, gate driver 15, and switching circuit 30 generate a feedback path that matches the output voltage Vout with the reference voltage 38.

[0067] When the PFM signal A_PFM is selected, the operation is as follows: When the output voltage Vout exceeds the reference voltage 38, the error signal from the error amplifier 49 is reduced. Then, when the error signal falls below the threshold voltage VT_L, the comparator 50 sets the PFM signal A_PFM low. This low-level PFM signal A_PFM is supplied to the gate driver 15 as gate driver signal 22, and the gate driver 15 turns off the transistor MP1. When the output voltage Vout exceeds the reference voltage 38, the output voltage Vout is reduced because the transistor MP1 is turned off, thus reducing the error between the output voltage Vout and the reference voltage 38. Conversely, if the output voltage Vout falls below the reference voltage 38, the error signal increases, and if the error signal rises above the threshold VT_H, the comparator 50 sets the PFM signal A_PFM high. This high-level PFM signal A_PFM is supplied to the gate driver 15 as gate driver signal 22, and the gate driver 15 turns on the transistor MP1. Therefore, the output voltage Vout increases, which reduces the difference between the reference voltage 38 and the output voltage Vout.

[0068] exist Figure 2 In register 39 shown, processor 18 executes a control program and then writes control parameters 21 read from flash memory 17. The control parameters 21 stored in register 39 are supplied to PID control circuit 43.

[0069] The mode switching signals mod1 and mod2 mentioned above are generated by control circuit 40. In the first embodiment, control circuit 40 generates mode switching signals mod1 and mod2 based on the power-on reset signal PonR. Although there are no specific limitations, Figure 1 The system control logic 16 shown includes a power-on reset circuit (not shown). In the first embodiment, when both the first power supply voltage Vd1 and the second power supply voltage Vd2 are turned on, the power-on reset circuit outputs a power-on reset signal PonR.

[0070] (Operation of a DC-DC converter) Figure 3 This is a waveform diagram illustrating the operation of the DC-DC converter 14 according to the first embodiment. Figure 3 In Figure 2 The waveforms of the control signals and output voltage Vout during the startup of the DC-DC converter 14 are shown. (Refer to the following text.) Figure 2 and Figure 3 The operation of DC-DC converter 14 will be explained.

[0071] By switching on both the first power supply voltage Vd1 and the second power supply voltage Vd2, the first power supply voltage Vd1 and the second power supply voltage Vd2 become predetermined potentials. To avoid complexity in the accompanying drawings, only the first power supply voltage Vd1 is shown, and the first power supply voltage Vd1 will be described thereafter.

[0072] When the first power supply voltage Vd1 reaches the predetermined potential, the power-on reset circuit changes the power-on reset signal PonR to a low level. After a predetermined time has elapsed since the power-on reset signal PonR was changed to a low level (logic value "0"), the power-on reset circuit releases the power-on reset. That is, at time t0, the power-on reset circuit changes the power-on reset signal PonR to a high level (logic value "1").

[0073] Although there are no specific restrictions, the power-on reset signal PonR is set to "0". Figure 2 The control circuit 40 changes the mode switching signal mod1 to "1" and the mode switching signal mod2 to "0". By setting the mode switching signal mod1 to "1", the selector 45 selects the input terminal (1). Furthermore, by setting the mode switching signal mod2 to "0", the mode switching circuit 37 selects the input terminal (0).

[0074] Therefore, the soft-start signal STO from the soft-start control circuit 44 is supplied to the comparator 47 via the selector 45. In the comparator 47, the sawtooth wave and the soft-start signal STO are compared, and based on the comparison result, the PWM signal D_PWM is output from the comparator 47. The PWM signal D_PWM is supplied to the gate driver 15 via the mode control circuit 37. The gate driver 15 outputs gate signals 23P and 23N according to the supplied PWM signal D_PWM. Transistors MP1 and MN1 start operating according to the supplied gate signals 23P and 23N. Figure 3 In this process, a toggling operation is performed according to the gate signal 23P. During the toggling operation, transistor MP1 repeatedly switches between on and off states. Through the toggling operation performed by transistor MP1, the switching circuit 30 gradually increases the output voltage Vout. That is, the soft-start control circuit 44 operates, causing the output voltage Vout to gradually increase.

[0075] Through this output voltage Vout, it is arranged in Figure 1 The flash memory 17, processor 18, static memory 19 and peripheral logic 20 in the secondary power area 12 are started and begin operation.

[0076] When the output voltage Vout reaches the predetermined voltage value, the control circuit 40 changes the mode switching signal mod1 to "0" and the mode switching signal mod2 to "1". Figure 3 At time t1, the output voltage Vout has reached the predetermined voltage value. By setting the mode switching signals mod1 and mod2 to "0" and "1" respectively, selector 45 selects input terminal (0), and mode switching circuit 37 selects input terminal (1). Because mode switching circuit 37 selects input terminal (1), the PFM signal A_PFM generated by analog control loop 36 is supplied to gate driver 15.

[0077] Gate driver 15 outputs gate signals 23P and 23N according to the supplied PFM signal A_PFM. Figure 3 In the example shown, gate driver 15 outputs a gate signal 23P for switching transistor MP1. Therefore, switching circuit 30 maintains the output voltage Vout at a voltage above a predetermined value. That is, the output voltage Vout is maintained above the predetermined value by the PFM signal A_PFM generated by analog control loop 36.

[0078] In the first embodiment, during an analog PFM period in which the output voltage Vout is maintained above a predetermined voltage value by the PFM signal A_PFM generated by the analog control loop 36, the processor 18 reads control parameters 21 from the flash memory 17, passes control parameters 21 to register 39, and writes to register 39. Figure 3 At time t2, processor 18 reads control parameter 21 from flash memory 17 and initiates the transfer and writing of control parameter 21 to register 39. The transfer and writing of control parameter 21 to register 39 ends at time t3.

[0079] When the writing of control parameter 21 to register 39 is completed, control parameter 21 is set to the PID control circuit 43. Of course, the transfer of control parameter 21 to register 39 and the setting of control parameter 21 from register to PID control circuit 43 can be performed in parallel time.

[0080] When the control parameter 21 is set to complete by the PID control circuit 43, the control circuit 40 maintains the mode switching signal mod1 at "0" while switching the mode switching signal mod2 to "0". By changing the mode switching signal mod2 to "0", the mode switching circuit 37 selects the input terminal (0). At this time, the comparator 47 compares the sawtooth wave with the PID output signal PIO of the PID control circuit 43 output through the selector 45, and outputs the PWM signal D_PWM according to the comparison result. Therefore, the mode switching circuit 37 outputs the PWM signal D_PWM to the gate driver 15, and the gate driver 15 outputs gate signals 23P and 23N based on the PID output signal PIO. Transistors MP1 and MN1 perform switching operations through the gate signals 23P and 23N, and the switching circuit 30 outputs the output voltage Vout corresponding to the PWM signal D_PWM.

[0081] exist Figure 3 In this context, the period in which the output voltage Vout is generated based on the PID output signal PIO of the PID control circuit 43 is shown as "digital PWM". Furthermore, in Figure 3 In the diagram, the period in which the output voltage Vout is generated based on the PFM signal A_PFM is shown as "Analog PFM," and the period in which the output voltage Vout is generated based on the soft-start signal STO is shown as "Soft Start." The output voltage Vout generated during the digital PWM period is used as, for example, in... Figure 1 The main power source for the flash memory 17, processor 18, static memory 19, and peripheral logic 20 shown is the flash memory 17, processor 18, static memory 19, and peripheral logic 20. The output voltage Vout generated during the analog PFM period and the output voltage Vout generated during the digital PWM period have the same voltage value, for example, but the output voltage Vout generated during the analog PFM period is an auxiliary power supply for properly operating the digital control loop 35 that generates the main power supply.

[0082] The soft-start period is used to prevent large inrush currents when the first power supply voltage Vd1 (and the second power supply voltage Vd2) are turned on and the DC-DC converter 14 is started. In the first embodiment, when the power supply voltage Vd1 is turned on, the DC-DC converter 14 sequentially transitions from the soft-start period to the analog PFM period, and then to the digital PWM period.

[0083] As described above, the transition from the soft-start period to the analog PFM period is executed when the output voltage Vout reaches a predetermined voltage. In the first embodiment, although there are no specific limitations, the transition from the soft-start period to the analog PFM period is executed when a predetermined time has elapsed since the reset is released, because the output voltage Vout is considered to have reached the predetermined voltage. That is, the control circuit 40 determines whether a predetermined time has elapsed since the time t0 when the reset signal PonR is changed to "1", and the control circuit 40 changes the logic values ​​of the mode switching signals mod1 and mod2 at the time t1 when the predetermined time has elapsed. Of course, the invention is not limited to this. For example, by supplying a predetermined voltage to the control circuit 40, the output voltage Vout is compared with the predetermined voltage, and the logic values ​​of the mode switching signals mod1 and mod2 can be changed based on the comparison result.

[0084] According to the control circuit 40 of the first embodiment, it is determined whether a predetermined time has elapsed since the reset release time t0, and if time t3 is the moment when the predetermined time has elapsed, the transition from the analog PFM period to the digital PWM period is performed by changing the logic value of the mode switching signal mod2.

[0085] exist Figure 3 For example, at time t2 during the simulated PFM period, processor 18 reads control parameter 21 from flash memory 17 and initiates transfer and writing to register 39, but is not limited to this. For example, time t2 can be during the soft-start period when the output voltage Vout reaches a stable operating voltage value for processor 18, flash memory 17, etc.

[0086] In the first embodiment, a soft-start period and / or an analog PFM period can be used to initiate the flash memory 17 and processor 18 initially installed in the semiconductor device 10. The initiated flash memory 17 and processor 18 can then be used to transition the semiconductor device 10 to a state where it can perform normal operation (where it is operated by the main power supply), thereby preventing it from falling into a deadlock state. The PID control circuit 43 is configured via control parameter 21 to have characteristics suitable for the switching frequencies of transistors MP1 and MN1, and the values ​​of inductors Lout and capacitor Cout included in the switching circuit 30. Therefore, it is possible to provide a digitally controlled DC-DC converter 14 capable of stabilizing feedback operation while suppressing any increase in area.

[0087] Typically, when comparing PFM control and PWM control, the power efficiency of the DC-DC converter 14 at low loads is higher in PFM control. Therefore, the DC-DC converter 14 can be switched to operate in PFM control not only during the startup of the flash memory 17 and processor 18, but also during the power-saving mode of the semiconductor device 10 used to reduce the operating current of the processor 18. That is, in power-saving modes, the mode switching signal mod2 can be controlled to be "1". Therefore, the output voltage Vout is generated based on the PFM signal A_PFM generated by the analog control loop 36.

[0088] exist Figure 1 Examples of transistors MP1 and MN1 provided on the outside of semiconductor device 10 have been described, but are not limited thereto. For example, as in Figure 9 As shown in, Figure 1 The transistors MP1 and MN1 shown can be incorporated into the semiconductor device 10. Figure 9 This is a block diagram illustrating another configuration of the semiconductor device related to the first embodiment. Figure 9 In the middle, the DC-DC converter 14_1 is included Figure 1 The DC-DC converter 14, gate driver 15, and transistors MP1 and MN1 are shown. In this case, the coupling node between transistors MN1 and MP1 is coupled to an external terminal T6, and inductor Lout and capacitor Cout are coupled in series between the external terminal T6 and the ground voltage Vs.

[0089] (Second Embodiment) Figure 4 This is a block diagram illustrating the configuration of the mode switching circuit 37 according to the first embodiment. Figure 4 The mode switching circuit 37 shown includes a selector 37S, which includes an input terminal (0), another input terminal (1), a selection terminal SL, and an output terminal OT. When the mode switching signal mod2 supplied to the selection terminal SL is "0", the PWM signal D_PWM is supplied from the output terminal OT to the gate driver 15, and when the mode switching signal mod2 is "1", the PFM signal A_PFM is supplied to the gate driver 15.

[0090] The selector 37S, due to its simple configuration, allows for a reduction in area by configuring the mode switching circuit 37 with a simple circuit. However, when the mode switching circuit 37 asynchronously switches between the PFM signal A_PFM and the PWM signal D_PWM, a relatively large overshoot may occur in the output voltage Vout. This is because when switching asynchronously from PFM control to PWM control, the output voltage Vout (ripple) changes significantly because the change in output voltage Vout (ripple) is larger in PFM control than in PWM control.

[0091] Next, the situation where a relatively large overshoot occurs due to asynchronous switching will be described with reference to the attached figures. Figure 5 Is using Figure 4 The waveform diagram of the DC-DC converter 14 of the mode switching circuit is shown in the figure. Figure 5 Corresponding to this waveform diagram, which shows more details Figure 3 The waveform near time t3 is shown in the waveform diagram. Furthermore, in... Figure 5 In the diagram, IL indicates the flow through... Figure 1 and Figure 2 The inductor current of inductor Lout is shown in the figure. A_PFM shows the PFM signal A_PFM, and D_PWM shows the PWM signal D_PWM.

[0092] At time t3, the mode switching signal mod2 switches from "1" to "0", and the transition from the analog PFM period to the digital PWM period is executed.

[0093] During the simulated PFM period, when the PFM signal A_PFM is set to "1", gate driver 15 sets gate signal 23P to "0", and when the PFM signal A_PFM is set to "0", gate driver 15 sets gate signal 23P to "1". When gate signal 23P is "0", transistor MP1 is turned on, and inductor current IL increases. Conversely, when gate signal 23P is "1", transistor MP1 is turned off, and inductor current IL decreases. The change in inductor current IL causes the output voltage Vout to change to match the reference voltage 38. In PFM control, the frequency of the PFM signal changes due to the error between the output voltage Vout and the reference voltage 38, but as in... Figure 5 As shown, the change in the controlled inductor current IL during one cycle (i.e., the control quantity) is relatively large because one cycle of the PFM signal A_PFM is relatively long.

[0094] As in Figure 5As shown, during PFM control, when switching to PWM control immediately after transistor MP1 switches from the ON state to the OFF state, i.e., when the inductor current IL approaches its peak value, an overshoot occurs in the output voltage Vout. One period of the PWM signal D_PWM is shorter than one period of the PFM signal A_PFM. Therefore, the amount of change in the inductor current IL controlled during one period of the PWM signal D_PWM is smaller than the amount of change in the inductor current IL controlled during one period of the PFM signal A_PFM. Consequently, it takes time for the inductor current IL to return to equilibrium from a state exceeding the desired output current, resulting in a relatively large overshoot in the output voltage Vout.

[0095] In flash memory 17 and processor 18, for example, the circuitry that supplies the output voltage Vout as the power supply voltage is being miniaturized and its voltage is being reduced, thus greatly limiting the acceptable range of voltage variations in the power supply voltage. Therefore, it is necessary to suppress overshoot of the output voltage Vout.

[0096] Figure 6 This is a block diagram illustrating the configuration of the mode switching circuit associated with the second embodiment. Figure 6 In Figure 37_1, a mode switching circuit is shown, and this mode switching circuit is used as... Figure 2 The mode switching circuit 37 in the DC-DC converter 14 shown in the figure.

[0097] The mode switching circuit 37_1 includes a selector 37S, inverter circuits 60, 61, and 64, AND circuits 62 and 65, NAND circuit 63, and flip-flop circuits (hereinafter referred to as FF circuits) FM1, FM2, WM1, and WM2. FF circuits FM1, FM2, WM1, and WM2 have the same configuration. To avoid complex diagrams, only the terminals of FF circuit FM1 are shown, and each terminal is labeled. That is, D indicates the input terminal, Q indicates the output terminal, CK indicates the clock terminal, and / R indicates the reset terminal. When "0" is supplied to the reset pin / R, FF circuit FM1 is reset, and then outputs "0" from the output pin Q. Furthermore, when the signal supplied to the clock pin CK changes, the logic value of the input supplied to the input pin D is latched, and the latched logic value is output from the output pin Q. The other FF circuits are the same as FF circuit FM1.

[0098] The output terminal Q of FF circuit FM1 is coupled to the input terminal D of FF circuit FM2. That is, FF circuits FM1 and FM2 are coupled subordinately to ground in the two stages or connected in series in the two stages. The mode switching signal mod2, inverted by inverter circuit 60, is supplied to the reset terminal / R of FF circuits FM1 and FM2, and the PFM signal A_PFM, inverted by inverter circuit 61, is supplied to the clock terminal CK of FF circuits FM1 and FM2. A high level of logic value "1" is supplied to the input terminal D of FF circuit FM1, and the output from the output terminal Q of FF circuit FM2, along with the inverted mode switching signal mod2, is supplied to AND circuit 62 (the first logic circuit).

[0099] The output terminal Q of FF circuit WM1 is coupled to the input terminal D of FF circuit WM2. That is, FF circuits WM1 and WM2 are also ground-coupled in the two stages or connected in series in the two stages. The output of AND circuit 62 is supplied to the reset terminal / R of FF circuits WM1 and WM2, and the PWM signal D_PWM is supplied to the clock terminal CK of FF circuits WM1 and WM2. A high level of logic value "1" is supplied to the input terminal D of FF circuit WM1, and the output signal C of AND circuit 62, as well as the output signal from the output terminal Q of FF circuit WM2, are supplied to NAND circuit 63 (the second logic circuit).

[0100] The output signal C of the AND circuit 62, inverted by the inverter circuit 64, and the PFM signal A_PFM are supplied to the AND circuit 65 (the third logic circuit), and the output of the AND circuit 65 is supplied to the input terminal (1) of the selector 37S. Additionally, D_PWM is supplied to the input terminal (0) of the selector 37S. The output of the NAND circuit 63 is supplied to the selection terminal SL of the selector 37S as the mode switching signal mod2_1 after synchronization. Similar to... Figure 4 The output terminal OT of selector 37S is coupled to gate driver 15.

[0101] The mode switching circuit 37_1, which generates a mode switching signal mod2_1 from the mode switching signal mod2, will be described later with reference to the accompanying drawings. When transitioning from an analog PFM period to a digital PWM period, this mode switching signal mod2_1 asynchronously switches from "1" to "0" relative to the switching operation of transistor MP1. The mode switching signal mod2_1 is a mode switching signal that switches from "1" to "0" at a predetermined timing relative to the switching operation of transistor MP1. Therefore, by transitioning from the analog PFM period to the digital PWM period at a timing when the inductor current IL is reduced, large overshoots occurring in the output voltage Vout can be suppressed.

[0102] Figure 7 This is a waveform diagram illustrating the operation of the mode switching circuit according to the second embodiment. Next, reference will be made to... Figure 6 and Figure 7 To describe the operation of the mode switching circuit 37_1.

[0103] At time t3, the mode switching instruction is issued. That is, the mode switching signal mod2 changes from "1" to "0". Therefore, the reset of the FF circuits FM1 and FM2 of the PFM signal A_PFM is released.

[0104] During the simulated PFM period, when the PFM signal A_PFM changes to "0" at time t_FM1, the FF circuit FM1 captures the logic value "1" supplied to input terminal D, latches it, and outputs "1" from output terminal Q. Subsequently, the PFM signal A_PFM changes from "0" to "1" and then changes to "0" again at time t_FM2. In response to the change of the PFM signal A_PFM to "0", the FF circuit FM2 captures, latches, and outputs the output "1" from the FF circuit FM1.

[0105] Since the mode switching signal mod2 is "1" and is inverted by the inverter circuit 60, when the logic value "1" is output from the FF circuit FM2, the AND circuit 62 changes the output signal C to the logic value "1". Therefore, the reset of the FF circuits WM1 and WM2, whose clock signal is the PWM signal D_PWM, is released.

[0106] When the PFM signal A_PFM changes to "0" at time t_FM2, and the PWM signal D_PWM changes from "0" to "1" at time t_WM1, the FF circuit WM1 captures the logic value "1" supplied to input terminal D, latches it, and outputs it. Subsequently, the PWM signal D_PWM changes to "0" and then changes to the logic value "1" again at time t_WM2. During the change of the PWM signal D_PWM at time t_WM2, the FF circuit WM2 captures, latches, and outputs the "1" output from the FF circuit WM1.

[0107] Since the output signal C of “1” is supplied from the AND circuit, when the output of the FF circuit WM2 becomes “1”, the NAND circuit 63 switches the logic value of the mode switching signal mod2_1 from logic value “1” to logic value “0”.

[0108] That is, even if the mode switching signal mod2 switches to the logic value "0" at time t3, the mode switching signal mod2_1 supplied to the selection terminal SL of the selector 37S also maintains the logic value "1", and is then switched to the logic value "0" at a predetermined time t3_R after time t3.

[0109] By setting the mode switching signal mod2_1 to "0" at time t3_R, selector 37S selects the PWM signal D_PWM and provides the PWM signal D_PWM to gate driver 15. Incidentally, since the output signal C of AND circuit 62 is "1", and then inverter circuit 64 supplies "0" to AND circuit 65, the supply of PFM signal A_PFM to input terminal (1) of selector 37S (1) is stopped.

[0110] In the mode switching circuit 37_1 according to the second embodiment, a predetermined logic value "1" is reached via two-stage series-coupled FF circuits FM1 and FM2 with a clock signal of PFM signal A_PFM, and then operation of two-stage series-coupled FF circuits WM1 and WM2 with a clock signal of PWM signal D_PWM is enabled. The logic value of the mode switching signal mod2_1 changes as the predetermined logic value "1" is reached via the two-stage series-coupled FF circuits WM1 and WM2 in which operation is enabled. Therefore, when the transition from the analog PFM period to the digital PWM period is instructed by the mode switching signal mod2, the mode switching is delayed by the sum of the following times: the time corresponding to the number of stages of the series-coupled FF circuits with a clock signal of PFM signal A_PFM, and the time corresponding to the number of stages of the series-coupled FF circuits with a clock signal of PWM signal D_PWM.

[0111] Furthermore, digital PWM control always begins at a timing delay from the point when the last transistor MP1 in the analog PFM period is turned off, corresponding to the number of stages in the series-coupled FF circuit where the clock signal is the PWM signal D_PWM, i.e., Figure 7 (Approximately 1.5 cycles of the PWM signal D_PWM in the simulation). As a result, it can be ensured that after the inductor current IL reaches its peak in the analog PFM period, the inductor current IL is reduced for a certain period of time, so that digital PWM control is initiated at the timing when the inductor current IL is in a reduced state, and large overshoot of the output voltage Vout is suppressed.

[0112] (Third Embodiment) Figure 8 This is a block diagram illustrating the structure of the mode switching circuit according to the third embodiment. Figure 8 The mode switching circuit 37_2 shown is used as Figure 2The mode switching circuit 37 in the DC-DC converter 14 shown is similar to that in... Figure 6 The mode switching circuit 37_1 shown is described differently from the mode switching circuit 37_2. In mode switching circuit 37_2, compared to mode switching circuit 37_1, FF circuits FM3 to FM5, FF circuits WM3 to WM5, inverter circuits 66 and 68, and three-input OR circuits 67 and 69 are added. Furthermore, in mode switching circuit 37_2, a test signal Test and a reset signal PonR are provided. For example, when testing semiconductor device 10, the test signal Test is set to the logic value "1", and the reset signal PonR becomes the logic value "0" based on the power-on described above, and changes back to the logic value "1" after a predetermined time has elapsed.

[0113] FF circuits FM3 to FM5 are coupled to each other via output terminal Q and input terminal D, forming a three-stage series-coupled circuit. The input terminal D of FF circuit FM3, corresponding to the first stage of the series-coupled circuit, is supplied with a high level of logic value "1", and the output terminal Q of FF circuit FM5, corresponding to the final stage, is coupled to inverter circuit 66. Similar to FF circuits FM1 and FM2, FF circuits FM3 to FM5 operate using the PFM signal A_PFM as a clock signal. More specifically, the corresponding clock terminal CK of FF circuits FM3 to FM5 is supplied with a clock signal inverted by the PFM signal A_PFM via inverter circuit 61, operating synchronously with changes in the PFM signal A_PFM. Furthermore, unlike FF circuits FM1 and FM2, a reset signal PonR is supplied to the corresponding reset terminal / R of FF circuits FM3 to FM5, and FF circuits FM3 to FM5 are reset when the reset signal PonR is "0".

[0114] exist Figure 6 In the mode switching circuit 37_1 shown, the output of the FF circuit FM2 is supplied to the AND circuit 62. However, in the mode switching circuit 37_2, the output of the FF circuit FM2 is supplied as output signal B to the three-input OR circuit 67. In addition to the output signal B, the output signal A of the inverter circuit 66 and the test signal Test are supplied to the three-input OR circuit 67, and the output of the three-input OR circuit 67 is supplied to the AND circuit 62.

[0115] The coupling of FF circuits WM3 to WM5, inverter circuit 68, and three-input OR circuit 69 is similar to the coupling of FF circuits FM3 to FM5, inverter circuit 66, and three-input OR circuit 67 described above. The difference is that, similar to FF circuits WM1 and WM2, the PWM signal D_PWM is supplied to the clock terminal CK of FF circuits WM3 to WM5, and FF circuits WM3 to WM5 operate synchronously with the change of the PWM signal D_PWM. Three-input OR circuit 69 is supplied with a test signal Test, the output signal D of inverter circuit 68, and the output signal E of FF circuit WM2. The output signal C of AND circuit 62 and the output of three-input OR circuit 69 are supplied to NAND circuit 63, and the mode switching signal mod2_2 is output from NAND circuit 63 to control selector 37S.

[0116] In the mode switching circuit 37_1 described in the second embodiment, after the mode switching signal mod2 becomes "0", the AND circuit 62 outputs an output signal C with a logic value of "1" only at a time corresponding to the number of stages of the series-coupled FF circuit, when the PFM signal A_PFM changes to "0". After the output signal C is set to "1", the NAND circuit 63 changes the mode switching signal mod2_1 to "0" only at a time corresponding to the number of stages of the series-coupled FF circuit, when the PWM signal D_PWM changes to "1", and then indicates a switch to PWM control.

[0117] Conversely, in the mode switching circuit 37_2, when the reset signal PonR is a logic value indicating a reset "0", each of the FF circuits FM3 to FM5 is reset, and a signal with a logic value of "0" will be output from FF circuits FM3 to FM5. The "0" output from FF circuit FM5 is inverted by inverter circuit 66, and then the output signal A becomes "1". Therefore, even without changing the PFM signal A_PFM, the three-input OR circuit 67 will set the output signal to "1". At this time, if the mode switching signal mod2 is "0", the output signal C of the AND circuit 62 is a logic value of "1". That is, even if the PFM signal A_PFM is not changed, the output signal C can be changed to "1" by setting the mode switching signal mod2 to "0" and the reset signal PonR to "0".

[0118] The FF circuits WM3 to WM5, inverter circuit 68, and three-input OR circuit 69 operate in the same manner as the FF circuits FM3 to FM5, inverter circuit 66, and three-input OR circuit 67. Furthermore, the output signal of the three-input OR circuit 69 can be changed by setting the reset signal PonR to "0" without altering the PWM signal D_PWM. Therefore, even if the PWM signals A_PWM and D_PWM remain unchanged, the NAND circuit 63 outputs a mode switching signal mod2_2 containing the logic value "0". That is, the PWM signal D_PWM is selected by the selector 37S.

[0119] Similarly, when the test signal Test is set to "1" to test the semiconductor device 10, even if the PFM signal A_PFM and the PWM signal D_PWM remain unchanged, the logic value of the mode switching signal mod2_2 is set to "0", so that the PWM signal D_PWM is selected by the selector 37S by setting the mode switching signal mod2_2 to the logic value "0".

[0120] The series-coupled circuits including FF circuits FM1 and FM2 can be considered as counters, used to count the number of cycles of the PFM signal A_PFM after the reset is released by the mode switching signal mod2 (hereinafter referred to as the synchronization cycle number of the mode switching signal). Furthermore, the series-coupled circuits including FF circuits FM3 to FM5 can be considered as counters, used to count the number of cycles of the PFM signal A_PFM after the reset is released by the reset signal PonR (hereinafter referred to as the synchronization cycle number of the reset signal).

[0121] The series-coupled circuits including FF circuits WM1 and WM2 can be considered as counters, used to count the number of cycles of the PWM signal D_PWM (also known as the synchronization cycle number of the mode switching signal) after being released by the reset signal C. Furthermore, the series-coupled circuits including FF circuits WM3 to WM5 can also be considered as counters, used to count the number of cycles of the PWM signal D_PWM (also known as the synchronization cycle number of the reset signal) after being released by the reset signal PonR.

[0122] exist Figure 8 In the configuration shown, the synchronization cycle number of the mode switching signal is 2, and the synchronization cycle number of the reset signal is 3.

[0123] When starting the digitally controlled DC-DC converter, after soft-start control, it is possible to switch to the digital PWM period without transitioning to the analog PFM period. That is, the main power supply controlled by digital PWM can be used to power the flash memory 17 and the processor 18, instead of using the auxiliary power supply controlled by analog PFM.

[0124] For example, semiconductor device 10 may have a power-saving mode that shuts down DC-DC converter 14. To save power, DC-DC converter 14 can be shut down and then restarted. In this case, since system power region 13 is as shown in... Figure 1 The second power supply voltage Vd2 shown in the figure is used for supply, so even if the DC-DC converter 14 is in the off state, the control parameter 21 is stored in the system control logic 16. Figure 2 The control parameter 21 is shown in register 39. Therefore, it is not necessary to read the control parameter 21 from flash memory 17, and then start it through the soft-start period of soft-start control circuit 44, and after switching to digital PWM period without switching to analog PFM period, the circuit block arranged in secondary power supply region 12 can be operated by the main power supply generated by PWM control.

[0125] However, when the mode switching circuit 37_1 described in the second embodiment is used as the mode switching circuit of the DC-DC converter 14, and the DC-DC converter 14 is started by setting the mode switching signal mod2 to "0", the DC-DC converter always switches to the analog PFM period for generating auxiliary power after the soft start period.

[0126] Conversely, when used in Figure 8 When the mode switching circuit 37_2 shown in the figure is used as the mode switching circuit of the DC-DC converter 14, the DC-DC converter 14 can be restarted by using the reset signal PonR, and then switched to the digital PWM period after the soft start period is completed.

[0127] During the reset period when the reset signal PonR is "0", although the synchronization control via the mode switching signal mod2 is disabled, as described above, the output signals A and D of inverter circuits 66 and 68 become "1". Therefore, by setting the mode switching signal mod2 to "0", the output signal C becomes "1", and the mode switching signal mod2_2 becomes the logic value "0". As a result, the state of the selected PWM signal D_PWM is implemented by selector 37S. Thereafter, the reset is released when the reset signal PonR is 1, and then the PWM signal D_PWM and the PFM signal A_PFM are generated by digital control loop 35 and analog control loop 36.

[0128] As mentioned above, the reset signal has 3 synchronization cycles, and the mode switching signal has 2 synchronization cycles. Therefore, in the third cycle of the PFM signal A_PFM, the output signal A changes its logic value from "1" to "0", while in the second cycle of the PFM signal A_PFM, the output signal B changes its logic value from "0" to "1". In the third cycle of the PWM signal D_PWM, the output signal D changes its logic value from "1" to "0", while in the second cycle of the PWM signal D_PWM, the output signal E changes its logic value from "0" to "1".

[0129] When the mode switching signal mod2 is set to "0" in the reset state, the mode switching signal mod2_2 is immediately set to "0". From this state, the reset is released, and when the PWM signal D_PWM and the PFM signal A_PFM are generated by the digital control loop 35 and the analog control loop 36, the output signal A remains "0" after the output signal B becomes "1" (synchronous disable release). As a result, the logic value "0" of the mode switching signal mod2_2 is maintained, and the selector 37S can continuously supply the generated PWM signal D_PWM to the gate driver 15.

[0130] As a result, the DC-DC converter 14 using the mode switching circuit 37_2 can switch to the digital PWM period after the soft-start period without switching to the analog PFM period.

[0131] When semiconductor device 10 is tested, the required control parameters 21 can be preset in register 39. Therefore, it is not necessarily necessary to insert an analog PFM period after the soft-start period.

[0132] exist Figure 8 In the mode switching circuit 37_2 shown, by setting the test signal Test to "1", the output signals of OR circuits 67 and 69 can be set to the logic value "1", and the mode switching signal mod2_2 can be set to the logic value "0". That is, by disabling the synchronous control of the mode switching signal mod2, analog PFM control and digital PWM control can be switched at any timing. This allows testing of both modes without the need for complex sequence operations.

[0133] exist Figure 8In this circuit, FF circuits FM3 to FM5, inverter circuit 66, and OR circuit 67 can be considered as constituting the fourth logic circuit. Furthermore, FF circuits WM3 to WM5, inverter circuit 68, and OR circuit 69 can be considered as constituting the fifth logic circuit. The fourth and fifth logic circuits can be considered as follows: at the timing of testing and reset, in response to the selection instruction for the PWM signal D_PWM via the mode switching signal mod2, selector 37S selects the PWM signal D_PWM and disables the delay caused by FF circuits FM1, FM2, WM1, and WM2.

[0134] Although the invention has been described in detail by the inventors based on embodiments, the invention is not limited to the embodiments described above, and it goes without saying that various modifications can be made without departing from the spirit of this document.

Claims

1. A semiconductor device comprising: a converter, the converter being characterized by a control parameter; a non-volatile storage device, the non-volatile storage device being operated with an output voltage of the converter; and a processor, the processor being operated with the output voltage of the converter, and controlling the non-volatile storage device, wherein the control parameter is stored in the non-volatile storage device, and wherein the control parameter is read by the processor from the non-volatile storage device, and is set in the converter when the converter outputs the output voltage, the converter comprising: a digital control loop, the digital control loop being characterized by the control parameter; an analog control loop, the analog control loop comprising a predetermined characteristic; a first mode switching circuit, the first mode switching circuit being coupled to the digital control loop and the analog control loop, and the first mode switching circuit being configured to select between the digital control loop and the analog control loop by a first mode switching signal, and wherein the output voltage of the converter is determined by the digital control loop or the analog control loop selected by the first mode switching circuit; wherein the converter further comprises a register, the register being coupled to the digital control loop, wherein the control parameter is set to the register when the analog control loop is selected by the first mode switching circuit; wherein the digital control loop comprises: a compensation circuit, the compensation circuit being characterized by the control parameter from the register, and the compensation circuit being supplied with a digital signal, the digital signal corresponding to an error between the output voltage of the converter and a reference voltage; and a first comparator, the first comparator comparing a comparison signal that changes over time, and outputting a PWM signal, wherein the analog control loop comprises a second comparator, the second comparator comparing an analog signal corresponding to the error with a predetermined threshold, and outputting a PFM signal, and wherein the PWM signal and the PFM signal are selected by the first mode switching circuit.

2. The semiconductor device according to claim 1, the converter further comprising: a soft start control circuit, the soft start control circuit outputting a predetermined signal before the compensation circuit operates; and a second mode switching circuit, the second mode switching circuit selecting between an output of the compensation circuit and an output of the soft start control circuit by a second mode switching signal; wherein the first comparator compares the signal selected by the second mode switching circuit with the comparison signal, and outputs the PWM signal.

3. The semiconductor device according to claim 1, the first mode switching circuit comprising: a plurality of first flip-flop circuits, the plurality of first flip-flop circuits being coupled in series, and the PFM signal being supplied to respective clock terminals of the plurality of first flip-flop circuits; a first logic circuit, a first signal being supplied to the first logic circuit via the plurality of first flip-flop circuits, and the first mode switching signal being supplied to the first logic circuit, a plurality of second flip-flop circuits, the plurality of second flip-flop circuits being coupled in series, and the PWM signal being supplied to respective clock terminals of the plurality of second flip-flop circuits; a second logic circuit, a second signal being supplied to the second logic circuit via the plurality of second flip-flop circuits, and an output of the first logic circuit being supplied to the second logic circuit; and a selector, the selector selecting the PWM signal or the PFM signal depending on an output of the second logic circuit; wherein the selector selects the PWM signal after a time delay corresponding to a number of stages of the first flip-flop circuits and the second flip-flop circuits coupled in series when the first mode switching signal indicates selection of the PWM signal.

4. The semiconductor device according to claim 3, wherein the plurality of first flip-flop circuits are reset based on the first mode switching signal; wherein the plurality of second flip-flop circuits are reset based on an output of the first logic circuit; wherein the selector is supplied with an output of a third logic circuit and the PWM signal, the third logic circuit being provided with the output of the first logic circuit and the PFM signal.

5. The semiconductor device according to claim 3, the first mode switching circuit further comprising: a fourth logic circuit, the first signal, a signal based on a reset signal, a signal based on the PFM signal, and a test signal being supplied to the fourth logic circuit; and a fifth logic circuit, the second signal, a signal based on the reset signal, the PWM signal, and the test signal being supplied to the fifth logic circuit; wherein the first logic circuit is supplied with the first mode switching signal and an output of the fourth logic circuit; and wherein the second logic circuit is supplied with the output of the first logic circuit and an output of the fifth logic circuit; and wherein the time delay corresponding to the number of stages of the first flip-flop circuits and the second flip-flop circuits coupled in series is disabled, and the selector selects the PWM signal in response to the first mode switching signal indicating selection of the PWM signal during a test time specified by the test signal, and during a reset time specified by the reset signal.

6. A system comprising a semiconductor device, the semiconductor device comprising a first external terminal and a second external terminal, and a switching circuit coupled to the first external terminal, the semiconductor device comprising: a processor; a non-volatile storage device, the processor and the non-volatile storage device being coupled to the second external terminal, and operating with a voltage at the second external terminal; and a converter, the converter being coupled to the first external terminal, and the converter being characterized by a control parameter, wherein the switching circuit comprises: a transistor that switches according to an output of the converter that is provided via the first external terminal; and an inductor and a capacitor that are supplied with current via the transistor, and wherein the switching circuit outputs a voltage corresponding to the output of the converter to the second external terminal, and wherein the control parameter is stored in the non-volatile storage device, and the control parameter is read by the processor from the non-volatile storage device and set to the converter, the converter includes: a digital control loop including: a compensation circuit that is characterized by the control parameter, and that is supplied with a digital signal corresponding to an error between an output voltage at the second external terminal and a reference voltage; and a first comparator that compares an output of the compensation circuit with a comparison signal that changes over time, and outputs a PWM signal; an analog control loop including a second comparator that compares an analog signal corresponding to the error with a predetermined threshold, and outputs a PFM signal; and a mode switching circuit that is coupled to the digital control loop and the analog control loop, and that is configured to select between the PWM signal and the PFM signal by a mode switching signal, and that is configured to output as an output of the converter.

7. The system according to claim 6, the converter further including a register to which the control parameter is set when the PFM signal is output as the output of the converter.

8. A control method for generating a power supply voltage to operate a semiconductor device including a non-volatile storage device that stores a control parameter and a converter including: a digital control loop including: a compensation circuit that is characterized by the control parameter, and that is supplied with a digital signal corresponding to an error between the power supply voltage and a reference voltage; and a first comparator that compares an output of the compensation circuit with a comparison signal that changes over time, and outputs a PWM signal; an analog control loop including a second comparator that compares an analog signal corresponding to the error with a predetermined threshold, and outputs a PFM signal; and a mode switching circuit that is coupled to the digital control loop and the analog control loop, and that is configured to select between the PWM signal and the PFM signal by a mode switching signal, and that is configured to output as an output of the converter, wherein the PFM signal is selected by the mode switching signal when a voltage value of the power supply voltage that is generated based on the output of the converter reaches a predetermined value, and the power supply voltage is generated based on the PFM signal, and wherein the PWM signal is selected by the mode switching signal when the voltage value of the power supply voltage that is generated based on the output of the converter does not reach the predetermined value, and the power supply voltage is generated based on the PWM signal. wherein the control parameter stored in the non-volatile storage device is transferred to the compensation circuit when the supply voltage is generated based on the PFM signal, and wherein the PWM signal is selected by the mode switching circuit and the supply voltage is generated based on the PWM signal after the control parameter is transferred to the compensation circuit.

9. The control method according to claim 8, the converter further comprising a soft start control circuit that outputs a predetermined signal before the compensation circuit operates, wherein the voltage value of the supply voltage is raised to the predetermined value based on the predetermined signal from the soft start control circuit.

10. The control method according to claim 9, wherein the soft start control circuit starts operation in response to power-up.

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