Circuit arrangement and method of forming the same

Abstract

A circuit arrangement is provided, having a first circuit configured to receive an input signal and a second circuit configured to provide an output signal, wherein the first circuit includes: a first pull-up network having a first transistor of a first conductivity type and a second transistor of a second conductivity type electrically coupled to each other; and a first pull-down network having a first transistor of the first conductivity type and a second transistor of the second conductivity type electrically coupled to each other, wherein the second circuit includes: a second pull-up network having a first transistor of the first conductivity type; and a second pull-down network having a second transistor of the second conductivity type, wherein the first pull-up network and the second pull-down network are electrically coupled to each other, and wherein the first pull-down network and the second pull-up network are electrically coupled to each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to Singapore Patent Application No. 10201802217V filed on March 19, 2018, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] Various embodiments relate to circuit arrangements and methods for forming circuit arrangements. Background Art

[0004] In terrestrial, satellite and space (S&S) applications, the robustness of integrated circuits (ICs) is one of the most important design considerations. This is because ICs implemented in electronic systems for S&S applications are subject to a variety of possible radiation effects, which can compromise the functionality of the ICs and, in the worst case, cause permanent and irreparable damage to the ICs. Possible radiation effects include single event effects (SEEs), where errors are caused when an excited particle hits the IC. One of the SEEs is a single event transient (SET), where a single event (e.g., an excited particle) hits at a transistor node to generate a charge that generates a transient pulse on the transistor node. The transient pulse can be harmful to the IC. For example, in digital circuits, a transient pulse can cause a single event upset (SEU) by flipping the logic state in sequential logic, thereby causing an error. When using advanced nanoscale manufacturing processes (e.g., feature size <90nm) and / or in severe radiation environments, the incidence of SEEs in ICs is expected to be high. Therefore, it is highly desirable to mitigate SETs (and thus SEUs) to enhance the overall robustness of ICs for S&S applications.

[0005] Similarly, for terrestrial high-reliability (high-rel) applications such as automobiles (e.g., Level 5 autonomous vehicles), the same robustness considerations apply due to the presence of heavy particles (including alpha-containing particles in packaging materials) in the environment (released by residual radioactive elements), which can cause undesirable failures.

[0006] To mitigate SEE, radiation hardening of ICs can be achieved through dedicated IC manufacturing processes, design techniques, or a combination thereof. Dedicated IC manufacturing processes for such applications are exotic in the sense that they are not readily available and their cost is often prohibitively high. On the other hand, design techniques for radiation hardening, also known as RHBD (Radiation Hardened Design), are becoming increasingly popular because RHBD techniques can be incorporated into current state-of-the-art commercially available manufacturing processes.

[0007] First, the basic mechanism explaining how to create a SET is briefly described below.

[0008] Figure 1A A schematic diagram of an inverter 180a having a PMOS (p-type metal oxide semiconductor) transistor 182a and an NMOS (n-type metal oxide semiconductor) transistor 184a is shown, where the PMOS transistor 182a is turned off and the drain (D) of the PMOS transistor 182a is hit by a radiation particle 186a. Figure 1B A cross-sectional view of an inverter 180a is depicted, wherein a radiation particle 186a strikes the p+ region 188a (the drain (D) of PMOS 182a). During the strike, an electron-hole pair is induced, but the electron is quickly absorbed in the p+ region 188a, which is already full of holes, leaving the induced hole in the p+ region 188a. Therefore, as Figure 1C As shown in , the output Q will temporarily switch from logic '0' to logic '1', thereby generating a positive SET pulse 192a. After the induced holes are finally absorbed, the SET pulse 192a will gradually die out. The SET pulse 192a is typically very short, on the order of 100ps to 250ps. In addition, although the drains (D) of the NMOS transistor 182a and the PMOS transistor 184a (p+ region 188a and n+ region 190a) are connected together, it is logically insignificant if the radiation particle 186a only hits the turned-on NMOS transistor 184a, because only a very small negative pulse will be generated, which will enhance the logic state '0'.

[0009] Figure 1D Similarly depicted is a schematic diagram of an inverter 180d having a PMOS transistor 182d and an NMOS transistor 184d, wherein the NMOS transistor 184d is off and the drain (D) of the NMOS transistor 184d is struck by a radiation particle 186d. Figure 1E A cross-sectional view of an inverter 180d is depicted, where a radiation particle 186d hits the n+ region 190d (the drain (D) of NMOS 184d). During the hit, an electron-hole pair is induced, but the hole is quickly absorbed in the n+ region 190d, which is already full of electrons, leaving the induced electron in the n+ region 190d. Therefore, as Figure 1FAs shown in , the output Q will temporarily switch from logic '1' to logic '0', thereby generating a negative SET pulse 192d. After eventually absorbing the induced electrons, the SET pulse 192d will gradually die out. The SET pulse 192d is also typically short, about 100ps to 250ps. In addition, although the drains (D) of the NMOS transistor 182d and the PMOS transistor 184d (p+ region 188d and n+ region 190d) are connected together, it is logically insignificant if the radiation particle 186d only hits the turned-on PMOS transistor 182d, because only a very small positive pulse will be generated, which will enhance the logic state '1'.

[0010] It is well-known that digital circuits are susceptible to SEE in radiation environments unless the transistors therein are intentionally greatly oversized, for example, 5 to 100 times larger than the default size (under surface / ground conditions). However, transistor oversizing is not generally practiced because the transistors therein would be so large that they would cost too much area and power overhead and would therefore be impractical. Therefore, other RHBD practices span from the layout level to the circuit level to the architectural level. These RHBD techniques are briefly summarized below.

[0011] At the layout level, a simple approach is to increase the critical charge on the transistor node by adding more capacitive loads, such as by increasing the diffusion area or by increasing the capacitance. Other techniques include careful layout techniques, such as hole separation. However, these layout-level techniques are particularly ineffective in situations where radiation particles carry higher energy per unit distance (for example, in high radiation environments such as geosynchronous earth orbit (GEO) or South Atlantic Anomaly (SAA)). At the circuit level, common RHBD practices include pulse filtering techniques, increased RC (resistance-capacitance) delays at key nodes, feedback techniques, antenna unit insertion, etc. These circuit-level RHBD practices help mitigate SET / SEU at the expense of slower speed, higher power consumption, and larger area overhead. At the architecture level, common RHBD techniques include dual redundancy, triple module redundancy, and error detection and error correction techniques. As expected, these architecture-level RHBD techniques trade off speed / power / area for the robustness of SET / SEU.

[0012] The main reason why independent transistor size increases are ineffective is because stacked (series) transistor paths make their transistor sizes prohibitively large. As a non-limiting example, Figure 2AA standard (earth-based) inverter 280a is shown with PMOS transistor T1 and NMOS transistor T2 sized 2x and 1x, respectively. For S&S and hi-rel (high reliability) conditions, the size of the transistors may need to be increased, for example, by a factor of 5, for example, by a factor of 10 for PMOS transistor T1 and by a factor of 5 for NMOS transistor T2, as shown in FIG. Figure 2B As shown in Figure 2B 280b. Figure 2C As shown in , the RHBD size increases for the RHBD NOR gate 280c, where two stacked PMOS transistors T1, T2 are required. In order to achieve the same effective size as the baseline RHBD inverter, the size of each of the PMOS transistors T1, T2 must be ×20. For higher stacked transistors (e.g., ≥3 stacked transistors), the size of the transistor increases even more, and therefore, is too expensive in terms of area and power consumption. For multi-stage gates such as an OR gate (i.e., a NOR gate followed by an inverter), the reference Figure 2D , shows an increase in RHBD size for RHBD or gate 280d, and the associated transistor sizes are similarly large, where the total PMOS diffusion area corresponding to PMOS transistors T1, T2, T5 is 50 times (i.e., 20 times + 20 times + 10 times), and the total NMOS diffusion area corresponding to NMOS transistors T3, T4, T6 is 15 times (i.e., 5 times + 5 times + 5 times). Such large diffusion areas are generally undesirable because they partly cause high error rates when their cross-sections are large.

[0013] In view of the increasing size of transistors used in digital circuits and the limitations of other RHBD technologies, techniques are needed to mitigate SEE and reduce error rates. Summary of the invention

[0014] The invention is defined in the independent claim. Further embodiments of the invention are defined in the dependent claims.

[0015] According to a first aspect of the present invention, there is provided a circuit arrangement, comprising: a first circuit configured to receive one or more input signals provided to the circuit arrangement; a second circuit configured to provide one or more output signals of the circuit arrangement, wherein the first circuit comprises: a first pull-up network comprising at least one first transistor of a first conductivity type and a second transistor of a second conductivity type electrically coupled to each other; and a first pull-down network comprising a first transistor of the first conductivity type and at least one second transistor of the second conductivity type electrically coupled to each other, and wherein the second circuit comprises: a second pull-up network comprising a first transistor of the first conductivity type; and a second pull-down network comprising a second transistor of the second conductivity type, and wherein the first pull-up network and the second pull-down network are electrically coupled to each other, and wherein the first pull-down network and the second pull-up network are electrically coupled to each other, a pull-up network electrically coupled to the first pull-down network and the second pull-up network, the auxiliary pull-up network comprising at least one first auxiliary transistor of the first conductivity type; and an auxiliary pull-down network electrically coupled to the first pull-up network and the second pull-down network, the auxiliary pull-down network comprising at least one second auxiliary transistor of the second conductivity type, wherein, in response to an input signal among the one or more input signals received, the input signal having a first value, the first pull-up network is configured to conduct electricity to turn on the second pull-down network, thereby providing a first output signal, and the auxiliary pull-up network is configured to conduct electricity to disconnect the second pull-up network, and wherein, in response to the input signal having a second value, the first pull-down network is configured to conduct electricity to turn on the second pull-up network, thereby providing a second output signal, and the auxiliary pull-down network is configured to conduct electricity to disconnect the second pull-down network.

[0016] According to a second aspect of the present invention, there is provided a method for forming a circuit arrangement, comprising: electrically coupling a first pull-up network of a first circuit and a second pull-down network of a second circuit to each other, and electrically coupling the first pull-down network of the first circuit and the second pull-up network of the second circuit to each other, wherein the first circuit is configured to receive one or more input signals provided to the circuit arrangement, wherein the second circuit is configured to provide one or more output signals of the circuit arrangement, wherein the first pull-up network comprises at least one first transistor of a first conductivity type and a second transistor of a second conductivity type electrically coupled to each other, wherein the first pull-down network comprises a first transistor of the first conductivity type and at least one second transistor of the second conductivity type electrically coupled to each other, wherein the second pull-up network comprises a first transistor of the first conductivity type, and wherein the second pull-down network comprises a second transistor of the second conductivity type A transistor, electrically coupling an auxiliary pull-up network to the first pull-down network and the second pull-up network, the auxiliary pull-up network comprising at least one first auxiliary transistor of the first conductivity type, and electrically coupling an auxiliary pull-down network to the first pull-up network and the second pull-down network, the auxiliary pull-down network comprising at least one second auxiliary transistor of the second conductivity type, wherein, in response to an input signal among the one or more input signals received, the input signal has a first value, the first pull-up network is configured to conduct electricity to turn on the second pull-down network, thereby providing a first output signal, and the auxiliary pull-up network is configured to conduct electricity to disconnect the second pull-up network, and wherein, in response to the input signal having a second value, the first pull-down network is configured to conduct electricity to turn on the second pull-up network, thereby providing a second output signal, and the auxiliary pull-down network is configured to conduct electricity to disconnect the second pull-down network. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In the accompanying drawings, like reference numerals generally refer to like parts throughout the different views. The drawings are not necessarily drawn to scale, but emphasis is generally placed on illustrating the principles of the invention. In the following description, various embodiments of the invention are described with reference to the following drawings, in which:

[0018] Figure 1A Schematic diagram showing an inverter with the PMOS transistor turned off and hit by a radiation particle, Figure 1B shows the corresponding cross-sectional view of a PMOS transistor being hit, while Figure 1C The created positive SET is shown.

[0019] Figure 1D Schematic diagram showing an inverter with an NMOS transistor turned off and hit by a radiation particle, Figure 1E shows the corresponding cross-sectional view of the NMOS transistor being hit, while Figure 1F The negative SET created is shown.

[0020] FIG. 2A to FIG. 2B A schematic diagram of an inverter of the prior art is shown, Figure 2C FIG. 1 shows a schematic diagram of a prior art NOR gate, and FIG. Figure 2D A schematic diagram of an OR gate in the prior art is shown.

[0021] Figure 3A Schematic diagrams of circuit arrangements according to various embodiments are shown.

[0022] Figure 3B A flow chart illustrating a method for forming a circuit arrangement according to various embodiments is shown.

[0023] Figure 3C Schematic diagrams of circuit arrangements according to various embodiments are shown.

[0024] Figure 4A shows a schematic diagram of a circuit arrangement according to various embodiments, and Figure 4B and Figure 4C Schematic diagrams showing circuit arrangements when A='0' and when A='1' are shown respectively.

[0025] Figure 5 Schematic diagrams of circuit arrangements according to various embodiments are shown.

[0026] FIG. 6A to FIG. 6E Schematic diagrams of circuit arrangements according to various embodiments are shown.

[0027] 7A to 7C Schematic diagrams showing a pull-up network and an auxiliary pull-up network of a first stage circuit of a circuit arrangement according to various embodiments are shown.

[0028] 7D to 7F show schematic diagrams of a pull-down network and an auxiliary pull-down network of a first stage circuit of a circuit arrangement according to various embodiments.

[0029] Figure 8 Schematic diagrams of circuit arrangements according to various embodiments are shown. DETAILED DESCRIPTION

[0030] The following specific embodiments refer to the accompanying drawings, which illustrate the specific details and embodiments of the present invention by way of illustration. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized, and structural, logical and electrical changes may be made without departing from the scope of the present invention. The various embodiments do not necessarily exclude each other, as some embodiments may be combined with one or more other embodiments to form new embodiments.

[0031] Embodiments described in the context of one of the method or the device are analogously valid for the other method or the device. Similarly, embodiments described in the context of the method are analogously valid for the device, and vice versa.

[0032] Features described in the context of an embodiment may be correspondingly applicable to the same or similar features in other embodiments. Features described in the context of an embodiment may be correspondingly applicable to these other embodiments even if not explicitly described in other embodiments. In addition, additions and / or combinations and / or substitutions described for features in the context of an embodiment may be correspondingly applicable to the same or similar features in other embodiments.

[0033] In the context of the various embodiments, the term "about" as applied to numerical values ​​encompasses the exact value and a reasonable variance.

[0034] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0035] As used herein, a phrase in the form “at least one of A or B” may include A or B or both A and B. Correspondingly, a phrase in the form “at least one of A or B or C” or including other listed items may include any and all combinations of one or more of the associated listed items.

[0036] Various embodiments may provide circuit arrangements (eg, digital gates) with ultra-low error rates.

[0037] Various embodiments may relate to transistor insertion and connection techniques for implementing one or more 2-level circuit arrangements (or 2-level digital gates).

[0038] For example, for S&S applications and high reliability applications, various embodiments may involve radiation hardened design (RHBD) techniques to mitigate SEE in digital (logic) gates.

[0039] Various embodiments may provide a transistor insertion and connection technique to virtually eliminate any SET. For example, various embodiments may provide a transistor insertion and connection technique for digital circuits, where the diffusion area causing SEE may be very limited, thus reducing the error rate. This technique may address the limitations of known transistor size increases and other RHBD techniques for digital circuits.

[0040] Various embodiments may involve a transistor insertion and connection technique to achieve a 2-stage digital gate (i.e., having a first stage and a second stage) that is radiation hardened to reduce soft errors (including errors caused by single event transients (SET)). A split logic with multiple stages of circuits may be provided. The technique may include inserting an NMOS transistor into a pull-up network in the first stage to drive a connected pull-down network in the second stage, and inserting a PMOS transistor into a pull-down network in the first stage to drive a connected pull-up network in the second stage. An auxiliary pull-up network in the first stage may be further introduced to drive the pull-up network in the second stage, and / or an auxiliary pull-down network in the first stage may be further introduced to drive the pull-down network in the second stage. The transistor insertion and connection technique may make the first stage circuit virtually SET-free, thereby reducing the associated (soft) error rate. Based on a basic gate design (including a buffer and an OR gate), the error rate of a gate design according to the techniques disclosed herein may be as low as 1 / 2 to 1 / 74 compared to a design with a known radiation hardened design (RHBD) size increase technique. When compared to non-RHBD designs, gate designs according to the techniques disclosed herein can have error rates as low as 1 / 7 to 1 / 215.

[0041] Various embodiments may be directed to a transistor insertion and connection technique for implementing a 2-stage digital gate, wherein the first stage circuit may be substantially SET-tolerant. A circuit arrangement (e.g., a digital gate) may be provided, comprising a first stage circuit driven by at least one primary input, and a second stage circuit producing a primary output. The first stage circuit may include or embody at least one pull-up network, at least one auxiliary pull-up network, at least one pull-down network, and at least one auxiliary pull-down network, and the second stage circuit may include or embody at least one pull-up network and at least one pull-down network. At least one pull-up network of the first stage circuit may be connected to at least one auxiliary pull-down network of the first stage circuit, at least one pull-down network of the first stage circuit may be connected to at least one auxiliary pull-up network of the first stage circuit, and at least one pull-up network of the second stage circuit may be connected to at least one pull-down network of the second stage circuit. The pull-up network of the first stage circuit may include at least one PMOS transistor and at least one NMOS transistor. The pull-down network of the first stage circuit may include at least one NMOS transistor and at least one PMOS transistor. The auxiliary pull-up network of the first stage circuit may include at least one PMOS transistor. The auxiliary pull-down network of the first stage circuit may include at least one NMOS transistor. The pull-up network of the second stage circuit may include at least one PMOS transistor. The pull-down network of the second stage circuit may include at least one NMOS transistor. At least one NMOS transistor of the pull-up network of the first stage circuit may be connected to at least one PMOS transistor of the pull-up network of the first stage circuit, so that the former can enable the pull-down network of the second stage circuit, otherwise, the auxiliary pull-down network of the first stage circuit can disable the pull-down network of the second stage circuit. At least one PMOS transistor of the pull-down network of the first stage circuit may be connected to at least one NMOS transistor of the pull-down network of the first stage circuit, so that the former can enable the pull-up network of the second stage circuit, otherwise, the auxiliary pull-up network of the first stage circuit can disable the pull-up network of the second stage circuit. When the pull-up network of the first stage circuit is 'on' and the auxiliary pull-down network of the first stage circuit is 'off', their connected NMOS transistors for enabling the pull-down network of the second stage may be induced by a negative SET pulse to temporarily turn off the pull-down network of the second stage, but may not affect the primary output. When the pull-down network of the first stage circuit is 'off' and the auxiliary pull-up network of the first stage circuit is 'on', their connected PMOS transistors for disabling the pull-up network of the second stage circuit can be induced by a positive SET pulse to keep disabling the pull-up network of the second stage circuit. When the pull-down network of the first stage circuit is 'on' and the auxiliary pull-up network of the first stage circuit is 'off', their connected PMOS transistors for enabling the pull-up network of the second stage can be induced by a positive SET pulse to temporarily turn off the pull-up network of the second stage, but may not affect the primary output.When the pull-up network of the first stage circuit is 'off' and the auxiliary pull-down network of the first stage circuit is 'on', their connected NMOS transistors for disabling the pull-down network of the second stage circuit can be induced by a negative SET pulse to keep disabling the pull-down network of the second stage circuit.

[0042] Various embodiments may provide a circuit arrangement including a first stage circuit having a pull-up network having an NMOS transistor, an auxiliary pull-up network coupled to the pull-up network, a pull-down network having a PMOS transistor, and an auxiliary pull-down network coupled to the pull-down network, and a second stage circuit having a pull-up network, and a pull-down network coupled to the pull-up network, wherein the NMOS transistor may be coupled to the auxiliary pull-down network of the first stage circuit and the pull-down network of the second stage circuit, and wherein the PMOS transistor may be coupled to the auxiliary pull-down network of the first stage circuit and the pull-up network of the second stage circuit. The circuit arrangement may include or may be a digital gate.

[0043] Various embodiments may further provide a method for designing a radiation hardened circuit arrangement, the method comprising: providing a first stage circuit having: a pull-up network having an NMOS transistor, an auxiliary pull-up network coupled to the pull-up network, a pull-down network having a PMOS transistor, and an auxiliary pull-down network coupled to the pull-down network; providing a second stage circuit having: a pull-up network, and a pull-down network coupled to the pull-up network; coupling the NMOS transistor to the auxiliary pull-down network of the first stage circuit and the pull-down network of the second stage circuit; and coupling the PMOS transistor to the auxiliary pull-up network of the first stage circuit and the pull-up network of the second stage circuit. The circuit arrangement may include or may be a digital gate.

[0044] Due to the inherent circuit configuration, various embodiments can actually eliminate any SET pulses in the first stage circuit. In other words, compared with the known techniques, the techniques disclosed herein can provide better SET hardening with low circuit overhead.

[0045] Various embodiments may provide one or more of the following compared to known approaches: (i) low cross-section (low area region) susceptible to SEE (generated due to particle hits), (ii) mitigation of SEE in digital circuits, thereby reducing associated error rates, (iii) enabling high linear energy transfer (LET) thresholds for digital circuits. In view of the above, the techniques disclosed herein may provide robust operation to mitigate SET / SEU.

[0046] Figure 3ASchematic diagram of a circuit arrangement 300 according to various embodiments is shown. The circuit arrangement 300 includes a first circuit 302 configured to receive one or more input signals (exemplarily showing an input signal D) provided to the circuit arrangement 300, and a second circuit 304 configured to provide one or more output signals (exemplarily showing an output signal Q) of the circuit arrangement 300, wherein the first circuit 302 includes a first pull-up network 306 and a first pull-down network 310, the first pull-up network having at least one first transistor 320 of a first conductivity type and a second transistor 322 of a second conductivity type electrically coupled to each other (as represented by line 343), and the first pull-down network having at least one first transistor 320 of a first conductivity type and a second transistor 322 of a second conductivity type electrically coupled to each other (as represented by line 343). A first transistor 326 of a first conductivity type and at least one second transistor 328 of a second conductivity type are electrically coupled (as represented by line 344), and wherein the second circuit 304 includes a second pull-up network 314 and a second pull-down network 316, the second pull-up network having a first transistor 340 of the first conductivity type, the second pull-down network having a second transistor 342 of the second conductivity type, and wherein the first pull-up network 306 and the second pull-down network 316 are electrically coupled to each other (as represented by line 346), and wherein the first pull-down network 310 and the second pull-up network 314 are electrically coupled to each other (as represented by dotted line 347).

[0047] In other words, a circuit arrangement 300 may be provided having a plurality of circuits 302, 304, a plurality of pull-up networks 306, 314, a plurality of pull-down networks 310, 316, and a plurality of transistors 320, 322, 326, 328, 340, 342. In various embodiments, the first circuit 302 of the circuit arrangement 300 may be arranged such that one or more input signals D may be provided to the first circuit 302. The first pull-up network 306 and the first pull-down network 310 may be connected to an input node of the circuit arrangement 300. As a non-limiting example, the first pull-up network 306 and the first pull-down network 310 may receive one or more input signals D. For example, at least one first transistor 320 and at least one second transistor D transistor 328 may receive one or more input signals D. The one or more input signals D may be received via the gate (G) terminals of the corresponding transistors 320, 328. It should be understood that each of the first pull-up network 306 and the first pull-down network 310 may receive a respective different input signal.

[0048] The second circuit 304 of the circuit arrangement 300 may be arranged such that one or more output signals Q may be provided or output from the second pull-up network 314 and the second pull-down network 316. The second pull-up network 314 and the second pull-down network 316 may be connected to an output node of the circuit arrangement 300. The one or more output signals Q may be provided via drain (D) terminals of corresponding transistors 340, 342.

[0049] The first circuit 302 may include a first pull-up network 306 and a first pull-down network 310, wherein the first pull-up network has one or more first transistors 320 of a first conductivity type and one or more second transistors 322 of a second conductivity type electrically coupled (or connected) to each other, and the first pull-down network has a first transistor 326 of the first conductivity type and one or more second transistors 328 of the second conductivity type electrically coupled (or connected) to each other.

[0050] The second circuit 304 may include a second pull-up network 314 having a first transistor 340 of a first conductivity type and a second pull-down network 316 having a second transistor 342 of a second conductivity type. The second pull-up network 314 and the second pull-down network 316 may be electrically coupled or connected to each other. The first transistor 340 and the second transistor 342 may be connected or electrically coupled to each other. The first transistor 340 and the second transistor 342 may define an inverter.

[0051] In various embodiments, the first circuit 302 and the second circuit 304 can be arranged so that the first pull-up network 306 and the second pull-down network 316 can be electrically coupled (or connected) to each other, and the first pull-down network 310 and the second pull-up network 314 can be electrically coupled (or connected) to each other. The second transistor 322 of the first pull-up network 306 and the second transistor 342 of the second pull-down network 316 can be connected or electrically coupled to each other. The first transistor 326 of the first pull-down network 310 and the first transistor 340 of the second pull-up network 314 can be connected or electrically coupled to each other.

[0052] The first pull-up network 306 can be connected to a power source (eg, V DD At least one first transistor 320 and a second transistor 322 may be connected to a power source (eg, V DD ).

[0053] The first pull-down network 310 may be connected to ground (eg, GND). The first transistor 326 and the at least one second transistor 328 may be connected to ground (eg, GND).

[0054] The second pull-up network 314 can be connected to a power source (eg, V DD The first transistor 340 may be connected to a power source (eg, V DD ).

[0055] The second pull-down network 316 may be connected to ground (eg, GND). The second transistor 342 may be connected to ground (eg, GND).

[0056] The circuit arrangement 300 may be a 2-level circuit arrangement, where the first circuit 302 defines a first level circuit and the second circuit 304 defines a second level circuit.

[0057] In the context of various embodiments, first circuit 302 may be SET fault tolerant due at least in part to incorporating second transistor 322 of the second conductivity type in first pull-up network 306 and first transistor 326 of the first conductivity type in first pull-down network 310 .

[0058] In the context of various embodiments, a "pull-up network" may mean a network or circuit that can pull a voltage up to a larger positive value. For example, the pull-up network can provide a voltage to a power source (e.g., V DD ) provides a low resistance path and in a second operation provides a high resistance to the power supply.

[0059] In the context of various embodiments, a "pull-down network" may mean a network or circuit that can pull a voltage down to a smaller positive value (or a larger negative value). For example, the pull-down network can provide a low resistance path to ground (e.g., GND) in a first operation and provide a high resistance to ground in a second operation.

[0060] In the context of various embodiments, the first conductivity type and the second conductivity type may be opposite conductivity types or opposite polarities. The first conductivity type may be p-type conductivity, and the transistor of the first conductivity type may be a P-type FET (field effect transistor) (e.g., a PMOS transistor (i.e., a p-channel MOSFET) or a P-type FinFET (i.e., a Fin FET)), while the second conductivity type may be n-type conductivity, and the transistor of the second conductivity type may be an N-type FET (e.g., an NMOS transistor (i.e., an n-channel MOSFET), an N-type FinFET).

[0061] In various embodiments, the source (S) terminal of the second transistor 322 of the first pull-up network 306 may be connected to the drain (D) terminal of the at least one first transistor 320 of the first pull-up network 306, the drain (D) terminal of the second transistor 322 of the first pull-up network 306 may be connected to the gate (G) terminal of the second transistor 342 of the second pull-down network 316, the drain (D) terminal of the first transistor 326 of the first pull-down network 310 may be connected to the gate (G) terminal of the first transistor 340 of the second pull-up network 314, and the source (S) terminal of the first transistor 326 of the first pull-down network 310 may be connected to the drain (D) terminal of the at least one second transistor 328 of the first pull-down network 310. The gate (G) terminal of the second transistor 322 of the first pull-up network 306 may be connected to a power source (e.g., V DD A gate (G) terminal of the first transistor 326 of the first pull-down network 310 may be grounded (eg, GND).

[0062] It should be understood that the source (S) terminal and the drain (D) terminal of a transistor (eg, a field effect transistor (FET)) are interchangeable, and the output of a transistor is typically the drain (D) terminal of the transistor.

[0063] In the first operation mode, in response to a received first input signal (e.g., 0), the first pull-up network 306 can be configured to be conductive to turn on (or enable) the second pull-down network 316 to provide a first output signal (e.g., 0), and in the second operation mode, in response to a received second input signal (e.g., 1), the first pull-down network 310 can be configured to be conductive to turn on (or enable) the second pull-up network 314 to provide a second output signal (e.g., 1). In response to the first input signal received in the first operation mode, the first pull-down network 310 can be configured to be non-conductive. In response to the second input signal received in the second operation mode, the first pull-up network 306 can be configured to be non-conductive.

[0064] In various embodiments, the circuit arrangement 300 may further include: an auxiliary pull-up network electrically coupled (or connected) to the first pull-down network 310 and the second pull-up network 314, the auxiliary pull-up network having at least one first auxiliary transistor of the first conductivity type; and an auxiliary pull-down network electrically coupled (or connected) to the first pull-up network 306 and the second pull-down network 316, the auxiliary pull-down network having at least one second auxiliary transistor of the second conductivity type. The auxiliary pull-up network may be further electrically coupled (or connected) to the first pull-up network 306. The auxiliary pull-up network may be further electrically coupled (or connected) to the first pull-down network 310.

[0065] The drain (D) terminal of the at least one first auxiliary transistor may be connected to the drain (D) terminal of the first transistor 326 of the first pull-down network 310 and to the gate (G) terminal of the first transistor 340 of the second pull-up network 314, and the drain (D) terminal of the at least one second auxiliary transistor may be connected to the drain (D) terminal of the second transistor 322 of the first pull-up network 306 and to the gate (G) terminal of the second transistor 342 of the second pull-down network 316. The source (S) terminal of the at least one first auxiliary transistor may be connected to a power source (e.g., V DD ). The at least one first auxiliary transistor may receive one or more input signals D via its gate terminal. The source (S) terminal of the at least one second auxiliary transistor may be grounded (e.g., GND). The at least one second auxiliary transistor may receive one or more input signals D via its gate terminal.

[0066] In the first operation mode, in response to a received first input signal (e.g., 0), the first pull-up network 306 may be configured to be conductive to turn on (or enable) the second pull-down network 316 to provide a first output signal (e.g., 0), and the auxiliary pull-up network may be configured to be conductive to turn off (or disable) the second pull-up network 314, and in the second operation mode, in response to a received second input signal (e.g., 1), the first pull-down network 310 may be configured to be conductive to turn on (or enable) the second pull-up network 314 to provide a second output signal (e.g., 1), and the auxiliary pull-down network may be configured to be conductive to turn off (or disable) the second pull-down network 316. In response to the first input signal received in the first operation mode, the first pull-down network 310 and the auxiliary pull-down network may be configured to be non-conductive. In response to the second input signal received in the second operation mode, the first pull-up network 306 and the auxiliary pull-up network may be configured to be non-conductive.

[0067] In various embodiments, at least one first transistor 320 of the first pull-up network 306 may include a plurality of first transistors of a first conductivity type, the plurality of first transistors being electrically coupled to each other and to the second transistor of the first pull-up network 306, and the plurality of first transistors may be arranged in at least one of a stacked connection or a parallel connection. This may mean that the plurality of first transistors may be stacked (or series) transistors, or may be connected in parallel to each other, or may be a combination of stacked connections and parallel connections. The plurality of first transistors may receive one or more input signals D. Different transistors in the plurality of first transistors may receive different input signals.

[0068] In the context of various embodiments, a stacked transistor (ie, a transistor that is part of a stacked connection) means a transistor that is connected in series with another transistor of the same conductivity type to drive an output.

[0069] In various embodiments, at least one second transistor 328 of the first pull-down network 310 may include a plurality of second transistors of a second conductivity type, the plurality of second transistors being electrically coupled to each other and to the first transistor 326 of the first pull-down network 310, and the plurality of second transistors may be arranged in at least one of a stacked connection or a parallel connection. This may mean that the plurality of second transistors may be stacked (or series) transistors, or may be connected in parallel to each other, or may be a combination of stacked connections and parallel connections. The plurality of second transistors may receive one or more input signals D. Different transistors in the plurality of second transistors may receive different input signals.

[0070] In various embodiments, at least one first auxiliary transistor may include a plurality of first auxiliary transistors of a first conductivity type, the plurality of first auxiliary transistors being electrically coupled to each other and to the first transistor 326 of the first pull-down network 310, and the plurality of first auxiliary transistors may be arranged in at least one of a stacked connection or a parallel connection. This may mean that the plurality of first auxiliary transistors may be stacked (or series) transistors, or may be connected in parallel to each other, or may be a combination of stacked connections and parallel connections. The plurality of first auxiliary stacked transistors may receive one or more input signals D. Different transistors in the plurality of first auxiliary stacked transistors may receive different input signals.

[0071] In various embodiments, at least one second auxiliary transistor may include a plurality of second auxiliary transistors of a second conductivity type, the plurality of second auxiliary transistors being electrically coupled to each other and to the second transistor 322 of the first pull-up network 306, and the plurality of second auxiliary transistors may be arranged in at least one of a stacked connection or a parallel connection. This may mean that the plurality of second auxiliary transistors may be stacked (or series) transistors, or may be connected in parallel to each other, or may be a combination of stacked connections and parallel connections. The plurality of second auxiliary transistors may receive one or more input signals D. Different transistors in the plurality of second auxiliary transistors may receive different input signals.

[0072] In various embodiments, the source (S) terminal of at least one first auxiliary transistor of the auxiliary pull-up network may be connected to the source (S) terminal of one of the plurality of first transistors of the first pull-up network 306. This may mean that the source (S) terminal of at least one first auxiliary transistor may be connected to the source (S) terminal of any one of the plurality of first transistors.

[0073] In various embodiments, the source (S) terminal of at least one second auxiliary transistor of the auxiliary pull-down network may be connected to the source (S) terminal of one of the plurality of second transistors of the first pull-down network 310. This may mean that the source (S) terminal of at least one second auxiliary transistor may be connected to the source (S) terminal of any one of the plurality of second transistors.

[0074] In various embodiments, the source (S) terminal of at least one first auxiliary transistor of the auxiliary pull-up network can be connected to the source (S) terminal of the second transistor 322 of the first pull-up network 306, and the gate (G) terminal of at least one first auxiliary transistor of the auxiliary pull-up network can be connected to the drain (D) terminal of the first transistor 340 of the second pull-up network 314 and to the drain (D) terminal of the second transistor 342 of the second pull-down network 316.

[0075] In various embodiments, the source (S) terminal of at least one second auxiliary transistor of the auxiliary pull-down network can be connected to the source (S) terminal of the first transistor 326 of the first pull-down network 310, and the gate (G) terminal of at least one second auxiliary transistor of the auxiliary pull-down network can be connected to the drain (D) terminal of the first transistor 340 of the second pull-up network 314, and to the drain (D) terminal of the second transistor 342 of the second pull-down network 316.

[0076] In various embodiments, for the first transistor 326 of the first pull-down network 310, the first transistor 326 may be adapted to be body biased by a first bias signal applied to the first transistor 326 to control a threshold voltage of the first transistor 326, and for the second transistor 322 of the first pull-up network 306, the second transistor 322 may be adapted to be body biased by a second bias signal applied to the second transistor 322 to control a threshold voltage of the second transistor 322. Each of the second transistor 322 and the first transistor 326 may include a fully depleted silicon-on-insulator (FDSOI) transistor.

[0077] In various embodiments, the first circuit 302 may include a plurality of cascaded (series) subcircuits electrically coupled to each other, wherein each of the plurality of cascaded subcircuits may include a pull-up network having at least one first transistor of a first conductivity type and a second transistor of a second conductivity type electrically coupled (or connected) to each other, and a pull-down network having a first transistor of a first conductivity type and at least one second transistor of a second conductivity type electrically coupled (or connected) to each other, and wherein for a last cascaded subcircuit in the plurality of cascaded subcircuits, the pull-up network may be defined by a first pull-up network 306, and the pull-down network may be defined by a first pull-down network 310. Here, the last cascaded subcircuit may refer to a cascaded subcircuit that may be arranged farthest from a first cascaded subcircuit in the plurality of cascaded subcircuits that may receive one or more input signals D. The operation of the last cascaded subcircuit may be based at least in part on an output signal provided by one or more preceding cascaded subcircuits.

[0078] For each cascade sub-circuit, the cascade sub-circuit may also include: an auxiliary pull-up network electrically coupled to the pull-down network, the auxiliary pull-up network having at least one first auxiliary transistor of a first conductivity type; and an auxiliary pull-down network electrically coupled to the pull-up network, the auxiliary pull-down network having at least one second auxiliary transistor of a second conductivity type.

[0079] For the last cascaded sub-circuit, the auxiliary pull-up network may be further electrically coupled to the second pull-up network 314 , and the auxiliary pull-down network may be further electrically coupled to the second pull-up network 316 .

[0080] In more detail, the first circuit 302 may include a plurality of cascaded (series) subcircuits electrically coupled to each other, wherein the plurality of cascaded subcircuits may include a first cascaded subcircuit and a last cascaded subcircuit, wherein the first cascaded subcircuit may include a first pull-up network having at least one first transistor of a first conductivity type and a second transistor of a second conductivity type electrically coupled (or connected) to each other, and a first pull-down network having a first transistor of a first conductivity type and at least one second transistor of a second conductivity type electrically coupled (or connected) to each other, and wherein the last cascaded subcircuit may include a last pull-up network defined by the first pull-up network 306 and a last pull-down network defined by the first pull-down network 310. The operation of the last cascaded subcircuit may be based at least in part on an output signal provided by the first cascaded subcircuit.

[0081] The starting cascade subcircuit may also include: a starting auxiliary pull-up network electrically coupled (or connected) to the starting pull-down network, the starting auxiliary pull-up network having at least one first auxiliary transistor of a first conductivity type; and a starting auxiliary pull-down network electrically coupled (or connected) to the starting pull-up network, the starting auxiliary pull-down network having at least one second auxiliary transistor of a second conductivity type.

[0082] The last cascade sub-circuit may also include: a last auxiliary pull-up network electrically coupled (or connected) to the last pull-down network and the second pull-up network 314, the last auxiliary pull-up network having at least one first auxiliary transistor of the first conductivity type; and a last auxiliary pull-down network electrically coupled (or connected) to the last pull-up network and the second pull-down network 316, the last auxiliary pull-down network having at least one second auxiliary transistor of the second conductivity type.

[0083] The plurality of cascade subcircuits may further include at least one intermediate cascade subcircuit, the at least one intermediate cascade subcircuit being arranged in an electrical path between the first cascade subcircuit and the last cascade subcircuit, wherein for each of the at least one intermediate cascade subcircuit, the intermediate cascade subcircuit may include: an intermediate first pull-up network having at least one first transistor of a first conductivity type and a second transistor of a second conductivity type electrically coupled (or connected) to each other; and an intermediate pull-down network having a first transistor of a first conductivity type and at least one second transistor of a second conductivity type electrically coupled (or connected) to each other. The intermediate cascade subcircuit may further include: an intermediate auxiliary pull-up network electrically coupled (or connected) to the intermediate pull-down network, the intermediate auxiliary pull-up network having at least one first auxiliary transistor of a first conductivity type; and an intermediate auxiliary pull-down network electrically coupled (or connected) to the intermediate pull-up network, the intermediate auxiliary pull-down network having at least one second auxiliary transistor of a second conductivity type.

[0084] In various embodiments, for each of the first transistor 340 of the second pull-up network 314 and the second transistor 342 of the second pull-down network 316, the transistors 340, 342 can be configured to drive a load associated with the transistors 340, 342, and the size of the aspect ratio of the first transistor 340 of the second pull-up network 314 or the second transistor 342 of the second pull-down network 316 can be larger than the size of the aspect ratio of the transistor that can be optimized for driving the load. For example, each transistor 340, 342 can drive a load associated with the transistors 340, 342, and the size of the aspect ratio of at least one of the transistors 340, 342 can be larger than (enlarged) the size of the aspect ratio of the transistor optimized for driving the load ("optimized transistor"). In various embodiments, the transistor can be optimized in at least one of speed, area or power consumption, which means that the size of the optimized transistor can be kept as small as possible while satisfying at least one of the speed, power or area constraints. This can mean that at least one of the transistors 340, 342 can be a transistor with an increased size (see the following description) compared to a transistor with a standard aspect ratio. Here "increased size" means that the aspect ratio of the transistor is even larger than that of a standard transistor. The value of the aspect ratio to be designed may depend on the linear energy transfer (LET) threshold of the corresponding circuit arrangement.

[0085] In the context of various embodiments, a load that may be driven by a transistor may include a total capacitive load, including internal capacitance contributed by the drain of the transistor and, if any, external capacitance contributed by the gate or drain of the transistor or circuit or by wires connected thereto.

[0086] In the context of various embodiments, the term "aspect ratio" applied to transistors means the ratio of the width W of the transistor to the length L of the transistor, that is, aspect ratio = W / L. The aspect ratio of a transistor, the width W of the transistor, and the length L of the transistor are terms familiar to technicians. The length L refers to the length of the gate of the transistor, and the width W refers to the width of the drain and / or source of the transistor. The length L is typically fixed by the manufacturing technology used, such as a 65 nanometer manufacturing process. For example, the width W can be controlled to match the length L so that the resulting aspect ratio (i.e., W / L) is 1, or the width W is greater than the length L so that the resulting aspect ratio is greater than 1. Typically (but not fixed for various manufacturing processes), the minimum width of W (referred to as W min ) is approximately twice L. In addition, the current level of the transistor is usually related to or determined by the width W, where the current I DαW / L. Thus, by providing a larger width W, where W>>Wmin, such that the corresponding aspect ratio is>>1, the current level of the transistor is increased, allowing for a stronger drive current. Under earth conditions, for circuits (e.g., digital circuits), for standard transistors, the width W is preferably sized W min , or slightly larger values, as long as the overall circuit just meets the speed, area, or power consumption specifications. For S&S conditions, the width W can be increased beyond the size of a standard transistor to mitigate the effects of SEE.

[0087] In the context of various embodiments, for transistors of increased size, the corresponding aspect ratio may be greater than 2, e.g., ≥2.5, ≥3, ≥5, ≥6, ≥8, ≥10, ≥20, ≥50, or ≥100, or between about 2.1 and about 100, between about 2.1 and about 50, between about 2.1 and about 20, between about 2.1 and about 10, between about 2.5 and about 100, between about 2.5 and about 50, between about 2.5 and about 20, between about 2.5 and about 10, or between about 5 and about 20. As a non-limiting example, the aspect ratio may be at least 2.5.

[0088] In the context of various embodiments, the circuit arrangement 300 may be or may include a digital gate, such as a buffer gate, an OR gate, an AND gate, or the like.

[0089] Figure 3B A flowchart 350 illustrating a method for forming a circuit arrangement according to various embodiments is shown.

[0090] At 352, a first pull-up network of the first circuit and a second pull-down network of the second circuit are electrically coupled to each other. At 354, the first pull-down network of the first circuit and the second pull-up network of the second circuit are electrically coupled to each other. The first circuit is configured to receive one or more input signals (e.g., D) provided to the circuit arrangement, and the second circuit is configured to provide one or more output signals (e.g., Q) of the circuit arrangement. The first pull-up network includes at least one first transistor of a first conductivity type and a second transistor of a second conductivity type electrically coupled to each other, the first pull-down network includes a first transistor of the first conductivity type and at least one second transistor of the second conductivity type electrically coupled to each other, the second pull-up network includes a first transistor of the first conductivity type, and the second pull-down network includes a second transistor of the second conductivity type.

[0091] The method may also include electrically coupling an auxiliary pull-up network to the first pull-down network and the second pull-up network, the auxiliary pull-up network having at least one first auxiliary transistor of a first conductivity type; and electrically coupling an auxiliary pull-down network to the first pull-up network and the second pull-down network, the auxiliary pull-down network having at least one second auxiliary transistor of a second conductivity type.

[0092] It should be understood that the description in the context of the circuit arrangement 300 may correspondingly apply to the method for forming the circuit arrangement described in the context of the flowchart 350 .

[0093] Figure 3C A schematic diagram of a circuit arrangement 300c for mitigating the effects of at least one transient voltage pulse generated in the circuit arrangement 300c according to various embodiments is shown. The circuit arrangement 300c includes a first circuit 302c and a second circuit 304c, wherein the first circuit 302c includes a pull-up network 306c and a pull-down network 310c, the pull-up network having a first pair of transistors 320c, 322c of opposite conductivity types electrically coupled to each other (as represented by line 343c), and the pull-down network having a second pair of transistors 326c, 328c of opposite conductivity types electrically coupled to each other (as represented by line 344c), wherein the pull-up network 306c and the pull-down network 310c are configured to receive one or more input signals (one input signal D is exemplarily shown), and are further configured to control the second circuit 304c to provide one or more output signals (one output signal Q is exemplarily shown) in response to the received one or more input signals D. Although in Figure 3C The circuit arrangement 300c is shown in FIG. 3 such that the pull-up network 306c and the pull-down network 310c receive the same input signal D, but it should be understood that each of the pull-up network 306c and the pull-down network 310c may receive a respective different input signal.

[0094] The pull-up network 306c may be configured to set a first potential level at the second circuit 304c. The pull-down network 310c may be configured to set a second potential level at the second circuit 304c.

[0095] In various embodiments, at least one transient voltage pulse may be generated in the first circuit 302c (e.g., due to an excited particle hitting the first circuit 302c), wherein the first pair of transistors 320c, 322c and the second pair of transistors 326c, 328c may mitigate the effect of the at least one transient voltage pulse on one or more output signals Q.

[0096] It should be appreciated that the circuit arrangement 300c including its various components and connections may be as described in the context of the circuit arrangement 300. Furthermore, it should be appreciated that the circuit arrangement 300c may include additional components similar to those described in the context of the circuit arrangement 300.

[0097] Various embodiments may further provide a method for forming a circuit arrangement 300c.

[0098] Figure 4AA schematic diagram of a circuit arrangement 400 according to various embodiments is shown. The circuit arrangement 400 may be a (digital) buffer gate. The circuit arrangement 400 may receive a primary input signal A, for example via an input node 471, and provide a primary output signal Q, for example via an output node 472. The circuit arrangement 400 may be a 2-stage circuit arrangement (e.g., a 2-stage digital gate) having a first stage circuit 402 and a second stage circuit 404 connected or electrically coupled to each other. The first stage circuit 402 may be SET tolerant in nature, protected by techniques to be further described below, while the second stage circuit 404 is a driver that may be protected by RHBD practices such as transistor size increase and / or layout techniques.

[0099] The first stage circuit 402 may have a shunt transistor configuration having a pull-up network 406, an auxiliary pull-up network 408, a pull-down network 410, and an auxiliary pull-down network 412. The pull-up network 406 may include a PMOS transistor T1 and an NMOS transistor T3. The pull-down network 410 may include a PMOS transistor T6 and an NMOS transistor T4. The reason why the first stage circuit 402 may be SET tolerant is due to the insertion of an NMOS transistor T3 in the pull-up network 406 and the insertion of a PMOS transistor T6 in the pull-down network 410. The insertion of the two transistors T3, T6 in the first stage circuit 402 may actually eliminate any SET that may otherwise erroneously trigger the second stage circuit 404. Therefore, the two transistors T3, T6 are inserted in the shunt transistor configuration. The PMOS transistor T2 is defined or included in the auxiliary pull-up network 408, and the NMOS transistor T5 is defined or included in the auxiliary pull-up network 412. The transistors T2, T5 are used to maintain voltage levels for proper logic operation and still SET tolerant.

[0100] The second stage circuit 404 may include a pull-up network 414 and a pull-down network 416 connected or electrically coupled to each other. The pull-up network 414 may include a PMOS transistor T7, and the pull-down network 416 may include an NMOS transistor T8. The PMOS transistor T7 and the NMOS transistor T8 may together define an inverter.

[0101] Pull-up network 406 and auxiliary pull-up network 408 may be connected or electrically coupled to each other. Pull-up network 406, auxiliary pull-up network 408, and pull-down network 416 may be electrically coupled to each other. Pull-down network 410 and auxiliary pull-down network 412 may be connected or electrically coupled to each other. Pull-down network 410, auxiliary pull-down network 412, and pull-up network 414 may be electrically coupled to each other.

[0102] In more detail, the gate (G) terminals of the transistors T1, T2, T4, T5 may receive the input signal A. For example, these gate (G) terminals of the transistors T1, T2, T4, T5 may be connected to or at the input node 471. The source (S) terminals of the PMOS transistors T1, T2 and the gate (G) terminal of the NMOS transistor T3 may be connected to a power supply (e.g., V DD ). The drain (D) terminal of the PMOS transistor T1 and the source (S) terminal of the NMOS transistor T3 may be connected to each other. The source (S) terminals of the NMOS transistors T4 and T5 and the gate (G) terminal of the PMOS transistor T6 may be grounded (e.g., GND). The drain (D) terminal of the NMOS transistor T4 and the source (S) terminal of the PMOS transistor T6 may be connected to each other. The drain (D) terminals of the PMOS transistors T2 and T6 and the gate (G) terminal of the PMOS transistor T7 may be connected to each other. The drain (D) terminals of the NMOS transistors T3 and T5 and the gate (G) terminal of the NMOS transistor T8 may be connected to each other. The source (S) terminal of the PMOS transistor T7 may be connected to a power supply (e.g., V DD ). The source (S) terminal of the NMOS transistor T8 may be grounded (e.g., GND). The drain (D) terminals of the PMOS transistor T7 and the NMOS transistor T8 may be connected to each other. An output signal Q may be provided from the drain (D) terminals of the transistors T7, T8. These drain (D) terminals of the transistors T7, T8 may be connected to or at the output node 472, for example.

[0103] The entire first stage circuit 402 may be SET fault tolerant, which means that the output Q in the second stage circuit 404 does not cause any error due to any SET in the first stage circuit 402. Using a single-input buffer gate as a non-limiting example for illustration, two cases will be considered for analysis as follows.

[0104] The first case is when A='0', refer to Figure 4B Analysis shows that there are four internal nodes 1 to 4 (represented by Figure 4B When A='0', the pull-up network 406 of the first stage circuit 402 is conductive, wherein the PMOS transistor T1 first charges the node 2 to V DD , while NMOS transistor T3 continues to charge node 1 to V DD- V TN , which experienced V TN The voltage level V at node 1 is DD- V TNcan be strong enough to turn on the pull-down network 416 of the second stage circuit 404, i.e., by turning on NMOS transistor T8 to make Q='0'. The auxiliary pull-up network 408 of the first stage circuit 402 is also conductive, with PMOS transistor T2 charging node 3 to V DD , thus turning off the pull-up network 414 of the second stage circuit 404 (i.e., the PMOS transistor T7 is turned off). The pull-down network 410 and the auxiliary pull-down network 412 of the first stage circuit 402 are not conductive in this first case. Nodes 1 to 4 will now be analyzed to describe why the impact of the energetic particle may not cause the first stage circuit 402 to be affected and cause an error at the output Q.

[0105] At node 1, any excited particle hitting the drain (D) terminal of NMOS transistor T3 or T5 can generate a negative SET pulse, which drives V DD- V TN Driven to a lower voltage level (e.g., 0V), the NMOS transistor T8 may then be temporarily turned off. However, the negative SET pulse is very short (e.g., <250ps), so the NMOS transistor T8 may be turned on again thereafter. Since the PMOS transistor T7 remains off (during the transient), Q may never be charged and may remain at '0', so there is no error.

[0106] At node 2, there are two cases where the excited particle may hit the source (S) terminal of NMOS transistor T3 or the drain (D) terminal of PMOS transistor T1. In the former case, the effect is the same as that described above with respect to node 1, where the voltage at node 1 can be lower (via NMOS transistor T3 as a resistive path). In short, no error will occur at Q. In the latter case, since the affected transistor is a PMOS transistor, a positive SET pulse can be generated, which will further charge the voltage level of node 2 and then node 1 to even higher (via a resistive path). This can continue to turn on NMOS transistor T8, so there is no error.

[0107] At node 3, any excited particle hitting the drain (D) terminal of PMOS transistor T2 or T6 can generate a positive SET pulse, thereby DD Charges to a higher voltage level. This can continue to turn off PMOS transistor T7, so there is no error.

[0108] At node 4, there are two cases, hitting the source (S) terminal of the PMOS transistor T6 or hitting the drain (D) terminal of the NMOS transistor T4. In the former case, the effect is the same as that described above regarding node 3, where the voltage of node 3 can be higher (via the PMOS transistor T6 as a resistance path). In short, no error will occur at Q. In the latter case, since the affected transistor is an NMOS transistor, a negative SET pulse can be generated, and therefore, the voltage level of node 4 and then node 3 can be discharged (via a resistance path). However, the resistance path of the PMOS transistor T6 can take time for delay propagation. Such a delay can be used as a time filter to attenuate the pulse delivered to node 3. In addition, there can be V on the PMOS transistor T6. TP Drop (where V TP is the threshold voltage of PMOS transistor T6), thus limiting the complete discharge of node 3. The amount of voltage attenuation can be further controlled by adjusting the size of PMOS transistor T6. In addition, the conduction of PMOS transistor T2 helps to maintain the V DD Therefore, a voltage drop at node 4 cannot cause a voltage drop at node 3 due to one or more of the above effects, and therefore, output errors are impossible.

[0109] After analyzing nodes 1 to 4, any SET in the first stage circuit 402 (if induced) is unlikely to cause errors in the second stage circuit 404, and therefore the first stage circuit 402 can be effectively SET tolerant even at high linear energy transfer (LET) levels. Therefore, the entire circuit arrangement (or digital gate) 400 can effectively have a very low cross-section. The second stage circuit 404 may have a cross-section that may be susceptible to SET, but can be designed to be SET tolerant by RHBD means - which is relatively cheap because the second stage circuit 404 can be just an inverter.

[0110] The second case is when A = "1", refer to Figure 4C Conduct analysis, Figure 4C The first stage circuit 402 has the same four internal nodes 1 to 4 (represented by Figure 4C When A='1', the pull-down network 410 of the first stage circuit 402 is conductive, wherein the NMOS transistor T4 first discharges the node 4 to GND, and the PMOS transistor T6 continues to discharge the node 3 to V TP , which has experienced a medium V TP The voltage level V at node 3 decreases. TPIt can be strong enough to turn on the pull-up network 414 of the second stage circuit 404, that is, by turning on the PMOS transistor T7 to make Q='1'. The auxiliary pull-down network 412 of the first stage circuit 402 is also conductive, wherein the NMOS transistor T5 discharges the node 1 to GND, thereby turning off the pull-down network 416 of the second stage circuit 404 (that is, the NMOS transistor T8 is turned off). The pull-up network 406 and the auxiliary pull-up network 408 of the first stage circuit 402 are not conductive in this second case. Nodes 1 to 4 will now be analyzed to describe why the hit of the energetic particle can cause errors at the output Q without affecting the first stage circuit 402.

[0111] At node 1, any excited particle that hits the drain (D) terminal of NMOS transistors T3 or T5 can generate a negative SET pulse, driving GND to a lower voltage level. This can continue to turn off NMOS transistor T7, so there is no error.

[0112] At node 2, there are two cases, hitting the source (S) terminal of the NMOS transistor T3 or hitting the drain (D) terminal of the PMOS transistor T1. In the former case, the effect is the same as that described above regarding node 1, where the voltage at node 1 can be lower (via the NMOS transistor T3 as a resistive path). In short, no error will occur at Q. In the latter case, since the affected transistor is a PMOS transistor, a positive SET pulse can be generated, so it is possible to charge the voltage level of node 2 and then node 1 (via a resistive path). However, the resistive path of the NMOS transistor T3 can take time for delay propagation. Such a delay can act as a time filter to attenuate the pulse delivered to node 1. In addition, there can be V on the NMOS transistor T3. TN Drop (where V TN is the threshold voltage of NMOS transistor T3), thereby limiting the node 1 from being fully charged. The amount of voltage decay can be further controlled by sizing of NMOS transistor T3. In addition, NMOS transistor T5 is turned on, helping to maintain the GND voltage level of node 1. Therefore, a voltage increase at node 2 (by charging) due to one or more of the above effects is unlikely to cause a large voltage rise at node 1, and therefore, output errors are unlikely.

[0113] At node 3, any excited particle hitting the drain (D) terminal of PMOS transistor T2 or T6 can generate a positive SET pulse, which drives V TP driven to a higher voltage level (e.g., V DD), and then the PMOS transistor T7 may be temporarily turned off. However, the positive SET pulse is very short (e.g., <250ps), so the PMOS transistor T7 can be turned on again afterwards. Since the NMOS transistor T8 remains in the off state (during the transient), Q may never discharge and remain at "1", so there is no error.

[0114] At node 4, there are two cases, hitting the source (S) terminal of PMOS transistor T6 or hitting the drain (D) terminal of NMOS transistor T4. In the former case, the effect is the same as that described above with respect to node 3, where the voltage of node 3 can be higher (via PMOS transistor T6 as a resistance path). In short, no error will occur at Q. In the latter case, since the affected transistor is an NMOS transistor, a negative SET pulse can be generated, thus further discharging the voltage level of node 4 and then node 3 to even lower (via a resistance path). This can continue to turn on PMOS transistor T7, so there is no error.

[0115] After analyzing nodes 1 to 4, any SET in the first stage circuit 402, if induced, is unlikely to cause an error in the second stage circuit 404, and therefore the first stage circuit 402 may be substantially SET tolerant even at high LET levels. The second stage circuit 404 may have a cross section that may be susceptible to SET, but may be designed to be SET tolerant by RHBD means - which is relatively inexpensive since it may be just an inverter.

[0116] Various circuit arrangements or digital gates can be similarly designed based on the techniques disclosed herein. Figure 5 , FIG. 6A to FIG. 6E , Fig. 7A To 7F and Figure 8 Non-limiting examples are further described.

[0117] Figure 5 A schematic diagram of a circuit arrangement 500 is shown, which shows a delay line circuit arrangement, according to various embodiments. The delay line circuit arrangement 500 may receive an input signal A and provide an output signal Q. The circuit arrangement 500 may include a first stage circuit 502 and a second stage circuit 504 connected or electrically coupled to each other. The first stage circuit 502 may be SET fault tolerant in nature, while the second stage circuit 504 may be protected by RHBD practices such as transistor size increase and / or layout techniques.

[0118] The first stage circuit 502 may have multiple cascaded split inverters and is SET fault tolerant in nature. The first stage circuit 502 may include multiple cascaded or consecutive sub-circuits (or cascaded split inverters), wherein Figure 54. The first two cascade subcircuits 505a, 505b and the last cascade subcircuit 505n are shown in FIG. A plurality of cascade subcircuits 505a, 505b, 505n may be connected or electrically coupled to each other, wherein a subsequent subcircuit (e.g., 505b) may receive or act on the output of a preceding subcircuit (e.g., 505a). Using the first cascade subcircuit 505a as a non-limiting example, the following description is also applicable to any other cascade subcircuits, similar to the circuit arrangement 400, the first cascade subcircuit 505a may include a pull-up network 506 having a PMOS transistor 520 and an NMOS transistor 522, an auxiliary pull-up network 508 having a PMOS transistor 524, a pull-down network 510 having a PMOS transistor 526 and an NMOS transistor 528, and an auxiliary pull-down network 512 having an NMOS transistor 530.

[0119] Similar to circuit arrangement 400, second stage circuit 504 may include a pull-up network 514 and a pull-down network 516 connected or electrically coupled to each other. Pull-up network 514 may include a PMOS transistor 540, and pull-down network 516 may include an NMOS transistor 542. PMOS transistor 540 and NMOS transistor 542 may together define an inverter.

[0120] The first level circuit 502 and the second level circuit 504 including their corresponding networks, transistors, and connections may be as described in the context of the circuit arrangement 400 , but with some modifications as described below.

[0121] The gate (G) terminals of transistors 520, 524, 528, 530 of the leading cascaded subcircuit 505a may receive an input signal A. The drain (D) terminals of the PMOS transistor (e.g., 524) of the auxiliary pull-up network (e.g., 508) and the PMOS transistor (e.g., 526) of the pull-down network (e.g., 510) of the preceding subcircuit (e.g., 505a) may be connected to the gate (G) terminals of the PMOS transistors of the pull-up network and the auxiliary pull-up network of the subsequent subcircuit (e.g., 505b). The drain (D) terminals of the NMOS transistor (e.g., 522) of the pull-up network (e.g., 506) of the preceding subcircuit (e.g., 505a) and the NMOS transistor (e.g., 530) of the auxiliary pull-down network (e.g., 512) may be connected to the gate (G) terminals of the NMOS transistors of the pull-down network and the auxiliary pull-down network of the subsequent subcircuit (e.g., 505b). The drain (D) terminal of the PMOS transistor of the auxiliary pull-up network and the pull-down network of the last cascaded subcircuit (e.g., 505n) is connected to the gate (G) terminal of the PMOS transistor 540 of the pull-up network 514 of the second stage circuit 504. The drain (D) terminal of the NMOS transistor of the pull-up network and the auxiliary pull-down network of the last cascaded subcircuit (e.g., 505n) is connected to the gate (G) terminal of the NMOS transistor 542 of the pull-down network 516 of the second stage circuit 504.

[0122] The circuit arrangement 500 acts as a delay line, whose delay is accumulated on multiple shunt inverters from the first cascade subcircuit 505a to the last cascade subcircuit 505n and to the second stage circuit 504. For illustration, consider the case when the input signal A changes from logic 'low' to logic 'high'. In this case, for the first cascade subcircuit 505a, when its input (i.e., input signal A) changes, the output of the associated pull-down network 510 (and the output of the associated auxiliary pull-up network 508) can be discharged to V TP (Although there is a threshold voltage difference, as a logic 'low'), and the output of the associated auxiliary pull-down network 512 (and the output of the associated pull-up network 506) can be discharged to GND (as a logic 'low'). These discharge processes take some time to trigger the subsequent sub-circuit 505b. For the subsequent or intermediate sub-circuit 505b, when its input (i.e., the output of the beginning cascaded sub-circuit 505a) changes, the output of the associated pull-up network (and the output of the associated auxiliary pull-down network) can be charged to V DD -V TN (although there is a threshold voltage difference, it acts as a logic 'high'), and the output of the associated auxiliary pull-up network (and the output of the associated pull-down network) can be charged to V DDThese charging processes take some time to trigger another subsequent subcircuit. The discharging and charging processes are alternated within the cascaded subcircuit (i.e., from 505a, 505b, ... to 505n). For the second stage circuit 504, when its input (i.e., the output of the last cascaded subcircuit 505n) changes, the output Q can be discharged to GND (if the number of all cascaded subcircuits is even), or can be charged to V DD (If the number of all cascaded sub-circuits is an odd number). For another case, when the input signal A is charged from logic 'high' to logic 'low', similar charging and discharging processes are alternately performed in the cascaded sub-circuit and reach the second stage circuit 504. For the second stage circuit 504, when its input (i.e., the output of the last cascaded sub-circuit 505n) changes, the output Q can be discharged to V DD (if the number of all cascaded subcircuits is even), or can be charged to GND (if the number of all cascaded subcircuits is odd). The final delay is the propagation delay from the change of the input signal A until the change of the output signal Q.

[0123] If there are N shunt inverters (or cascaded subcircuits), the error rate can be reduced to 1 / (N+1) compared to known RHBD size increase designs. A potential application is the implementation of a local clock generator. If 1000 inverters are provided in the local generator, the error rate reduction can be up to 3 orders of magnitude (1000×).

[0124] Various embodiments may also provide a multi-input circuit arrangement, for example a multi-input digital gate. Fig. 6A A schematic diagram of a circuit arrangement 600a is shown, illustrating a 3-input OR gate design, according to various embodiments.

[0125] Circuit arrangement 600a can receive three main inputs A, B, C and provide a main output Q. Similar to circuit arrangement 400( FIG. 4A to FIG. 4C ), the circuit arrangement 600a may include a first-level circuit 602a that is substantially SET-tolerant and a second-level circuit 604a that is connected or electrically coupled to the first-level circuit 602a and may be protected by RHBD technology. Although the first-level circuit 602a is relatively more complex, the size of the transistors in the first-level circuit 602a may be close to the minimum size, with minimal or no challenges of SET errors.

[0126] The first stage circuit 602a may include a pull-up network 606a and an auxiliary pull-up network 608a connected or electrically coupled to each other, and a pull-down network 610a and an auxiliary pull-down network 612a connected or electrically coupled to each other. The pull-up network 606a may include a plurality of stacked PMOS transistors 620a, 621a, 622a (where adjacent transistors are connected in a manner of drain (D) terminal to source (S) terminal) and an NMOS transistor 623a. The transistors 622a, 623a may be connected in a manner of drain (D) terminal to source (S) terminal. The auxiliary pull-up network 608a may include a plurality of stacked PMOS transistors 625a, 626a, 627a, where adjacent transistors are connected in a manner of drain (D) terminal to source (S) terminal. The source (S) terminals of the PMOS transistors 620a, 625a and the gate (G) terminal of the NMOS transistor 623a may be connected to a power supply (e.g., V DD ). The pull-down network 610a may include a plurality of NMOS transistors 630a, 631a, 632a and a PMOS transistor 633a connected in parallel to each other. The drain (D) terminals of the NMOS transistors 630a, 631a, 632a may be connected to the source (S) terminal of the PMOS transistor 633a. The auxiliary pull-down network 612a may include a plurality of NMOS transistors 635a, 636a, 637a connected in parallel to each other. The sources (S) of the NMOS transistors 630a, 631a, 632a, 635a, 636a, 637a and the gate (G) terminal of the PMOS transistor 633a may be grounded (e.g., GND). Similar to the node ( FIG. 4A to FIG. 4C ), nodes 1 and 3 are shown in the first stage circuit 602a (by Fig. 6A The numbers in the circles in the figure are marked).

[0127] The second stage circuit 604a can be electrically coupled to the first stage circuit 602a and can include a pull-up network 614a and a pull-down network 616a connected or electrically coupled to each other. The pull-up network 614a can include a PMOS transistor 640a, and the pull-down network 616a can include an NMOS transistor 642a. The transistors 640a and 642a can together define an inverter. The gate (G) terminal of the PMOS transistor 640a can be connected to the drain (D) terminal of the PMOS transistors 627a and 633a. The gate (G) terminal of the NMOS transistor 642a can be connected to the drain (D) terminal of the NMOS transistors 623a, 635a, 636a, and 637a. The source (S) terminal of the PMOS transistor 640a can be connected to a power supply (e.g., V DD), and the source (S) terminal of the NMOS transistor 642a can be grounded (eg, GND). The drain (D) terminals of the transistors 640a, 642a can be connected to each other, and an output signal Q can be output therefrom.

[0128] The circuit arrangement 600a may be as described in the context of the circuit arrangement 400, but with some modifications. It may be appreciated that, compared to the circuit arrangement 400 having a corresponding one transistor in each corresponding network, the pull-up network 606a may include stacked PMOS transistors 620a, 621a, 622a, the auxiliary pull-up network 608a may include stacked PMOS transistors 625a, 626a, 627a, the pull-down network 610a may include parallel-connected NMOS transistors 630a, 631a, 632a, and the auxiliary pull-down network 612a may include parallel-connected NMOS transistors 635a, 636a, 637a. A first input signal A may be provided to the gate (G) terminals of transistors 622a, 627a, 630a, 635a, a second input signal B may be provided to the gate (G) terminals of transistors 621a, 626a, 631a, 636a, and a third input signal C may be provided to the gate (G) terminals of transistors 620a, 625a, 632a, 637a. However, it should be understood that the respective input signals may be provided to the gate (G) terminals of different transistors, and / or there may be a different number of input signals.

[0129] Circuit arrangement 600a acts as an OR gate. For illustration, consider the case when input signals A, B and C are all 'low', the output of pull-up network 606a (and the output of auxiliary pull-down network 612a) can be charged to V DD -V TP (although there is a threshold voltage difference, but as a logic 'high'), and the output of the auxiliary pull-up network 608a (and the output of the pull-down network 610a) can be charged to V DD (as a logic 'high'). These charging processes can trigger the second stage circuit 604a to generate a 'low' output. Considering another case when at least one of the input signals A, B and C is 'high', the output of the pull-down network 610a (and the output of the auxiliary pull-up network 608a) can be discharged to V TN (Logic 'low' although there is a threshold voltage difference), and the output of the auxiliary pull-down network 612a (and the output of the pull-up network 606a) can be discharged to GND (as logic 'low'). These discharge processes can trigger the second stage circuit 604a to generate a 'high' output.

[0130] Although known OR gates may have only 6 transistors, the size of these transistors needs to be very large in order to mitigate SET. Such large transistors generally result in a large cross-section and may result in a higher error rate. In general, as will be further described below, known OR gates will have a higher error rate than the OR gates according to various embodiments. It should be understood that various circuit arrangements (such as OR, MUX, XOR, XNOR, etc.) in the form of multi-input gates with a 2-level structure can be similarly implemented according to the technology disclosed herein.

[0131] Figure 6B A schematic diagram of a circuit arrangement 600b is shown, illustrating another 3-input OR gate design, according to various embodiments. The circuit arrangement 600b may include a first stage circuit 602b that may be SET fault tolerant in nature, and a second stage circuit 604b that may be protected by RHBD techniques and connected or electrically coupled to the first stage circuit 602b.

[0132] The first stage circuit 602b may include a pull-up network 606b, an auxiliary pull-up network 608b, a pull-down network 610b, and an auxiliary pull-down network 612b. The second stage circuit 604b may include a pull-up network 614b and a pull-down network 616b. The first stage circuit 602b and the second stage circuit 604b may be electrically coupled to each other. The first stage circuit 602b and the second stage circuit 604b include their corresponding networks, transistors, and connections, which may be as described in the context of the circuit arrangement 600a, except that instead of using three series transistors to maintain the voltage level at node 3, the auxiliary pull-up network 608b may include only one PMOS transistor (T1) 628b, wherein the source (S) terminal of the PMOS transistor 628b may be connected to the drain (D) terminal of the PMOS transistor (T2) 621b. The source (S) terminal of the PMOS transistor 628b may also be connected to the source (S) terminal of the PMOS transistor 622b. The drain (D) terminal of the PMOS transistor 628b may be connected to the drain (D) terminal of the PMOS transistor 633b and the gate (G) terminal of the PMOS transistor 640b. An input signal A may be provided to the gate (G) terminal of the PMOS transistor 628b.

[0133] Circuit arrangement 600b enables saving two transistors with little tradeoff in soft error rate. Fig. 6A ), circuit arrangement 600b has slightly improved area (ie, smaller area) and improved (ie, lower) power.

[0134] Circuit arrangement 600b acts as an OR gate. For illustration, consider the case when input signals A, B and C are all 'low', the output of pull-up network 606b (and the output of auxiliary pull-down network 612b) can be charged to VDD -V TP (although there is a threshold voltage difference, but as a logic 'high'), and the output of the auxiliary pull-up network 608b (and the output of the pull-down network 610b) can be charged to V DD (as a logic 'high'). Auxiliary pull-up network 608b shares a charging path via transistors 621b and 620b in pull-up network 606b. These charging processes can trigger second stage circuit 604b to generate a 'low' output. Considering another case when at least one of input signals A, B, and C is 'high', the output of pull-down network 610b (and the output of auxiliary pull-up network 608b) can discharge to V TN (Although there is a threshold voltage difference, as a logic 'low'), and the output of the auxiliary pull-down network 612b (and the output of the pull-up network 606b) can be discharged to GND (as a logic 'low'). These discharge processes can trigger the second stage circuit 604b to generate a 'high' output.

[0135] Figure 6C A schematic diagram of a circuit arrangement 600c is shown, illustrating another 3-input OR gate design, according to various embodiments. The circuit arrangement 600c may include a first stage circuit 602c that may be SET fault tolerant in nature, and a second stage circuit 604c that may be protected by RHBD techniques and connected or electrically coupled to the first stage circuit 602c.

[0136] The first stage circuit 602c may include a pull-up network 606c, an auxiliary pull-up network 608c, a pull-down network 610c, and an auxiliary pull-down network 612c. The second stage circuit 604c may include a pull-up network 614c and a pull-down network 616c. The first stage circuit 602c and the second stage circuit 604c may be electrically coupled to each other. The circuit arrangement 600c may be optimized, for example, by having a (single) transistor in each of the auxiliary pull-up network 608c and the auxiliary pull-down network 612c.

[0137] The first stage circuit 602c and the second stage circuit 604c include their corresponding networks, transistors, and connections, which may be as described in the context of the circuit arrangement 600a, except that a feedback PMOS transistor (T1) 629c is used in the auxiliary pull-up network 608c, and a feedback NMOS transistor (T2) 638c is used in the auxiliary pull-up network 608c. The source (S) terminal of the feedback PMOS transistor 629c is connected to the node 4, and its gate (G) terminal is connected to the drain (D) terminal of the PMOS transistor 640c and the NMOS transistor 642c, or to the output node, for receiving the output signal Q to maintain the voltage level at the node 3. The drain (D) terminal of the feedback PMOS transistor 629c may be connected to the drain (D) terminal of the PMOS transistor 633c and the gate (G) terminal of the PMOS transistor 640c. The source (S) terminal of the feedback NMOS transistor 638c is connected to the node 2, and the gate (G) terminal thereof is connected to the drain (D) terminals of the PMOS transistor 640c and the NMOS transistor 642c, or to the output node, for receiving the output signal Q so as to maintain the voltage level at the node 1. The drain (D) terminal of the feedback NMOS transistor 638c may be connected to the drain (D) terminal of the NMOS transistor 623c and the gate (G) terminal of the NMOS transistor 642c.

[0138] Circuit arrangement 600c enables saving four transistors with little tradeoff in soft error rate. Fig. 6A ), circuit arrangement 600c has slightly improved area (ie, smaller area) and improved (ie, lower) power.

[0139] Circuit arrangement 600c acts as an OR gate. For illustration, consider the case when input signals A, B and C are all 'low', the output of pull-up network 606c (and the output of auxiliary pull-down network 612c) can be charged to V DD -V TP (Although there is a threshold voltage difference, it acts as a logic 'high'.) This charging process can trigger the second stage circuit 604c to generate a 'low' output, which can trigger the output of the auxiliary pull-up network 608c (and the output of the pull-down network 610c) to be charged to V DD (as logic 'high'); auxiliary pull-up network 608c shares a charging path via transistors 622c, 621c, and 620c in pull-up network 606c. Considering another case when at least one of input signals A, B, and C is 'high', the output of pull-down network 610c (and the output of auxiliary pull-up network 608c) can be discharged to V TN(Although there is a threshold voltage difference, it is as a logic 'low'.) This discharge process can trigger the second stage circuit 604c to generate a 'high' output, which can trigger the output of the auxiliary pull-down network 612c (and the output of the pull-up network 606c) to be charged to GND (as a logic 'low'). The auxiliary pull-down network 612c shares a discharge path via transistors 632c, 631c, and 630c in the pull-down network 610c.

[0140] Fig.6D A schematic diagram of a circuit arrangement 600d is shown, illustrating a 3-input AND gate design, according to various embodiments. The circuit arrangement 600b may receive three primary inputs A, B, C and provide a primary output Q. The circuit arrangement 600d may include a first stage circuit 602d that may be SET fault tolerant in nature and a second stage circuit 604d that may be protected by RHBD techniques connected or electrically coupled to the first stage circuit 602d.

[0141] The first stage circuit 602d may include a pull-up network 606d and an auxiliary pull-up network 608d connected or electrically coupled to each other, and a pull-down network 610d and an auxiliary pull-down network 612d connected or electrically coupled to each other. The second stage circuit 604d may include a pull-up network 614d and a pull-down network 616d connected or electrically coupled to each other. The first stage circuit 602d and the second stage circuit 604d may be electrically coupled to each other.

[0142] The pull-up network 606d may include a plurality of PMOS transistors 620d, 621d, 622d connected in parallel to each other, and an NMOS transistor 623d. The drain (D) terminals of the PMOS transistors 620d, 621d, 622d may be connected to the source (S) terminal of the NMOS transistor 623d. The auxiliary pull-up network 608d may include a plurality of PMOS transistors 625d, 626d, 627d connected in parallel to each other. The sources (S) of the PMOS transistors 620d, 621d, 622d, 625d, 626d, 627d and the gate (G) terminal of the NMOS transistor 623d may be connected to a power supply (e.g., V DD). The pull-down network 610d may include a plurality of stacked NMOS transistors 630d, 631d, 632d (where adjacent transistors are connected in a drain (D) terminal to a source (S) terminal), and a PMOS transistor 633d. The transistors 632d, 633d may be connected in a drain (D) terminal to a source (S) terminal. The auxiliary pull-down network 612d may include a plurality of stacked NMOS transistors 635d, 636d, 637d, where adjacent transistors are connected in a drain (D) terminal to a source (S) terminal. The source (S) terminals of the NMOS transistors 630d, 635d and the gate (G) terminal of the PMOS transistor 633d may be grounded (e.g., GND).

[0143] In the second stage circuit 604d, the pull-up network 614d may include a PMOS transistor 640d, and the pull-down network 616d may include an NMOS transistor 642d. The transistors 640d, 642d may together define an inverter. The gate (G) terminal of the PMOS transistor 640d may be connected to the drain (D) terminals of the PMOS transistors 625d, 626d, 627d, 633d. The gate (G) terminal of the NMOS transistor 642d may be connected to the drain (D) terminals of the NMOS transistors 623d, 637d. The source (S) terminal of the PMOS transistor 640d may be connected to a power supply (e.g., V DD ), and the source (S) terminal of the NMOS transistor 642d may be grounded (eg, GND). The drain (D) terminals of the transistors 640d, 642d may be connected to each other, and an output signal Q may be output therefrom.

[0144] Compared to the corresponding networks of circuit arrangement 600a, the transistor connection types or layouts (i.e., stacked connections or parallel connections) in pull-up network 606d, auxiliary pull-up network 608d, pull-down network 610d, and auxiliary pull-down network 612d are swapped ( Fig. 6A ).

[0145] Although in Fig.6D It is shown that a first input signal A can be provided to the gate (G) terminals of transistors 622d, 625d, 630d, and 635d, a second input signal B can be provided to the gate (G) terminals of transistors 621d, 626d, 631d, and 636d, and a third input signal C can be provided to the gate (G) terminals of transistors 620d, 627d, 632d, and 637d, but it should be understood that individual input signals can be provided to the gate (G) terminals of different transistors, and / or there may be different numbers of input signals.

[0146] Circuit arrangement 600d acts as an AND gate. For illustration, consider the case when at least one of input signals A, B, and C is 'low', the output of pull-up network 606d (and the output of auxiliary pull-down network 612d) can be charged to V DD -V TP (although there is a threshold voltage difference, it acts as a logic 'high'), and the output of the auxiliary pull-up network 608d (and the output of the pull-down network 610d) can be charged to V DD (as a logic 'high'). These charging processes can trigger the second stage circuit 604d to generate a 'low' output. Considering another case when all input signals A, B and C are 'high', the output of the pull-down network 610d (and the output of the auxiliary pull-up network 608d) can be discharged to V TN (Although there is a threshold voltage difference, as a logic 'low'), and the output of the auxiliary pull-down network 612d (and the output of the pull-up network 606d) can be discharged to GND (as a logic 'low'). These discharge processes can trigger the second stage circuit 604d to generate a 'high' output.

[0147] Fig. 6E A schematic diagram of a circuit arrangement 600e according to various embodiments is shown, which illustrates a 3-input composite gate (AND-OR function) design. The circuit arrangement 600e can receive three main inputs A, B, C and provide a main output Q. The circuit arrangement 600e may include a first-level circuit 602e that can be SET fault-tolerant in practice and a second-level circuit 604e that is connected or electrically coupled to the first-level circuit 602e and can be protected by RHBD technology. The first-level circuit 602e may include a pull-up network 606e and an auxiliary pull-up network 608e connected or electrically coupled to each other, and a pull-down network 610e and an auxiliary pull-down network 612e connected or electrically coupled to each other. The second-level circuit 604e may include a pull-up network 614e and a pull-down network 616e connected or electrically coupled to each other. The first-level circuit 602e and the second-level circuit 604e may be electrically coupled to each other.

[0148] like Fig. 6E As shown in FIG. 6 , a plurality of transistors in each of the pull-up network 606 e , the auxiliary pull-up network 608 e , the pull-down network 610 e , and the auxiliary pull-down network 612 e may be stacked and connected in parallel with each other.

[0149] In more detail, the pull-up network 606e may include a plurality of PMOS transistors 620e, 621e, 622e and an NMOS transistor 623e connected or electrically coupled to each other. Each of the PMOS transistors 620e, 621e may be stacked with a PMOS transistor 622e, and the PMOS transistors 620e, 621e may be connected in parallel to each other. The drain (D) terminal of the PMOS transistor 622e may be connected to the source (S) terminal of the NMOS transistor 623e. The auxiliary pull-up network 608e may include a plurality of PMOS transistors 625e, 626e, 627e connected or electrically coupled to each other. Each of the PMOS transistors 626e, 627e may be stacked with a PMOS transistor 625e, and the PMOS transistors 626e, 627e may be connected in parallel to each other. The source (S) terminals of the PMOS transistors 620e, 621e, 626e, 627e and the gate (G) terminals of the NMOS transistor 623e may be connected to a power source (e.g., V DD ). The pull-down network 610e may include a plurality of NMOS transistors 630e, 631e, 632e and a PMOS transistor 633e connected or electrically coupled to each other. The NMOS transistors 631e, 632e may form a stacked transistor and be commonly connected in parallel with the NMOS transistor 630e. The source (S) terminal of the PMOS transistor 633e may be connected to the drain (D) terminal of the NMOS transistors 630e, 631e. The auxiliary pull-down network 612e may include a plurality of NMOS transistors 635e, 636e, 637e connected or electrically coupled to each other. The NMOS transistors 636e, 637e may form a stacked transistor and be commonly connected in parallel with the NMOS transistor 635e. The source (S) terminal of the NMOS transistors 630e, 632e, 635d, 637e and the gate (G) terminal of the PMOS transistor 633e may be grounded (e.g., GND).

[0150] In the second stage circuit 604e, the pull-up network 614e may include a PMOS transistor 640e, and the pull-down network 616e may include an NMOS transistor 642e. The transistors 640e, 642e may together define an inverter. The gate (G) terminal of the PMOS transistor 640e may be connected to the drain (D) terminal of the PMOS transistors 625e, 633e. The gate (G) terminal of the NMOS transistor 642e may be connected to the drain (D) terminal of the NMOS transistors 623e, 635e, 636e. The source (S) terminal of the PMOS transistor 640e may be connected to a power supply (e.g., V DD), and the source (S) terminal of the NMOS transistor 642e can be grounded (eg, GND). The drain (D) terminals of the transistors 640e, 642e can be connected to each other, and an output signal Q can be output therefrom.

[0151] Although in Fig. 6E It is shown that a first input signal A can be provided to the gate (G) terminals of transistors 622e, 625e, 630e, and 635e, a second input signal B can be provided to the gate (G) terminals of transistors 621e, 626e, 631e, and 636e, and a third input signal C can be provided to the gate (G) terminals of transistors 620e, 627e, 632e, and 637e, but it should be understood that individual input signals can be provided to the gate (G) terminals of different transistors, and / or there may be different numbers of input signals.

[0152] Circuit arrangement 600e acts as an AND-OR gate. For illustration, consider the case when input signal A is 'low' and at least one of input signals B and C is 'low', the output of pull-up network 606e (and the output of auxiliary pull-down network 612e circuit) can be charged to V DD -V TP (although there is a threshold voltage difference, but as a logic 'high'), and the output of the auxiliary pull-up network 608e (and the output of the pull-down network 610e) can be charged to V DD (as a logic 'high'). These charging processes can trigger the second stage circuit 604e to generate a 'low' output. Considering another case when input signal A is 'high' or input signals B and C are both 'high', the output of the pull-down network 610e (and the output of the auxiliary pull-up network 608e) can be discharged to V TN (Although there is a threshold voltage difference, as a logic 'low'), and the output of the auxiliary pull-down network 612e (and the output of the pull-up network 606e) can be discharged to GND (as a logic 'low'). These discharge processes can trigger the second stage circuit 604e to generate a 'high' output.

[0153] It will be appreciated that for CMOS, PMOS and NMOS transistors are typically configured as parallel series pairs, as in Fig. 6A , Fig.6D and Fig. 6E As a non-limiting example, this parallel-serial pair arrangement can be employed in a static CMOS design.

[0154] 7A to 7C Schematic diagram showing pull-up and auxiliary pull-up networks of a first stage circuit of a circuit arrangement according to various embodiments. 7A to 7CThe transistor connection optimization between the pull-up network of the first stage circuit and the corresponding auxiliary pull-up network is shown. For simplicity, 7A to 7C Other parts of the circuit arrangement are not shown, including, for example, a pull-down network, an auxiliary pull-down network, and a second stage circuit. However, it should be understood that each combination of a pull-up network and a corresponding auxiliary pull-up network, i.e., 706a and 708a ( Fig. 7A ), 706b and 708b( Figure 7B ), 706c and 708c( Figure 7C ) can be used with any of the pull-down networks and any auxiliary pull-down networks described herein for the first stage circuit.

[0155] refer to Fig. 7A , showing standard connections without optimization, the pull-up network 706a may include a plurality of stacked PMOS transistors 720a, 721a, 722a and NMOS transistor 723a connected or electrically coupled to each other, and the auxiliary pull-up network 708a may include a plurality of stacked PMOS transistors 725a, 726a, 727a connected or electrically coupled to each other. The source terminals of the PMOS transistors 720a, 725a may be connected or electrically coupled to each other. The pull-up network 706a and the auxiliary pull-up network 708a and their corresponding transistors and connections may be similar to the circuit arrangement 600a ( Fig. 6A )

[0156] refer to Figure 7B , showing the Fig. 7A The design is optimized compared to the first connection in which one transistor is removed in the auxiliary pull-up network, the pull-up network 706b may include a plurality of stacked PMOS transistors 720b, 721b, 722b and an NMOS transistor 723b connected or electrically coupled to each other, and the auxiliary pull-up network 708b may include a plurality of stacked PMOS transistors 726b, 727b connected or electrically coupled to each other. The source (S) terminals of the PMOS transistors 721a, 726a and the drain (D) terminal of the PMOS transistor 720b may be connected or electrically coupled to each other.

[0157] refer to Figure 7C , showing the Fig. 7ACompared to the design of the auxiliary pull-up network, the second connection with two transistors is removed. The pull-up network 706c may include a plurality of stacked PMOS transistors 720c, 721c, 722c and NMOS transistor 723c connected or electrically coupled to each other, and the auxiliary pull-up network 708c may include a PMOS transistor 727c. The source (S) terminals of the PMOS transistors 722c, 727c and the drain (D) terminal of the PMOS transistor 721c may be connected or electrically coupled to each other. The pull-up network 706c and the auxiliary pull-up network 708c have their corresponding transistors and connections, which may be similar to the circuit arrangement 600b ( Figure 6B ).

[0158] 7D to 7F show schematic diagrams of pull-down networks and auxiliary pull-down networks of the first-stage circuit of the circuit arrangement according to various embodiments. FIG. 7D to 7F show optimization of transistor connections between the pull-down network of the first-stage circuit and the corresponding auxiliary pull-down network. For simplicity, other parts of the circuit arrangement are not shown in FIG. 7D to 7F, including, for example, pull-up networks, auxiliary pull-up networks, and second-stage circuits. However, it should be understood that each combination of the pull-down network and the corresponding auxiliary pull-down network, i.e., 710d and 712d (FIG. 7D), 710e and 712e (FIG. 7E), 710f and 712f (FIG. 7F) can be used together with any pull-up network and any auxiliary pull-up network described herein for the first-stage circuit.

[0159] Referring to FIG. 7D , a standard connection without optimization is shown, the pull-down network 710 d may include a plurality of stacked NMOS transistors 730 d, 731 d, 732 d and a PMOS transistor 733 d connected or electrically coupled to each other, and the auxiliary pull-down network 712 d may include a plurality of stacked NMOS transistors 735 d, 736 d, 737 d connected or electrically coupled to each other. The source terminals of the NMOS transistors 730 d, 735 d may be connected or electrically coupled to each other. The pull-down network 710 d and the auxiliary pull-down network 712 d have their corresponding transistors and connections, which may be similar to those of the circuit arrangement 600 d ( Fig.6D ).

[0160] Referring to FIG. 7E , a first connection optimization is shown in which one transistor is removed from the auxiliary pull-down network compared to the design of FIG. 7D , the pull-down network 710e may include a plurality of stacked NMOS transistors 730e, 731e, 732e and a PMOS transistor 733e connected or electrically coupled to each other, and the auxiliary pull-down network 712e may include a plurality of stacked NMOS transistors 736e, 737e connected or electrically coupled to each other. The source (S) terminals of the NMOS transistors 731e, 736e and the drain (D) terminal of the NMOS transistor 730e may be connected or electrically coupled to each other.

[0161] Referring to FIG. 7F , a second connection optimization is shown in which two transistors are removed from the auxiliary pull-down network compared to the design of FIG. 7D , the pull-down network 710 f may include a plurality of stacked NMOS transistors 730 f , 731 f , 732 f and a PMOS transistor 733 f connected or electrically coupled to each other, and the auxiliary pull-down network 712 f may include an NMOS transistor 737 f . The source (S) terminals of the NMOS transistors 732 f , 737 f and the drain (D) terminal of the NMOS transistor 731 f may be connected or electrically coupled to each other.

[0162] The circuit arrangement (e.g., digital gate) of various embodiments can provide reduced error rates. An analysis will now be provided on many features of the circuit arrangement for several designs, starting from simple buffer designs to more complex unit circuits. First, it should be understood that in more complex units or circuits, the effects or advantages of various embodiments may be more apparent.

[0163] Table 1 is based on standard designs (non-RHBD), known RHBD size increases, and designs of various embodiments (see, for example, FIG. 4A to FIG. 4C ) lists the normalized (relative to the design disclosed herein) LET, power, delay, area, and error rate of a simple 2-level buffer. Actual physical values ​​are shown in parentheses based on the buffer design of various embodiments.

[0164] Table 1: Comparison of LET, power, delay, area and error rate for simple buffer design using standard (non-RHBD), known RHBD (resized) and various embodiments

[0165]

[0166] As can be seen from Table 1, the standard non-RHBD buffer has better power, delay and area properties (than the RHBD design), but it suffers from low LET (i.e., high error rate due to low excitation particles) and high error rate (estimated by GEO). Although the buffer design with RHBD sizing is sized to have the same LET threshold as the design according to the various embodiments, the error rate of the latter design is expected to be as small as 1 / 2. It is expected that the designs of the various embodiments consume higher power, operate slower (longer delay) and occupy a larger area. This is probably because the buffer design is a very simple unit (without any stacked transistors in the known design).

[0167] Now consider a more complex cell, where the digital gates of various embodiments can be more advantageous for multi-input gates that require stacked transistors. Table 2 is based on a standard design (non-RHBD), a known RHBD size increase, and the design of various embodiments (see, e.g., Fig. 6A) lists the normalized (again for the design disclosed herein) LET, power, delay, area, and error rate of a 2-stage 3-input OR gate. As mentioned above, the actual physical values ​​are shown in brackets based on the OR gates of various embodiments.

[0168] Table 2: Comparison of LET, power, delay, area and error rate for 3-input OR designs using standard (non-RHBD), known RHBD (resized) and various embodiments.

[0169]

[0170]

[0171] As can be seen from Table 2, as expected, the standard non-RHBD OR gate also has better power, delay and area properties (than the RHBD design), but it suffers from a very high error rate, i.e., according to various embodiments, up to 215 times higher than the OR gate (more than two orders of magnitude). Although the buffer design with the increased RHBD size is sized to have a similar LET threshold as the design of the various embodiments, the latter design is very notable for having an error rate as small as 1 / 74, and the required area is still smaller. In short, the various embodiments can be very beneficial for reducing the error rate and area of ​​multi-input gates, but potentially at the expense of slower delay (and possibly higher power).

[0172] It should be understood that the techniques disclosed herein can be applied to design any circuit arrangement or gate (including combinational gates or sequential logic (e.g., latches, flip-flops)) or other circuits with the following modifications: without departing from the technique that one or more NMOS transistors can be used to enable / disable NMOS pull-down networks and one or more PMOS transistors can be used to enable / disable PMOS pull-up networks. The modifications include the insertion of transistors and changes in the connections of transistors.

[0173] As mentioned above, inserting an NMOS transistor in the pull-up network of the first stage circuit may result in a slightly weaker voltage swing for logic 1 (e.g., from 0 to V DD -V TN Similarly, inserting a PMOS transistor in the pull-down network of the first stage circuit may result in a slightly weaker voltage swing for logic 0 (e.g., from V DD To V TP). The non-full voltage swing may cause the entire circuit to operate slower. However, if the threshold voltages of the PMOS and NMOS transistors are low, the overall speed performance can be improved. In view of the above, various embodiments may provide an application using a fully depleted silicon-on-insulator (FDSOI) process, wherein the NMOS transistors in the pull-up network of the first stage circuit and the PMOS transistors in the pull-down network of the first stage circuit may be internally configured to have low threshold voltages V TN and V TP , for example V TN ≈0.1 and V TP ≈0.1.

[0174] Figure 8 A schematic diagram of a circuit arrangement 800 is shown, illustrating a (digital) buffer gate with FDSOI transistors, according to various embodiments. The circuit arrangement 800 includes a first stage circuit 802 and a second stage circuit 804 electrically coupled to each other, wherein the first stage circuit 802 may include a pull-up network 806, an auxiliary pull-up network 808, a pull-down network 810, and an auxiliary pull-down network 812, and the second stage circuit 804 may include a pull-up network 814 and a pull-down network 816 connected or electrically coupled to each other. The circuit arrangement 800 includes corresponding networks, transistors, and connections, which may be as described in the circuit arrangement 400 ( FIG. 4A to FIG. 4C ), except that the FDSOI transistor is used for the NMOS transistor T3 of the pull-up network 806 and the PMOS transistor T6 of the pull-down network 810, where respective bias or control signals Vs1 and Vs2 can be applied to the transistors T3 and T6 to control the threshold voltages V TN and V TP As a non-limiting example, NMOS transistor T3 may be body biased via Vs1 to reduce the V TN , and the NMOS transistor T6 can be similarly body biased via Vs2 to reduce the V TP .

[0175] The various embodiments can be used in various applications, including but not limited to circuits / systems for S&S applications and high-reliability applications. For example, one possible application involves S&S applications. In space, radiation effects are severe, and the various embodiments can help satellite applications (e.g., microsatellites in low earth orbit (LEO), nanosatellites, large satellites, and large satellites in GEO) to mitigate SEE, thereby making these satellites more versatile and reliable, thereby extending their service life. Another possible application involves the automotive industry, such as self-driving cars. For self-driving cars, especially level 5 self-driving cars, the error rate of digital circuits needs to be very low for safety reasons, where the digital circuit design according to the technology disclosed in this article can help solve this problem. The third possible application involves high-reliability medical applications. For example, for safety reasons, implantable electronic devices require high reliability, where the digital circuit design according to the technology disclosed in this article can help solve this problem. However, it should be understood that the technology and various embodiments disclosed herein can also be used in various other applications, including applications where reliability may be an issue.

[0176] Although the present invention has been specifically shown and described with reference to specific embodiments, it will be appreciated by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present invention as defined by the appended claims. Therefore, the scope of the present invention is indicated by the appended claims, and is therefore intended to include all changes within the equivalent meaning and scope of the claims.

Claims

1. A circuit device, include: a first circuit configured to receive one or more input signals provided to the circuit arrangement; a second circuit configured to provide one or more output signals of the circuit arrangement, The first circuit comprises: a first pull-up network including at least one first transistor of a first conductivity type and a second transistor of a second conductivity type electrically coupled to each other; and a first pull-down network including a first transistor of the first conductivity type and at least one second transistor of the second conductivity type electrically coupled to each other, and The second circuit comprises: a second pull-up network comprising a first transistor of the first conductivity type; and a second pull-down network including a second transistor of the second conductivity type, and wherein the first pull-up network and the second pull-down network are electrically coupled to each other, and wherein the first pull-down network and the second pull-up network are electrically coupled to each other, an auxiliary pull-up network electrically coupled to the first pull-down network and the second pull-up network, the auxiliary pull-up network comprising at least one first auxiliary transistor of the first conductivity type; and an auxiliary pull-down network electrically coupled to the first pull-up network and the second pull-down network, the auxiliary pull-down network comprising at least one second auxiliary transistor of the second conductivity type, wherein, in response to an input signal among the one or more input signals received, the input signal having a first value, the first pull-up network is configured to conduct electricity to turn on the second pull-down network to provide a first output signal, and the auxiliary pull-up network is configured to conduct electricity to turn off the second pull-up network, and In response to the input signal having a second value, the first pull-down network is configured to conduct to turn on the second pull-up network to provide a second output signal, and the auxiliary pull-down network is configured to conduct to turn off the second pull-down network.

2. The circuit arrangement according to claim 1, wherein a source terminal of the second transistor of the first pull-up network is connected to a drain terminal of the at least one first transistor of the first pull-up network, wherein a drain terminal of the second transistor of the first pull-up network is connected to a gate terminal of the second transistor of the second pull-down network, wherein a drain terminal of the first transistor of the first pull-down network is connected to a gate terminal of the first transistor of the second pull-down network, and Wherein a source terminal of the first transistor of the first pull-down network is connected to a drain terminal of the at least one second transistor of the first pull-down network.

3. The circuit arrangement according to claim 1, wherein a drain terminal of the at least one first auxiliary transistor is connected to a drain terminal of the first transistor of the first pull-down network and a gate terminal of the first transistor of the second pull-up network, and Wherein a drain terminal of the at least one second auxiliary transistor is connected to a drain terminal of the second transistor of the first pull-up network and to a gate terminal of the second transistor of the second pull-down network.

4. The circuit arrangement according to claim 1, wherein the at least one first transistor of the first pull-up network comprises a plurality of first transistors of a first conductivity type, the plurality of first transistors being electrically coupled to each other and to the second transistor of the first pull-up network, and The plurality of first transistors are arranged in at least one of a stacked connection or a parallel connection.

5. The circuit arrangement according to claim 1, wherein the at least one second transistor of the first pull-down network comprises a plurality of second transistors of the second conductivity type, the plurality of second transistors being electrically coupled to each other and to the first transistor of the first pull-down network, and The plurality of second transistors are arranged in at least one of a stacked connection or a parallel connection.

6. The circuit arrangement according to claim 4 or 5, wherein the at least one first auxiliary transistor comprises a plurality of first auxiliary transistors of the first conductivity type, the plurality of first auxiliary transistors being electrically coupled to each other and to the first transistor of the first pull-down network, and The plurality of first auxiliary transistors are arranged in at least one of a stacked connection or a parallel connection.

7. The circuit arrangement according to claim 4 or 5, wherein the at least one second auxiliary transistor comprises a plurality of second auxiliary transistors of the second conductivity type, the plurality of second auxiliary transistors being electrically coupled to each other and to the second transistor of the first pull-up network, and The plurality of second auxiliary transistors are arranged in at least one of a stacked connection or a parallel connection.

8. The circuit arrangement according to claim 4, Wherein a source terminal of the at least one first auxiliary transistor of the auxiliary pull-up network is connected to a source terminal of one first transistor among the plurality of first transistors of the first pull-up network.

9. The circuit arrangement according to claim 5, Wherein a source terminal of the at least one second auxiliary transistor of the auxiliary pull-down network is connected to a source terminal of one second transistor among the plurality of second transistors of the first pull-down network.

10. The circuit arrangement according to claim 4 or 5, wherein a source terminal of the at least one first auxiliary transistor of the auxiliary pull-up network is connected to a source terminal of the second transistor of the first pull-up network, and Wherein a gate terminal of the at least one first auxiliary transistor of the auxiliary pull-up network is connected to a drain terminal of the first transistor of the second pull-up network and to a drain terminal of the second transistor of the second pull-down network.

11. The circuit arrangement according to claim 4 or 5, wherein a source terminal of said at least one second auxiliary transistor of said auxiliary pull-down network is connected to a source terminal of said first transistor of said first pull-down network, and Wherein a gate terminal of the at least one second auxiliary transistor of the auxiliary pull-down network is connected to a drain terminal of the first transistor of the second pull-up network and to a drain terminal of the second transistor of the second pull-down network.

12. The circuit arrangement according to claim 1, in, For the first transistor of the first pull-down network, the first transistor is adapted to be body biased by a first bias signal applied to the first transistor to control a threshold voltage of the first transistor, or Wherein, for the second transistor of the first pull-up network, the second transistor is suitable for being body biased by a second bias signal applied to the second transistor to control a threshold voltage of the second transistor.

13. The circuit arrangement according to claim 1, wherein the first circuit comprises a plurality of cascaded sub-circuits electrically coupled to each other, Each of the plurality of cascaded sub-circuits include: a pull-up network comprising at least one first transistor of the first conductivity type and a second transistor of the second conductivity type electrically coupled to each other; as well as a pull-down network including a first transistor of the first conductivity type and at least one second transistor of the second conductivity type electrically coupled to each other, and Wherein, for the last cascaded sub-circuit in the plurality of cascaded sub-circuits, the pull-up network is defined by the first pull-up network, and the pull-down network is defined by the first pull-down network.

14. The circuit arrangement according to claim 13, in, For each cascade sub-circuit, the cascade sub-circuit further includes: an additional auxiliary pull-up network electrically coupled to the pull-down network, the additional auxiliary pull-up network comprising at least one first auxiliary transistor of the first conductivity type; and An additional auxiliary pull-down network is electrically coupled to the pull-up network, the additional auxiliary pull-down network comprising at least one second auxiliary transistor of the second conductivity type.

15. The circuit arrangement according to claim 14, wherein for the last cascaded subcircuit, The additional auxiliary pull-up network is also electrically coupled to the second pull-up network, and The additional auxiliary pull-down network is also electrically coupled to the second pull-down network.

16. The circuit arrangement according to any one of claims 1 to 5 or 13 to 15, in, For each of the first transistor of the second pull-up network and the second transistor of the second pull-down network, the transistor is configured to drive a load associated with the transistor, and The aspect ratio of the first transistor of the second pull-up network or the second transistor of the second pull-down network is greater than the aspect ratio of a transistor optimized for driving the load. The circuit arrangement of claim 16 , wherein the aspect ratio is at least 2.

5.

18. A method for forming a circuit arrangement, include: electrically coupling a first pull-up network of the first circuit and a second pull-down network of the second circuit to each other, and electrically coupling a first pull-down network of the first circuit and a second pull-up network of the second circuit to each other, wherein the first circuit is configured to receive one or more input signals provided to the circuit arrangement, wherein the second circuit is configured to provide one or more output signals of the circuit arrangement, wherein the first pull-up network comprises at least one first transistor of a first conductivity type and a second transistor of a second conductivity type electrically coupled to each other, wherein the first pull-down network comprises a first transistor of the first conductivity type and at least one second transistor of the second conductivity type electrically coupled to each other, wherein the second pull-up network comprises a first transistor of the first conductivity type, and wherein the second pull-down network comprises a second transistor of the second conductivity type, electrically coupling an auxiliary pull-up network to the first pull-down network and the second pull-up network, the auxiliary pull-up network comprising at least one first auxiliary transistor of the first conductivity type, and electrically coupling an auxiliary pull-down network to the first pull-up network and the second pull-down network, the auxiliary pull-down network comprising at least one second auxiliary transistor of the second conductivity type, wherein, in response to an input signal among the one or more input signals received, the input signal having a first value, the first pull-up network is configured to conduct electricity to turn on the second pull-down network to provide a first output signal, and the auxiliary pull-up network is configured to conduct electricity to turn off the second pull-up network, and In response to the input signal having a second value, the first pull-down network is configured to conduct to turn on the second pull-up network to provide a second output signal, and the auxiliary pull-down network is configured to conduct to turn off the second pull-down network.

19. A circuit arrangement for mitigating the effects of at least one transient voltage pulse generated in a circuit arrangement, the circuit arrangement include: a first circuit configured to receive one or more input signals provided to the circuit arrangement; a second circuit configured to provide one or more output signals of the circuit arrangement, in The first circuit comprises: a first pull-up network including at least one first transistor of a first conductivity type and a second transistor of a second conductivity type electrically coupled to each other; and a first pull-down network including a first transistor of the first conductivity type and at least one second transistor of the second conductivity type electrically coupled to each other, and The second circuit comprises: a second pull-up network comprising a first transistor of the first conductivity type; and a second pull-down network including a second transistor of the second conductivity type, and wherein the first pull-up network and the second pull-down network are electrically coupled to each other, and wherein the first pull-down network and the second pull-up network are electrically coupled to each other, an auxiliary pull-up network electrically coupled to the first pull-down network and the second pull-up network, the auxiliary pull-up network comprising at least one first auxiliary transistor of the first conductivity type; and an auxiliary pull-down network electrically coupled to the first pull-up network and the second pull-down network, the auxiliary pull-down network comprising at least one second auxiliary transistor of the second conductivity type, wherein, in response to an input signal among the one or more input signals received, the input signal having a first value, the first pull-up network is configured to conduct electricity to turn on the second pull-down network to provide a first output signal, and the auxiliary pull-up network is configured to conduct electricity to turn off the second pull-up network, and In response to the input signal having a second value, the first pull-down network is configured to conduct to turn on the second pull-up network to provide a second output signal, and the auxiliary pull-down network is configured to conduct to turn off the second pull-down network.

Images