Electronic devices

Abstract

The present invention relates to an electronic device. The electronic device includes a switching regulator. Here, the switching regulator has a first wiring portion (including a parasitic inductance) coupling a high-side element and a low-side element, and a second wiring portion (including a parasitic inductance) coupling the low-side element. In addition, the switching regulator has a first area in which the first wiring portion and the second wiring portion are parallel to each other. Therefore, the performance of the electronic device can be improved.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2019-119880 filed on June 27, 2019, including specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to electronic devices, and for example, the present invention relates to a technique applicable to electronic devices including a switching regulator. Background Art

[0004] There are the following disclosed technologies.

[0005] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2005-294464

[0006] [Patent Document 2] Japanese Unexamined Patent Application Publication No. 2018-200963

[0007] Patent Document 1 discloses a technology for reducing the size of a non-insulated DC-DC converter and improving voltage conversion efficiency.

[0008] Patent Document 2 discloses a technology for improving the performance of electronic equipment. Summary of the invention

[0009] For example, a switching regulator represented by a DC-DC converter is configured to output a desired voltage by periodically repeating a switching operation.

[0010] In this manner, a switching operation is performed in the switching regulator, and a current is turned on / off by the switching operation.

[0011] Therefore, when the parasitic inductance existing (parasitic) in the switching regulator is large, high-frequency noise generated by changing the current based on the switching operation becomes large.

[0012] Therefore, the switching regulator becomes a source of large-scale high-frequency noise, which adversely affects electronic components arranged in the periphery. Therefore, it is desirable to reduce the high-frequency noise generated from the switching regulator.

[0013] Other objects and novel features will become apparent based on the description of this specification and the accompanying drawings.

[0014] An electronic device according to one embodiment includes: a switching regulator. Here, the switching regulator includes: a first wiring portion that couples a high-side element and a low-side element to each other, and a second wiring portion that is coupled to the low-side element. In addition, the switching regulator has a first region in which the first wiring portion and the second wiring portion are parallel to each other. In addition, the operation period of the switching regulator includes: a conduction period in which the high-side element is turned on and the low-side element is turned off, a transition period in which the high-side element is turned on and the low-side element is turned on, and a turn-off period in which the high-side element is turned off and the low-side element is turned on. Here, in the first region, the direction of the current flowing through the first wiring portion during each period of the transition period and the turn-off period and the direction of the current flowing through the second wiring portion during each period of the transition period and the turn-off period are opposite to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a diagram showing a circuit configuration of an electronic device.

[0016] Figure 2 is a timing diagram of each MOS transistor of the high-side MOS transistor and the low-side MOS transistor.

[0017] Figure 3 is a circuit diagram showing a step-down (voltage drop) type DC-DC converter according to the related art.

[0018] Figure 4 is a plan view showing a mounting layout of a step-down DC-DC converter according to the related art.

[0019] Figure 5 is a circuit diagram showing a step-down DC-DC converter according to an embodiment.

[0020] Figure 6 is a circuit diagram showing a current path of a current flowing through a step-down DC-DC converter during an on / off operation (on period).

[0021] Figure 7 is a circuit diagram showing a current path of a current flowing through a step-down DC-DC converter during a transition period.

[0022] Figure 8 is a circuit diagram showing a current path of a current flowing through a step-down DC-DC converter during an off / on operation (off period).

[0023] Fig. 9 is a plan view schematically showing a wiring layout of a wiring substrate constituting a step-down DC-DC converter according to the embodiment.

[0024] Fig.10is a plan view schematically showing a state in which components constituting the step-down DC-DC converter according to the embodiment are mounted on a wiring substrate.

[0025] Fig.11 is a mounting layout diagram showing a current path of a current flowing through a step-down DC-DC converter during an on / off operation (on period).

[0026] Fig.12 is a mounting layout diagram showing a current path of a current flowing through a step-down DC-DC converter in a transition period.

[0027] Fig.13 is a mounting layout diagram showing a current path of a current flowing through a step-down DC-DC converter during an off / on operation (off period).

[0028] Fig.14 is a graph showing conducted EMI characteristics according to the related art.

[0029] Fig.15 is a graph showing conducted EMI characteristics according to an embodiment.

[0030] Fig.16 is a graph showing a relationship between a load current and electric power conversion efficiency in a step-down DC-DC converter according to the related art.

[0031] Fig.17 is a graph showing a relationship between a load current and electric power conversion efficiency in a step-down DC-DC converter according to an embodiment.

[0032] Fig.18 is a plan view showing a mounting layout of a step-down DC-DC converter according to a modified example. DETAILED DESCRIPTION

[0033] In the following embodiments, the description is divided into multiple parts or embodiments for convenience when necessary, but unless otherwise specified, they are not independent of each other, and one of them is related to part or all of the modified examples, details and supplementary descriptions, etc. of another.

[0034] In the following embodiments, unless a number is explicitly indicated and in principle the number is clearly limited to a specific number, the number of elements, etc. (including the number of elements, numerical values, quantities, ranges, etc.) is not limited to a specific number, but may be not less than or equal to a specific number.

[0035] Furthermore, in the following embodiments, unless a constituent element is clearly specified and is considered to be obviously essential in principle, it goes without saying that the constituent elements (including element steps and the like) are not necessarily essential.

[0036] Similarly, in the following embodiments, unless otherwise clearly specified and considered obvious in principle, when referring to the shape, positional relationship, etc. of reference components, etc., it is assumed that the shape, etc. is substantially approximated or similar to the shape, etc. This also applies to the above numerical values and ranges.

[0037] In all the drawings used to illustrate the embodiments, the same reference numerals are used in principle to denote the same components, and their repeated description is omitted. Note that, for clarity, it may be shaded even in a plan view.

[0038] The technical concept of this embodiment can be widely applied to various types of switching regulators. That is, the technical concept in this embodiment can be applied to a switching regulator in a DC-DC conversion system or a switching regulator in an AC / DC conversion system. Further, the technical concept in this embodiment can be applied to any one of a buck-type, boost-type, and buck-boost-type switching regulator.

[0039] Hereinafter, a buck-type DC-DC converter will be described as an exemplary switching regulator to which the technical concept of this embodiment is applied.

[0040] <Circuit Configuration and Operation of DC-DC Converter>

[0041] Figure 1 is a diagram showing the circuit configuration of the buck-type DC-DC converter CV. As shown in Figure 1 it is shown that, in the buck-type DC-DC converter CV, a high-side MOS transistor QH and a low-side MOS transistor QL are connected in series between an input terminal TE1 and a ground (reference potential) GND. An inductor L and a load RL are serially coupled between a node NA between the high-side MOS transistor QH and the low-side MOS transistor QL, and the ground GND on the load RL side, and a capacitor C is coupled in parallel with the load RL.

[0042] The gate electrode of the high-side MOS transistor QH and the gate electrode of the low-side MOS transistor QL are connected to a control circuit CC, and the on / off operation of the high-side MOS transistor QH and the on / off operation of the low-side MOS transistor QL are controlled by the control circuit CC. Specifically, when the high-side MOS transistor QH is turned on, the control circuit CC controls the low-side MOS transistor QL to turn it off, and when the high-side MOS transistor QH is turned off, it controls the low-side MOS transistor QL to turn it on.

[0043] Here, for example, when the high-side MOS transistor QH is turned on and the low-side MOS transistor QL is turned off, current flows from the input terminal TE1 to the load RL through the high-side MOS transistor QH and the inductor L. Thereafter, when the high-side MOS transistor QH is turned off and the low-side MOS transistor QL is turned on, first, the high-side MOS transistor QH is turned off so that the current flowing from the input terminal TE1 to the load RL through the high-side MOS transistor QH and the inductor L is cut off. That is, the current flowing through the inductor L is cut off. However, in the inductor L, when the current decreases, the current flowing through the inductor L is attempted to be maintained. At this time, since the low-side MOS transistor QL is turned on, the current flows from the ground GND to the load RL via the low-side MOS transistor QL and the inductor L. Thereafter, the high-side MOS transistor QH is turned on, and the low-side MOS transistor QL is turned off again. By repeating this operation, in Figure 1 In the step-down DC-DC converter CV shown in , when the input voltage Vin is input to the input terminal TE1 , an output voltage Vout lower than the input voltage Vin is output to both ends of the load RL.

[0044] Hereinafter, the reason why an output voltage Vout lower than the input voltage Vin is output to both ends of the load RL when the input voltage Vin is input to the input terminal TE1 by repeating the above switching operation will be briefly described. In the following description, it is assumed that the current flowing through the inductor L is uninterrupted.

[0045] First, it is assumed that the high-side MOS transistor QH is controlled by the control circuit CC and is turned on during the conduction period T ON and the off period T OFF Switching operation is performed in the switching frequency f = 1 / (T ON +T OFF ).

[0046] Here, for example, Figure 1 In the embodiment, the capacitor C inserted in parallel with the load RL has the function of preventing the output voltage Vout from changing significantly in a short time. Figure 1 In the step-down DC-DC converter CV shown in FIG. 1 , since the capacitor C having a relatively large capacitance value is inserted in parallel with the load RL, the ripple voltage included in the output voltage Vout is smaller than the output voltage Vout in a steady state. For this reason, it is assumed that the change in the output voltage Vout within one cycle of the switching operation is negligible.

[0047] First, the case where the high-side MOS transistor QH is turned on will be considered. At this time, since it is assumed that the output voltage Vout does not fluctuate within one cycle, the voltage applied to the inductor L can be considered to be constant in Vin-Vout. Therefore, when the inductance of the inductor L is L1, the current increment ΔI in the on period TON isON It is given by Equation (1).

[0048] ΔI ON =(Vin - Vout) / L1 × T ON ···(1)

[0049] Next, consider the case where the high-side MOS transistor QH is turned off. In this case, since the low-side MOS transistor QL is turned on, the voltage applied to the inductor L becomes 0 - Vout = -Vout. Therefore, during the off period T OFF the current increment ΔI OFF is given by Equation (2).

[0050] ΔI OFF =-Vout / L1 × T OFF ···(2)

[0051] Here, when in the steady state, the current flowing through the inductor L does not increase or decrease during one period of the switching operation. In other words, if the current flowing through the inductor L increases or decreases during one cycle, it means that the steady state has not been reached. Therefore, in the steady state, the following Equation (3) holds.

[0052] ΔI ON +ΔI OFF = 0···(3)

[0053] Moreover, by substituting each of the relationships of Equation (1) and Equation (2) into Equation (3), the following Equation (4) can be obtained.

[0054] Vout = Vin × T ON / (T ON + T OFF )···(4)

[0055] In this Equation (4), since T ON is greater than or equal to 0, and T OFF is greater than or equal to 0, it can be seen that Vout < Vin. That is, the buck DC-DC converter CV shown in Figure 1 is a circuit that outputs an output voltage Vout lower than the input voltage Vin. Then, it can be seen that by controlling the switching operation by the control circuit CC according to Equation (4), any output voltage Vout lower than the input voltage Vin can be obtained by changing the on period T ON and the off period T OFF . In particular, if the on period T ON and the off period T OFF are controlled to be constant, a constant output voltage Vout can be obtained.

[0056] As mentioned above, according to Figure 1 In the step-down DC-DC converter CV shown in FIG. 1 , the control circuit CC controls the on / off operation of the high-side MOS transistor QH and the on / off operation of the low-side MOS transistor QL to output an output voltage Vout lower than the input voltage Vin.

[0057] In this manual, Figure 1 , a component surrounded by a dotted line is a step-down DC-DC converter CV as an exemplary switching regulator, and the electronic device EA is formed by combining the step-down DC-DC converter CV and the control circuit CC.

[0058] Figure 2 is a timing diagram of each MOS transistor of the high-side MOS transistor QH and the low-side MOS transistor QL. Figure 2 In the conduction period T ON Indicates the time during which the high-side MOS transistor QH is turned on and the off period T OFF Indicates the time during which the high-side MOS transistor QH is turned off. Here, as in Figure 2 As shown in FIG. 1 , it can be understood that when the high-side MOS transistor QH is turned on, the low-side MOS transistor QL is turned off, and when the high-side MOS transistor QH is turned off, the low-side MOS transistor QL is turned on. Therefore, it can be said that the conduction period T ON Indicates the time when the low-side MOS transistor QL is turned off, and the off period T OFF Indicates when the low-side MOS transistor QL is turned on.

[0059] Here, as shown in the above equation (4), when the output voltage Vout is sufficiently lower than the input voltage Vin, the conduction period T ON In other words, in order to sufficiently reduce the output voltage Vout relative to the input voltage Vin, the off period T OFF Therefore, considering that the output voltage Vout is sufficiently lower than the input voltage Vin, the control circuit CC needs to control the high-side MOS transistor QH through the control circuit CC so that the off period T during which the high-side MOS transistor QH is turned off OFF In other words, during the off period of the high-side MOS transistor QH, a longer off period T OFF This means a longer on-period of the low-side MOS transistor QL. Therefore, especially when the output voltage Vout is low enough, the on-period of the low-side MOS transistor QL becomes longer, and therefore, in view of improving the efficiency of the DC-DC converter, the on-resistance of the low-side MOS transistor QL needs to be small enough.

[0060] <Related technical description>

[0061] As described above, for example, the step-down DC-DC converter CV is configured to output a desired voltage by periodically repeating a switching operation. In the switching operation, a current is turned on / off.

[0062] Therefore, when there is a large parasitic inductance in the buck DC-DC converter CV, the high-frequency noise generated by the current change caused by the switching operation will become larger. Therefore, the buck DC-DC converter CV becomes a large source of high-frequency noise, which has an adverse effect on the electronic components in the periphery of the buck DC-DC converter CV.

[0063] Therefore, it is desirable to reduce the high frequency noise generated from the step-down DC-DC converter. In this regard, there is a related art for reducing the high frequency noise. Therefore, the related art will be described first below.

[0064] The "related technology" cited in this specification is a technology with a problem newly discovered by the inventor, rather than a known prior art. Although it is not a known prior art, it is a technology described as a prerequisite technology (unknown technology) for obtaining a new technical concept.

[0065] Figure 3 is a circuit diagram showing the configuration of a step-down DC-DC converter CV according to the related art.

[0066] exist Figure 3 In the related art, a step-down DC-DC converter CV is connected to a power supply E for supplying an input voltage, and an input capacitor Cin is connected in parallel with the power supply E. Between the power supply potential of the power supply E and the ground potential (reference potential) of the power supply E, a high-side element SW1 and a low-side element SW2, for example, formed by a field effect transistor (MOS transistor), are connected in series. At this time, each of the high-side element SW1 and the low-side element SW2 is used as a switching element. Since the high-side element SW1 and the low-side element SW are connected to each other by, for example, a wiring pattern, Figure 3 , the parasitic inductance L1 present in the wiring pattern is illustrated in FIG. Similarly, since the low-side element SW is connected to the wiring pattern to be supplied with the ground potential, Figure 3 Also shown is a parasitic inductance L2 present in a wiring pattern to be supplied with a ground potential.

[0067] Next, in Figure 3In the embodiment, the inductor Lc is connected to the connection node between the high-side element SW1 and the low-side element SW2, and the load RL is connected between the inductor Lc and the wiring pattern to be supplied with the ground potential. That is, the step-down DC-DC converter CV is configured to generate an output voltage between the inductor Lc and the interconnection pattern to be supplied with the ground potential, and the output voltage is applied to the load RL. Since the output capacitor Cout is connected in series with the load RL, and the output capacitor Cout is connected to the wiring pattern to be supplied with the ground potential, the parasitic inductance L3 existing in the wiring pattern is Figure 3 As described above, the circuit of the step-down DC-DC converter CV in the related art is configured.

[0068] In a step-down DC-DC converter CV according to the related art, a switching operation is performed in each of the high-side element SW1 and the low-side element SW2. Specifically, an on / off operation of turning on the high-side element SW1 and turning off the low-side element SW2, and an off / on operation of turning off the high-side element SW1 and turning on the low-side element SW2 are repeated. Here, there is actually a transition period between the on / off operation and the off / on operation, in which the high-side element SW1 and the low-side element SW2 are turned on at the same time. During the transition period, for example, Figure 3 In the example, as a result of the high-side element SW1 and the low-side element SW2 being turned on at the same time, the power supply potential and the ground potential are short-circuited, and a large current flows between the power supply potential and the ground potential. Therefore, considering the fact that high-frequency noise (noise voltage) is represented by the product of parasitic inductance and current change, it can be understood that, for example, when Figure 3 When the magnitude of the parasitic inductance L1 and the parasitic inductance L2 increases, a large high-frequency noise is generated in the transition period. In particular, in the transition period, since a large current flows in a short time, the current change rate also increases, and the high-frequency noise increases.

[0069] For this reason, in the step-down DC-DC converter CV, it is particularly essential to reduce the high-frequency noise generated during the transition period. In this regard, since it is difficult to reduce the current change rate and thus reduce the high-frequency noise, the magnitude of the parasitic inductance L1 and the parasitic inductance L2 must be reduced as much as possible to reduce the high-frequency noise during the transition period.

[0070] Therefore, in the related art, in order to minimize the magnitude of the parasitic inductance L1 and the parasitic inductance L2 as much as possible, for example, a device is manufactured to minimize the magnitude of the parasitic inductance L1 and the parasitic inductance L2. Figure 3 The path length of the loop 100 shown in FIG. This is because if Figure 3If the path length of the loop 100 shown in FIG. 1 can be minimized, the magnitude of the parasitic inductance L1 and the parasitic inductance L2 can be reduced. That is, since the magnitude of the parasitic inductance L1 and the parasitic inductance L2 decreases as the length of the wiring pattern becomes shorter, the related art attempts to minimize the parasitic inductance L1 and the parasitic inductance L2 by design. Figure 3 The path length of the loop 100 shown in FIG. 1 is minimized, thereby reducing the parasitic inductance L1 and the parasitic inductance L2. Specifically, in the related art, the installation layout is designed to minimize the parasitic inductance L1 and the parasitic inductance L2. Figure 3 The path length of the loop 100 is shown in FIG.

[0071] Figure 4 1 is a plan view showing the installation layout of a step-down DC-DC converter CV according to the related art. Figure 4 In the example, an input pattern WI, an output pattern WO, a wiring pattern W1, and a wiring pattern W2 are formed on a wiring substrate. Figure 4 As shown in FIG, a semiconductor component SP1 forming a high-side element is installed between the input pattern WI and the wiring pattern W1. Similarly, a semiconductor component SP2 forming a low-side element is installed between the wiring pattern W1 and the wiring pattern W2. In the related art, an inductor component LP is installed between the wiring pattern W1 and the output pattern WO. In addition, in the related art, a capacitive component CP1 forming an input capacitor is installed between the input pattern WI and the wiring pattern W2, and a capacitive component CP2 forming an output capacitor is installed between the wiring pattern W2 and the output pattern WO.

[0072] In the step-down DC-DC converter CV of the related art configured as described above, the semiconductor component SP1 forming the high-side element and the semiconductor component SP2 forming the low-side element are arranged close to each other. Figure 4 As shown in FIG. 1 , the parasitic inductance L1 existing between the semiconductor component SP1 and the semiconductor component SP2 and the parasitic inductance L2 caused by the interconnection pattern W2 connected to the semiconductor component SP2 can be reduced. In this way, according to the mounting layout in the related art, it is considered that the parasitic inductance L1 and the parasitic inductance L2 can be reduced.

[0073] However, even if Figure 3The path length of the loop 100 shown in the figure is minimized, and the parasitic inductance L1 and the parasitic inductance cannot be eliminated. That is, in the related art, the parasitic inductance L1 and the parasitic inductance L2 are limited by the ratio of the component size, resulting in that the limitation can be reduced. That is, in the related art, it is difficult to reduce the high-frequency noise generated in the transition period to a predetermined amount or less. Therefore, in the related art, in order to further reduce the high-frequency noise, countermeasures for high-frequency noise are required, such as noise countermeasures for bypass capacitors and buffer circuits. Therefore, in the related art, the increase in the size of electronic equipment and the increase in the manufacturing cost of electronic equipment are caused by the increase in the number of components constituting the step-down DC-DC converter CV. That is, in the related art, the high-frequency noise countermeasures are not enough. That is, without increasing the size and manufacturing cost of the electronic equipment constituting the step-down DC-DC converter CV, from the perspective of achieving sufficient countermeasures for high-frequency noise, there is still room for improvement in the related art. Therefore, the present embodiment designs measures to deal with the scope of improvement existing in the related art. Hereinafter, the technical concept of applying the present invention to the present embodiment will be described.

[0074] <Circuit Configuration of Step-Down DC-DC Converter According to Embodiment>

[0075] Figure 5 is a circuit diagram showing a step-down (voltage drop) type DC-DC converter CV1 according to the embodiment.

[0076] exist Figure 5 In the embodiment, a power source E for supplying an input voltage to the step-down DC-DC converter CV1 is connected to the step-down DC-DC converter CV1 in the present embodiment, and an input capacitor Cin is connected in series with the power source E. In the present embodiment, the step-down DC-DC converter CV1 having the high-side element SW1 and the low-side element SW2 is connected between the power source potential and the ground potential. Here, in Figure 5 , a parasitic inductance L1 present at a connection portion between the high-side element SW1 and the low-side element SW2 is shown. Figure 5 Also shown is a parasitic inductance L2 present in the second wiring portion between the low-side device SW2 and the ground potential. Here, each of the high-side element SW1 and the low-side element SW2 is composed of, for example, a field effect transistor MOSFET as a switching element.

[0077] As in Figure 5 As shown in FIG. 1 , in the step-down DC-DC converter CV1 of the present embodiment, the high-side element SW1 and the low-side element SW2 connected in series with each other are arranged to form a closed loop in a plan view. Figure 5As shown in , the high-side element SW1 and the low-side element SW2 are arranged facing each other. The wiring connecting the high-side element SW1 and the low-side element SW2 (the first wiring including the parasitic inductance L1) and the wiring connecting the low-side element SW2 and the ground potential (the second wiring including the parasitic inductance L2) are also arranged facing each other. In particular, in the plan view, the second wiring connecting the low-side element SW2 and the ground potential crosses the high-side element SW1. This is as shown in Figure 5 A loop is formed in the plan view shown in FIG.

[0078] The first wiring that couples the high-side element SW1 and the low-side element SW2 to each other, and the second wiring that couples the low-side element SW2 and the ground potential to each other are configured to include a region 200, wherein the first wiring and the second wiring are parallel to each other (more preferably, in parallel) through such a loop in a plan view. In particular, in the region 200, the first wiring and the second wiring are arranged close to each other so that the distance between the first wiring and the second wiring in the region 200 is the minimum distance among the distances between the first wiring and the second wiring.

[0079] Then, as in Figure 5 As shown in FIG. 1 , the step-down DC-DC converter CV1 in the present embodiment includes an inductor Lc, one end of which is connected to a connection node between the high-side element SW1 and the low-side element SW2, and the other end of the inductor Lc is connected to a load RL. In particular, according to the step-down DC-DC converter CV1 of the present embodiment, an output voltage is output between the other end of the inductor Lc and the ground potential, and the output voltage is supplied to the load RL. As shown in FIG. Figure 5 As shown in FIG. 1 , the step-down DC-DC converter CV1 of the present embodiment further has an output capacitor Cout connected in parallel with the load RL. A parasitic inductance L3 exists in the wiring connecting the output capacitor Cout and the ground potential, and the wiring having the parasitic inductance L3 and the inductor Lc is arranged close to each other. That is, as shown in FIG. Figure 5 As shown in FIG. 3 , the wiring having the parasitic inductance L3 is configured to include the region 300 connected in parallel with the inductor Lc. As described above, the step-down DC-DC converter CV1 in the present embodiment is configured.

[0080] <Circuit Operation of Step-Down DC-DC Converter According to Embodiment>

[0081] Next, the circuit operation of the step-down type DC-DC converter CV1 in the present embodiment will be described.

[0082] The buck DC-DC converter CV1 in the present embodiment performs a switch operation on each element of the high-side element SW1 and the low-side element SW2 to generate an output voltage whose absolute value is lower than the input voltage from the input voltage. Specifically, the buck DC-DC converter CV1 in the present embodiment generates an output voltage lower than the input voltage by repeatedly connecting the high-side element SW1 and disconnecting the on / off operation of the low-side element SW2, and repeatedly disconnecting the high-side element SW1 and connecting the off / on operation of the low-side element SW2. At this time, there is a transition period between the on / off operation and the off / on operation, and in the transition period, the high-side element SW1 and the low-side element SW2 are both connected at the same time, and therefore, the through current (short-circuit current) flows between the power supply potential and the ground potential.

[0083] Figure 6 is a circuit diagram showing the current path of the current flowing through the step-down DC-DC converter CV1 during the on / off operation (on period). Figure 6 In the on / off operation of turning on the high-side element SW1 and turning off the low-side element SW2, the current flows through the path consisting of "power supply potential", "high-side element SW1", "inductor Lc", "output capacitor Cout (load RL)" and "ground potential" in sequence. Here, as in Figure 6 As shown in , the direction of the current flowing through the inductor Lc (current direction) and the direction of the current flowing through the parasitic inductance L3 (current direction) are opposite to each other (the parasitic inductance L3 is close to and parallel to the inductor Lc).

[0084] Next, Figure 7 is a circuit diagram showing the current path of the current flowing through the step-down DC-DC converter CV1 during the transition period. Figure 7 In the transition period when the high-side element SW1 is turned on and the low-side element SW2 is turned on at the same time, the current mainly flows through the path consisting of "power supply potential", "high-side element SW1", "low-side element SW2" and "ground potential" in sequence. Here, as in Figure 7 As shown in FIG. 1 , currents in opposite directions flow through the parasitic inductance L1 and the parasitic inductance L2 (which are close to each other and in parallel), respectively.

[0085] Next, Figure 8 is a circuit diagram showing the current path of the current flowing through the step-down DC-DC converter CV1 during the OFF / ON operation (OFF period). Figure 8 In the example, when the high-side element SW1 is turned off and the low-side element SW2 is turned on, the current flows through the path consisting of "ground potential", "low-side element SW2", "inductor Lc", "output capacitor Cout (load RL)" and "ground potential" in sequence. Figure 8As shown in FIG. 1 , currents in opposite directions flow in the parasitic inductance L1 and the parasitic inductance L2 (which are close to each other and in parallel), and currents in opposite directions also flow in the inductor Lc and the parasitic inductance L3 (which are close to each other and in parallel).

[0086] As described above, in the step-down DC-DC converter CV1 of the present embodiment, the Figure 6 The on / off operation shown in Figure 7 The transition period operation shown in Figure 8 The off / on operation shown in FIG. 1 is performed, whereby the input voltage (power supply potential) supplied from the power supply E to the load RL outputs an output voltage whose absolute value is smaller than the input voltage.

[0087] <Regarding Features of Circuit According to Embodiment>

[0088] Next, the features (characteristic points) of the circuit of the step-down DC-DC converter CV1 in this embodiment will be described. The first feature of this embodiment is that, for example, Figure 5 As shown in , the first wiring (first wiring portion) coupling the high-side element SW1 and the low-side element SW2 to each other, and the second wiring (second wiring portion) coupling the low-side element SW2 and the ground potential to each other are arranged close to each other and in parallel (more preferably, in parallel with each other). That is, the first feature of the present embodiment is that the arrangement relationship of the high-side element SW1 and the low-side element SW2 coupled in series with each other is designed so as to provide a region 200 in which the first wiring and the second wiring are parallel to each other (more preferably, in parallel with each other). More specifically, as shown in Figure 5 As shown in , the connection path between the high-side element SW1 and the low-side element SW2 is designed so as to form a closed loop in the plan view. Therefore, according to the first feature in the present embodiment, the effective inductance in the region 200 where the first wiring and the second wiring are parallel to each other can be reduced. This is because the effective inductance between the first wiring and the second wiring is reduced by arranging the first wiring and the second wiring where the current flows in opposite directions close to each other and in parallel with each other. Therefore, according to the first feature of the present embodiment, the high-frequency noise generated during the transition period due to the presence of parasitic inductance L1 and parasitic inductance L2 in the current path of the through current flowing from the power supply potential to the ground potential can be reduced. In other words, according to the first feature in the present embodiment, since the effective inductance can be reduced by combining the parasitic inductance L1 and the parasitic inductance L2 with each other in the region 200, the generation of high-frequency noise proportional to the inductance can be reduced. In particular, from the perspective of reducing the effective inductance, it is desirable to reduce the distance between the first wiring where the current flows in one direction and the second wiring where the current flows in another direction opposite to the direction.

[0089] As described above, the basic concept underlying the first feature in the present embodiment is to reduce high-frequency noise by coupling the parasitic inductance L1 and the parasitic inductance L2 to each other so as to reduce the effective inductance. According to this concept, even if the parasitic inductance L1 and the parasitic inductance L2 are inevitably present, the effective inductance can be reduced. That is, the basic concept in the present embodiment is not to reduce each parasitic inductance of the parasitic inductance L1 and the parasitic inductance L2, but to couple the parasitic inductance L1 and the parasitic inductance L2 to each other so that the effective inductance becomes smaller. In this respect, the basic concept in the present embodiment is different from the related art that focuses on reducing the parasitic inductance L1 and the parasitic inductance L2 itself. In particular, in the related art that focuses on reducing the parasitic inductance L1 and the parasitic inductance L2 itself, since the parasitic inductance L1 and the parasitic inductance L2 themselves cannot be eliminated, there is a limit to reducing the parasitic inductance L1 and the parasitic inductance L2 themselves, and it is impossible to suppress the generation of high-frequency noise exceeding a certain amount.

[0090] On the other hand, according to the basic concept in the present embodiment, even if there are parasitic inductance L1 and parasitic inductance L2, the effective inductance can be reduced by coupling the parasitic inductance L1 and the parasitic inductance L2, so that the effective inductance can be reduced to the minimum value of the parasitic inductance L1 and the parasitic inductance L2 or less. Therefore, according to the basic concept in the present embodiment, it is also possible to achieve the reduction of high-frequency noise that is difficult to achieve by the related art. Therefore, according to the present embodiment, noise countermeasures such as bypass capacitors and buffer circuits for high-frequency noise are not required. Therefore, in the present embodiment, the increase in the number of components constituting the step-down DC-DC converter CV1 can be suppressed. Therefore, according to the present embodiment, while achieving sufficient measures for high-frequency noise, the size of the electronic device can be reduced and the manufacturing cost can be reduced.

[0091] Next, the second feature of this embodiment is that, for example, Figure 5 As shown in FIG. 1 , the wiring that couples the output capacitor Cout and the ground potential to each other is arranged close to the inductor Lc and in parallel with the inductor Lc (more preferably, in parallel with the inductor Lc). In other words, the second feature of the present embodiment is that, for example, as in Figure 5As shown in FIG. 3 , the wiring that couples the output capacitor Cout and the ground potential to each other includes a region 300 that is close to the inductor Lc and also parallel to the inductor Lc (more preferably, in parallel to the inductor Lc). Therefore, high-frequency noise generated by the load current including noise such as humming flowing through the inductor Lc can be suppressed. That is, according to the second feature in the present embodiment, since the wiring that couples the output capacitor Cout and the ground potential is close to the inductor Lc and in parallel with the inductor Lc, the inductance of the inductor Lc and the parasitic inductance L3 of the wiring that couples the output capacitor Cout and the ground potential to each other are combined with each other, thereby reducing the effective inductance. In other words, according to the second feature in the present embodiment, the wiring that couples the output capacitor Cout and the ground potential to each other is arranged near the inductor Lc and in parallel with the inductor Lc. In addition, according to the second feature in the present embodiment, the direction of the current flowing through the wiring that couples the output capacitor Cout and the ground potential to each other, and the direction of the current flowing through the inductor Lc are opposite to each other. Therefore, since the effective inductance is reduced by coupling the inductance of the inductor Lc and the parasitic inductance L3 of the wiring to each other, both of the generation of high-frequency noise caused by the inductor Lc and the generation of high-frequency noise caused by the parasitic inductance L3 can be suppressed. That is, according to the second feature in the present embodiment, in order to reduce the high-frequency noise generated by the inductor Lc and the high-frequency noise generated by the parasitic inductance L3, the effective inductance is reduced by combining the inductance of the inductor Lc and the parasitic inductance L3 present in the wiring that couples the output capacitor Cout and the ground potential to each other. Therefore, the generation of high-frequency noise caused by the inductance of the inductor Lc and the parasitic inductance L3 can be suppressed.

[0092] The high-frequency noise generated by the inductor Lc is represented by the inductance of the inductor Lc multiplied by the current change rate. In this regard, since the load current flowing through the inductor Lc does not change with time in a steady state, the current change rate becomes zero. Therefore, since the continuously flowing load current does not affect the generation of high-frequency noise, the low-voltage DC-DC converter CV1 in this embodiment can suppress the generation of high-frequency noise without affecting the electric power conversion efficiency.

[0093] As described above, by adopting the first feature of the present embodiment, the generation of high-frequency noise caused by each parasitic inductance of the parasitic inductance L1 and the parasitic inductance L2 can be reduced. On the other hand, by adopting the second feature in the present embodiment, the generation of high-frequency noise caused by the inductance of the inductor Lc and the parasitic inductance L3 can be reduced. Therefore, by adopting at least one of the first feature in the present embodiment and the second feature in the present embodiment, the high-frequency noise generated from the step-down DC-DC converter CV1 can be suppressed. In this regard, from the perspective of sufficiently suppressing the generation of high-frequency noise in the step-down DC-DC converter CV1, it is desirable to adopt both the above-mentioned first feature and the second feature. This is because, by adopting both the first feature and the second feature in the present embodiment, not only the high-frequency noise caused by the parasitic inductance L1 and the parasitic inductance L2 can be suppressed, but also the high-frequency noise caused by the inductance of the inductor Lc and the parasitic inductance L3 can be suppressed.

[0094] In the step-down DC-DC converter CV1 of the present embodiment, noise countermeasures such as bypass capacitors and buffer circuits for high-frequency noise are not required. Therefore, in the present embodiment, the increase in the number of components constituting the step-down DC-DC converter CV1 can be suppressed. Therefore, according to the present embodiment, the size of the electronic device can be reduced and the manufacturing cost can be reduced while achieving sufficient measures for high-frequency noise, thereby obtaining a significant effect.

[0095] <Mounting Configuration of Step-Down DC-DC Converter According to Embodiment>

[0096] Next, the mounting configuration of the step-down type DC-DC converter CV1 in the present embodiment will be described.

[0097] Fig. 9 1 is a plan view schematically showing the wiring layout of the wiring substrate constituting the step-down DC-DC converter CV1 according to the present embodiment. The wiring substrate WB in the present embodiment is composed of, for example, a rigid substrate of epoxy resin, polyimide resin, maleimide resin, etc. impregnated in glass fiber. The wiring substrate WB has, for example, a multilayer wiring structure, and, for example, as in Fig. 9 As shown in FIG. 1 , a plurality of wiring portions are formed on the surface of the wiring substrate WB.

[0098] exist Fig. 9 In the present embodiment, a power supply wiring portion 10 to which a power supply potential is to be supplied is formed on the surface of the wiring substrate WB. The first wiring portion 11 is spaced apart from the power supply wiring portion 10. Furthermore, a second wiring portion 14 is formed on the surface of the wiring substrate WB so as to be inserted between the power supply wiring portion 10 and the first wiring portion 11 in a plan view. The second wiring portion 14 includes a portion passing between the power supply wiring portion 10 and the first wiring portion 11 and forming a Figure 5 The extended portion 12 which is a part of the region 200 shown in FIG. 1 , and the large-area portion 13 connected to the extended portion 12. The ground potential is supplied to the second wiring portion 14 configured as described above.

[0099] In addition, Fig. 9 In the embodiment, the output wiring portion 15 is formed at a position spaced apart from the first wiring portion 11 and the second wiring portion 14 in a plan view. The output voltage is output from the output wiring portion 15. Fig. 9 In the embodiment, the gate wiring portion 16 is formed in the vicinity of the second wiring portion 14 , and the gate wiring portion 17 is formed in the vicinity of the first wiring portion 11 .

[0100] In the wiring substrate WB configured as described above, as in Fig. 9 As shown in FIG. 2 , parasitic inductance L1 exists on the first wiring portion 11, and parasitic inductance L2 exists on the extension portion 12 of the second wiring portion 14. The first wiring portion 11 having parasitic inductance L1 and the extension portion 12 of the second wiring portion 14 having parasitic inductance L2 are arranged close to each other and in parallel. Therefore, it can be seen that the portion 200 is formed in Fig. 9 On the other hand, as shown in the wiring substrate WB Fig. 9 As shown in FIG. 1 , the parasitic inductance L3 exists in the large area portion 13 of the second wiring portion 14 .

[0101] Then, as in Fig. 9 As shown in FIG. 1 , the via VA is connected to the vicinity of the connection portion between the large area portion 13 of the second wiring portion 14 and the extension portion 12 of the second wiring portion 14. That is, the wiring substrate WB in the present embodiment has a first wiring layer forming the first wiring portion 11, the second wiring portion 14, the power supply wiring portion 10, and the output wiring portion 15, and the wiring substrate WB has a multilayer wiring configuration including a second wiring layer different from the first wiring layer. In the second wiring layer different from the first wiring layer, another wiring portion is formed, and, for example, as in Fig. 9 As shown in FIG. 1 , the second wiring portion 14 and another wiring portion are connected through a via VA near a connection region between the extension portion 12 and the large area portion 13 .

[0102] As described above, a plurality of wiring portions (wiring patterns) for realizing the step-down type DC-DC converter CV1 in the present embodiment are formed in the wiring substrate WB.

[0103] Next, Fig.10 1 is a plan view schematically showing a state in which components constituting the step-down DC-DC converter CV1 are mounted on a wiring substrate WB. Fig.10In the embodiment, the semiconductor component SP1 is arranged on the wiring substrate WB so as to cross the extension portion 12 of the second wiring portion 14, and the semiconductor component SP1 is arranged on the wiring substrate WB so as to connect the power supply wiring portion 10 with the first wiring portion 11. Specifically, for example, the components Figure 5 The field effect transistor (power transistor) of the high-side element ( SW1 ) shown in is formed in the semiconductor component SP1 .

[0104] At this time, the drain of the high-side element is connected to the power wiring portion 10 , the source of the high-side element is connected to the first wiring portion 11 , and the gate of the high-side element is connected to the gate wiring portion 16 .

[0105] Subsequently, the semiconductor component SP2 is arranged on the wiring substrate WB so as to connect the first wiring portion 11 with the second wiring portion 14. More specifically, the components such as Figure 5 A field effect transistor (power transistor) of the low-side element (SW2) shown in FIG. 1 is also formed in the semiconductor component SP2. Here, the drain of the low-side element is connected to the first wiring portion 11, the source of the low-side element is connected to the extension portion 12 of the second wiring portion 14, and the gate of the low-side element is connected to the gate wiring portion 17.

[0106] In addition, as in Fig.10 As shown in FIG. 1 , the capacitive component CP1 is arranged on the wiring substrate WB so as to connect the power wiring portion 10 with the large area portion 13 of the second wiring portion 14. For example, in the capacitive component CP1, the components Figure 5 The chip capacitor of the input capacitance Cin shown in FIG. 1 is formed. The capacitive component CP2 is arranged on the wiring substrate WB so as to connect the output wiring portion 15 with the large area portion 13 of the second wiring portion 14. The capacitive component CP2 is composed of, for example Figure 5 The output capacitor (Cout) shown in FIG. 1 is formed of a chip capacitor.

[0107] As in Fig.10 As shown in FIG. 1 , the inductor component LP is arranged on the wiring substrate WB so as to connect the first wiring portion 11 with the output wiring portion 15. For example, Figure 5 The inductor Lc shown in FIG. 1 is formed in the inductor part LP, and the inductor Lc is composed of one of the winding type inductor part and the chip inductor. At this time, as in Fig.10 As shown in FIG. 1 , the large-area portion 13 of the second wiring portion 14 includes a portion (region) in parallel with the inductor component LP.

[0108] In this way, the mounting layout for realizing the step-down DC-DC converter CV1 in this embodiment is constructed. Fig.10The installation layout shown in FIG. 1 realizes the first feature of this embodiment (in Figure 5 region 200 in the Figure 5 The circuit configuration of the region 300 in FIG. Figure 5 ).

[0109] Next, refer to Fig.10 1 and 2. The mounting layout of the step-down type DC-DC converter CV1 shown in FIG. 2 will now be described with reference to the drawings. A current path of a current flowing through the step-down type DC-DC converter CV1 will be described.

[0110] Fig.11 is an installation layout diagram showing the current path of the current flowing through the step-down DC-DC converter CV1 during the on / off operation (on period). Fig.11 In the on / off operation of turning on the high-side element SW1 and turning off the low-side element SW2, the current flows sequentially through the path consisting of the "power supply wiring portion 10 (power supply potential)", "semiconductor component SP1", "inductor component LP", "output wiring portion 15", "capacitor component CP2" and "large area portion 13 of the second wiring portion 14 (ground potential)".

[0111] Next, Fig.12 is an installation layout diagram showing the current path of the current flowing through the step-down DC-DC converter CV1 during the transition period. Fig.12 In the figure, during the transition period in which the high-side element SW1 is turned on and the low-side element SW2 is turned on at the same time, the current mainly flows in sequence through the path consisting of the "power supply wiring portion 10 (power supply potential)", "semiconductor component SP1", "first wiring portion 11", "semiconductor component SP2" and "extension portion 12 of the second wiring portion 14 (ground potential)".

[0112] Next, Fig.13 is an installation layout diagram showing the current path of the current flowing through the step-down DC-DC converter CV1 during the OFF / ON operation (OFF period). Fig.13 In the embodiment, when the high-side element SW1 is disconnected and the low-side element SW2 is turned on in the off / on operation, the current flows sequentially through the path consisting of "the large area portion 13 of the second wiring portion 14 (ground potential)", "the extended portion 12 of the second wiring portion 14", "the semiconductor component SP2", "the first wiring portion 11", "the inductor component LP", "the output wiring portion 15", "the capacitor component CP2" and "the large area portion 13 of the second wiring portion 14 (ground potential)".

[0113] As described above, in the step-down DC-DC converter CV1 of the present embodiment, by repeatedly Fig.11The on / off operation shown in Fig.12 The transition period operation shown in Fig.13 In the off / on operation shown in FIG. 1 , based on the input voltage (power supply potential) input to the power supply wiring unit 10 , an output voltage having an absolute value smaller than the input voltage is output from the output wiring unit 15 .

[0114] Here, for example, Fig.12 The region 200 is schematically shown. However, in Fig.12 The region 200 shown in FIG. 1 is a main region of the region 200, and the region 200 is not limited to the shape of the main region. Fig.12 The region 200 shown in FIG. 1 is configured to include the first wiring portion 11 and the second wiring portion 12 extending in parallel with each other in the y direction. At this time, the region 200 is defined as a portion including the following region in order to enhance the effect of reducing the effective inductance due to the combination of the parasitic inductance of the first wiring portion 11 and the parasitic inductance of the extension portion 12 of the second wiring portion 14. That is, in Fig.12 The region 200 shown in FIG. 1 is defined as a portion including a region in which at least the direction of the current flowing through the first wiring portion 11 and the direction of the current flowing through the extending portion 12 of the second wiring portion 14 are opposite to each other, and Fig.12 In the embodiment, the maximum distance D1 between the extension portions 12 of the first wiring portion 11 and the second wiring portion 14 is smaller than the first wiring layer (such as in Fig.12 The wiring layer shown in FIG. 1 ) is located one layer lower than the first wiring layer (in FIG. Fig.12 This is because, when the maximum distance D1 between the first wiring portion 11 and the extending portion 12 of the second wiring portion 14 in the region 200 is greater than the distance D2 between the first wiring layer and the second wiring layer in the thickness direction of the wiring substrate WB, the effect of reducing the effective inductance is weakened due to the coupling between the parasitic inductance existing in the first wiring portion 11 and the parasitic inductance existing in the extending portion 12 of the second wiring portion 14.

[0115] Since the distance D2 between the first wiring layer and the second wiring layer in the thickness direction of the wiring substrate WB is, for example, 0.15 mm, it is desirable that the maximum distance D1 between the extension portions 12 of the first wiring portion 11 and the second wiring portion 14 in the region 200 is less than 0.15 mm. More specifically, the maximum distance D1 between the extension portions 12 of the first wiring portion 11 and the second wiring portion 14 in the region 200 is desirable to be 0.1 mm or less. However, when the distance (D2) between the first wiring layer and the second wiring layer in the thickness direction of the wiring substrate WB is less than 0.1 mm (such as 0.065 mm), by designing that a wiring pattern that does not overlap with the region 200 in a plane is arranged in a second wiring layer located one layer below the first wiring layer, the following relationship can be maintained: the maximum distance D1 between the extension portions 12 of the first wiring portion 11 and the second wiring portion 14 in the region 200 is greater than the distance (D2) between the first wiring layer and the second wiring layer in the thickness direction of the wiring substrate WB. In this case, the effective inductance can be reduced by a combination of the parasitic inductance existing in the first wiring portion 11 and the parasitic inductance existing in the extending portion 12 of the second wiring portion 14 .

[0116] Next, for example, Fig.13 The area 300 is schematically shown. However, in Fig.13 The portion 300 shown in FIG. 1 is a main region of the portion 300, and the portion 300 is not limited to the shape of the main region. Fig.13 The region 300 shown in FIG. 1 is configured to include the inductor component LP and the second wiring portion 12 extending in parallel with each other in the x direction. At this time, the region 300 is defined as a portion including the following region in order to enhance the effect of reducing the effective inductance due to the coupling between the parasitic inductance of the inductor component LP and the parasitic inductance of the large area portion 13 of the second wiring portion 14. That is, in Fig.13 The region 300 shown in FIG. 1 is defined as a portion including a region in which at least the direction of the current flowing through the inductor part LP and the direction of the current flowing through the large area portion 13 of the second wiring portion 14 are opposite to each other, and the maximum distance D3 between the large area portion 13 of the first wiring portion 11 and the second wiring portion 14 is smaller than the first wiring layer (in the case of the first wiring layer 11 and the second wiring portion 12) respectively forming the first wiring portion 11 and the second wiring portion 12. Fig.13 The wiring layer shown in FIG. 1 ), and the wiring layer located one layer lower than the first wiring layer (in FIG. 1 ). Fig.1214). Therefore, the distance D4 between the inductor component LP and the large area portion 12 of the second wiring portion 14 is necessarily smaller than the maximum distance D3 between the first wiring portion 11 and the large area portion 13 of the second wiring portion 14. Therefore, in the region 300, the inductor component LP and the large area portion 13 of the second wiring portion 14 are arranged close to each other, whereby the effect of reducing the effective inductance due to the coupling between the parasitic inductance existing in the large area portion 13 of the second wiring portion 14 and the parasitic inductance existing in the inductor component LP can be exhibited.

[0117] Since the distance D2 between the first wiring layer and the second wiring layer in the thickness direction of the wiring substrate WB is, for example, 0.15 mm, it is desirable that the maximum distance D3 between the large area portion 13 of the first wiring portion 11 and the second wiring portion 12 in the region 300 should be less than 0.15 mm. More specifically, the maximum distance D3 between the large area portion 13 of the first wiring portion 11 and the second wiring portion 12 in the region 300 is desirable to be 0.1 mm or less. However, for example, when the interval (D2) between the first wiring layer and the second wiring layer in the thickness direction of the wiring substrate WB is less than 0.1 mm (such as 0.065 mm), by designing that a wiring pattern that does not overlap with the region 300 in a plane is arranged in the second wiring layer located at a lower layer of the first wiring layer, the following relationship can be maintained: the maximum interval D3 between the large area portion 13 of the first wiring portion 11 and the second wiring portion 14 in the region 300 is greater than the interval (D2) between the first wiring layer and the second wiring layer in the thickness direction of the wiring substrate WB. In this case, the effective inductance can be reduced by coupling between the parasitic inductance existing in the inductor part LP and the parasitic inductance existing in the large-area portion 13 of the second wiring portion 14 .

[0118] <Installation Features According to Embodiment>

[0119] Next, the installation features (characteristic points) of the step-down DC-DC converter CV1 in the present embodiment will be described. The third feature of the present embodiment is that, for example, Fig.10In the embodiment of the present invention, the configuration of the inductor component LP is designed so that the direction of the current flowing through the inductor component LP and the direction of the current flowing through the large area portion 13 of the second wiring portion 14 are opposite to each other. More specifically, the inductor component LP may be composed of one of a winding type inductor component and a chip inductor. For example, when the inductor component LP is composed of a winding type inductor component, the winding direction of the winding is set so that the direction of the current flowing through the inductor component LP and the direction of the current flowing through the large area portion 13 of the second wiring portion 14 are opposite to each other. Therefore, a configuration is achieved in which the direction of the current flowing through the parasitic inductance L3 present in the large area portion 13 of the second wiring portion 14 and the direction of the current flowing through the inductor component LP are opposite to each other, and the portion in which the parasitic inductance L3 exists and the inductor component LP are arranged close to each other and in parallel with each other. Therefore, since the effective inductance is reduced by combining the parasitic inductance L3 and the inductance of the inductor component LP, the high-frequency noise caused by the inductor component LP and the high-frequency noise caused by the parasitic inductance L3 can be reduced.

[0120] Next, as in Fig.10 As shown in FIG. 1 , for example, the fourth feature in the present embodiment is that the arrangement position of the via hole VA is set near the connection area between the extension portion 12 of the second wiring portion 14 and the large area portion 13, and the via hole connects the second wiring portion 14 supplied with the ground potential and the ground wiring formed in the first wiring layer different from the second wiring layer forming the second wiring portion 14. In other words, the fourth feature in the present embodiment is that the arrangement position of the via hole VA is set near the connection area between the extension portion 12 and the large area portion 13 of the second wiring portion 14. Fig.10 Thus, for example, as in Fig.11 and Fig.13 As shown in , the current can flow through the path consisting of "capacitive component CP2", "large area portion 13 of the second wiring portion 14" ("portion where parasitic inductance L3 exists") and "via VA" in sequence. That is, by arranging the via VA to realize the fourth feature in the present embodiment, it is possible to cause the current flowing through the large area portion 13 of the second wiring portion 14 to flow in the opposite direction to the current flowing through the inductor component LP. Therefore, the second feature in the present embodiment described above is realized. That is, when the fourth feature in the present embodiment is adopted, the inductance of the inductor component LP and the parasitic inductance L3 of the second wiring portion 14 are coupled to each other to cause the effect of reducing the effective inductance. Therefore, according to the fourth feature of the present embodiment, both of the following can be suppressed: the occurrence of high-frequency noise caused by the inductor component LP, and the generation of high-frequency noise caused by the parasitic inductance L3.

[0121] <Effects of the Embodiment>

[0122] Next, the effects in this embodiment will be described.

[0123] Fig.14 is a graph showing the conducted EMI (electromagnetic interference) characteristics according to the related art. Fig.14 In , the horizontal axis represents frequency (Hz), and the vertical axis represents noise level (dBμV). Fig.14 In , "12-M", "10-K" and "8-H" indicate standards based on the international standard IEC61967-4, for example, "8-H" indicates a looser standard, and "12-M" indicates the strictest standard. Fig.14 As shown in FIG. 1 , in the related art, the standard of "12-M" is not met, and it is understood that the EMI performance is not good enough. In particular, in the related art, although nine bypass capacitors (anti-noise capacitors) are installed in addition to the minimum two capacitors (power stabilization capacitors) required for the CV operation of the step-down DC-DC converter for removing high-frequency noise, it is understood that sufficient EMI performance cannot be achieved.

[0124] on the other hand, Fig.15 is a graph showing the conducted EMI characteristics according to this embodiment. Fig.15 In , the horizontal axis represents frequency (Hz), and the vertical axis represents noise level (dBμV). Fig.15 In , "12-M", "10-K" and "8-H" indicate standards based on the international standard IEC61967-4, for example, "8-H" indicates a looser standard, and "12-M" indicates the strictest standard. Fig.15 As shown in FIG. 1 , the step-down DC-DC converter CV1 in the present embodiment satisfies the most stringent "12-M" standard, and it can be understood that the EMI performance is sufficiently good. In particular, it can be seen that in the present embodiment, even if a bypass capacitor (noise countermeasure capacitor) for removing high-frequency noise is not installed in addition to the minimum two capacitors (power stabilization capacitor) required for the operation of the step-down DC-DC converter CV1, sufficient EMI performance can be achieved.

[0125] As described above, compared with the step-down DC-DC converter CV in the related art, the step-down DC-DC converter CV1 in the present embodiment can reduce 9 capacitive components, and therefore, can achieve sufficiently good EMI characteristics while reducing the component area by 59%. Therefore, it can be seen that the technical concept in the present embodiment is excellent, in which the electronic device can be miniaturized and the manufacturing cost can be reduced while achieving sufficient suppression of high-frequency noise.

[0126] Next, Fig.16 is a graph showing the relationship between load current and electric power conversion efficiency in a step-down DC-DC converter CV according to the related art. Fig.16 In FIG. 1 , the horizontal axis represents the load current (A), and the vertical axis represents the electric power conversion efficiency (%). Fig.16 As shown in , the maximum electric power conversion efficiency of the step-down DC-DC converter CV in the related art is 86.5%.

[0127] on the other hand, Fig.17 : is a graph showing the relationship between the load current and the electric power conversion efficiency in the step-down DC-DC converter CV1 according to the present embodiment. Fig.17 In FIG. 1 , the horizontal axis represents the load current (A), and the vertical axis represents the electric power conversion efficiency (%). Fig.17 As shown in FIG. 1 , the maximum power conversion efficiency of the step-down DC-DC converter CV1 in this embodiment is 87.9% of the maximum power conversion efficiency. Fig.16 and Fig.17 It can be seen that the buck DC-DC converter CV1 in this embodiment has a higher maximum electric power conversion efficiency than the buck DC-DC converter CV in the related art. This means that when the technical concept in this embodiment is adopted, sufficient high-frequency noise countermeasures can be achieved, and the maximum electric power conversion efficiency can also be improved. Therefore, it can be seen that the technical concept in this embodiment is a very excellent technical concept, which not only reduces the size of the electronic device and reduces the manufacturing cost, but also improves the maximum electric power conversion efficiency, and at the same time achieves sufficient suppression measures for high-frequency noise.

[0128] <Modified example>

[0129] Next, modification examples will be described.

[0130] Fig.18 1 is a plan view showing the installation layout of the step-down DC-DC converter CV2 according to the present modification example. Fig.18 In the step-down DC-DC converter CV2 of the present modification example, the input capacitor is formed using a plurality of capacitive components CP1, and the output capacitor is formed using a plurality of capacitive components CP2.

[0131] Therefore, according to the buck DC-DC converter CV2 of this modified example, the following advantages can be obtained. That is, the buck DC-DC converter CV2 is configured to output an output voltage less than the input voltage from the input voltage. The amplitude of the output voltage output from the buck DC-DC converter CV2 depends on the switching frequency. That is, in the buck DC-DC converter CV2, by setting the switching frequency to a predetermined frequency, the desired output voltage can be obtained. Here, the capacitance value of the input capacitor and the capacitance value of the output capacitor change based on the switching frequency. Therefore, when the input capacitor and the output capacitor are composed of a plurality of capacitive components, the number of the plurality of capacitive components can be adjusted to adjust the capacitance value of the input capacitor and the capacitance value of the output capacitor, thereby obtaining the desired output voltage. Further, in the case where the input capacitor and the output capacitor are composed of a plurality of capacitive components, even if a part of the capacitive components between the plurality of capacitive elements is defective, although the capacitance value changes due to the presence of other capacitive elements, an output voltage close to the desired output voltage can be ensured. As described above, according to the buck DC-DC converter CV2 of this modified example, the reliability of the buck DC-DC converter CV2 can be improved.

[0132] The invention of the present inventors has been described in detail above based on the embodiments, but the present invention is not limited to the embodiments described above, and it is needless to say that various modifications can be made without departing from the gist thereof.

Claims

1. An electronic device, comprising: A switching regulator comprising a high-side element and a low-side element, wherein the high-side element and the low-side element are coupled in series between a first potential and a second potential lower than the first potential, The switching regulator comprises: a first wiring portion coupling the high-side element and the low-side element to each other, and a second wiring portion coupled to the low-side element and supplied with the second potential, wherein the switching regulator has a first region where the first wiring portion and the second wiring portion are close to each other and parallel to each other, The operation period of the switching regulator includes: a conduction period during which the high-side element is turned on and the low-side element is turned off, a transition period during which the high-side element is turned on and the low-side element is turned on, and an off period during which the high-side element is turned off and the low-side element is turned on, and In the first region, a direction of a current flowing through the first wiring portion during each of the transition period and the turn-off period is opposite to a direction of a current flowing through the second wiring portion during each of the transition period and the turn-off period.

2. The electronic device according to claim 1, wherein the first wiring portion and the second wiring portion are formed in a first wiring layer of a wiring substrate, wherein the wiring substrate includes a second wiring layer located one layer below the first wiring layer, and Wherein in the first region, a maximum distance between the first wiring portion and the second wiring portion is smaller than a distance between the first wiring layer and the second wiring layer.

3. The electronic device according to claim 2, The maximum distance is 0.1 mm or less.

4. The electronic device according to claim 1, in, The second wiring portion intersects the high-side element in a plan view.

5. The electronic device according to claim 1, The switching regulator comprises: an inductor coupled with the first wiring portion, a third wiring portion coupled with the inductor and supplied with a third potential, and a capacitor coupling the third wiring portion and the second wiring portion to each other, and The second wiring portion has a second region parallel to the inductor.

6. The electronic device according to claim 5, wherein the inductor comprises a winding, and The winding direction of the winding is set so that the direction of the current flowing through the inductor and the direction of the current flowing through the second region are opposite to each other.

7. The electronic device according to claim 1, further comprising: a first semiconductor component including said high-side element, a second semiconductor component including said low-side element, and A wiring substrate includes the first wiring portion and the second wiring portion.

8. The electronic device according to claim 7, wherein the wiring substrate includes a power supply wiring portion supplied with the first potential, wherein the first wiring portion is spaced apart from the power supply wiring portion, and The second wiring portion includes: an extension portion passing between the power wiring portion and the first wiring portion and constituting a part of the first region, and A large area portion connected to the extension portion.

9. The electronic device according to claim 8, wherein the first semiconductor component is arranged on the wiring substrate so as to straddle the extending portion of the second wiring portion, and is arranged on the wiring substrate so as to connect the power supply wiring portion with the first wiring portion, and The second semiconductor component is arranged on the wiring substrate so as to connect the first wiring portion and the second wiring portion.

10. The electronic device according to claim 9, wherein the wiring substrate includes an output wiring portion supplied with a third potential, The electronic device according to claim 9 further comprises: an inductor arranged on the wiring substrate so as to connect the first wiring portion and the output wiring portion, and A capacitor is arranged on the wiring substrate so as to connect the large area portion and the output wiring portion.

11. The electronic device according to claim 10, The large-area portion has a second region parallel to the inductor.

12. The electronic device according to claim 11, wherein the first wiring portion and the second wiring portion are formed in a first wiring layer of the wiring substrate, wherein the wiring substrate includes a second wiring layer located one layer below the first wiring layer, and Wherein in the second region, a maximum distance between the large area portion and the first wiring portion is smaller than a distance between the first wiring layer and the second wiring layer.

13. The electronic device according to claim 12, In the second region, a distance between the large-area portion and the inductor is smaller than the maximum distance.

14. The electronic device according to claim 11, wherein the first wiring portion, the second wiring portion, the power supply wiring portion, and the output wiring portion are formed in a first wiring layer of the wiring substrate, wherein the wiring substrate includes a second wiring layer located one layer below the first wiring layer, wherein the wiring substrate includes other wiring portions formed in the second wiring layer, and The second wiring portion and the other wiring portions are electrically connected through a via hole formed in a connection region between the extension portion and the large area portion.

15. The electronic device according to claim 10, The large area portion is electrically connected to the output wiring portion through the plurality of capacitors.

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