Output configurable memory - in - computing chip and electronic device

Abstract

The present invention provides an output-configurable memory-computing integrated chip and an electronic device. The output-configurable memory-computing integrated chip includes a memory-computing unit array and a current detection output circuit; the current detection output circuit includes a plurality of current detection output branches; the analog current output terminal of each column of units in the memory-computing unit array is connected to a current detection output branch for processing and outputting the analog current output signal output by the analog current output terminal; wherein, the current detection output branch includes a plurality of resistors with different resistance values and a multiplexer for selecting resistors, so as to select resistors with different resistance values through the multiplexer, thereby realizing amplification of different magnitudes of output signals of different columns, and capable of realizing high-precision reading of the output signals of each column of memory-computing units according to the requirements of specific algorithms and applications.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuits, and in particular, to an output configurable memory - in - computing chip and an electronic device. Background Art

[0002] In recent years, in order to solve the bottleneck of the traditional von Neumann computing architecture, the memory - in - computing chip architecture has received extensive attention. Its basic idea is to directly use the memory for logical computing, thereby reducing the data transfer volume and transfer distance between the memory and the processor, and improving the performance while reducing power consumption.

[0003] The memory - in - computing chip architecture is currently considered to be one of the efficient hardware platforms for solving big data real - time intelligent processing, and the memory - in - computing unit array is the core circuit of the memory - in - computing chip.

[0004] Existing memory - in - computing chips that use Flash for matrix multiplication and addition operations use memory - in - computing units to perform matrix multiplication and addition operations. The output ends of each column of memory - in - computing units are output through a current detection output circuit. See Figure 1 , which shows the current detection output circuit in the gate - coupled memory - in - computing unit array. See Figure 2 , which shows the current detection output circuit in the source - coupled memory - in - computing unit array; it can be seen that the current detection output circuits used for each column of memory - in - computing units are the same, and it is difficult to achieve high - precision reading of each column of flash memory cells according to the requirements of specific algorithms and applications. Summary of the Invention

[0005] Aiming at the problems in the prior art, the present invention provides a configurable memory - in - computing chip and an electronic device, which can at least partially solve the problems existing in the prior art.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] In a first aspect, an output configurable memory - in - computing chip is provided, including: a memory - in - computing unit array and a current detection output circuit; the current detection output circuit includes a plurality of current detection output branches; the analog current output end of each column of memory - in - computing units in the memory - in - computing unit array is connected to a current detection output branch, which is used to process and output the analog current output signal output by the analog current output end;

[0008] Wherein, the current detection output branch includes a plurality of resistors with different resistances and a multiplexer for selecting resistors.

[0009] Further, the memory - in - computing unit array is of a gate - coupled structure;

[0010] The current detection output branch further includes: an operational amplifier, whose non-inverting input terminal is connected to a bias voltage, whose inverting input terminal is connected to the corresponding analog current output terminal, and whose output terminal serves as the output terminal of the current detection output branch;

[0011] Moreover, the inverting input terminal is further connected to one end of each resistor, the other ends of the resistors are respectively connected to multiple input terminals of the multiplexer in one-to-one correspondence, and the output terminal of the multiplexer is connected to the output terminal of the operational amplifier.

[0012] Furthermore, the in-memory computing unit array is a source-coupled structure;

[0013] The current detection output branch further includes: a capacitor;

[0014] One end of the capacitor and each resistor is connected to the corresponding analog current output terminal and serves as the output terminal of the current detection output branch;

[0015] The other end of the capacitor is connected to a power supply; the other ends of the resistors are respectively connected to multiple input terminals of the multiplexer in one-to-one correspondence, and the output terminal of the multiplexer is connected to the power supply.

[0016] Furthermore, the output-configurable in-memory computing chip further includes: an ADC (Analog-to-Digital Converter); the ADC is connected to the output terminal of the current detection output branch.

[0017] Furthermore, there are multiple capacitors with different capacitance values, and the current detection output branch further includes: a capacitor multiplexer;

[0018] The other ends of the capacitors are selectively connected to the power supply through the capacitor multiplexer.

[0019] Furthermore, the in-memory computing unit is a programmable semiconductor device.

[0020] Furthermore, the programmable semiconductor device is a floating-gate transistor, a resistive random access memory device, a phase change memory device, or a spin memory device.

[0021] Furthermore, the output-configurable in-memory computing chip further includes:

[0022] A programming circuit, connected to the source, gate, and / or substrate of each programmable semiconductor device, for regulating the threshold voltage of the programmable semiconductor device.

[0023] Further, the output configurable memory - in - computing chip further includes: a conversion device connected before the multiple analog voltage input ends of the memory - in - computing unit array, configured to convert multiple analog current input signals into analog voltage input signals respectively and output them to the corresponding analog voltage input ends.

[0024] Further, the conversion device includes: a plurality of operational amplifiers and a plurality of programmable semiconductor devices connected to the plurality of operational amplifiers one - to - one;

[0025] The inverting input end of each operational amplifier is connected to the drain of the corresponding programmable semiconductor device, and the non - inverting input end is connected to a first fixed bias voltage.

[0026] The output end of the operational amplifier is connected to the source of the programmable semiconductor device and is connected to the corresponding analog voltage input end.

[0027] The gate of the programmable semiconductor device is connected to a fixed bias voltage.

[0028] In a second aspect, an electronic device is provided, including the above - mentioned output configurable memory - in - computing chip.

[0029] The output configurable memory - in - computing chip and the electronic device provided by the embodiments of the present invention. The output configurable memory - in - computing chip includes: a memory - in - computing unit array and a current detection output circuit; the current detection output circuit includes a plurality of current detection output branches; the analog current output ends of each column of memory - in - computing units in the memory - in - computing unit array are each connected to a current detection output branch, configured to process and output the analog current output signals output from the analog current output ends; wherein, the current detection output branch includes a plurality of resistors with different resistances and a multiplexer for selecting resistors, so as to select resistors with different resistances through the multiplexer, thereby realizing the amplification of different magnitudes of output signals of different columns, and being able to achieve high - precision reading of each column of flash memory cells according to the requirements of specific algorithms and applications.

[0030] To make the above - mentioned and other objects, features, and advantages of the present invention more obvious and understandable, the following specific preferred embodiments are given in conjunction with the accompanying drawings and are described in detail as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts. In the drawings:

[0032] Figure 1Shows the current detection output circuit in the gate-coupled memory-in-computation unit array;

[0033] Figure 2 Shows the current detection output circuit in the source-coupled memory-in-computation unit array;

[0034] Figure 3 Shows the current detection output circuit in the gate-coupled memory-in-computation unit array in an embodiment of the present invention;

[0035] Figure 4 Shows a current detection output circuit in a source-coupled memory-in-computation unit array in an embodiment of the present invention;

[0036] Figure 5 Shows another current detection output circuit in a source-coupled memory-in-computation unit array in an embodiment of the present invention.

[0037] Figure 6 Shows yet another current detection output circuit in a source-coupled memory-in-computation unit array in an embodiment of the present invention. Detailed implementation manners

[0038] In order to enable those skilled in the art of this technology to better understand the solution of this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of this application.

[0039] The detailed features and advantages of the present invention are described in detail in the following implementation manners. The content is sufficient for any person skilled in the art to understand the technical content of the present invention and implement it accordingly. And according to the content disclosed in this specification, the claims and the drawings, any person skilled in the art can easily understand the related purposes and advantages of the present invention. The following embodiments further illustrate the viewpoints of the present invention in detail, but do not limit the scope of the present invention in any way.

[0040] It should be noted that, without conflict, the embodiments in this application and the features in the embodiments can be combined with each other. The following will refer to the drawings and combine the embodiments to detail this application.

[0041] In existing memory-in-computation chips, the current detection output circuits used for each column of memory-in-computation units are the same, and it is difficult to achieve high-precision reading of each column of flash memory units according to the requirements of specific algorithms and applications.

[0042] To at least partially solve the above technical problems in the prior art, an embodiment of the present invention provides an output configurable memory - in - computing chip, including: a memory - in - computing unit array and a current detection output circuit.

[0043] Among them, the memory - in - computing unit array is used for performing analog vector - matrix multiplication operations, and the current detection output circuit is used for reading the output of the memory - in - computing unit array.

[0044] The current detection output circuit includes a plurality of current detection output branches; the analog current output terminals of each column of memory - in - computing units in the memory - in - computing unit array are each connected to a current detection output branch, which is used for processing and outputting the analog current output signal output from the analog current output terminal.

[0045] Among them, the current detection output branch includes a plurality of resistors with different resistance values and a multiplexer MUX for selecting resistors.

[0046] It should be noted that the memory - in - computing unit array is composed of a plurality of arranged memory - in - computing unit arrays, and the memory - in - computing unit can be a programmable semiconductor device.

[0047] Specifically, the programmable semiconductor device can be a floating - gate transistor, a resistive - random - access - memory device, a phase - change - memory device, a spin - memory device, etc.

[0048] For example, the memory - in - computing unit array can be a NOR - type flash - memory processing array or a NAND - type flash - memory processing array, etc.

[0049] Those skilled in the art can understand that in practical applications, some of the flash - memory processing arrays in multiple flash - memory processing arrays can be used for operation processing, or all of the flash - memory processing arrays can be used for operation processing. The number of input flash - memory processing arrays depends on the operation requirements. Similarly, for each flash - memory processing array, some of its devices can be used for operation processing, or all of its devices can be used for operation processing, and the number of input devices depends on the operation requirements.

[0050] In summary, by selecting resistors with different resistance values through a multiplexer, different - magnitude amplification of the output signals of different columns can be achieved, and high - precision reading of each column of flash - memory cells can be realized according to the requirements of specific algorithms and applications.

[0051] Figure 3 Shows the current detection output circuit in the gate - coupled memory - in - computing unit array in the embodiment of the present invention; as Figure 3 shown, the memory - in - computing unit array has a gate - coupled and source - summing topological structure;

[0052] Specifically, the memory - in - computing unit array includes: a plurality of programmable semiconductor devices arranged in an array.

[0053] The gates of all programmable semiconductor devices in each row are connected to the same analog voltage input terminal. The M rows of programmable semiconductor devices are correspondingly connected to M analog voltage input terminals for receiving analog voltages.

[0054] The drains of all programmable semiconductor devices in each column are connected to the same bias voltage input terminal. The N columns of programmable semiconductor devices are correspondingly connected to N bias voltage input terminals for inputting bias voltages. The bias voltages of the programmable semiconductor devices in each column can be the same or different, which are selected according to needs.

[0055] The sources of all programmable semiconductor devices in each column are connected to the same analog voltage output terminal. The N columns of programmable semiconductor devices are correspondingly connected to N analog voltage output terminals for outputting operation results.

[0056] Among them, the threshold voltage of each programmable semiconductor device is adjustable. N is a positive integer greater than or equal to zero, and M is a positive integer greater than or equal to zero. M and N can be equal or unequal.

[0057] Among them, the current detection output branch 6 includes: an operational amplifier, resistors R1 to R N and a multiplexer MUX; the resistances of resistors R1 to R N are different.

[0058] The non-inverting input terminal of the operational amplifier is connected to a bias voltage V S , its inverting input terminal is connected to the corresponding analog current output terminal, and its output terminal serves as the output terminal Vout2 of the current detection output branch;

[0059] In addition, the inverting input terminal is also connected to one end of each resistor, and the other ends of the resistors are respectively connected to multiple input terminals of the multiplexer MUX in one-to-one correspondence. The output terminal of the multiplexer is connected to the output terminal of the operational amplifier.

[0060] It should be noted that the multiplexer MUX has a control terminal R S2 for receiving a selection control signal. According to the selection control signal, one of the resistors R1 to R N is selected to be connected.

[0061] In practical applications, the non-inverting input terminal can be grounded. The operational amplifier controls the voltage of the analog current output terminal to be equal to the voltage of the non-inverting input terminal, so as to ensure that the gate-source voltage V GS of the programmable semiconductor device is only controlled by the input voltage corresponding to the programmable semiconductor device, and further makes the voltage of the output terminal of the operational amplifier represent the amplitude of the output current of the programmable semiconductor device in the corresponding column.

[0062] By adopting the above technical solutions, it is possible to achieve amplification of different magnitudes of output signals for different columns, and high-precision reading of each column of flash memory cells can be realized according to the requirements of specific algorithms and applications.

[0063] In another alternative embodiment, refer to Figure 4 , the memory-computation integrated unit array adopts a gate-coupled and drain-sum topology structure. The memory-computation integrated unit array circuit includes: a plurality of programmable semiconductor devices arranged in an array.

[0064] The gates of all programmable semiconductor devices in each row are connected to the same analog voltage input terminal, and M rows of programmable semiconductor devices are correspondingly connected to M analog voltage input terminals;

[0065] The sources of all programmable semiconductor devices in each column are connected to the same bias voltage input terminal, and N columns of programmable semiconductor devices are correspondingly connected to N bias voltage input terminals for inputting bias voltages. The bias voltages of each column of programmable semiconductor devices can be the same or different, and are selected according to needs;

[0066] The drains of all programmable semiconductor devices in each column are connected to the same analog voltage output terminal, and N columns of programmable semiconductor devices are correspondingly connected to N analog voltage output terminals for outputting operation results.

[0067] Among them, the threshold voltage of each programmable semiconductor device can be adjusted. N is a positive integer greater than or equal to zero, M is a positive integer greater than or equal to zero, and M and N can be equal or unequal.

[0068] One end of the resistor R2 and the capacitor C2 in the current detection output circuit 6 is connected between the analog current output terminal and the input terminal of the ADC, and the other end is connected to the power supply V dd or V ss , and the current signal is converted into a voltage signal through resistor-capacitor sampling and then output through the ADC.

[0069] In an alternative embodiment, refer to Figure 5 , the current detection output branch includes: resistors R1 to R N , a multiplexer MUX, and a capacitor C2; the resistance values of the resistors R1 to R N are different.

[0070] One end of the capacitor C2 and each resistor are connected to the corresponding analog current output terminal and serve as the output terminal of the current detection output branch;

[0071] The other end of the capacitor C2 is connected to the power supply V dd or V ss; The other ends of the respective resistors are respectively and correspondingly connected to multiple input ends of the multiplexer MUX, and the output end of the multiplexer is connected to the power supply V dd or V ss .

[0072] It should be noted that the multiplexer MUX has a control terminal R S2 , which is used to receive a selection control signal, and according to the selection control signal, select one of the resistors R1 to R N to access.

[0073] By adopting the above technical solution, it is possible to achieve amplification of different magnitudes of output signals for different columns, and to achieve high-precision reading of each column of flash memory cells according to the requirements of specific algorithms and applications.

[0074] In an optional embodiment, the output configurable memory-computation integrated chip may further include: an ADC; the ADC is connected to the output end of the current detection output branch, and is used to convert the current signal output by the current detection output circuit into a digital signal.

[0075] In an optional embodiment, referring to Figure 6 , there are multiple capacitors and their capacitance values are different. The current detection output branch further includes: a capacitor multiplexer;

[0076] One end of the capacitor and each resistor are both connected to the corresponding analog current output end and serve as the output end of the current detection output branch. The other ends of the respective capacitors are respectively and correspondingly connected to multiple input ends of the capacitor multiplexer, and the output end of the capacitor multiplexer is connected to the power supply, that is, each capacitor is selectively connected to the power supply through the capacitor multiplexer.

[0077] The other ends of the respective resistors are respectively and correspondingly connected to multiple input ends of the multiplexer, and the output end of the multiplexer is connected to the power supply,

[0078] It should be noted that the capacitor multiplexer has a control terminal C S2 , which is used to receive a selection control signal, and according to the selection control signal, select one of the multiple capacitors to access.

[0079] By adopting the above technical solution, flexible selection of capacitors can be achieved, and the applicability is stronger.

[0080] In an optional embodiment, the memory-computation integrated unit is a programmable semiconductor device.

[0081] It should be noted that the programmable semiconductor device is a floating-gate transistor, a resistive random access memory device, a phase change memory device or a spin memory device.

[0082] For example, a floating-gate transistor includes a substrate, an insulating layer, a gate G, a source S, a drain D, and a floating gate F. The floating gate is disposed between the gate and the insulating layer, and the insulating layer is disposed between the floating gate and the substrate, which is used to protect the electrons in the floating gate from leakage. Electrons can be stored in the floating gate. By adjusting the number of electrons in the floating gate, the threshold voltage of the floating-gate transistor can be dynamically adjusted. Due to this structural characteristic of the floating-gate transistor, it can be regarded as a variable equivalent analog weight to store an analog data.

[0083] In an optional embodiment, the output configurable memory-compute integrated chip may further include: a programming circuit, connected to the source, gate, and / or substrate of each programmable semiconductor device, for regulating the threshold voltage of the programmable semiconductor device.

[0084] A floating-gate transistor includes a substrate, an insulating layer, a gate G, a source S, a drain D, and a floating gate F. The floating gate is disposed between the gate and the insulating layer, and the insulating layer is disposed between the floating gate and the substrate, which is used to protect the electrons in the floating gate from leakage. Electrons can be stored in the floating gate. By adjusting the number of electrons in the floating gate, the threshold voltage of the floating-gate transistor can be dynamically adjusted. Due to this structural characteristic of the floating-gate transistor, it can be regarded as a variable equivalent analog weight to store an analog data.

[0085] In an optional embodiment, the output configurable memory-compute integrated chip may further include: a conversion device, connected before the multiple analog voltage input ends of the memory-compute integrated unit array, for respectively converting multiple analog current input signals into analog voltage input signals and outputting them to the corresponding analog voltage input ends.

[0086] In a further embodiment, the conversion device includes: a plurality of operational amplifiers and a plurality of programmable semiconductor devices respectively connected to the plurality of operational amplifiers in one-to-one correspondence;

[0087] The inverting input end of each operational amplifier is connected to the drain of the corresponding programmable semiconductor device, and the non-inverting input end is connected to a first fixed bias voltage.

[0088] The output end of the operational amplifier is connected to the source of the programmable semiconductor device and is connected to the corresponding analog voltage input end.

[0089] The gate of the programmable semiconductor device is connected to a fixed bias voltage.

[0090] When the circuit works, a row of analog current input signals is converted into a row of analog voltage input signals through the conversion device and then respectively applied to N columns of programmable semiconductor devices. By setting the conversion device, the memory-compute integrated unit array in the embodiment of the present invention is not only suitable for analog voltage input signals but also suitable for analog current input signals, which can increase the applicability of the entire memory-compute integrated chip.

[0091] It should be noted that the implementation method of the above conversion device is only an example. Any circuit structure or circuit element that can convert a current input signal into a voltage input signal can be used to implement the conversion device. It can be understood that the programmable semiconductor device in the above conversion device can also be implemented by devices such as resistors and metal-semiconductor field effect transistors.

[0092] An embodiment of the present invention further provides an electronic device, which may include the above output-configurable memory-computing integrated chip. More specifically, the electronic device may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0093] In the present invention, specific embodiments are used to elaborate on the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present invention.

[0094] It should also be noted that the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, commodity or device. Without further limitation, the element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, commodity or device including the said element.

[0095] Each embodiment in this specification is described in a progressive manner. The same or similar parts between each embodiment can be referred to each other, and the key point of each embodiment is to illustrate the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiment.

[0096] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to equivalent embodiments by using the disclosed technical content within the scope of the technical solution of the present invention. However, as long as it does not depart from the technical content of the technical solution of the present invention, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. An output-configurable in-memory computing chip, characterized in that, Comprising: An in-memory computing unit array and a current detection output circuit; The current detection output circuit includes a plurality of current detection output branches; The analog current output terminals of the in-memory computing units in each column of the in-memory computing unit array are each connected to a current detection output branch, for processing and outputting the analog current output signal output from the analog current output terminal; Wherein, the current detection output branch includes a plurality of resistors with different resistances and a multiplexer, the multiplexer has a control terminal for receiving a selection control signal and selecting a resistor according to the selection control signal, The in-memory computing unit array is a gate-coupled structure; The current detection output branch further includes: an operational amplifier, whose non-inverting input terminal is connected to a bias voltage, whose inverting input terminal is connected to the corresponding analog current output terminal, and whose output terminal is used as the output terminal of the current detection output branch; And, the inverting input terminal is further connected to one end of each resistor, the other ends of the resistors are respectively connected to a plurality of input terminals of the multiplexer in one-to-one correspondence, and the output terminal of the multiplexer is connected to the output terminal of the operational amplifier.

2. A configurable in-memory computing chip, characterized in that, Comprising: An in-memory computing unit array and a current detection output circuit; The current detection output circuit includes a plurality of current detection output branches; The analog current output terminals of the in-memory computing units in each column of the in-memory computing unit array are each connected to a current detection output branch, for processing and outputting the analog current output signal output from the analog current output terminal; Wherein, the current detection output branch includes a plurality of resistors with different resistances and a multiplexer, the multiplexer has a control terminal for receiving a selection control signal and selecting a resistor according to the selection control signal, and the in-memory computing unit array is a source-coupled structure; The current detection output branch further includes: a capacitor; One end of the capacitor and each resistor are both connected to the corresponding analog current output terminal and serve as the output terminal of the current detection output branch; The other end of the capacitor is connected to a power supply; the other ends of the resistors are respectively connected to a plurality of input terminals of the multiplexer in one-to-one correspondence, and the output terminal of the multiplexer is connected to the power supply.

3. The output configurable in-memory computing chip according to claim 2, wherein Further comprising: An ADC; the ADC is connected to the output terminal of the current detection output branch.

4. The output-configurable memory-compute integrated chip according to claim 3, wherein There are a plurality of capacitors and their capacitance values are different, and the current detection output branch further includes: a capacitor multiplexer; The other ends of the capacitors are selectively connected to the power supply through the capacitor multiplexer.

5. The configurable in-memory computing chip with an output according to claim 1 or 2, characterized in that, The in-memory computing unit is a programmable semiconductor device.

6. The output configurable memory - in - computing chip according to claim 5, characterized in that, The programmable semiconductor device is a floating-gate transistor, a resistive random access memory device, a phase change memory device or a spin memory device.

7. The configurable in-memory computing chip according to claim 5, characterized in that Further comprising: A programming circuit, connected to the source, gate and / or substrate of each programmable semiconductor device, for regulating the threshold voltage of the programmable semiconductor device.

8. The configurable in-memory computing chip with an output according to claim 1 or 2, characterized in that Further comprising: A conversion device, connected before the plurality of analog voltage input terminals of the in-memory computing unit array, for respectively converting a plurality of analog current input signals into analog voltage input signals and inputting them to the corresponding analog voltage input terminals among the plurality of analog voltage input terminals.

9. An electronic device, characterized in that, Comprising the output-configurable in-memory computing chip according to any one of claims 1 to 8.

Images