Gate contact over the active area in the cell

Abstract

A system and method for arranging grid connections for standard cells is described. In various embodiments, a gate metal is placed on a non-planar vertical conductive structure that is used to form a non-planar device (transistor). A gate contact connects the gate metal to a gate extension metal (GEM) above the gate metal. The GEM is placed above the gate metal and is connected to the gate metal via one or more gate contacts. A gate extension contact is formed on the GEM above the active area. Similar to the gate contact, the gate extension contact is formed using a less complex manufacturing process than using a self-aligned contact process. The gate extension contact connects the GEM to an interconnect layer, such as a metal zero layer. The gate extension contact is vertically aligned with one of the non-planar vertical conductive structures. Therefore, in an embodiment, one or more gate extension contacts are located above the active area.

Description

Background Art

[0001] Description of Related Technology

[0002] As semiconductor manufacturing processes develop and on-chip geometries decrease, semiconductor chips provide more functionality and performance while consuming less space. Although many advances have been made, design issues that limit potential benefits still occur in modern technologies for processing and integrated circuit design. For example, capacitive coupling, electromigration, leakage current, and process yield are some of the issues that affect the device layout and signal routing of the entire bare die across the semiconductor chip. In addition, as transistor size decreases, short channel effects increase. In addition to leakage current, other examples of short channel effects are latch-up, drain-induced barrier lowering (DIBL), punch-through, performance dependence on temperature, impact ionization, and parasitic capacitance to the silicon substrate and the well for the source and drain regions. Therefore, these issues are likely to delay design completion and affect time to market.

[0003] Non-planar transistors are a recent development in semiconductor processing for reducing short channel effects. Tri-gate transistors, fin field effect transistors (FETs) and gate all around (GAA) transistors are examples of non-planar transistors. The processing steps of non-planar devices (transistors) are more complex than those of planar devices (transistors). In order to improve each of the telescoping and metal wiring of the standard cell layout with non-planar devices, these changes are made when changing the processing steps can provide sufficient yields and will not increase manufacturing costs beyond the limit. When these changes are made to the layout, the layout and routing (PNR) layout tools and rule settings for non-planar devices also change.

[0004] When contact placement is flexible in standard cell layout, scaling and metal routing across the standard cell library are improved. However, flexibility is reduced when shorts occur, which reduces yield and significantly complicates processing steps. When contact placement flexibility is reduced, the size of the standard cell increases, and the amount of metal traces available for routing decreases.

[0005] In view of the foregoing, there is a need for efficient methods and systems for creating layouts of non-planar cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Advantages of the methods and mechanisms described herein may be better understood by referring to the following description in conjunction with the accompanying drawings, in which:

[0007] Figure 1 is an overview of top and cross-sectional views of a cell layout with non-planar devices.

[0008] Figure 2 An overview of the top view and cross-section of the unit layout.

[0009] Figure 3 is an overview of a method for creating a cell layout with contacts over a gate in an active area of a non-planar device.

[0010] Figure 4 is an overview of a method for creating a cell layout with contacts over a gate in an active area of a non-planar device.

[0011] Figure 5 is an overview of top and cross-sectional views of a cell layout with non-planar devices.

[0012] Figure 6 is an overview of top and cross-sectional views of a cell layout with non-planar devices.

[0013] Figure 7 is an overview of a method for creating a cell layout with contacts over a gate in an active area of a non-planar device.

[0014] While the invention is susceptible to various modifications and alternative forms, specific embodiments are shown by way of example in the drawings and are herein described in detail. However, it should be understood that the drawings and detailed description thereof are not intended to limit the invention to the particular forms disclosed, but on the contrary, the invention is to cover all modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims. DETAILED DESCRIPTION

[0015] In the following description, numerous specific details are set forth to provide a thorough understanding of the methods and mechanisms presented herein. However, one of ordinary skill in the art will recognize that various embodiments may be practiced without these specific details. In some cases, well-known structures, components, signals, computer program instructions, and techniques are not shown in detail to avoid confusing the methods described herein. It should be understood that the elements shown in the drawings may not be drawn to scale to make the description clear and simple. For example, the size of some elements may be enlarged relative to other elements.

[0016] Considered the system and method for creating the layout of non-planar cell.In some embodiments, cell layout is a standard cell in the cell layout library.In other embodiments, cell layout is a custom designed cell, which is separated from the standard cell layout library.In various embodiments, gate metal is placed on the non-planar vertical conductive structure.The non-planar vertical conductive structure is used to form a non-planar device (transistor).The example of non-planar device is a tri-gate transistor, a fin field effect transistor (FET) and a gate all around (GAA) transistor.In some embodiments, the gate metal is connected to the gate extension metal (GEM) above the gate metal by the gate contact.In one embodiment, GEM is used only above the gate metal.

[0017] In one embodiment, each column of gate metal in the cell layout includes a single gate contact to connect the gate metal to the GEM. In other embodiments, two or more gate contacts are used to connect the gate metal to the GEM, which improves yield. In some embodiments, two or more separate gate contacts are placed in columns at the top and bottom of the cell layout.

[0018] Typically, the gate contact or gate via is not located directly above the active area, for example, above one of the non-planar vertical conductive structures. This typically involves complex semiconductor manufacturing processes, including the use of self-aligned contact processes for the diffusion contacts and gate contacts. By placing the gate contact outside the active area and therefore separate from the non-planar vertical conductive structures, complex semiconductor manufacturing processes, including the use of self-aligned contact processes for the gate contacts, are eliminated. Instead, a less complex manufacturing process is used to place the gate contact. The GEM is then placed above the gate metal and connected to the gate metal via one or more gate contacts.

[0019] In various embodiments, a gate extension contact is formed above the active area on the GEM. Similar to the gate contact between the gate metal and the GEM, in various embodiments, the gate extension contact is formed using a less complex manufacturing process than using a self-aligned contact process. The gate extension contact connects the GEM to an interconnect layer, such as a metal zero layer. The gate extension contact is not connected to the gate contact or gate metal. In some embodiments, the gate extension contact is vertically aligned with one of the non-planar vertical conductive structures. Thus, in embodiments, one or more gate extension contacts are located above the active area. Thus, in embodiments, the height of the cell layout is reduced, which improves scalability and metal trace routing.

[0020] See also Figure 1, a generalized block diagram of a non-planar cell layout 100 is shown, i.e., a top view of the cell layout. In addition, a generalized block diagram of a cross-sectional view of the same cell layout as viewed from side A is shown. As shown, side A is on the left side of the non-planar cell layout 100. In the illustrated embodiment, a p-type metal oxide semiconductor (PMOS) field effect transistor (FET) is located at the top of the cell layout 100. An n-type metal oxide semiconductor (NMOS) field effect transistor (FET) is located at the bottom of the cell layout 100. Here, for ease of illustration, the active area is not shown in the cell layout 100. In some embodiments, the cell layout 100 is part of a standard cell layout library. In other embodiments, the cell layout 100 is a custom layout cell for a specific area of a chip design.

[0021] In various embodiments, Figures 1 to 2 and Figures 5 to 7 The layout techniques shown in are used for various other standard cells and custom cells, which are used for various complex gates and functional cells. In various embodiments, the devices (transistors) in cell layout 100 are non-planar devices (transistors). Non-planar devices are a recent development in semiconductor processing for reducing short channel effects. Tri-gate transistors, fin field effect transistors (FETs), and gate all around (GAA) transistors are examples of non-planar devices.

[0022] The non-planar vertical conductive structure 110 extends out of the page in three dimensions. As used herein, the non-planar vertical conductive structure 110 is also referred to as a "vertical structure 110." Note that although the vertical structure 110 is wired in a horizontal direction, because the vertical structure 110 extends out of the page in three dimensions, the vertical structure is considered vertical. In various embodiments, the vertical structure 110 is included in one of the above-mentioned types of non-planar devices: for example, a tri-gate transistor, a fin field-effect transistor (FET), and a gate-all-around (GAA) transistor.

[0023] In some embodiments, the non-planar devices in the cell layout 100 are manufactured by one of immersion lithography, double patterning, extreme ultraviolet lithography (EUV) and directed self-assembly (DSA) lithography. In some embodiments, EUV technology provides more flexibility with respect to through-hole and contact modules relative to other technologies. As shown, the cell layout 100 uses gate metal 112 in the vertical direction. In some embodiments, titanium nitride (TiN) is used for gate metal 112. For ease of illustration, the boundaries of the active area are not shown, but the rectangular boundaries of the active area are within a relatively close distance of the vertical structure 110 and the gate metal 112. Layer 140 is used to cut the gate layer and show where the gate metal 112 starts and stops. As shown, since layer 140 is placed in the middle of the cell layout 100, each of the third and sixth columns has a separate gate for the top and bottom of the column.

[0024] Local interconnect 130 is routed in a vertical direction similar to gate metal 112. In some embodiments, local interconnect 130 is copper, tungsten, or cobalt, and the material used is based on a design tradeoff between resistance and process reliability. In one embodiment, copper, tungsten, or cobalt contacts 132 are used for the source and drain regions. Metal 0 (M0 or Metal0) 120 is used for local interconnect in the horizontal direction. For ease of illustration, Metal0 120 is not shown in cell layout 100, but only in the cross-sectional view.

[0025] Gate contacts 114 connect the gate metal 112 to a gate extension metal (GEM) 116. In the embodiment shown, the GEM 116 is used only above the gate metal 112. Several columns of separate gate contacts 114 are seen at the top of the cell layout 100 and at the bottom of the cell layout 100. In some embodiments, each column in the cell layout 100 includes a single gate contact 114 to connect the gate metal 112 to the GEM 116. In other embodiments, two or more gate contacts 114 are used to connect the gate metal 112 to the GEM 116, which increases yield.

[0026] Typically, a gate contact or gate via is not located directly above an active area, such as above one of the vertical structures 110. This typically involves a complex semiconductor manufacturing process that uses a self-aligned contact process for the diffusion contact and the gate contact. Here, as shown in cell layout 100 and in each of the cross-sectional views, gate contact 114 is placed outside the active area and, therefore, separate from vertical structure 110. Therefore, a complex semiconductor manufacturing process that uses a self-aligned contact process for gate contact 114 is not used. Instead, a less complex manufacturing process is used to place gate contact 114 outside the active area. Next, GEM 116 is placed above gate metal 112 and connected to gate metal 112 via gate contact 114. Now, in various embodiments, gate contact 118 is formed above the active area. Similar to gate contact 114, in various embodiments, gate extension contact 118 is formed using a less complex manufacturing process than using a self-aligned contact process.

[0027] Gate extension contact 118 connects GEM 116 to horizontal Metal 0 120. Gate extension contact 118 is not connected to gate contact 114 or gate metal 112. Note that one or more of gate extension contacts 118 are vertically aligned with one of vertical structures 110. Thus, in one embodiment, one or more gate extension contacts 118 are located above the active area. Thus, in one embodiment, the height of cell layout 100 is reduced, which improves scalability and metal trace routing.

[0028] Now turn Figure 2 , a generalized block diagram of a non-planar cell layout 100 is shown, i.e., a top view of the cell layout. Additionally, a generalized block diagram of a cross-sectional view of the same cell layout as viewed from side B is shown. As shown, side B is at the bottom of the non-planar cell layout 100. The layout elements described earlier are numbered identically. Although each cell layout 100 is shown as a two-dimensional diagram, three-dimensional elements are depicted in these figures. As previously described, although the vertical structures 110 are wired in a horizontal direction, since each of the vertical structures 110 extends off the page in a three-dimensional manner, the vertical structures are considered to be vertical.

[0029] In an embodiment, in the cross-sectional view, the source / drain contact 132 extends three-dimensionally further out of the page than the gate extension contact 118. Next, the gate extension contact 118 extends further out of the page than each gate contact 114. The Metal0120 in contact with the source / drain contact 132 extends further out of the page than the metal0120 in contact with the gate extension contact 118. Therefore, the dotted line in the cross-sectional view is used to separate the two separate horizontal wirings of the metal0120. The metal0120 to the right of the dotted line extends further out of the page than the metal0120 to the left of the dotted line. In an embodiment, in the cross-sectional view, each of the gate extension contact 118 and the vertical structure 110 extends as much out of the page as each other. Therefore, in the cross-sectional view, the gate extension contact 118 is vertically aligned with the vertical structure 110, and the gate extension contact 118 is located above the active area.

[0030] Now refer to Figure 3 , shows a generalized block diagram of a method 300 for creating a cell layout having contacts over a gate in an active region of a non-planar device. For discussion purposes, the embodiments in this embodiment (and Figure 4 and Figure 2 However, in other embodiments, some steps occur in an order different from that shown, some steps are performed simultaneously, some steps are combined with other steps, and some steps are not present.

[0031] One or more non-planar vertical conductive structures are formed on a silicon substrate (block 302). In various embodiments, the non-planar vertical conductive structures are used to fabricate one of a variety of non-planar devices, such as tri-gate transistors, fin field-effect transistors (FETs), and gate-all-around (GAA) transistors. Gate metal is placed on a portion of the one or more non-planar vertical conductive structures (block 304). Gate contacts are formed on one or more ends of the metal gate (block 306). In various embodiments, the gate contact is not formed on one of the non-planar vertical conductive structures.

[0032] A gate extension metal (GEM) is placed over the metal gate on one or more gate contacts (block 308). In one embodiment, the length of the GEM is equal to or greater than the length of the gate metal. In another embodiment, the length of the GEM is less than the length of the gate metal. A gate extension contact is formed on the GEM at a position on and aligned with one of the non-planar vertical conductive structures (block 310). Thus, in various embodiments, a gate extension contact is formed over the active area. Local metal layers are placed to connect local wiring and power connections (block 312). For example, a metal zero layer is placed to contact the gate extension contact and route signals to other vias. In some embodiments, the cell layout is a standard cell in a cell layout library. In other embodiments, the cell layout is a custom designed cell that is separate from the standard cell layout library.

[0033] Now refer to Figure 4 , a generalized block diagram of a method 400 for creating a cell layout having contacts over a gate in an active region of a non-planar device is shown. A region having an existing gate extension contact on a gate extension metal (GEM) over a non-planar vertical conductive structure formed on a silicon substrate is selected (block 402). In one example, again briefly referring to Figure 2 In the cell layout 100 of FIG. 4 , the region at the top of the sixth column from the left is selected, including the gate extension contact 118. A local interconnect layer is positioned so that it extends parallel to a portion of the metal gate beneath the GEM between the selected region and the source / drain regions that do not include the gate extension contact (block 404).

[0034] Source / drain contacts are formed at locations on the local interconnect layer in the source / drain regions (block 406). Referring again briefly to Figure 2 In the cell layout 100, the source / drain contact 132 is placed to the right and below the gate extension contact 118 at the top of the sixth column from the left. Figure 2 As shown in the cross-sectional view of FIG, each of the local interconnect layer 130 and the source / drain contacts 132 is placed between each of the two gate metals and the two gate extension metals (GEMs). A local metal layer for connecting local wiring and power connections is placed (block 408). In some embodiments, the cell layout is a standard cell in a cell layout library. In other embodiments, the cell layout is a custom designed cell that is separate from the standard cell layout library.

[0035] Now turn Figure 5, a generalized block diagram of the non-planar cell layout 100 is shown, i.e., a top view of the cell layout. In addition, a generalized block diagram of a cross-sectional view of the same cell layout as viewed from side B is shown. As shown, side B is at the bottom of the non-planar cell layout 100. The layout elements described earlier are numbered identically. Although each of the cell layouts 100 and 500 is shown as a two-dimensional diagram, three-dimensional elements are depicted in these figures. As previously described, although the vertical structures 110 are wired in the horizontal direction, since each of the vertical structures 110 extends out of the page in a three-dimensional manner, the vertical structures are considered to be vertical. In addition, in an embodiment, in the cross-sectional view, the source / drain contact 132 extends out of the page more in three dimensions than the gate extension contact 118. Next, the gate extension contact 118 extends out of the page more than each gate contact 114.

[0036] As previously described, the metal0120 in contact with the source / drain contacts 132 extends further out of the page than the metal0120 in contact with the gate extension contact 118. Therefore, the dashed line in the cross-sectional view is used to separate the two separate horizontal routings of metal0120. The metal0120 to the right of the dashed line extends further out of the page than the metal0120 to the left of the dashed line. In one embodiment, in the cross-sectional view, each of the gate extension contact 118 and the vertical structure 110 extends the same amount out of the page as the other. Therefore, in the cross-sectional view, the gate extension contact 118 is vertically aligned with the vertical structure 110, and the gate extension contact 118 is located above the active area.

[0037] As shown, the local interconnect layer 130 is formed over the source / drain region (region) 142. In various embodiments, the source / drain region 142 is formed by an implantation process. In the illustrated embodiment, each gate metal 112 in the cross-sectional view is surrounded by an isolated spacer 150. Similarly, each GEM 116 is surrounded by an isolated spacer 152. In some embodiments, each of the isolated spacers 150 and 152 comprises the same material. In other embodiments, each of the isolated spacers 150 and 152 comprises a different material. In an embodiment, the material used for one or more of the isolated spacers 150 and 152 is silicon nitride.

[0038] In an embodiment, the gate metal 112 is placed to a height that reaches the top of the isolated spacer 150. An isolated spacer is formed above the gate metal 112, and the two materials are etched to near the final height of the gate metal 112. A more isolated spacer 150 is placed on top of the gate metal 112, and then etched and polished. For example, SiN deposition and chemical mechanical planarization (CMP) steps are used. The area for the gate contact 114 is etched into the isolated spacer 150 so that the gate contact 114 is physically connected to the GEM 116 and the gate 112. Next, tetraethyl orthosilicate (TEOS) or other oxide deposition is performed, and then a groove for the GEM 116 is formed. In another embodiment, after the isolated spacer 150 is deposited on the gate metal 112, the isolated spacer 150 is patterned and etched, followed by oxide deposition, such as TEOS deposition. Thereafter, a groove for the GEM 116 is formed, and then a final through-hole etching is performed.

[0039] Cell layout 500 shows that source / drain contacts 132 are doubly self-aligned by GEM 116 and Metal0 layer 120. Metal0 layer 120 self-aligns source / drain contacts 132 within and outside the page. Isolating spacers 152 on GEM 116 self-align source / drain contacts 132. If GEM 116 is misaligned, isolated spacers 150 on gate metal 112 self-align source / drain contacts 132 to local interconnect layer 130.

[0040] Now turn Figure 6 , a generalized block diagram of a non-planar cell layout 100 is shown, i.e., a top view of the cell layout. In addition, a generalized block diagram of a cross-sectional view of the same cell layout as viewed from side B is shown. As shown, side B is at the bottom of the non-planar cell layout 100. The layout elements described earlier are numbered identically. In the illustrated embodiment, as shown in the cross-sectional view, the isolating spacers 154 extend downwardly to the gate metal 112. The isolating spacers 154 provide further alignment and further isolation. In some embodiments, each of the isolating spacers 150 and 154 comprises the same material. In other embodiments, each of the isolating spacers 150 and 154 comprises different materials.

[0041] Now turn Figure 7, a generalized block diagram of a method 700 for creating a cell layout having a contact above a gate in an active region of a non-planar device is shown. Gate metal is placed on a portion of one or more non-planar vertical conductive structures (block 702). Isolating spacers are placed on either side of the gate metal (block 704). Isolating spacers are placed on top of the gate metal (block 706). A local interconnect layer is placed so that the layer extends parallel to a portion of the metal gate between the side spacers of the gate metal (block 708).

[0042] A gate extension metal (GEM) is placed over the metal gate on one or more gate contacts (block 710). Isolating spacers are placed on either side of the GEM (block 712). Isolating spacers are placed on top of the GEM (block 714). Source / drain contacts are formed at locations on the local interconnect layer in the source / drain region (block 716). Local metal layers are placed for connecting local wiring and power connections (block 718). In some embodiments, the cell layout is a standard cell in a cell layout library. In other embodiments, the cell layout is a custom designed cell that is separate from the standard cell layout library.

[0043] It should be noted that one or more of the above-mentioned embodiments include software. In such embodiments, the program instructions of implementation method and / or mechanism are transmitted or stored on a computer-readable medium. The various types of media configured to store program instructions are available and include hard disk, floppy disk, CD-ROM, DVD, flash memory, programmable ROM (PROM), random access memory (RAM) and various other forms of volatile or non-volatile storage devices. In general, computer-accessible storage media is included in any storage medium that can be accessed by the computer during instruction and / or data are provided to the computer. For example, computer-accessible storage media includes storage media, such as magnetic or optical media, such as, disk (fixed or removable), tape, CD-ROM or DVD-ROM, CD-R, CD-RW, DVD-R, DVD-RW or Blu-ray. Storage media also include volatile or non-volatile memory media, such as RAM (e.g., synchronous dynamic RAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM, low power DDR (LPDDR2, etc.) SDRAM, Rambus DRAM (RDRAM), static RAM (SRAM), etc.), ROM, flash memory, non-volatile memory (e.g., flash memory) accessible via a peripheral interface (e.g., a universal serial bus (USB) interface), etc. Storage media include microelectromechanical systems (MEMS) and storage media accessible via a communication medium (e.g., a network and / or a wireless link).

[0044] Additionally, in various embodiments, the program instructions comprise a behavioral level description or a register transfer level (RTL) description of the hardware functionality in a high level programming language (e.g., C) or a design language (HDL) (e.g., Verilog, VHDL) or a database format (e.g., GDSII stream format (GDSII)). In some cases, the description is read by a synthesis tool that synthesizes the description to generate a netlist comprising a series of gates from a synthesis library. The netlist comprises a collection of gates that also represent the functionality of the hardware comprising the system. The netlist is then placed and routed to produce a data set describing the geometry to be applied to a mask. The mask is then used in various semiconductor fabrication steps to produce one or more semiconductor circuits corresponding to the system. Alternatively, the instructions on the computer accessible storage medium are a netlist (with or without a synthesis library) or a data set, as desired. Additionally, the instructions are utilized to generate a system from such vendors (e.g., and ) based on hardware-type simulators for simulation.

[0045] Although the above embodiments have been described in considerable detail, various changes and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such changes and modifications.

Claims

1. A semiconductor device manufacturing method for creating a standard cell layout, comprising: forming one or more non-planar vertical conductive structures on a silicon substrate; placing a gate metal on a portion of the one or more non-planar vertical conductive structures; forming one or more gate contacts on one or more ends of the gate metal; placing a gate extension metal (GEM) over the gate metal on the one or more gate contacts, wherein the gate extension metal is placed only over the gate metal throughout the standard cell layout; as well as A gate extension contact is formed on the gate extension metal at a location on and aligned with one of the one or more non-planar vertical conductive structures, wherein a metal zero layer among a plurality of metal layers for routing signals can be used to wire a gate connection, wherein the metal zero layer contacts one or more of the gate extension contact and the source / drain contacts.

2. The method for manufacturing a semiconductor device according to claim 1, further comprising: selecting a region having a gate extension contact on the gate extension metal above a non-planar vertical conductive structure formed on a silicon substrate; as well as A local interconnect layer is positioned to extend parallel to a portion of the gate metal beneath the gate extension metal between the region and the source / drain region excluding the gate extension contact. 3 . The method for manufacturing a semiconductor device according to claim 2 , further comprising forming the source / drain contact at a position on the local interconnect layer in the source / drain region excluding a gate extension contact.

4. The method for manufacturing a semiconductor device according to claim 1 , further comprising: placing isolating spacers on either side of the gate metal and on top of the gate metal; as well as A local interconnect layer is positioned to extend parallel to a portion of the gate metal along the spacer on the side of the gate metal, wherein the local interconnect layer is separated from each of the source / drain regions and the source / drain electrode contacts.

5. The method for manufacturing a semiconductor device according to claim 1 , further comprising: placing isolation spacers on either side of the gate extension metal and on top of the gate extension metal; as well as Source / drain contacts are formed along spacers on the sides of the gate extension metal. 6 . The method for manufacturing a semiconductor device according to claim 1 , wherein a length of the gate extension metal is equal to a length of a gate metal below the gate extension metal. 7 . The method of claim 1 , wherein each of the one or more non-planar vertical conductive structures comprises a semiconductor fin. 8 . The method of claim 1 , wherein each of the one or more non-planar vertical conductive structures comprises a semiconductor nanowire.

9. A semiconductor structure comprising: one or more non-planar vertical conductive structures on a silicon substrate; a gate metal on a portion of the one or more non-planar vertical conductive structures; one or more gate contacts on one or more ends of the gate metal; a gate extension metal (GEM) on the one or more gate contacts over the gate metal, wherein the gate extension metal is placed only over the gate metal in an entire standard cell layout; as well as A gate extension contact on the gate extension metal at a position on and aligned with one of the one or more non-planar vertical conductive structures, wherein a metal zero layer of a plurality of metal layers for routing signals can be used to wire a gate connection, wherein the metal zero layer contacts one or more of the gate extension contact and the source / drain contacts.

10. The semiconductor structure of claim 9, further comprising: a region having a gate extension contact on the gate extension metal above a non-planar vertical conductive structure formed on a silicon substrate; as well as A local interconnect layer extends parallel to a portion of the gate metal beneath the gate extension metal between the region and the source / drain region excluding the gate extension contact.

11. The semiconductor structure of claim 10, further comprising the source / drain contacts at locations on the local interconnect layer in the source / drain regions excluding gate extension contacts.

12. The semiconductor structure of claim 9, further comprising: isolated spacers on either side of the gate metal and on top of the gate metal; as well as A local interconnect layer extends parallel to a portion of the gate metal along the spacer on the side of the gate metal, wherein the local interconnect layer is separated from each of the source / drain regions and the source / drain electrode contacts.

13. The semiconductor structure of claim 9, further comprising: isolated spacers on either side of the gate extension metal and on top of the gate extension metal; as well as Source / drain contacts are extended along spacers on the sides of the gate metal.

14. The semiconductor structure of claim 9, wherein a length of the gate extension metal is equal to a length of a gate metal below the gate extension metal.

15. The semiconductor structure of claim 9, wherein each of the one or more non-planar vertical conductive structures comprises a semiconductor fin.

16. The semiconductor structure of claim 9, wherein each of the one or more non-planar vertical conductive structures comprises a semiconductor nanowire.

17. A non-transitory computer-readable storage medium storing program instructions, wherein the program instructions for performing a semiconductor manufacturing method are executable by a processor to: forming one or more non-planar vertical conductive structures on a silicon substrate; placing a gate metal on a portion of the one or more non-planar vertical conductive structures; forming one or more gate contacts on one or more ends of the gate metal; placing a gate extension metal (GEM) over the gate metal on the one or more gate contacts, wherein the gate extension metal is placed only over the gate metal in the entire standard cell layout; as well as A gate extension contact is formed on the gate extension metal at a location on and aligned with one of the one or more non-planar vertical conductive structures, wherein a metal zero layer among a plurality of metal layers for routing signals can be used to wire a gate connection, wherein the metal zero layer contacts one or more of the gate extension contact and the source / drain contacts.

18. The non-transitory computer-readable storage medium of claim 17, wherein the program instructions are further executable by a processor to: selecting a region having a gate extension contact on the gate extension metal above a non-planar vertical conductive structure formed on a silicon substrate; and A local interconnect layer is positioned to extend parallel to a portion of the gate metal beneath the gate extension metal between the region and the source / drain region excluding the gate extension contact.

19. The non-transitory computer-readable storage medium of claim 18, wherein the program instructions are further executable by a processor to form the source / drain contacts at locations on the local interconnect layer in the source / drain regions excluding gate extension contacts.

20. The non-transitory computer-readable storage medium of claim 17, wherein the program instructions are further executable by a processor to: placing isolating spacers on either side of the gate metal and on top of the gate metal; and A local interconnect layer is positioned to extend parallel to a portion of the gate metal along the spacer on the side of the gate metal, wherein the local interconnect layer is separated from each of the source / drain regions and the source / drain electrode contacts.

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