Semiconductor system and method for operating a semiconductor system

Abstract

A semiconductor system is provided. The semiconductor system includes: a Universal Flash Storage (UFS) host; a UFS device configured to exchange data with the UFS host through a UFS interface; and an application processor configured to control the UFS host. The UFS device is configured to maintain a powered-on state when the application processor operates in a suspend mode.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2019 - 0079908, filed on Jul. 3, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] One or more example embodiments of the present disclosure relate to a semiconductor system and a method for operating a semiconductor system. Background art

[0004] When an application processor that controls a Universal Flash Storage (UFS) host enters a suspend mode, the power of the UFS device is turned off, and the UFS device loses the set values and information exchanged with the UFS host during Link startup. As a result, when the application processor exits the suspend mode, the UFS host needs to perform the Link startup task again. However, since the Link startup task proceeds at a relatively slow rate, it is desirable to reduce the time required to re - establish a connection between the UFS host and the UFS device when the application processor exits the suspend mode. Summary of the invention

[0005] One or more example embodiments of the present disclosure provide a semiconductor system and a method for operating a semiconductor system, which can reduce the time required to perform the initialization of a Universal Flash Storage (UFS) host, such that a connection between the UFS host and the UFS device can be quickly established when an application processor that controls the UFS host exits the suspend mode.

[0006] It should be noted that aspects of the present disclosure are not limited to those set forth herein. By referring to the detailed description of the present disclosure given below, the above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains.

[0007] According to an aspect of an example embodiment of the present disclosure, there is provided a semiconductor system including: a UFS host; a UFS device configured to exchange data with the UFS host through a UFS interface; and an application processor configured to control the UFS host. The UFS device is configured to maintain a powered - on state when the application processor operates in a suspend mode.

[0008] According to one aspect of an exemplary embodiment of the present disclosure, a semiconductor system is provided, the semiconductor system including: a Universal Flash Storage (UFS) host; a UFS device configured to exchange data with the UFS host through a UFS interface; and an application processor that controls the UFS host. The UFS device is configured to maintain a powered-on state when the UFS host is in a powered-off state.

[0009] According to one aspect of an exemplary embodiment of the present disclosure, a method for operating a semiconductor system is provided, the method including: entering a sleep mode through a Universal Flash Storage (UFS) device; controlling the UFS host to enter a suspend mode through an application processor; maintaining the powered-on state of the UFS device through the application processor; exiting the suspend mode through the application processor; and exiting the sleep mode through the UFS device. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0011] Figure 1 is a diagram for illustrating a semiconductor system according to an exemplary embodiment of the present disclosure;

[0012] Figure 2 is a diagram for illustrating a semiconductor system according to an exemplary embodiment of the present disclosure;

[0013] Figure 3 is a diagram for illustrating an operation of a UFS device according to an exemplary embodiment of the present disclosure;

[0014] Figure 4 is a diagram for illustrating a method for operating a semiconductor system according to an exemplary embodiment of the present disclosure;

[0015] Figure 5 is a diagram for illustrating a method for operating a semiconductor system according to an exemplary embodiment of the present disclosure; and

[0016] Figure 6 is a diagram for illustrating a comparative example compared with a semiconductor system and a method for operating a semiconductor system according to an exemplary embodiment of the present disclosure, in which a Universal Flash Storage (UFS) Link startup task is performed. DETAILED DESCRIPTION

[0017] Hereinafter, various exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0018] Figure 1 is a diagram for illustrating a semiconductor system according to an exemplary embodiment of the present disclosure. Figure 2It is a diagram for explaining a semiconductor system according to an exemplary embodiment of the present disclosure.

[0019] Reference Figure 1 , a semiconductor system 1 according to an exemplary embodiment of the present disclosure includes an application processor 5, a Universal Flash Storage (UFS) host 10, and a UFS device 20.

[0020] The application processor 5 may control the UFS host 10 to store data in the UFS device 20 or may read data from the UFS device 20. To this end, the application processor 5 may provide a reset signal Reset_n and a reference clock signal RefClk to the UFS device 20.

[0021] The UFS host 10 may store data on the UFS device 20 in response to a request from the application processor 5, and may read data from the UFS device 20 in response to a request from the application processor 5 and provide the data to the application processor 5. The UFS host 10 may be connected to the UFS device 20 through a Universal Flash Storage (UFS) interface.

[0022] For example, the UFS host 10 may send data to the UFS device 20 through data lines DIN0 and DIN1. On the other hand, the UFS host 10 may receive data from the UFS device 20 through data lines DOUT0 and DOUT1. The data lines DIN0 and DIN1 and the data lines DOUT0 and DOUT1 may be implemented by differential signal lines, respectively.

[0023] The UFS device 20 may receive a power supply VCC separately from the UFS host 10, and may maintain a power-on state through the power supply VCC. Although only VCC is shown in the drawing as the power supply to be provided to the UFS device 20, this is merely an example for simplifying the description, and the exemplary embodiment is not limited thereto. In some embodiments, various forms of power supplies other than VCC may be provided to the UFS device 20. For example, VCCQ, VCCQ2, and / or VCC may be provided to the UFS device 20 as power supplies. Moreover, as Figure 3 shown, various power supplies may be provided to the UFS device 20.

[0024] The application processor 5 may operate in various power modes. For example, the application processor 5 may operate in a suspend mode to reduce power consumption. For example, when the user does not use the device driven by the application processor 5 for a certain period of time, the application processor 5 may reduce wasted power consumption by switching the operation mode to the suspend mode.

[0025] However, in the related art, when the application processor 5 enters the suspend mode, the power supply VCC of the UFS device 20 is turned off, and the UFS device 20 may lose the set values and information exchanged with the UFS host 10. The set values and information mentioned herein refer to the set values and information exchanged between the UFS host 10 and the UFS device 20 through the Linkstartup task among the initialization tasks for establishing a connection between the UFS host 10 and the UFS device 20 via the UFS interface.

[0026] Therefore, when the application processor 5 exits the suspend mode, the UFS host 10 needs to exchange the set values and information with the UFS device 20 again. Therefore, the UFS host 10 and the UFS device 20 need to execute the Linkstartup task and need to execute the Power Mode Change task again.

[0027] However, the Linkstartup task and the power mode change task are executed at a relatively low speed of about 3 Mbps to 9 Mbps. On the other hand, after the power mode change is executed, the UFS host 10 and the UFS device 20 can exchange data at a relatively high speed of 12 Gbps (6 Gbps per channel) to 24 Gbps (12 Gbps per channel) through the UFS interface.

[0028] Therefore, in the case of maintaining the UFS device 20 in the powered-on state while the application processor 5 operates in the suspend mode, when the application processor 5 exits the suspend mode, the time required to re-establish a connection between the UFS host 10 and the UFS device 20 can be reduced and a connection can be quickly established between the UFS host 10 and the UFS device 20.

[0029] In some embodiments of the present disclosure, the semiconductor system 1 may further include a buffer memory. The buffer memory may be used as the main memory of the UFS host 10, or may be used as a cache memory, a temporary memory, etc. for temporarily storing data. In some embodiments of the present disclosure, although the buffer memory may include a volatile memory including a dynamic random access memory (DRAM), the scope of the present disclosure is not limited thereto.

[0030] Reference Figure 2 , the semiconductor system 2 according to an exemplary embodiment of the present disclosure includes a UFS host 10 and a UFS device 20. Figure 2 More specifically shown is Figure 1 the UFS host 10 and the UFS device 20 described in

[0031] Specifically, the UFS host 10 includes an application 100, a UFS driver 110, a UFS host controller interface 130, a UFS host UniPro 140, and a UFS host M-PHY 150.

[0032] The application 100 can control the semiconductor system 2 based on a command set that runs on the UFS host 10 and can be used in the semiconductor system 2.

[0033] The UFS driver 110 can drive the UFS device 20 connected to the UFS host 10. Specifically, the UFS driver 110 can receive a command for controlling the UFS device 20 from the application 100, process the command using the UFS host controller interface 130, and provide its processing result to the application 100.

[0034] Although, according to some embodiments, the application 100 and the UFS driver 110 can be implemented by software, the scope of the present disclosure is not limited thereto.

[0035] The UFS host controller interface 130 controls the overall operation within the UFS host 10. For example, in response to a write command received from the UFS driver 110, the UFS host controller interface 130 can send the data D IN0_t , D IN0_c , D IN1_t , D IN1_c stored in the buffer memory to the UFS device 20 through the UFS host UniPro 140 and the UFS host M-PHY 150. In addition, in response to a read command received from the UFS driver 110, the UFS host controller interface 130 can receive the data D OUT0_t , D OUT0_c , D OUT1_t , D OUT1_c from the UFS device 20 through the UFS host UniPro 140 and the UFS host M-PHY 150.

[0036] The UFS host UniPro 140 and the UFS host M-PHY 150 exchange data with the UFS device UniPro 250 and the UFS device M-PHY 260 of the UFS device 20 described below through the data lines DIN and DOUT.

[0037] Other details of the application 100, the UFS driver 110, the UFS host controller interface 130, the UFS host UniPro 140, and the UFS host M-PHY 150 of the UFS host 10 are known in the UFS specification, and thus, their descriptions will not be provided.

[0038] The UFS device 20 includes a user storage device 200, a logic unit 210, a device-level management unit 230, a descriptor 240, a UFS device UniPro 250, and a UFS device M-PHY 260.

[0039] Although the user storage device 200 may include a flash memory, a magnetoresistive random access memory (MRAM), a phase change random access memory (PRAM), a ferroelectric random access memory (FeRAM), etc., the scope of the present disclosure is not limited thereto.

[0040] The logic unit 210, the device-level management unit 230, and the descriptor 240 control the overall operation within the UFS device 20. For example, the logic unit 210, the device-level management unit 230, and the descriptor 240 may perform tasks of writing, reading, and / or erasing data requested by the UFS host 10 on the user storage device 200. To this end, like the UFS host 10, the UFS device 20 may also include a buffer memory.

[0041] Other details of the user storage device 200, the logic unit 210, the device-level management unit 230, the descriptor 240, the UFS device UniPro 250, and the UFS device M-PHY 260 in the UFS device 20 are known in the UFS specification, and thus, their descriptions will not be provided in this specification.

[0042] Figure 3 is a diagram for explaining the operation of a UFS device according to an exemplary embodiment of the present disclosure.

[0043] Reference Figure 1 and Figure 3 , the UFS device 20 of the semiconductor system according to an exemplary embodiment of the present disclosure includes a UFS I / O that receives a reset signal Reset_n and a reference clock signal RefClk from the application processor 5, exchanges data D IN0_t / c , D IN1_t / c , D OUT0_t / c , D OUT1_t / c with the UFS host 10, an M-PHY, and provides an interface NAND I / O block to the MLC NAND, and includes a core logic that generally controls the UFS I / O, the M-PHY, the NAND I / O block, etc.

[0044] As Figure 3 shown, electric power can be supplied to the above elements of the UFS device 20 through one or more power supplies VCC, VCCQ, VCCQ2, VDDi, VDDiQ2, and capacitors C CP-IN , C VDDiQ2 , C VDDi etc. connected to the power supplies.

[0045] In some embodiments according to the present disclosure, when the application processor 5 operates in a suspend mode, the UFS device 20 maintains a powered-on state.

[0046] That is, in some embodiments, when the application processor 5 operates in a suspend mode, the UFS device 20 operates in a hibernation mode. Specifically, before the application processor 5 enters the suspend mode, the UFS device 20 may enter the hibernation mode. Before the UFS device 20 enters the hibernation mode, the application processor 5 may store at least one of setting values or status information in the host controller interface, UniPro, and M-PHY of the UFS host 10.

[0047] In addition, in some embodiments, when the application processor 5 operates in a suspend mode, the application processor 5 may provide a reference clock signal RefClk to the UFS device 20. In some embodiments, the application processor 5 may provide the reference clock signal RefClk to the UFS device 20 before the UFS device 20 enters the hibernation mode, and the application processor 5 may not provide the reference clock signal RefClk to the UFS device 20 when the UFS device 20 enters the hibernation mode. In some embodiments, the application processor 5 may provide the reference clock signal RefClk to the UFS device 20 before the UFS device 20 exits the hibernation mode.

[0048] On the other hand, when the application processor 5 operates in a suspend mode, the application processor 5 continues to provide a reset signal Reset_n to the UFS device 20.

[0049] In addition, in response to the application processor 5 exiting the suspend mode, the UFS device 20 exits the hibernation mode. Specifically, before the UFS device 20 exits the hibernation mode, the application processor 5 restores at least one of setting values or status information related to at least one of the host controller interface, UniPro, or M-PHY of the UFS host 10.

[0050] Therefore, in response to the application processor 5 exiting the suspend mode, the UFS host 10 does not need to perform a UFS Link startup task, that is, the UFS host 10 skips the UFS Link startup task.

[0051] In addition, in response to the application processor 5 exiting the suspend mode, the UFS host 10 does not need to perform a UFS power mode change task, that is, the UFS host 10 skips the power mode change task.

[0052] On the other hand, in some embodiments according to the present disclosure, the UFS device 20 maintains a powered-on state while the UFS host 10 is in a powered-off state.

[0053] That is, when the UFS host 10 is in a power-off state, the UFS device 20 operates in a sleep mode. Specifically, before the UFS host 10 transitions to the power-off state, the UFS device 20 enters the sleep mode. Before the UFS device 20 enters the sleep mode, the application processor 5 stores at least one of the set values or status information in the host controller interface, UniPro, and M-PHY of the UFS host 10.

[0054] In addition, in some embodiments, when the UFS host 10 is in a power-off state, the application processor 5 may provide a reference clock signal RefClk to the UFS device 20. In some embodiments, the application processor 5 provides the reference clock signal RefClk to the UFS device 20 before the UFS device 20 enters the sleep mode, and the application processor 5 may not provide the reference clock signal RefClk to the UFS device 20 when the UFS device 20 operates in the sleep mode. In some embodiments, the application processor 5 may provide the reference clock signal RefClk to the UFS device 20 before the UFS device 20 exits the sleep mode.

[0055] On the other hand, when the UFS host 10 is in a power-off state, the application processor 5 continues to provide a reset signal Reset_n to the UFS device 20.

[0056] In addition, in response to the UFS host 10 transitioning to a power-on state, the UFS device 20 exits the sleep mode. Specifically, before the UFS device 20 exits the sleep mode, the application processor 5 restores at least one of the set values or status information related to at least one of the host controller interface, UniPro, or M-PHY of the UFS host 10.

[0057] As a result, in response to the UFS host 10 transitioning to a power-on state, the UFS host 10 does not need to perform a UFS Link startup task.

[0058] In addition, in response to the UFS host 10 transitioning to a power-on state, the UFS host 10 does not need to perform a UFS power mode change task.

[0059] Figure 4 It is a diagram for explaining a method for operating a semiconductor system according to an exemplary embodiment of the present disclosure.

[0060] Reference Figure 4 , a method for operating a semiconductor system according to an exemplary embodiment of the present disclosure includes storing at least one of the set values or status information related to at least one of the host controller interface, UniPro, or M-PHY of the UFS host 10 (S401).

[0061] The method further includes putting the UFS device 20 into a sleep mode (S403).

[0062] The method further includes putting the application processor 5 used to control the UFS host 10 into a suspend mode (S405).

[0063] The method further includes waking the application processor 5 out of the suspend mode (S407).

[0064] The method further includes initializing the UFS host 10 (S409).

[0065] The method further includes restoring at least one of setting values or status information related to at least one of the host controller interface, UniPro, or M-PHY of the UFS host 10 (S411).

[0066] The method further includes waking the UFS device 20 out of the sleep mode (S413).

[0067] That is to say, when the application processor 5 is operating in the suspend mode, the UFS device 20 can operate in the sleep mode.

[0068] In some embodiments, when the application processor 5 is operating in the suspend mode, the application processor 5 can provide a reference clock signal RefClk to the UFS device 20. In some embodiments, the application processor 5 provides the reference clock signal RefClk to the UFS device 20 before the UFS device 20 enters the sleep mode, and the application processor 5 can stop providing the reference clock signal RefClk to the UFS device 20 when the UFS device 20 is operating in the sleep mode. In some embodiments, the application processor 5 can provide the reference clock signal RefClk to the UFS device 20 before the UFS device 20 wakes out of the sleep mode.

[0069] On the other hand, when the application processor 5 is operating in the suspend mode, the application processor 5 can continue to provide a reset signal Reset_n to the UFS device 20.

[0070] As a result, in response to the application processor 5 waking out of the suspend mode, the UFS host 10 does not execute the UFSLinkstartup task, that is, the UFS host 10 skips the UFS Linkstartup task.

[0071] In addition, in response to the application processor 5 waking out of the suspend mode, the UFS host 10 does not run the UFS power mode change task, that is, the UFS host 10 skips the UFS power mode change task.

[0072] Figure 5It is a diagram for explaining a method for operating a semiconductor system according to an exemplary embodiment of the present disclosure. Figure 6 It is a diagram for explaining a comparative example as compared with a semiconductor system and a method for operating a semiconductor system according to an exemplary embodiment of the present disclosure, in which a Universal Flash Storage (UFS) Linkstartup task is performed.

[0073] In Figure 5 “Sequence 1” indicates a comparative case where the UFS device does not maintain a powered-on state when the application processor 5 operates in a suspended mode. “Sequence 2” indicates a case where the UFS device remains in a powered-on state when the application processor 5 operates in a suspended mode according to an exemplary embodiment.

[0074] Figure 6 It is a diagram specifically showing the operation of performing the UFS Linkstartup task.

[0075] As can be seen from Figure 5 and Figure 6 When the suspend mode is executed according to “Sequence 1” and the application processor 5 resumes, it is necessary to perform the UFS Linkstartup task and the UFS power mode change task after the application processor 5 exits the suspend mode. However, the UFS Linkstartup task is a time-consuming task that requires a large amount of data exchange between the UFS host 10 and the UFS device 20, thus delaying the establishment of the connection between the UFS host 10 and the UFS device 20.

[0076] According to an exemplary embodiment, the suspend and resume of the application processor 5 are performed according to “Sequence 2”, in which the UFS device 20 maintains a powered-on state when the application processor 5 operates in a suspended mode. Therefore, the time required to re-establish the connection between the UFS host 10 and the UFS device 20 can be reduced, and the connection between the UFS host 10 and the UFS device 20 can be established quickly.

[0077] According to an example embodiment, at least one of the components, elements, modules, or units described herein may be implemented as various numbers of hardware, software, and / or firmware structures that perform the respective functions described above. For example, at least one of these components, elements, or units may use a direct circuit structure, such as a memory, a processor, a logic circuit, a look-up table, etc., which may perform the respective functions under the control of one or more microprocessors or other control devices. Moreover, at least one of these components, elements, or units may be embodied specifically by a module, a program, or a portion of code that includes one or more executable instructions for performing a specified logical function and is run by one or more microprocessors or other control devices. Moreover, at least one of these components, elements, or units may also include a processor (such as a central processing unit (CPU) that performs the respective functions), a microprocessor, etc., or be implemented thereby. Two or more of these components, elements, or units may be combined into a single component, element, or unit that performs all the operations or functions of the combined two or more components, elements, or units. Moreover, at least a portion of the functions of at least one of these components, elements, or units may be performed by another of these components, elements, or units. In addition, although a bus is not shown in the block diagram, communication between the components, elements, or units may be performed via a bus. The functional aspects of the above example embodiments may be implemented by an algorithm running on one or more processors. In addition, the components, elements, or units represented by blocks or processing steps may employ any number of related technologies for electronic configuration, signal processing and / or control, data processing, etc.

[0078] Although some example embodiments have been described above, the scope of the present disclosure is not limited thereto, and various modifications and improvements made by those of ordinary skill in the art to the concepts defined in the appended claims should be understood to fall within the scope of the present disclosure.

Claims

1. A semiconductor system, comprising: A Universal Flash Storage (UFS) host; A UFS device configured to exchange data with the UFS host through a UFS interface; And An application processor configured to control the UFS host, wherein the UFS device is configured to maintain a powered-on state when the application processor operates in a suspend mode, wherein after the application processor exits the suspend mode, the UFS host is configured not to perform a UFS Link startup task.

2. The semiconductor system according to claim 1, wherein, The UFS device is configured to operate in a sleep mode when the application processor operates in a suspend mode.

3. The semiconductor system according to claim 2, wherein, The application processor is configured to provide a reference clock signal to the UFS device before the UFS device enters the sleep mode, and the application processor is configured not to provide a reference clock signal to the UFS device when the UFS device operates in the sleep mode.

4. The semiconductor system according to claim 2, wherein, The application processor is configured to provide a reset signal to the UFS device when the application processor operates in a suspend mode.

5. The semiconductor system according to claim 2, wherein, Before the application processor enters the suspend mode, the UFS device is configured to enter the sleep mode.

6. The semiconductor system according to claim 5, wherein, Before the UFS device enters the sleep mode, the application processor is configured to store at least one of setting values or status information related to at least one of a host controller interface, UniPro, or M-PHY of the UFS host.

7. The semiconductor system according to claim 2, wherein, After the application processor exits the suspend mode, the UFS device is configured to exit the sleep mode.

8. The semiconductor system according to claim 7, wherein, Before the UFS device exits the sleep mode, the application processor is configured to restore at least one of setting values or status information related to at least one of a host controller interface, UniPro, or M-PHY of the UFS host.

9. The semiconductor system according to claim 1, wherein, After the application processor exits the suspend mode, the UFS host is further configured not to perform a UFS power mode change task.

10. A method for operating a semiconductor system, the method comprising: Entering a sleep mode through a Universal Flash Storage (UFS) device; Controlling the UFS host to enter a suspend mode through an application processor; Maintaining a powered-on state of the UFS device through an application processor; Exiting the suspend mode through an application processor; and Exiting the sleep mode through the UFS device, wherein after the application processor exits the suspend mode, the UFS host is configured not to perform a UFS Link startup task.

11. The method for operating a semiconductor system according to claim 10, further comprising: Storing at least one of setting values or status information related to at least one of a host controller interface, UniPro, or M-PHY of the UFS host through an application processor before the UFS device enters the sleep mode; and Restoring at least one of setting values or status information related to at least one of a host controller interface, UniPro, or M-PHY of the UFS host through an application processor before the UFS device exits the sleep mode.

12. The method for operating a semiconductor system according to claim 10, wherein, The UFS device is configured to operate in a sleep mode when the application processor operates in a suspend mode.

13. The method for operating a semiconductor system according to claim 12, wherein, The application processor is configured to provide a reference clock signal to the UFS device before the UFS device enters the sleep mode, and the application processor is configured not to provide the reference clock signal to the UFS device when the UFS device is operating in the sleep mode.

14. The method for operating a semiconductor system according to claim 12, wherein, When the UFS host is in the powered-off state, the application processor is configured to provide a reset signal to the UFS device.

15. The method for operating a semiconductor system according to claim 12, wherein, After the application processor exits the suspend mode, the UFS host is further configured not to perform the UFS power mode change task.

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